Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The method comprises the following steps: providing a substrate, and forming a hard mask material layer on the substrate; the hard mask material layer is etched, so that the thickness of the hard mask material layer in the target area has gradient, and a hard mask layer is obtained; ion implantation is carried out on the substrate based on the hard mask layer, a buried dielectric layer is formed in the substrate, and the thickness of a target part, directly facing the target area, of the buried dielectric layer has gradient; and removing the hard mask layer. The heat dissipation performance of the semiconductor structure can be easily improved while the characteristic requirement of a high-voltage device is met, so that the device performance and reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the wide application of very large scale integrated circuits in various fields, the system has higher and higher requirements for the development of high-voltage and high-power semiconductor devices. The integrated high-voltage devices using Silicon On Insulator (SOI) technology combine the advantages of SOI technology and the devices themselves, such as fast working speed, low parasitic effect, high breakdown voltage, simple process preparation, and convenient integration. Therefore, they can be widely used in fields closely related to human beings, such as automobiles, aircraft, household appliances, robots, motors, lighting, etc.

[0003] At present, the SOI technology has pioneered the solution to the isolation problem between the high-voltage module and the low-voltage module in the high-voltage integrated circuit (HVIC), as well as the operation problem of sub-circuits at different voltage levels. However, as the cornerstone of the SOI high-voltage integrated circuit, the SOI high-voltage LDMOS (lateral double-diffused MOSFET) device has two major disadvantages: relatively low vertical breakdown voltage and self-heating effect, which easily limit the application of the SOI high-voltage integrated circuit. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof.

[0005] In some embodiments of the present disclosure, a manufacturing method of a semiconductor structure includes: providing a substrate, forming a hard mask material layer on the substrate; etching the hard mask material layer to make the thickness of the hard mask material layer have a gradient in a target area, obtaining a hard mask layer; performing ion implantation on the substrate based on the hard mask layer to form a buried dielectric layer in the substrate, and the thickness of the target part of the buried dielectric layer facing the target area has a gradient; removing the hard mask layer.

[0006] The manufacturing method of the above semiconductor structure can form a hard mask layer with a thickness gradient in the target area on the substrate, form a buried dielectric layer in the substrate based on the hard mask layer, and make the thickness of the target part of the buried dielectric layer facing the target area have a gradient. In this way, the present disclosure can effectively optimize the electric field lines of the semiconductor structure by using the thickness gradient of the buried dielectric layer, so as to easily improve the heat dissipation performance of the semiconductor structure while meeting the characteristics requirements of high-voltage devices, thereby effectively improving the device performance and reliability of the semiconductor structure. Moreover, the manufacturing method provided by the present disclosure has a simple process and is easy to implement, which is beneficial to improving production efficiency and yield.

[0007] In one embodiment, the etching of the hard mask material layer to make the thickness of the hard mask material layer have a gradient in the target area to obtain the hard mask layer includes: forming a photoresist layer with an opening pattern on the hard mask material layer; based on the opening pattern, wet etching the hard mask material layer to make the thickness of the hard mask material layer have a gradient in the target area to obtain the hard mask layer; removing the photoresist layer.

[0008] In one embodiment, the substrate is a silicon wafer. The ion implantation of the substrate based on the hard mask layer to form a buried dielectric layer in the substrate includes: performing oxygen ion implantation on the substrate based on the hard mask layer; performing a high-temperature treatment on the substrate after the oxygen ion implantation to form a buried dielectric layer.

[0009] In one embodiment, the manufacturing method of the semiconductor structure further includes: forming an epitaxial layer on the surface of the substrate after removing the hard mask layer. Wherein, the surface of the buried dielectric layer close to the epitaxial layer is parallel to the surface of the substrate. The distance between the surface of the buried dielectric layer close to the epitaxial layer and the surface of the epitaxial layer facing away from the substrate is equal to the target threshold. In this way, the manufacturing method provided by the present disclosure can easily match the requirements to form epitaxial layers with various thicknesses, so as to effectively extend the applicable range of high- and low-voltage grade transistor devices.

[0010] In one embodiment, the manufacturing method of the semiconductor structure further includes: forming a plurality of transistor devices based on the substrate and the epitaxial layer above the buried dielectric layer. Wherein, at least one transistor device includes a drain region and a source region arranged at intervals in a direction parallel to the substrate; the target part includes a first sub-target part facing the drain region and a second sub-target part facing the source region; the minimum thickness of the first sub-target part is greater than the maximum thickness of the second sub-target part.

[0011] In some embodiments of the present disclosure, a semiconductor structure can be obtained by using the manufacturing method described in any of the above embodiments. The semiconductor structure includes: a substrate and a buried dielectric layer. The buried dielectric layer is disposed in the substrate and includes a target part with a thickness gradient. Wherein, the upper surface of the buried dielectric layer is parallel to the surface of the substrate. The lower surface of the target part is an inclined surface.

[0012] The semiconductor structure can utilize the thickness gradient of the target portion in the buried dielectric layer to effectively optimize the electric field lines of the semiconductor structure, so as to easily improve the heat dissipation performance of the semiconductor structure while meeting the high-voltage device characteristic requirements, thereby effectively improving the device performance and reliability of the semiconductor structure.

[0013] In some embodiments of the present disclosure, the semiconductor structure further includes: an epitaxial layer disposed on the substrate; wherein the distance between the upper surface of the buried dielectric layer close to the epitaxial layer and the upper surface of the epitaxial layer facing away from the substrate is equal to the target threshold.

[0014] The above-mentioned semiconductor structure has an epitaxial layer arranged on the substrate, and it is also easy to control the formation thickness of the epitaxial layer according to the requirements, so as to control the total thickness of the substrate and the epitaxial layer above the buried dielectric layer, thereby ensuring the voltage resistance characteristics of the transistor device based on the total thickness of the substrate and the epitaxial layer above the buried dielectric layer, so as to effectively extend the application range of high and low voltage transistor devices.

[0015] In one embodiment, the semiconductor structure further includes: at least one LDMOS device. The LDMOS device is located in the substrate and the epitaxial layer above the target portion, and includes a drain region and a source region spaced apart in a direction parallel to the substrate. The target portion includes: a first sub-target portion directly opposite to the drain region of the LDMOS device, and a second sub-target portion directly opposite to the source region of the LDMOS device; the minimum thickness of the first sub-target portion is greater than the maximum thickness of the second sub-target portion.

[0016] In one of the embodiments, the buried dielectric layer also includes: a first portion having a thickness greater than or equal to the maximum thickness of the target portion. The semiconductor structure also includes: at least one vertical transistor device. The vertical transistor device is located in the substrate and the epitaxial layer above the first portion, and is located on one side of the drain region of the LDMOS device. The vertical transistor device includes a first electrode doping region and a first electrode doping region lead-out structure. The first electrode doping region is at least partially located in the substrate on the buried dielectric layer, or at least partially located at the bottom of the epitaxial layer. The first electrode doping region lead-out structure includes a conductive structure disposed in a lead-out groove, the bottom of the conductive structure is electrically connected to the first electrode doping region, the first electrode doping region lead-out structure is used to lead the first electrode doping region to the front side of the device, and the inner wall of the lead-out groove is provided with an insulating layer surrounding the conductive structure.

[0017] In one embodiment, the vertical transistor device is a VDMOS device. The first electrode doping region is the drain doping region of the VDMOS and has a first conductivity type. The vertical transistor device further includes: a VDMOS well region, a drift region, a VDMOS source region, and a VDMOS gate. The VDMOS well region has a second conductivity type and is disposed above the drain doping region, and the first conductivity type and the second conductivity type are opposite conductivity types. The drift region has a first conductivity type and is disposed between the drain doping region and the VDMOS well region. The VDMOS source region has a first conductivity type and is disposed in the VDMOS well region. The VDMOS gate is disposed on the drift region.

[0018] In one embodiment, the buried dielectric layer further includes: a second portion having a thickness less than or equal to the minimum thickness of the target portion. The semiconductor structure further includes: at least one lateral transistor device. The lateral transistor device is located in the substrate and the epitaxial layer above the second portion and on the source region side of the LDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the inventions disclosed, the embodiments and / or examples currently described, and the best mode currently understood of these inventions.

[0020] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure in some embodiments of the present disclosure;

[0021] Figure 2 is a flowchart of another method for manufacturing a semiconductor structure in some embodiments of the present disclosure;

[0022] Figure 3a is a cross-sectional schematic view of a structure obtained after forming a mask material layer in some embodiments of the present disclosure;

[0023] Figure 3b is a cross-sectional schematic view of a structure obtained after forming a mask layer in some embodiments of the present disclosure;

[0024] Figure 3c is a cross-sectional schematic view of an inclined surface in some mask layers in some embodiments of the present disclosure;

[0025] Figure 3d is a cross-sectional schematic view of a structure obtained after forming a buried dielectric layer in some embodiments of the present disclosure;

[0026] Figure 3e is a cross-sectional schematic view of a structure obtained after forming an epitaxial layer in some embodiments of the present disclosure;

[0027] Figure 3f is a cross-sectional schematic view of a semiconductor structure in some embodiments of the present disclosure;

[0028] Figure 4 is a cross-sectional schematic view of another semiconductor structure in some embodiments of the present disclosure. Detailed implementation manners

[0029] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention is thorough and complete.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0031] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection", etc. if there is an electrical signal or data transfer between the connected circuits, modules, units, etc. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part.

[0032] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "below them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It will be understood that "at least one" means one or more and "a plurality" means two or more. "At least a portion of an element" means a portion or all of the element. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0034] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes as shown are to be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present invention.

[0035] The semiconductor-related terms used in this article are common technical terms for those skilled in the art. For example, regarding P-type and N-type impurities, to distinguish the doping concentration, simply P+ type represents the P-type with a high doping concentration, P type represents the P-type with a medium doping concentration, P- type represents the P-type with a low doping concentration, N+ type represents the N-type with a high doping concentration, N type represents the N-type with a medium doping concentration, and N- type represents the N-type with a low doping concentration.

[0036] Currently, in an exemplary high-voltage tap changer design process, the top silicon thickness and dielectric layer thickness of the SOI wafer are usually designed to be relatively thick based on the highest voltage tap to ensure that the high-voltage device can have the best parameter design values, and then low-voltage devices are parasitically generated therefrom to form a complete process flow. However, with the high integration of circuits, more and more sub-circuits are designed on a single chip. At this time, the design value indicators of the low-voltage devices parasitically formed on the high-voltage SOI wafer are often difficult to reach the optimum, and there is a situation where the voltage withstand characteristics of the dielectric layer cannot be fully utilized, resulting in a loss of the overall circuit performance. Moreover, the preparation method of the SOI high-voltage device is also mainly based on the thick-layer structure of the SOI wafer, which easily reduces the reliability of the chip significantly due to its severe self-heating effect.

[0037] Based on this, the embodiments of the present disclosure propose a semiconductor structure and a manufacturing method thereof, which can utilize the thickness gradient of the buried dielectric layer to effectively optimize the electric field lines of the semiconductor structure, so as to easily improve the heat dissipation performance of the semiconductor structure while meeting the characteristic requirements of high-voltage devices, thereby effectively improving the device performance and reliability of the semiconductor structure. Moreover, the manufacturing method provided by the embodiments of the present disclosure has a simple process and is easy to implement, which is beneficial to improving the production efficiency and yield.

[0038] Please refer to Figure 1 and Figure 2 In some embodiments of the present disclosure, the manufacturing method of the semiconductor structure includes the following steps S100 to S400.

[0039] S100, as Figure 3a shown, provide a substrate 1, and form a hard mask material layer 20 on the substrate 1.

[0040] Exemplarily, the substrate 1 includes but is not limited to a silicon wafer.

[0041] Exemplarily, the hard mask material layer 20 includes but is not limited to an oxide layer, for example, it can be a silicon oxide layer.

[0042] S200, as Figure 3b shown, etch the hard mask material layer 20 so that the thickness of the hard mask material layer 20 has a gradient in the target area M to obtain a hard mask layer 2.

[0043] Exemplarily, the thickness of the hard mask material layer 20 in the target region M has a gradient, which can be manifested as: the upper surface of the hard mask material layer 20 located in the target region M is an inclined surface SA having an angle with the substrate 1.

[0044] Exemplarily, the inclined surface SA includes an inclined plane or an inclined curved surface. The inclined curved surface includes a convex inclined surface or a concave inclined surface. Figure 3c The inclined plane is illustrated in (A), the convex inclined surface is illustrated in (B), and the concave inclined surface is illustrated in (C).

[0045] In one embodiment, please refer to Figure 2 , step S200 may include the following steps S210, S220, and S230.

[0046] S210, please refer to Figure 3a and Figure 3b for understanding. A photoresist layer 3 having an opening pattern K is formed on the hard mask material layer 20.

[0047] S220, please refer to Figure 3a and Figure 3b for understanding. Based on the opening pattern K, the hard mask material layer 20 is wet-etched so that the thickness of the hard mask material layer 20 in the target region M has a gradient. For example, an inclined surface SA is formed in the target region M of the hard mask material layer 20, thereby obtaining the hard mask layer 2.

[0048] S230, remove the photoresist layer 3.

[0049] It can be understood that the area, topography, and the included angle α between the inclined surface SA in the hard mask layer 2 and the substrate 1 can all match the thickness of the buried dielectric layer to be formed, and the relevant process parameters of the wet etching can be set to achieve this. The embodiments of the present disclosure do not expand on this description.

[0050] S300, as Figure 3d shown, based on the hard mask layer 2, ion implantation is performed on the substrate 1 to form a buried dielectric layer 4 in the substrate 1. The thickness D1 of the target portion 41 of the buried dielectric layer 4 facing the target region M has a gradient.

[0051] Here, the hard mask layer 2 is an implantation barrier layer. The thickness D1 of the target portion 41 having a gradient means that the thickness D1 of each longitudinal section of the target portion 41 along the direction perpendicular to the substrate 1 gradually changes along the direction parallel to the substrate 1. For example, it can show an equal increment change or an equal ratio change, etc.

[0052] In one embodiment, the substrate 1 is a silicon wafer. Please continue to refer to Figure 2 , step S300 may include the following steps S310 and S320.

[0053] S310, asFigure 3d As shown, oxygen ions are implanted into the substrate 1 based on the hard mask layer 2.

[0054] Here, the implantation depth of the oxygen ions is related to the ion implantation concentration and the ion implantation energy, and the implantation of the oxygen ions can be achieved by controlling the relevant process parameters.

[0055] S320, please refer to Figure 3d for understanding, the substrate 1 after the oxygen ions are implanted is heat-treated (high-temperature treatment) to form a buried dielectric layer 4.

[0056] Here, the high-temperature treatment can be, for example, an annealing treatment. Moreover, the treatment temperature of the high-temperature treatment can be selected and set according to requirements. The embodiments of the present disclosure do not limit this.

[0057] Exemplarily, the buried dielectric layer 4 is a buried oxide layer, and its material can be silicon oxide, such as silicon dioxide.

[0058] In an embodiment of the present disclosure, the value range of the minimum thickness of the buried dielectric layer 4 is from 1 micron to 8 microns.

[0059] In the embodiments of the present disclosure, heat-treating the substrate 1 after the oxygen ions are implanted can also effectively eliminate the internal defects of the buried dielectric layer 4 and the substrate 1.

[0060] S400, please refer to Figure 3d and Figure 3e for understanding, the hard mask layer 2 is removed.

[0061] Exemplarily, the hard mask layer 2 can be removed by, but not limited to, a wet etching process.

[0062] For the manufacturing method of the above semiconductor structure, by forming a hard mask layer 2 with a thickness gradient in the target area M on the substrate 1, a buried dielectric layer 4 is formed in the substrate 1 based on the hard mask layer 2, and the thickness D1 of the target portion 41 of the buried dielectric layer 4 facing the target area M has a gradient. Thus, the present disclosure can effectively optimize the electric field lines of the semiconductor structure by using the thickness D1 gradient of the buried dielectric layer 4, so as to easily improve the heat dissipation performance of the semiconductor structure while meeting the characteristics requirements of high-voltage devices, thereby effectively improving the device performance and reliability of the semiconductor structure. Moreover, the manufacturing method provided by the present disclosure has a simple process and is easy to implement, which is beneficial to improving the production efficiency and yield.

[0063] It should be added that in one of the embodiments, as Figure 3eAs shown in the figure, the buried dielectric layer 4 in the substrate 1 can divide the substrate 1 into a bottom layer 11 and a top layer 12. In this way, the distance between the upper surface of the buried dielectric layer 4 and the upper surface of the substrate 1, that is, the thickness of the top layer 12 of the substrate 1, can be selected and set according to requirements, so as to fabricate transistor devices with multiple different voltage levels based on the top layer 12 of the substrate 1 above the buried dielectric layer 4.

[0064] In one embodiment, please continue to refer to Figure 2 , the manufacturing method of the semiconductor structure further includes step S500.

[0065] S500, please refer to Figure 3e , an epitaxial layer 5 is formed on the surface of the substrate 1 after removing the hard mask layer 2.

[0066] Exemplarily, as Figure 3e shown in the figure, the upper surface of the buried dielectric layer 4 close to the epitaxial layer 5 is parallel to the upper surface of the substrate 1. The distance D2 between the upper surface of the buried dielectric layer 4 close to the epitaxial layer 5 and the upper surface of the epitaxial layer 5 facing away from the substrate 1 is equal to the target threshold.

[0067] Here, the buried dielectric layer 4 in the substrate 1 can divide the substrate 1 into a bottom layer 11 and a top layer 12. The distance D2 between the upper surface of the buried dielectric layer 4 close to the epitaxial layer 5 and the upper surface of the epitaxial layer 5 facing away from the substrate 1 is the sum of the thicknesses of the top layer 12 of the substrate 1 and the epitaxial layer 5.

[0068] Exemplarily, the materials of the epitaxial layer 5 and the substrate 1 are the same. Moreover, the epitaxial layer 5 and the top layer 12 of the substrate 1 can have the same conductivity type. The doping types of the epitaxial layer 5 and the bottom layer 11 of the substrate 1 can be the same or different.

[0069] In one example, the bottom layer 11 of the substrate 1 is a P-type silicon layer, and the epitaxial layer 5 and the top layer 12 of the substrate 1 are both N-type silicon layers. Alternatively, the bottom layer 11 of the substrate 1 is an N-type silicon layer, and the epitaxial layer 5 and the top layer 12 of the substrate 1 are both P-type silicon layers.

[0070] In one embodiment, please continue to refer to Figure 2 , the manufacturing method of the semiconductor structure further includes step S600.

[0071] S600, as Figure 3f shown in the figure, based on the substrate 1 above the buried dielectric layer 4 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5, a plurality of transistor devices T are formed. Among them, at least one transistor device T includes a drain region 61 and a source region 62 spaced apart in a direction parallel to the substrate 1; the target portion 41 includes a first sub-target portion 411 facing the drain region 61 and a second sub-target portion 412 facing the source region 62, and the minimum thickness of the first sub-target portion 411 is greater than the maximum thickness of the second sub-target portion 412.

[0072] Exemplarily, please refer to Figure 3f Understand that the drain region 61 and the source region 62 are arranged at intervals along a direction parallel to the substrate 1. In the embodiment of the present disclosure, trenches may be formed in the substrate 1 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5 above the buried dielectric layer 4 first, and a shallow trench isolation structure STI is formed in the trenches. The shallow trench isolation structure STI is used to separate the substrate 1 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5 above the buried dielectric layer 4 into a plurality of active regions 60, so that each active region 60 is respectively used to fabricate corresponding transistor devices T. It is allowed for each active region 60 to be ion-doped or not processed.

[0073] Optionally, after forming the shallow trench isolation structure STI, the drain region 61 and the source region 62 of the transistor device T can be respectively obtained by selectively performing ion doping on the active region 60.

[0074] It can be understood that the internal structures of transistor devices T with different voltage levels may be different. Thus, to match the internal structures of different transistor devices T, the manufacturing processes of each transistor device T may have other different implementations other than the above-mentioned manufacturing process, and the embodiment of the present disclosure does not specifically limit the manufacturing processes of each transistor device T.

[0075] As described above, the manufacturing method provided by the embodiment of the present disclosure can easily match the requirements to control the formation thickness of the epitaxial layer 5, so as to control the total thickness of the substrate above the buried dielectric layer 4 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5, thereby being able to ensure the breakdown voltage resistance of the transistor device T based on the total thickness of the substrate above the buried dielectric layer 4 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5, so as to effectively extend the applicable range of the transistor devices T with high and low voltage levels.

[0076] Moreover, in the embodiment of the present disclosure, the drain region 61 of at least one transistor device T is formed above the first sub-target portion 411 in the target portion 41 of the buried dielectric layer 4, and the source region 62 of the transistor device T is formed above the second sub-target portion 412 in the target portion 41 of the buried dielectric layer 4. This can not only effectively bear the longitudinal breakdown voltage of the transistor device T based on the larger thickness of the first sub-target portion 411, so as to effectively improve the breakdown voltage resistance of the transistor device T, but also effectively slow down the self-heating effect of the transistor device T based on the smaller thickness of the second sub-target portion 412.

[0077] It is worth mentioning that in some embodiments, please refer to Figure 4, among the multiple transistor devices prepared in step S600, there is at least one LDMOS device. The LDMOS device is located above the target portion 41 of the buried dielectric layer 4 and includes a drain region 61 and a source region 62 that are spaced apart in a direction parallel to the substrate 1. The target portion 41 includes a first sub-target portion 411 that is directly opposite to the drain region 61 of the LDMOS device and a second sub-target portion 412 that is directly opposite to the source region 62 of the LDMOS device; wherein, the minimum thickness of the first sub-target portion 411 is greater than the maximum thickness of the second sub-target portion 412.

[0078] Please continue to refer to Figure 4 , exemplarily, the LDMOS device further includes a gate structure 63. The gate structure 63 can be formed above the epitaxial layer 5. The orthographic projection of the gate structure 63 on the substrate 1 can be located within the interval between the drain region 61 and the source region 62, or it can not only be located within the interval between the drain region 61 and the source region 62, but also partially overlap with at least one of the drain region 61 and the source region 62.

[0079] Please continue to refer to Figure 4 , exemplarily, in the LDMOS device, a drift region 64 and a well region 65 are formed in the active region 60, wherein, the drain region 61 can be formed in the drift region 64, and the source region 62 can be formed in the well region 65. And, the conductive types of the drift region 64 and the well region 65 are different, and the conductive types of the drain region 61 and the source region 62 are different from the conductive type of the well region 65.

[0080] In some examples, as Figure 4 shown, in the LDMOS device, the drift region 64, the drain region 61, and the source region 62 are all N-type doped regions, and the well region 65 is a P-type doped region; wherein, the ion doping concentration of the drain region 61 and the source region 62 is greater than the ion doping concentration of the drift region 64.

[0081] Please continue to refer to Figure 4 , exemplarily, the semiconductor structure further includes an interlayer dielectric layer 7 formed above the drain region 61, the source region 62, and the gate structure 63 of the LDMOS device. The interlayer dielectric layer 7 has a plurality of through holes to respectively expose the surfaces of the drain region 61, the source region 62, and the gate structure 63 of the LDMOS device. The semiconductor structure further includes lead electrodes 8 formed in each through hole of the interlayer dielectric layer 7 to respectively realize the lead connection of the drain region 61, the source region 62, and the gate structure 63 of the LDMOS device.

[0082] In some embodiments, please continue to refer to Figure 4, the buried dielectric layer 4 further includes: a first portion R1 having a thickness greater than or equal to the maximum thickness of the target portion 41. The plurality of transistor devices T prepared in step S600 further includes at least one vertical transistor device; the vertical transistor device is located in the substrate 1 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5 above the first portion R1, and is located on one side of the drain region 61 of the LDMOS device.

[0083] Exemplarily, the vertical transistor device includes, but is not limited to, a VDMOS (Vertical Double-diffused MOSFET) device. For example, the vertical transistor device can also be an IGBT (Insulated Gate Bipolar Transistor) device or an SGT (Shielded Gate Trench) device, etc.

[0084] Exemplarily, as Figure 4 shown, the vertical transistor device includes a first electrode doping region 61' and a first electrode doping region lead-out structure 9. The first electrode doping region 61' is at least partially located in the substrate 1 (i.e., the top layer 12 of the substrate 1) on the buried dielectric layer 4, or at least partially located at the bottom of the epitaxial layer 5. The first electrode doping region lead-out structure 9 includes a conductive structure 91 disposed in a lead-out groove, the bottom of the conductive structure 91 is electrically connected to the first electrode doping region 61', and the first electrode doping region lead-out structure 9 is used to lead out the first electrode doping region 61' to the front of the device, and an insulating layer 92 surrounding the conductive structure 91 is provided on the inner wall of the lead-out groove.

[0085] Exemplarily, as Figure 4 shown, the first electrode doping region 61' is the drain doping region of the VDMOS and has a first conduction type. The vertical transistor device further includes: a VDMOS well region 65', a drift region 64', a VDMOS source region 62', and a VDMOS gate 63'. The VDMOS well region 65' has a second conduction type and is disposed above the drain doping region (i.e., the first electrode doping region 61'), and the first conduction type and the second conduction type are opposite conduction types. The drift region 64' has a first conduction type and is disposed between the drain doping region (i.e., the first electrode doping region 61') and the VDMOS well region 65'. The VDMOS source region 62' has a first conduction type and is disposed in the VDMOS well region 65'. The VDMOS gate 63' is disposed on the drift region 64'.

[0086] Exemplarily, the first conduction type is, for example, N-type, and the second conduction type is, for example, P-type.

[0087] Exemplarily, as Figure 4As shown, the semiconductor structure further includes an interlayer dielectric layer 7 formed above the VDMOS source region 62' and the VDMOS gate 63'. The interlayer dielectric layer 7 also has a plurality of through holes to expose the VDMOS source region 62' and the VDMOS gate 63' respectively. The semiconductor structure further includes lead electrodes 8 formed in each through hole of the interlayer dielectric layer 7 to respectively achieve the lead connection of the VDMOS gate 63' and the VDMOS gate 63'.

[0088] Exemplarily, the first electrode doping region lead-out structure 9 can be obtained by first forming a lead-out groove and then sequentially depositing an insulating layer 92 and filling a conductive structure 91 in the lead-out groove after the interlayer dielectric layer 7 is formed. The key dimension (CD) of the lead-out groove can be in the range of, for example, 0.5 micrometer to 2 micrometers.

[0089] Exemplarily, the insulating layer 92 includes a silicon dioxide layer with a thickness in the range of 0.2 micrometer to 0.8 micrometer.

[0090] Exemplarily, the material of the conductive structure 91 can be metal and / or alloy. In one embodiment of the present disclosure, the conductive structure 91 can be a tungsten plug.

[0091] In some embodiments, please continue to refer to Figure 4 , the buried dielectric layer 4 further includes: a second part R2 with a thickness less than or equal to the minimum thickness of the target part 41. The plurality of transistor devices T prepared in step S600 further includes at least one lateral transistor device. The lateral transistor device is located in the substrate 1 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5 above the second part R2 and on one side of the source region 62 of the LDMOS device.

[0092] In one example, the lateral transistor device includes, but is not limited to, a CMOS (Complementary Metal Oxide Semiconductor) device.

[0093] Exemplarily, as Figure 4 shown, in the CMOS device, the well region 65 can be formed at the top of the active region 60 facing away from the buried dielectric layer 4, and the drain region 61 and the source region 62 are located in the same well region 65 and are spaced apart along the direction parallel to the substrate 1. The CMOS device further includes a gate structure 63 formed above the epitaxial layer 5.

[0094] Exemplarily, as Figure 4As shown in [the figure], the semiconductor structure further includes an interlayer dielectric layer 7 formed above the drain region 61, source region 62, and gate structure 63 of the CMOS device. The interlayer dielectric layer 7 has a plurality of through holes to expose the surfaces of the drain region 61, source region 62, and gate structure 63 of the CMOS device respectively. The semiconductor structure further includes lead electrodes 8 formed in each through hole of the interlayer dielectric layer 7 to respectively achieve the lead connection of the drain region 61, source region 62, and gate structure 63 of the CMOS device.

[0095] Some embodiments of the present disclosure also provide a semiconductor structure, which can be obtained by using the manufacturing method described in any of the above embodiments. The semiconductor structure also has all the technical advantages of the foregoing manufacturing method.

[0096] Please refer to Figure 3e , the semiconductor structure includes: a substrate 1 and a buried dielectric layer 4. The buried dielectric layer 4 is disposed in the substrate 1 and includes a target portion 41 with a gradient thickness. Wherein, the upper surface of the buried dielectric layer 4 is parallel to the surface of the substrate 1. The lower surface of the target portion 41 is an inclined surface.

[0097] Exemplarily, the substrate 1 is a P-type silicon substrate. The buried dielectric layer 4 is a buried oxide layer, and its material can be silicon oxide, such as silicon dioxide. In an embodiment of the present disclosure, the value range of the minimum thickness of the buried dielectric layer 4 can be 1 micron to 8 microns.

[0098] In one of the embodiments, the inclined surface of the target portion 41 includes: an inclined plane or an inclined curved surface. Exemplarily, the inclined curved surface includes a convex inclined surface or a concave inclined surface.

[0099] Exemplarily, the distance between the upper surface of the buried dielectric layer 4 and the upper surface of the substrate 1, that is, the thickness of the top layer 12 of the substrate 1, can be selected and set according to requirements to prepare transistor devices with multiple different voltage levels based on the top layer 12 of the substrate 1 above the buried dielectric layer 4.

[0100] The above semiconductor structure can effectively optimize the electric field lines of the semiconductor structure by using the thickness gradient of the target portion 41 in the buried dielectric layer 4, so as to easily improve the heat dissipation performance of the semiconductor structure while meeting the characteristics requirements of high-voltage devices, thereby effectively improving the device performance and reliability of the semiconductor structure.

[0101] In some embodiments, please refer to Figure 4 , the semiconductor structure further includes an epitaxial layer 5 disposed on the substrate 1. Wherein, the distance D2 between the upper surface of the buried dielectric layer 4 close to the epitaxial layer 5 and the upper surface of the epitaxial layer 5 facing away from the substrate 1 is equal to the target threshold. In this way, the semiconductor structure is also easy to form epitaxial layers with multiple thicknesses according to requirements to effectively extend the applicable range of high- and low-voltage transistor devices.

[0102] In some of the following embodiments, the semiconductor structure further includes an epitaxial layer 5 as an example for illustration. However, it can be understood that in the examples where the epitaxial layer 5 is not provided, it is also possible to fabricate the following transistor devices only based on the top layer 12 of the substrate 1 above the buried dielectric layer 4 using the same or similar processes.

[0103] In one embodiment, please refer to Figure 4 , the semiconductor structure further includes: a shallow trench isolation structure STI. The shallow trench isolation structure STI separates the substrate 1 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5 above the buried dielectric layer 4 into multiple active regions 60, so that each active region 60 can be respectively used to fabricate corresponding transistor devices. It is allowed for each active region 60 to be ion-doped or not processed.

[0104] It can be understood that the internal structures of transistor devices with different voltage levels can be different. The following embodiments of the present disclosure exemplarily list some possible structures of transistor devices, but are not limited thereto.

[0105] In some of these embodiments, please refer to Figure 4 , the semiconductor structure further includes: at least one LDMOS device. The LDMOS device is located in the substrate 1 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5 above the target portion 41, and includes a drain region 61 and a source region 62 that are spaced apart along a direction parallel to the substrate 1. The target portion 41 includes: a first sub-target portion 411 facing the drain region 61 of the LDMOS device, and a second sub-target portion 412 facing the source region 62 of the LDMOS device; the minimum thickness of the first sub-target portion 411 is greater than the maximum thickness of the second sub-target portion 412.

[0106] Please continue to refer to Figure 4 , exemplarily, the LDMOS device further includes a gate structure 63. The gate structure 63 can be formed above the epitaxial layer 5. The orthographic projection of the gate structure 63 on the substrate 1 can be located within the interval between the drain region 61 and the source region 62, or it can not only be located within the interval between the drain region 61 and the source region 62, but also partially overlap with at least one of the drain region 61 and the source region 62.

[0107] Please continue to refer to Figure 4 , exemplarily, in the LDMOS device, a drift region 64 and a well region 65 are formed in the active region 60, where the drain region 61 can be formed in the drift region 64, and the source region 62 can be formed in the well region 65. Moreover, the conductivity types of the drift region 64 and the well region 65 are different, and the conductivity types of the drain region 61 and the source region 62 are different from the conductivity type of the well region 65.

[0108] In some examples, such as Figure 4As shown in [Figure 0], in the LDMOS device, the drift region 64, the drain region 61, and the source region 62 are all N-type doped regions, and the well region 65 is a P-type doped region; among them, the ion doping concentration of the drain region 61 and the source region 62 is greater than that of the drift region 64.

[0109] Please continue to refer to Figure 4 , for example, the semiconductor structure further includes an interlayer dielectric layer 7 formed above the drain region 61, the source region 62, and the gate structure 63 of the LDMOS device. The interlayer dielectric layer 7 has a plurality of through holes to expose the surfaces of the drain region 61, the source region 62, and the gate structure 63 of the LDMOS device respectively. The semiconductor structure further includes lead-out electrodes 8 formed in each through hole of the interlayer dielectric layer 7 to respectively realize the lead-out connection of the drain region 61, the source region 62, and the gate structure 63 of the LDMOS device.

[0110] In some of the embodiments, please continue to refer to Figure 4 , the buried dielectric layer 4 further includes: a first part R1 whose thickness is greater than or equal to the maximum thickness of the target part 41. The semiconductor structure further includes: at least one vertical transistor device; the vertical transistor device is located in the substrate 1 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5 above the first part R1, and is located on one side of the drain region 61 of the LDMOS device.

[0111] For example, the vertical transistor device includes, but is not limited to, a VDMOS device. For example, the vertical transistor device can also be an IGBT (Insulated Gate Bipolar Transistor) device or an SGT (Shielded Gate Trench) device, etc.

[0112] For example, as Figure 4 shown in [Figure 18], the vertical transistor device includes a first electrode doped region 61' and a first electrode doped region lead-out structure 9. The first electrode doped region 61' is at least partially located in the substrate 1 (i.e., the top layer 12 of the substrate 1) on the buried dielectric layer 4, or at least partially located at the bottom of the epitaxial layer 5. The first electrode doped region lead-out structure 9 includes a conductive structure 91 disposed in an extraction groove, the bottom of the conductive structure 91 is electrically connected to the first electrode doped region 61', and the first electrode doped region lead-out structure 9 is used to lead out the first electrode doped region 61' to the front of the device, and an insulating layer 92 surrounding the conductive structure 91 is provided on the inner wall of the extraction groove.

[0113] For example, as Figure 4As shown, the first electrode doping region 61' is the drain doping region of the VDMOS and has a first conductivity type. The vertical transistor device further includes: a VDMOS well region 65', a drift region 64', a VDMOS source region 62', and a VDMOS gate 63'. The VDMOS well region 65' has a second conductivity type and is disposed above the drain doping region (i.e., the first electrode doping region 61'), and the first conductivity type and the second conductivity type are opposite conductivity types. The drift region 64' has a first conductivity type and is disposed between the drain doping region (i.e., the first electrode doping region 61') and the VDMOS well region 65'. The VDMOS source region 62' has a first conductivity type and is disposed in the VDMOS well region 65'. The VDMOS gate 63' is disposed on the drift region 64'.

[0114] Exemplarily, the first conductivity type is, for example, N-type, and the second conductivity type is, for example, P-type.

[0115] Exemplarily, as Figure 4 shown, the semiconductor structure further includes an interlayer dielectric layer 7 formed above the VDMOS source region 62' and the VDMOS gate 63'. The interlayer dielectric layer 7 also has a plurality of through holes to respectively expose the VDMOS source region 62' and the VDMOS gate 63'. The semiconductor structure further includes lead electrodes 8 formed in each through hole of the interlayer dielectric layer 7 to respectively realize the lead connection of the VDMOS gate 63' and the VDMOS gate 63'.

[0116] In some embodiments, the conductive structure 91 in the first electrode doping region lead-out structure 9 can also be used as a field plate of the VDMOS device, which plays a role in reducing the surface electric field (RESURF), thereby increasing the breakdown voltage of the vertical device.

[0117] Exemplarily, the cross-sectional shape of the conductive structure 91 in the direction parallel to the substrate 1 includes, but is not limited to, a circular shape, an elliptical shape, a rectangular shape, etc.

[0118] In some embodiments, please continue to refer to Figure 4 , the buried dielectric layer 4 further includes: a second part R2 whose thickness is less than or equal to the minimum thickness of the target part 41. The semiconductor structure further includes: at least one lateral transistor device. The lateral transistor device is located in the substrate 1 (i.e., the top layer 12 of the substrate 1) and the epitaxial layer 5 above the second part R2, and is located on one side of the source region 62 of the LDMOS device.

[0119] Exemplarily, the lateral transistor device includes, but is not limited to, a CMOS device.

[0120] Exemplarily, as Figure 4As shown in the figure, in a CMOS device, a well region 65 may be formed at the top of the active region 60 away from the buried dielectric layer 4. The drain region 61 and the source region 62 are located within the same well region 65 and are spaced apart in a direction parallel to the substrate 1. The CMOS device further includes a gate structure 63 formed above the epitaxial layer 5.

[0121] Exemplarily, as Figure 4 shown in the figure, an interlayer dielectric layer 7 is also located above the drain region 61, the source region 62, and the gate structure 63 of the CMOS device. Each through hole of the interlayer dielectric layer 7 also exposes the surfaces of the drain region 61, the source region 62, and the gate structure 63 of the CMOS device respectively. The lead electrodes 8 located in the through holes of the interlayer dielectric layer 7 can also respectively achieve the lead connection of the drain region 61, the source region 62, and the gate structure 63 of the CMOS device.

[0122] As described above, the CMOS device is a low-voltage device, while the VDMOS device and the LDMOS device are high-voltage devices. Embodiments of the present disclosure can integrate multiple transistors with different voltage levels, such as VDMOS devices, LDMOS devices, and CMOS devices, on the same substrate 1 based on SOI technology, so as to effectively achieve high-density integration and miniaturization of the transistors on the basis of meeting the breakdown voltage requirements and heat dissipation performance of each transistor. Moreover, by increasing the thickness of the buried dielectric layer 4 below the drain region 61 of the LDMOS device and decreasing the thickness of the buried dielectric layer 4 below the source region 62 of the LDMOS device, embodiments of the present disclosure can simultaneously take into account the requirements of the LDMOS device for breakdown voltage characteristics and heat dissipation performance.

[0123] It should be understood that although the steps in the flowcharts of the present disclosure are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0124] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0125] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as falling within the scope described in this specification.

[0126] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, Comprising: Providing a substrate, and forming a hard mask material layer on the substrate; Etching the hard mask material layer to make the thickness of the hard mask material layer have a gradient in a target region, thereby obtaining a hard mask layer; Based on the hard mask layer, performing ion implantation on the substrate to form a buried dielectric layer in the substrate; the thickness of the target portion of the buried dielectric layer facing the target region has a gradient; Removing the hard mask layer.

2. The manufacturing method of the semiconductor structure according to claim 1, wherein The etching the hard mask material layer to make the thickness of the hard mask material layer have a gradient in the target region, thereby obtaining the hard mask layer, includes: Forming a photoresist layer with an opening pattern on the hard mask material layer; Based on the opening pattern, performing wet etching on the hard mask material layer to make the thickness of the hard mask material layer have a gradient in the target region, thereby obtaining the hard mask layer; Removing the photoresist layer.

3. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The substrate is a silicon wafer; the performing ion implantation on the substrate based on the hard mask layer to form a buried dielectric layer in the substrate includes: Performing oxygen ion implantation on the substrate based on the hard mask layer; Performing a high-temperature treatment on the substrate after the oxygen ion implantation to form the buried dielectric layer.

4. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, Further comprising: Forming an epitaxial layer on the surface of the substrate after removing the hard mask layer; Wherein, the surface of the buried dielectric layer close to the epitaxial layer is parallel to the surface of the substrate; The distance between the surface of the buried dielectric layer close to the epitaxial layer and the surface of the epitaxial layer facing away from the substrate is equal to a target threshold.

5. The manufacturing method of the semiconductor structure according to claim 4, characterized in that, Further comprising: Based on the substrate and the epitaxial layer above the buried dielectric layer, forming a plurality of transistor devices; Wherein, at least one of the transistor devices includes a drain region and a source region spaced apart along a direction parallel to the substrate; the target portion includes a first sub-target portion facing the drain region and a second sub-target portion facing the source region; the minimum thickness of the first sub-target portion is greater than the maximum thickness of the second sub-target portion.

6. A semiconductor structure, characterized in that, Comprising: A substrate; A buried dielectric layer disposed in the substrate, including a target portion with a gradient in thickness; Wherein, the upper surface of the buried dielectric layer is parallel to the surface of the substrate; the lower surface of the target portion is an inclined surface.

7. The semiconductor structure according to claim 6, wherein, Further comprising: An epitaxial layer disposed on the substrate; wherein, the distance between the upper surface of the buried dielectric layer close to the epitaxial layer and the upper surface of the epitaxial layer facing away from the substrate is equal to a target threshold.

8. The semiconductor structure according to claim 7, wherein Further comprising: At least one LDMOS device; wherein, The LDMOS device is located in the substrate and the epitaxial layer above the target portion, and includes a drain region and a source region spaced apart along a direction parallel to the substrate; The target portion includes: a first sub-target portion facing the drain region of the LDMOS device and a second sub-target portion facing the source region of the LDMOS device; the minimum thickness of the first sub-target portion is greater than the maximum thickness of the second sub-target portion.

9. The semiconductor structure according to claim 8, wherein The buried dielectric layer further includes: a first portion with a thickness greater than or equal to the maximum thickness of the target portion; The semiconductor structure further includes: at least one vertical transistor device; the vertical transistor device is located in the substrate and the epitaxial layer above the first portion, and on the drain region side of the LDMOS device; the vertical transistor device includes a first electrode doping region and a first electrode doping region lead-out structure, the first electrode doping region is at least partially located in the substrate on the buried dielectric layer, or at least partially located at the bottom of the epitaxial layer; the first electrode doping region lead-out structure includes a conductive structure disposed in a lead-out groove, the bottom of the conductive structure is electrically connected to the first electrode doping region, and the first electrode doping region lead-out structure is used to lead out the first electrode doping region to the front of the device, and an insulating layer surrounding the conductive structure is provided on the inner wall of the lead-out groove.

10. The semiconductor structure according to claim 9, wherein The vertical transistor device is a VDMOS device, the first electrode doping region is the drain doping region of the VDMOS and has a first conductivity type, and the vertical transistor device further includes: a VDMOS well region having a second conductivity type, disposed above the drain doping region, and the first conductivity type and the second conductivity type are opposite conductivity types; a drift region having a first conductivity type, disposed between the drain doping region and the VDMOS well region; a VDMOS source region having a first conductivity type, disposed in the VDMOS well region; a VDMOS gate, disposed on the drift region.

11. The semiconductor structure according to claim 9, wherein The buried dielectric layer further includes: a second portion having a thickness less than or equal to the minimum thickness of the target portion; The semiconductor structure further includes: at least one lateral transistor device; the lateral transistor device is located in the substrate and the epitaxial layer above the second portion, and on the source region side of the LDMOS device.

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