A shallow trench isolation structure and its preparation method and semiconductor device

Abstract

The present application discloses a shallow trench isolation structure, a preparation method thereof, and a semiconductor device, and relates to the field of semiconductor technology. The preparation method comprises: providing a semiconductor substrate, wherein the semiconductor substrate comprises a device-dense area and a device-sparse area, forming a sacrificial layer on the semiconductor substrate, and modifying the sacrificial layer in the device-sparse area, etching the sacrificial layer and the semiconductor substrate at the bottom thereof to form a groove, and leaving at least the modified sacrificial layer around the groove so that the remaining sacrificial layer forms a pad layer, forming an isolation layer on the semiconductor substrate, so that the isolation layer fills the groove and covers the pad layer around the groove, and grinding the isolation layer and the pad layer so that the groove forms a shallow trench isolation structure with a flat surface, thereby eliminating depressions on the surface of the shallow trench isolation structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a shallow trench isolation structure, a preparation method thereof, and a semiconductor device. Background Art

[0002] Current semiconductor manufacturing processes primarily use shallow trench isolation (STI) to isolate different active devices. To create STI, the semiconductor substrate is typically etched to form a trench, followed by an isolation layer formed within the trench and chemical mechanical polishing. However, STI structures often experience depressions in areas with sparsely populated devices, impacting semiconductor device performance. Summary of the Invention

[0003] The present application discloses a shallow trench isolation structure, a preparation method thereof, and a semiconductor device, so as to solve the problem that the shallow trench isolation structure in a sparse area of ​​the device has a depression.

[0004] In the first aspect, the present application discloses a method for preparing a shallow trench isolation structure, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a device-dense area and a device-sparse area; forming a sacrificial layer on the semiconductor substrate, and modifying the sacrificial layer in the device-sparse area; etching the sacrificial layer and the semiconductor substrate at the bottom thereof to form a groove, and leaving at least the modified sacrificial layer around the groove so that the remaining sacrificial layer forms a pad layer; forming an isolation layer on the semiconductor substrate, so that the isolation layer fills the groove and covers the pad layer around the groove; grinding the isolation layer and the pad layer so that the groove forms a shallow trench isolation structure with a flat surface.

[0005] In some embodiments of the present application, the pad layer only includes the modified sacrificial layer remaining around the groove.

[0006] In some embodiments of the present application, the pad layer includes an unmodified sacrificial layer remaining around the groove and a modified sacrificial layer remaining; wherein the thickness of the remaining unmodified sacrificial layer is less than the thickness of the remaining modified sacrificial layer.

[0007] In some embodiments of the present application, the thickness of the sacrificial layer is greater than a preset thickness, so that after the groove is formed, at least the modified sacrificial layer remains around the groove.

[0008] In some embodiments of the present application, the preset thickness ranges from 100 angstroms to 1000 angstroms.

[0009] In some embodiments of the present application, after forming an isolation layer on the semiconductor substrate, the height of the isolation layer in the device sparse area away from the surface of one side of the semiconductor substrate is greater than the height of the isolation layer in the device dense area away from the surface of one side of the semiconductor substrate.

[0010] In some embodiments of the present application, before the step of forming a sacrificial layer on the semiconductor substrate, it also includes: forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate, so that the pad nitride layer serves as the isolation layer and the grinding stop layer of the pad layer.

[0011] In some embodiments of the present application, the step of modifying the sacrificial layer in the sparse area of ​​the device includes: doping the sacrificial layer in the sparse area of ​​the device; the sacrificial layer includes a silicon oxide layer; the doping ions of the sacrificial layer include boron ions or phosphorus ions.

[0012] In a second aspect, the present application discloses a shallow trench isolation structure, which is prepared by using any of the above methods for preparing a shallow trench isolation structure.

[0013] In a third aspect, the present application discloses a semiconductor device comprising the shallow trench isolation structure as described above.

[0014] The present application discloses a shallow trench isolation structure, a method for preparing the same, and a semiconductor device, comprising: providing a semiconductor substrate comprising a device-dense region and a device-sparse region; forming a sacrificial layer on the semiconductor substrate; modifying the sacrificial layer in the device-sparse region; etching the sacrificial layer and the semiconductor substrate below it to form a trench, leaving at least the modified sacrificial layer around the trench so that the remaining sacrificial layer forms a cushion layer; forming an isolation layer on the semiconductor substrate so that the isolation layer fills the trench and covers the cushion layer around the trench; and polishing the isolation layer and the cushion layer so that the trench forms a shallow trench isolation structure having a flat surface. The present application has the unexpected technical effect of modifying the sacrificial layer in the device-sparse region so that after etching the sacrificial layer and the semiconductor substrate below it to form a trench, at least the modified sacrificial layer remains around the trench, thereby allowing the remaining sacrificial layer to form a cushion layer that raises the isolation layer in the device-sparse region. Furthermore, after polishing the isolation layer, the surface of the shallow trench isolation structure becomes a flat surface without depressions. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0016] Figure 1This is a schematic cross-sectional structure diagram of a semiconductor substrate having a first trench and a second trench disclosed in an embodiment of the present application.

[0017] Figure 2 This is a schematic cross-sectional structure diagram of a semiconductor substrate having a first trench, a second trench and an isolation layer disclosed in an embodiment of the present application.

[0018] Figure 3 This is a schematic cross-sectional view of a semiconductor substrate having a first shallow trench isolation structure and a second shallow trench isolation structure disclosed in an embodiment of the present application.

[0019] Figure 4 This is a flow chart of a method for preparing a shallow trench isolation structure disclosed in an embodiment of the present application.

[0020] Figure 5 This is a schematic diagram of the cross-sectional structure of a semiconductor substrate disclosed in an embodiment of the present application.

[0021] Figure 6 This is a schematic diagram of the cross-sectional structure of a semiconductor substrate having a pad oxide layer and a pad nitride layer disclosed in an embodiment of the present application.

[0022] Figure 7 This is a schematic diagram of the cross-sectional structure of a semiconductor substrate having a pad oxide layer, a pad nitride layer and a sacrificial layer disclosed in an embodiment of the present application.

[0023] Figure 8 This is a schematic diagram of the cross-sectional structure of a semiconductor substrate having a pad oxide layer, a pad nitride layer, a sacrificial layer and a first photoresist layer disclosed in an embodiment of the present application.

[0024] Figure 9 This is a schematic diagram of the cross-sectional structure of a semiconductor substrate having a pad oxide layer, a pad nitride layer, a sacrificial layer and a hard mask layer disclosed in an embodiment of the present application.

[0025] Figure 10 This is a schematic diagram of the cross-sectional structure of a semiconductor substrate disclosed in an embodiment of the present application, which has a pad oxide layer, a pad nitride layer, a sacrificial layer, a hard mask layer and a second photoresist layer.

[0026] Figure 11 This is a schematic cross-sectional structure diagram of a semiconductor substrate having a pad oxide layer, a pad nitride layer, a sacrificial layer and a patterned hard mask layer disclosed in an embodiment of the present application.

[0027] Figure 12 This is a schematic cross-sectional structure diagram of another semiconductor substrate disclosed in an embodiment of the present application, having a first trench, a second trench and a pad layer.

[0028] Figure 13This is a schematic cross-sectional structure diagram of another semiconductor substrate disclosed in an embodiment of the present application, having a first trench, a second trench, a pad layer and an isolation layer.

[0029] Figure 14 This is a schematic cross-sectional structure diagram of another semiconductor substrate disclosed in an embodiment of the present application, having a first trench, a second trench, a pad layer and an isolation layer.

[0030] Figure 15 This is a schematic cross-sectional view of another semiconductor substrate having a first shallow trench isolation structure and a second shallow trench isolation structure disclosed in an embodiment of the present application.

[0031] Explanation of reference numerals: 10, semiconductor substrate; 101, device-dense area; 102, device-sparse area; 103, first trench; 104, second trench; 11, pad oxide layer; 12, pad nitride layer; 13, sacrificial layer; 14, first photoresist layer; 15, hard mask layer; 16, second photoresist layer; 17, isolation layer. DETAILED DESCRIPTION

[0032] The following will describe the technical solutions in the embodiments of this application in conjunction with the accompanying drawings. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0033] In the process of forming shallow trench isolation structure, such as Figure 1 As shown, the device dense area 101 and the device sparse area 102 of the semiconductor substrate 10 are usually etched to form a narrow first trench 103 and a wide second trench 104, and then Figure 2 As shown, an isolation layer 17 is formed on the semiconductor substrate 10, and then Figure 3 As shown, chemical mechanical polishing is performed on the isolation layer 17 to form a narrower first shallow trench isolation structure in the first trench 103 and a wider second shallow trench isolation structure in the second trench 104 .

[0034] However, the applicant has discovered that during the etching process of the semiconductor substrate 10, the depth D1 of the first trench 103 is often smaller than the depth D2 of the second trench 104, resulting in the height L1 of the isolation layer 17 in the device dense area 101 being greater than the height L2 of the isolation layer 17 in the device sparse area 102. In order to ensure the flatness of the isolation layer 17, the isolation layer 17 in the device sparse area 102 will be over-polished during chemical mechanical polishing, resulting in the second shallow trench isolation structure formed by the second trench 104 having a depression, which affects the performance of the semiconductor device.

[0035] Based on this, the present application discloses a preparation scheme for a shallow trench isolation structure, in which the sacrificial layer in the sparse area of ​​the device is modified so that the modified sacrificial layer can remain around the groove after the groove is etched to form the groove, so that the remaining sacrificial layer can form a pad layer for raising the isolation layer in the sparse area of ​​the device, thereby eliminating the depression on the surface of the shallow trench isolation structure.

[0036] As an optional implementation of the disclosure of this application, the embodiment of this application discloses a method for preparing a shallow trench isolation structure, such as Figure 4 As shown, Figure 4 This is a flow chart of a method for preparing a shallow trench isolation structure disclosed in an embodiment of the present application, the method comprising:

[0037] S101: providing a semiconductor substrate, wherein the semiconductor substrate includes a device-intensive region and a device-sparse region.

[0038] In the embodiment of this application, Figure 5 As shown, the semiconductor substrate 10 includes a device-intensive region 101 and a device-sparse region 102. The density of devices to be formed in the device-intensive region 101 is greater than that in the device-sparse region 102. The devices to be formed may be PMOS transistors and / or NMOS transistors, etc. The material of the semiconductor substrate 10 may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or InGaAs, etc. Furthermore, the semiconductor substrate 10 may be a single-layer structure formed of the above materials, or a multi-layer structure formed of the above materials.

[0039] S102: forming a sacrificial layer on the semiconductor substrate, and performing a modification process on the sacrificial layer in the device sparse area.

[0040] In some embodiments of the present application, after providing the semiconductor substrate 10, as shown in FIG. Figure 6 As shown, a pad oxide layer 11 and a pad nitride layer 12 may be formed on the semiconductor substrate 10 first, and then a sacrificial layer may be formed on the semiconductor substrate 10. Of course, the present application is not limited thereto, and in other embodiments, a sacrificial layer may also be formed directly on the semiconductor substrate 10, which will not be described in detail here.

[0041] The pad oxide layer 11 can serve as a protective layer for the semiconductor substrate 10 and can be made of silicon dioxide, etc. The pad nitride layer 12 can serve as a grinding stop layer for the subsequently formed isolation layer and can be made of silicon nitride, oxynitride, or metal nitride, etc.

[0042] In some embodiments of the present application, Figure 7As shown, a sacrificial layer 13 can be formed on the semiconductor substrate 10. The material of the sacrificial layer 13 includes silicon oxide, silicon nitride or silicon oxynitride, etc., and then as shown in FIG. Figure 8 As shown, the sacrificial layer 13 in the device sparse region 102 is doped to modify the sacrificial layer 13 in the device sparse region 102. The sacrificial layer 13 in the device sparse region 102 is a modified sacrificial layer 13, while the sacrificial layer 13 in the device dense region 101 is an unmodified sacrificial layer 13. Furthermore, the etching rate of the modified sacrificial layer 13 is lower than that of the unmodified sacrificial layer 13.

[0043] In some embodiments of the present application, Figure 8 As shown, a first photoresist layer 14 can be formed on the sacrificial layer 13 to expose only the sacrificial layer 13 in the device sparse region 102. Then, using the first photoresist layer 14 as a mask, ion implantation is performed on the sacrificial layer 13 in the device sparse region 102 to dope the sacrificial layer 13 in the device sparse region 102. The doped ions can include boron ions or phosphorus ions.

[0044] Of course, the present application is not limited to this. In other embodiments, a film layer containing ions to be doped, such as boron ions or phosphorus ions, may be formed on the sacrificial layer 13 in the device sparse region 102, so that the ions to be doped diffuse into the sacrificial layer 13 in the device sparse region 102, thereby doping the sacrificial layer 13 in the device sparse region 102. The concentration of the doped boron ions or phosphorus ions can be set according to actual needs and will not be further described here.

[0045] S103: etching the sacrificial layer and the semiconductor substrate at the bottom thereof to form a groove, and leaving at least the modified sacrificial layer around the groove, so that the remaining sacrificial layer forms a pad layer.

[0046] In some embodiments of the present application, Figure 9 As shown, a hard mask layer 15 may be formed on the sacrificial layer 13, and then as shown in FIG. Figure 10 As shown, a patterned second photoresist layer 16 is formed on the hard mask layer 15, and then as shown in FIG. Figure 11 As shown, the hard mask layer 15 is etched with the patterned second photoresist layer 16 as a mask to form a patterned hard mask layer 15, and then Figure 12 As shown, the hard mask layer 15 is used as a mask to etch the sacrificial layer 13 and the semiconductor substrate 10 at the bottom thereof to form a trench, and at least the modified sacrificial layer 13 remains around the trench, so that the remaining sacrificial layer 13 forms a pad layer.

[0047] The trenches include a first trench 103 and a second trench 104 , and a width W1 of the first trench 103 is smaller than a width W2 of the second trench 104 . A depth D1 of the first trench 103 is equal to or approximately equal to a depth D2 of the second trench 104 .

[0048] In some embodiments of the present application, the hard mask layer 15 may include a multi-layer structure, for example, a first hard mask layer 151 and a second hard mask layer 152, or a single-layer structure. The first hard mask layer 151 may be a silicon oxide layer, for example, and the second hard mask layer 152 may be a silicon nitride layer, for example.

[0049] S104: forming an isolation layer on the semiconductor substrate, so that the isolation layer fills the trench and covers the pad layer around the trench.

[0050] In the embodiment of the present application, after the first trench 103 and the second trench 104 are formed, Figure 13 As shown, an isolation layer 17 can be formed on the semiconductor substrate 10, so that the isolation layer 17 fills the first trench 103 and the second trench 104 and covers the semiconductor substrate 10 around the first trench 103 and the pad layer around the second trench 104, such as the remaining modified sacrificial layer 13. The material of the isolation layer 17 includes silicon oxide, etc. Of course, in other embodiments, such as Figure 14 As shown, the isolation layer 17 may also cover the pad layer around the first trench 103 , such as the remaining unmodified sacrificial layer 13 , and the pad layer around the second trench 104 , such as the remaining modified sacrificial layer 13 .

[0051] The padding layer around the second trench 104 can raise the isolation layer 17 in the device-sparse region 102, so that the height difference between the raised isolation layer 17 in the device-sparse region 102 and the height of the isolation layer 17 in the device-dense region 101 is relatively small. In some embodiments, after the isolation layer 17 is formed on the semiconductor substrate 10, the height of the isolation layer 17 in the device-sparse region 102 facing away from the surface of the semiconductor substrate 10 is greater than the height of the isolation layer 17 in the device-dense region 101 facing away from the surface of the semiconductor substrate 10.

[0052] S105: grinding the isolation layer and the pad layer to form a shallow trench isolation structure with a flat surface in the trench.

[0053] In the embodiment of this application, Figure 15 As shown, the isolation layer 17 and the pad layer such as the remaining modified sacrificial layer 13 are chemically mechanically polished to form a first shallow trench isolation structure with a flat surface in the first trench 103 and a second shallow trench isolation structure with a flat surface in the second trench 104.

[0054] In an embodiment of the present application, by modifying the sacrificial layer 13 in the device sparse area 102, the etching rate of the modified sacrificial layer 13 can be made lower than the etching rate of the unmodified sacrificial layer 13, so that after the sacrificial layer 13 and the semiconductor substrate 10 at the bottom thereof are etched to form a groove, at least the modified sacrificial layer 13 can remain around the groove, and the remaining sacrificial layer 13 can form a pad for the isolation layer 17 that raises the device sparse area 102, and after the isolation layer 17 is ground, the surface of the shallow trench isolation structure can be a flat surface without depressions.

[0055] In some embodiments of the present application, Figure 13 As shown, the pad layer only includes the modified sacrificial layer 13 remaining around the groove. Of course, the present application is not limited to this. In other embodiments, such as Figure 14 As shown, the pad layer includes the remaining unmodified sacrificial layer 13 around the groove and the remaining modified sacrificial layer 13 ; wherein the thickness of the remaining unmodified sacrificial layer 13 is less than the thickness of the remaining modified sacrificial layer 13 .

[0056] It is understood that because the etching rate of the modified sacrificial layer 13 is lower than that of the unmodified sacrificial layer 13, the thickness of the remaining modified sacrificial layer 13 will be greater than the thickness of the remaining unmodified sacrificial layer 13, or the modified sacrificial layer 13 may remain after the unmodified sacrificial layer 13 is completely etched away. The remaining modified sacrificial layer 13 may be present in the entire area surrounding the trench or in a portion of the area surrounding the trench; similarly, the remaining unmodified sacrificial layer 13 may be present in the entire area surrounding the trench or in a portion of the area surrounding the trench.

[0057] In some embodiments of the present application, the thickness of the sacrificial layer 13 is greater than a preset thickness so that after the groove is formed, at least the modified sacrificial layer 13 remains around the groove. The preset thickness ranges from 100 angstroms to 1000 angstroms. For example, the preset thickness can be 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, or 1000 angstroms. Based on this, while ensuring that the depths of the first trench 103 and the second trench 104 reach the desired depths, at least a portion of the modified sacrificial layer 13 remains.

[0058] As an optional implementation of the content disclosed in the present application, an embodiment of the present application discloses a shallow trench isolation structure, which can be prepared by using the preparation method of the shallow trench isolation structure disclosed in any of the above embodiments.

[0059] As an optional implementation of the disclosure of this application, an embodiment of this application discloses a semiconductor device, which includes the shallow trench isolation structure disclosed in the above embodiment. The semiconductor device includes a PMOS transistor and / or an NMOS transistor, etc.

[0060] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] The above embodiments merely represent several implementation methods of this specification. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of this specification, and these modifications and improvements fall within the scope of protection of this specification. Therefore, the scope of protection of the patent in this specification shall be based on the appended claims.

Claims

1. A method for preparing a shallow trench isolation structure, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate includes a device-intensive region and a device-sparse region; forming a sacrificial layer on the semiconductor substrate, and performing a modification process on the sacrificial layer in the sparsely populated area of ​​the device; Etching the sacrificial layer and the semiconductor substrate at the bottom thereof to form a groove, and leaving at least the modified sacrificial layer around the groove, so that the remaining sacrificial layer forms a pad layer; forming an isolation layer on the semiconductor substrate, so that the isolation layer fills the trench and covers the pad layer around the trench; Grinding the isolation layer and the pad layer to form a shallow trench isolation structure with a flat surface in the trench; The pad layer only includes the modified sacrificial layer remaining around the groove; or, the pad layer includes the unmodified sacrificial layer remaining around the groove and the remaining modified sacrificial layer, and the thickness of the remaining unmodified sacrificial layer is less than the thickness of the remaining modified sacrificial layer.

2. The method for preparing a shallow trench isolation structure according to claim 1, wherein: The thickness of the sacrificial layer is greater than a preset thickness, so that after the groove is formed, at least the modified sacrificial layer remains around the groove.

3. The method for preparing a shallow trench isolation structure according to claim 2, wherein: The preset thickness ranges from 100 angstroms to 1000 angstroms.

4. The method for preparing a shallow trench isolation structure according to claim 1, wherein: After forming an isolation layer on the semiconductor substrate, the height of the isolation layer in the device sparse area away from the surface of the semiconductor substrate is greater than the height of the isolation layer in the device dense area away from the surface of the semiconductor substrate.

5. The method for preparing a shallow trench isolation structure according to claim 1, wherein: Before the step of forming a sacrificial layer on the semiconductor substrate, the method further includes: A pad oxide layer and a pad nitride layer are sequentially formed on the semiconductor substrate, so that the pad nitride layer serves as the isolation layer and the grinding stop layer of the pad layer.

6. The method for preparing a shallow trench isolation structure according to claim 1, wherein: The step of modifying the sacrificial layer in the sparse area of ​​the device comprises: The sacrificial layer in the sparse area of ​​the device is doped; the sacrificial layer comprises a silicon oxide layer; and the doping ions of the sacrificial layer comprise boron ions or phosphorus ions.

7. A shallow trench isolation structure, characterized in that: The shallow trench isolation structure is prepared by the method for preparing a shallow trench isolation structure according to any one of claims 1 to 6.

8. A semiconductor device, characterized in that: Including the shallow trench isolation structure according to claim 7.

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