Hybrid ball / bump and wire bond semiconductor device package

Abstract

The invention relates to a hybrid ball / bump and wire bond semiconductor device package. A packaged semiconductor device is disclosed, comprising: a semiconductor die having an array of contact pads in a central region of a first major surface of the semiconductor die and for contacting an array of solder balls; an encapsulant partially encapsulating the semiconductor die and having an aperture in a first major surface of the semiconductor die that exposes the array of contact pads; and a plurality of leads extending from a side surface of the encapsulant and extending beyond the first main surface of the encapsulant. A corresponding method is also disclosed.

Description

Technical Field

[0001] The present disclosure relates to packaged semiconductor devices having both solder bumps or balls and leads for interconnection, and to associated manufacturing methods. Background Art

[0002] Widely used conventional methods for packaging semiconductor devices involve bonding individual contact pads from an integrated circuit wire to individual leads of a lead frame. Although effective and versatile, the technique is time-consuming and thus expensive because individual wire bonds generally must be produced one by one. Many advanced packaging technologies have been developed and introduced to address this issue, for example, using so-called flip-chip packaging, which has a die having bumps on its active surface; the die is flipped and connected to a substrate using, for example, solder balls. Other techniques include wafer-level packaging, where die-sized packages consisting of a die with signal paths redistributed to more widely spaced solder bumps can then be directly mounted onto a printed circuit board. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a packaged semiconductor device, comprising: a semiconductor die having an array of contact pads in a central region of a first major surface of the semiconductor die and for contacting an array of solder balls, an array of bumps, or an array of metal-based pillars (such as copper pillars); an encapsulant that partially encapsulates the semiconductor die and has a pore exposing the array of contact pads in the first major surface of the semiconductor die; and a plurality of leads extending from a side surface of the encapsulant and extending beyond the first major surface of the encapsulant. By only partially encapsulating the semiconductor die, a central region of the surface of the semiconductor die can be exposed. By exposing the central region of the first major surface of the semiconductor die, bump bonding or ball grid array bonding or the like can be used to provide electrical connection to the die, while additional connections are provided using wire bonds between other contacts on the die and the plurality of leads.

[0004] In one or more embodiments, the device further comprises an array of solder balls or an array of bumps or an array of metal-based pillars (such as copper pillars).

[0005] In one or more embodiments, the solder balls extend further beyond the first surface of the encapsulant than the end portions of the leads, and the leads have an "L" shape profile. Subsequent connection of the solder balls to a substrate (such as a circuit board) can thus result in mechanical and electrical connection of the solder balls to the circuit board, where the solder balls can be slightly deformed or "squeezed", while allowing the leads to provide additional electrical connection to the circuit board without significant deformation of the leads.

[0006] In one or more embodiments, the lead has a "J" - shaped profile and has a terminal portion that extends beyond the first major surface of the encapsulant and bends back towards the first major surface of the encapsulant below the first major surface of the encapsulant. This can assist in anchoring the lead to the circuit board during subsequent soldering of the lead to the circuit board. It can further provide a degree of tolerance that allows for different thermal expansions during use.

[0007] In one or more embodiments, the encapsulated semiconductor device further includes a substrate that is connected to the semiconductor die through the leads and through solder balls that attach the contact pads. The substrate can be a circuit board or a laminate, or made of other suitable materials familiar to those skilled in the art.

[0008] The semiconductor die can further include an additional plurality of contact pads around its periphery. The additional plurality of contact pads can be distributed around four sides of the periphery, or can be localized to fewer than four sides. For example, it can be provided on two opposite sides of the periphery. Its position and number can depend on the requirements for the number of individual electrical contacts needed for the IC or any requirements for localized signal paths into and out of the IC.

[0009] In one or more embodiments, the leads are connected to the additional plurality of contact pads by wire bonds. The form of the wire bonds can be selected to conform to a particular manufacturing technique and application. For example, in applications that require high power, the bonding wires can be selected to be relatively thick and have a relatively wide pitch; in other applications that do not require high power, finer wires can be selected and the wire bonds can be made with a finer pitch, that is, the spacing between them is smaller relative to high - power applications.

[0010] In one or more embodiments, the lead can be part of a lead - frame assembly that further includes a die pad attached to the second major surface of the semiconductor die.

[0011] According to a second aspect of the present disclosure, a method of manufacturing an encapsulated semiconductor die is provided, the method comprising: performing die attachment between the semiconductor die and a lead - frame assembly; wire - bonding the peripheral contact pads on the semiconductor die to the leads of the lead - frame assembly; encapsulating the semiconductor die in an encapsulant and providing pores in a first major surface of the encapsulant that expose an array of contact pads on the semiconductor die; and forming the leads that extend beyond the first major surface of the encapsulant.

[0012] Before the step of forming the leads, the method may further comprise the step of providing on the contact pad array one of the group consisting of solder balls, solder bumps or copper pillars. Further, after the step of encapsulating the semiconductor die in the encapsulant, the method may further comprise the step of providing on the contact pad array one of the group consisting of solder balls, solder bumps or copper pillars.

[0013] These and other aspects of the invention will be made apparent and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The embodiments will be described by way of example only with reference to the drawings, in which:

[0015] Figure 1 A schematic diagram showing a semiconductor die or integrated circuit before encapsulation according to one or more embodiments of the present disclosure;

[0016] Figure 2 A schematic diagram showing a semiconductor die or integrated circuit before encapsulation according to one or more other embodiments of the present disclosure;

[0017] Figure 3 A schematic diagram showing yet another semiconductor die or integrated circuit according to the present disclosure;

[0018] Figure 4 A schematic cross-section showing through an encapsulated semiconductor device 400 according to one or more embodiments of the present disclosure;

[0019] Figure 5 Schematically showing Figure 4 A side view of the encapsulated semiconductor device shown in;

[0020] Figure 6 An encapsulated semiconductor device according to one or more other embodiments of the present disclosure;

[0021] Figure 7 Showing Figure 6 A side view of the encapsulated semiconductor device shown in;

[0022] Figure 8 Showing the mounting of an encapsulated semiconductor device on a substrate according to one or more embodiments;

[0023] Figure 9 Showing the mounting of an encapsulated semiconductor device on a substrate according to one or more other embodiments;

[0024] Figure 10 Showing a cross-section through an assembly comprising an encapsulated semiconductor device mounted on a substrate;

[0025] Figure 11 Shows Figure 10 a schematic side view of an assembly;

[0026] Figure 12 Schematically shows a manufacturing process for encapsulating a semiconductor die according to an embodiment of the present disclosure;

[0027] Figure 13 Shows an alternative manufacturing process for the assembly of encapsulating a semiconductor device according to one or more other embodiments of the present disclosure; and

[0028] Figure 14 Shows yet another alternative variant of the processing flow.

[0029] It should be noted that the figures are illustrative and not drawn to scale. For clarity and convenience in the drawings, the relative dimensions and proportions of the various parts of these figures have been shown as exaggerated or reduced in size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. Detailed Description

[0030] The present disclosure relates to encapsulating semiconductor dies and associated methods of manufacturing encapsulated semiconductor dies, where a combination of wire bonding connections to individual leads of a lead frame and bump bonding, such as a ball grid array, is deployed.

[0031] Figure 1 Shows a schematic view of a semiconductor die or integrated circuit 100 prior to encapsulation according to one or more embodiments of the present disclosure. The die has a plurality of contact pads 110 in a central region 120 of its first major surface, which may also be referred to as its active surface. The contact pads may have solder thereon. The plurality of contact pads 110 may be arranged in an array, as shown. A plurality of bond pads 140 are positioned around a peripheral region 130 of the semiconductor die. The bond pads 140 may be arranged around all four sides of the semiconductor die, or may be arranged on less than four sides, e.g., only at two locations.

[0032] Figure 2 Shows a schematic view of a semiconductor die or integrated circuit 200 prior to encapsulation according to one or more other embodiments of the present disclosure. The die has a plurality of solder balls or bumps 210 in a central region 220 of its first major surface. The plurality of solder balls or bumps 210 may be arranged in an array. Similar to Figure 1For the die shown, a plurality of bonding pads 240 are positioned around the peripheral region 230 of the semiconductor die. The plurality of bonding pads 240 may be arranged around all four sides of the semiconductor die or may be arranged on less than four sides, for example, only on two sides. Those skilled in the art will appreciate that within the scope of the present disclosure, alternative types of bumps may be used in place of solder balls or solder bumps: for example and without limitation, metal pillars may be provided on the surface. Typically, copper is used as the metal or as part of a metal-based alloy, and thus this alternative may be referred to as copper pillars. Such metals or metal-based alloys may be deposited, for example, by plating or printing in paste form via a mask. Figure 3 FIG. shows a schematic diagram of yet another semiconductor die or integrated circuit 300 in accordance with the present disclosure. At this time, the die is similar to Figure 2 the die shown, except that there are no solder balls or bumps 210, and instead, individual contact pads 310 suitable for solder balls or bumps are shown.

[0033] Figure 4 FIG. shows a schematic cross-section through a packaged semiconductor device 400 in accordance with one or more embodiments of the present disclosure. The packaged semiconductor device includes, for example, Figure 1 the semiconductor die 100 shown, having a plurality of contact pads 110. The plurality of contact pads 110 may be arranged in an array as shown and are attached to a plurality of solder balls 410 in the central region of its first major surface, and for contacting the array of solder balls or bumps 410, may be made of materials familiar to those skilled in the art of semiconductor packaging, such as, but not limited to, Sn / Ag alloy or Sn / Ag / Cu alloy. Similarly, the contact pads 110 may be made of any suitable material (e.g., copper, nickel, or aluminum), as will also be familiar to those skilled in the art. The contact pads 110 and the solder balls or bumps 410 are generally arranged above the central region of the die 100.

[0034] The packaged semiconductor device further includes a plurality of leads 420, two of the plurality of leads 420 being shown in Figure 4 FIG. The leads may be part of a lead frame assembly, as shown, the lead frame assembly may include die pads or die pads 430, which are joined, for example using solder (not shown), to the second major surface of the semiconductor die. The individual leads 420 are physically separated and electrically isolated from the die pads 430, for example using conventional packaging processing techniques. The leads 420 are electrically connected to bonding pads 140 arranged around the peripheral region of the die 100 by bonding wires 440, which are wire bonded to the bonding pads 140 and the leads 420 by conventional techniques such as, for example, wedge bonding or ball bonding or a combination thereof. In one or more embodiments, the wire loop profile may be minimized, that is, the height of the wire bond above the surface of the die, in order to facilitate a shallow packaged device.

[0035] The encapsulated semiconductor device further includes an encapsulant 450, typically a molding compound, as would be familiar to those skilled in the art. This encapsulant molding compound (EMC) partially encapsulates the semiconductor die. Specifically, it has pores 460 in its first major surface 470. That is, the encapsulant does not extend over the central region 120 of the semiconductor die 100. The pores 460 expose an array of contact pads 110. The thickness of the encapsulant on the peripheral region of the first major surface is less than the thickness (i.e., diameter) of the solder balls 410. According to one or more embodiments, the leads 420 extend beyond the encapsulant; that is, the leads 420 project beyond the sidewall 455 of the molding compound. The leads are formed to extend beyond the first major surface of the semiconductor die; that is, in the orientation shown in the figure, the leads extend downward. In Figure 4 the embodiment shown, the leads are formed to have a folded-back profile; that is, they have a "J" shape (laterally aligned in the Figure 4 orientation shown). The leads thus have a terminal portion that extends beyond the first major surface 470 of the encapsulant and bends back below the first major surface of the encapsulant. Additionally, the end of the terminal portion can be formed to extend back (as drawn upward) toward the first major surface 470 of the encapsulant. The leads can be formed such that they project beyond the first major surface of the die 100, projecting beyond the first major surface of the die to the same or a lesser extent compared to the solder balls. In other words, in Figure 4 the orientation shown, the bottom 415 of the solder ball can be flush with or lower than the bottom of the lead. Such an arrangement where the lower surface of the solder ball is lower than the bottom or lower surface 425 of the lead, and in particular only lower than the bottom or lower surface 425 of the lead by a small distance (e.g., 50 μm for a typical solder ball), can be beneficial in helping to control the degree of solder ball collapse or solderable damage during subsequent mounting of the encapsulated semiconductor device onto a board.

[0036] Figure 5 is schematically shown Figure 4 a side view of the encapsulated semiconductor device 400 shown in. Specifically, in this embodiment, the lowermost surface of the leads 420 is at the same depth as the bottom of the solder balls 410. The side surface 540 of the molding compound can be vertical as shown, or can include an angled profile, as would be familiar to those skilled in the art. The pores in the encapsulant that are not visible in the side view of the device are shown in dashed outline for enhanced understanding of the embodiment.

[0037] Figure 6Shows a packaged semiconductor device 600 in accordance with one or more other embodiments of the present disclosure. The figure includes a semiconductor die 300 having a plurality of contact pads 310 in a central region of its first major surface, the contact pads being arranged in an array, the pitch of the array being less than Figure 1 the pitch of the array shown therein. The packaged semiconductor device 600 further includes a plurality of leads 620, which may form part of a lead frame assembly together with die pads or die pads 630. The packaged semiconductor device 600 further includes a molding compound or EMC 650 that partially encapsulates the die 300. The molding compound 650 has gaps, holes or pores 660 in its lower major surface 670, the pores exposing the central region of the die 300, and in particular the contact pads 310. The die 300 has a further plurality of contact pads 340 arranged around its periphery. These contact pads are electrically connected to the leads 620 by bonding wires 640. As shown, the bonding wires may be arranged to have low wire loops. The leads 620 are "L"-shaped; that is, they extend outwardly beyond the molding compound 650 and are formed to extend towards and beyond the first major surface of the die and the first major surface 670 of the molding compound. In the orientation shown in the figure, this means that the ends of the leads extend downwardly and beyond the lower surface 670 of the molding compound. Compared with Figure 4 and Figure 5 the embodiments shown therein, the encapsulant may have a thinner mold (that is, its thickness below the die is less than the thickness of the encapsulant 450 below the die in the Figure 4 embodiment shown therein), and thus have a shallower cavity depth or pore depth, thereby exposing the central region of the surface of the die 300. Those skilled in the art will appreciate that this may match the appropriate size of the solder bumps for the final portion of the die attachment ( Figure 6 not shown therein). The "L"-shaped configuration of the formed leads may assist in anchoring the device to the PCB board to which it may subsequently be bonded, and may further assist in controlling solder bump collapse or damage during subsequent mounting of the packaged device onto the board.

[0038] Figure 7 Shows a side view of the packaged semiconductor device 600 as described above with respect to Figure 6 . In each of the end leads 620, the "L"-shaped profile of the lead is visible. The pores that are not visible in the device are depicted in dashed lines to assist in understanding the present disclosure.

[0039] Figure 8 Shows the mounting of a packaged semiconductor device 810 on a substrate 820 in accordance with one or more embodiments. The packaged semiconductor device 810 may be similar to Figure 6 and Figure 7The device 600 shown in [reference], and includes leads 620 and contact pads 310 exposed at pores 660 in the exposed area of the die. The substrate 820 includes contact pads 830 having solder balls or solder bumps 840 thereon, and can thus alternatively be described as a "pre-bumped substrate". It includes additional contact pads 850 for connection to external leads on the same side as the solder balls or solder bumps. The additional contact pads 850 can be pre-soldered, that is, the additional contact pads 850 can have a solder layer thereon. The substrate can include a redistribution layer including conductive traces between solder balls or bumps 840 and lead contact pads 850 on a first surface and additional solder pads 860 on a second surface opposite the first surface. The additional solder pads can be further spaced apart or otherwise arranged for connection to additional components, such as discrete components or wires, etc. During the mounting operation, the packaged semiconductor device 810 is aligned with the substrate 820, and the solder balls or bumps 840 contact the contact pads 310 on the die. Heat treatment is used to soften or melt the solder and achieve electrical and mechanical contact. At the same time, the "L"-profile leads 620 are in electrical contact with the contact pads 850, and the solder therebetween achieves electrical contact and mechanical bonding.

[0040] Figure 9 Shows the mounting of a packaged semiconductor device 910 on a substrate 920 according to one or more embodiments. The packaged semiconductor device 910 is similar to Figure 8 the packaged semiconductor device 810 shown in [reference], except that the semiconductor die already has solder balls or bumps 210 mounted thereon, corresponding to Figure 2 the die shown in [reference]. Correspondingly, the substrate 920 does not have solder balls or bumps on the contact pads 830. Similar to Figure 8 the process shown in [reference], the packaged semiconductor device 910 is aligned with the substrate 920, and the solder balls or bumps contact the contact pads 830.

[0041] Figure 10 Shows a cross-section through an assembly 1000 that includes a packaged semiconductor device 810 mounted on a substrate 820. The substrate has additional solder balls 1010 on its lower or second surface, and the additional solder balls 1010 are on the additional solder pads 860. Figure 11 Shows a schematic side view of the assembly 1000, where pores 1110 in the molding compound and the solder balls or bumps 840 between the semiconductor die and the substrate are shown hashily to assist in understanding the present disclosure.

[0042] Turning to Figure 12 , which schematically shows the manufacturing process of a packaged semiconductor die according to an embodiment of the present disclosure. In the example shown, the semiconductor die 100 corresponds to Figure 1The semiconductor die shown in Figure 12 and includes a plurality of contact pads 110 in the central region 120 of its first major surface. The result of the first stage is shown at (i), i.e., die attachment between the semiconductor die and the lead frame assembly, including electrical isolation of the leads from the die pads. Die attachment can be performed in a conventional manner familiar to those skilled in the art of semiconductor packaging. At (ii), the result of the second stage is shown, i.e., wire bonding of the wire bonding peripheral contact pads or bonding pads 140 on the semiconductor die to the leads 420 of the lead frame assembly by means of bonding wires 440. Again, this can be performed in a conventional manner familiar to those skilled in the art of semiconductor packaging. At (iii), the result of the third stage of encapsulating the semiconductor die in the encapsulant molding compound 450 is shown. This step is a partial encapsulation because the central region of the first major surface is exposed, and thus it provides pores or gaps in the first major surface of the encapsulant, thereby exposing the array of contact pads on the semiconductor die. At (iv), the result of another stage, i.e., solder ball attachment, is shown, where solder balls 410 are again attached to the contact pads 110 using known techniques. At (v), the result of another stage of forming leads 420 to extend beyond the first major surface of the encapsulant is shown. In Figure 12 In the embodiment shown, the leads have a "J" - shaped profile, which is oriented such that the end of the tip returns towards the encapsulant 450.

[0043] Turning now to Figure 13 , this figure shows an alternative manufacturing process for the assembly of a semiconductor device package according to one or more other embodiments of the present disclosure. In this non - limiting example, the semiconductor die 100 includes solder balls or solder bumps 210 pre - attached to the contact pads 110, in which case corresponding to Figure 9 the bumped IC die shown in Figure 12 . The result of die attachment of the semiconductor die 100 to the lead frame assembly including leads 620 is shown at (i). This stage is generally similar to Figure 12 the stage shown in the process flow of Figure 12 , and those skilled in the art will appreciate that modifications may be required due to the presence of the solder balls or bumps 210. Similarly, the wire bonding stage (the result of which is shown in (ii)) is similar to Figure 12 the wire bonding stage shown in Figure 12 , as is the encapsulation in the molding compound, the result of which is depicted in (iii). Since solder balls or bumps are already present on the die, there is no need for the processing stage corresponding to Figure 12 (iv) in the process flow depicted in

[0044] Figure 14Another alternative variant depicting a processing flow is shown. In this case, there are no solder balls or bumps on the semiconductor die 100 that expose the contact pads 110 thereon. At (i), the result of attaching the die to a lead frame assembly is shown, the lead frame assembly including leads 620 and die pads or die pads, similar to Figure 12 , Figure 13 as shown in; at (ii), the result of wire bonding of the bonding wires 440 to connect the peripheral contact pads 140 to the leads 620 is shown; at (iii), the result of partial encapsulation of the die in the molding compound 450 is shown; and at (iv), the result of forming the leads 620 into an "L" - shaped profile that extends beyond the die and the encapsulant in this case is shown.

[0045] Those skilled in the art will appreciate that the processing stages of forming the leads 420 and 620, as shown respectively in Figure 12 and Figure 13 and Figure 14 may include additional processing steps, such as trimming the leads to the appropriate size and removing the support bus bars.

[0046] By reading this disclosure, those skilled in the art will understand other variations and modifications. Such variations and modifications may involve equivalent features and other features known in the field of semiconductor device packaging and that may be used in place of or in addition to the features described herein.

[0047] Although the appended claims are directed to specific combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features or any generalization thereof that is explicitly or implicitly disclosed herein, regardless of whether it relates to the same invention as currently claimed in any claim or whether it alleviates the same technical problems as any or all of the technical problems alleviated by the present invention.

[0048] It should be noted that the above one or more embodiments have been described with reference to different subject matters. Specifically, some embodiments may have been described with reference to method - type claims, while other embodiments may have been described with reference to device - type claims. However, those skilled in the art will understand from the above that, unless otherwise stated, any combination of features related to different subject matters, in particular the combination of features of method - type claims and device - type claims, in addition to any combination of features belonging to one type of subject matter, is also considered to be disclosed with this document.

[0049] Features described in the context of multiple embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features described in the context of a single embodiment may also be provided separately or in any suitable sub - combination.

[0050] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, a single processor or other unit may fulfill the functions of several components recited in the claims [delete if not relevant], and the reference signs in the claims should not be construed as limiting the scope of the claims. In addition, the word "may" is used in a permissive sense (i.e., meaning having the possibility of...) rather than a mandatory sense (i.e., meaning must). Similarly, the words "include", "including" and "includes" mean including but not limited to.

Claims

1. An encapsulated semiconductor device, characterized in that, Comprising: A semiconductor die having a contact pad array in a central region of a first major surface of the semiconductor die for contacting a bump array, a stud array, or a solder ball array; An encapsulant that partially encapsulates the semiconductor die and has a pore exposing the contact pad array in the first major surface of the semiconductor die; And A plurality of leads extending from a side surface of the encapsulant and extending beyond the first major surface of the encapsulant.

2. The packaged semiconductor device according to claim 1, wherein The solder balls extend further beyond the first surface of the encapsulant than the end portions of the leads, and the leads have an "L" shaped profile.

3. The packaged semiconductor device according to claim 1, wherein The leads have a "J" shaped profile and have end portions that extend beyond the first major surface of the encapsulant and bend back toward the first major surface of the encapsulant below the first major surface of the encapsulant.

4. The packaged semiconductor device according to claim 1, wherein Further comprising a substrate connected to the semiconductor die through the leads and by attaching a corresponding one of the bump array, the stud array, or the solder ball array of the contact pads.

5. The packaged semiconductor device according to claim 1, wherein The leads are part of a lead frame assembly that further includes a die pad attached to a second major surface of the semiconductor die.

6. A method of manufacturing an encapsulated semiconductor die, characterized in that, The method includes: Performing die attachment between the semiconductor die and the lead frame assembly; Wire bonding the peripheral contact pad lines on the semiconductor die to the leads of the lead frame assembly; Encapsulating the semiconductor die in an encapsulant and providing a pore in the first major surface of the encapsulant to expose the contact pad array on the semiconductor die; and Forming the leads that extend beyond the first major surface of the encapsulant.

7. The method according to claim 6, wherein Before the step of forming the leads, further comprising the steps of: Providing one of the group consisting of solder balls, solder bumps, or copper pillars on the contact pad array.

8. The method according to claim 6, wherein After the step of encapsulating the semiconductor die in an encapsulant, further comprising the steps of: Providing one of the group consisting of solder balls, solder bumps, or copper pillars on the contact pad array.

9. The method according to claim 6, characterized in that, The step of forming the leads that extend beyond the first major surface of the encapsulant includes: Forming the leads having a "J" shaped profile, wherein the end portions extend beyond the first major surface of the encapsulant and bend back toward the first major surface of the encapsulant below the first major surface of the encapsulant.

10. The method according to claim 6, characterized in that, The step of forming the leads that extend beyond the first major surface of the encapsulant includes: Forming the leads having an "L" shaped profile.

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