Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first surface and a second surface which are opposite to each other; an interconnection via penetrating through the substrate; the first electrode layer is positioned on the surface of the first surface and the side wall surface of the interconnection through hole; the dielectric layer is positioned on the surface of the first electrode layer; the second electrode layer is positioned on the surface of the dielectric layer; the isolation layer is positioned on the surface of the second electrode layer in the interconnection through hole; the conductive layer is located on the surface of the isolation layer in the interconnection through hole, the interconnection through hole is filled with the conductive layer, the second surface exposes the conductive layer, the first electrode layer, the dielectric layer and the second electrode layer, the forming space of the isolation layer in the interconnection through hole is reduced, the forming thickness of the isolation layer in the interconnection through hole is reduced, and the processing efficiency is improved; and on the other hand, after the interconnection through holes penetrate through the substrate, passivation layers are formed on the surfaces of the second surface and the conductive layer, so that the risk of cracking of the conductive layer on the second surface is avoided, and the yield of the semiconductor structure is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the increase in the driving strength of semiconductor devices, the devices have higher current density and larger current transients, resulting in the chip being more sensitive to the fluctuations of the power supply voltage. The circuit needs to reduce the PDN impedance through decoupling capacitors and suppress noise through decoupling or bypass circuits. Therefore, parasitic resistance and inductance must be controlled, and the decoupling capacitors must be close to the circuit. Therefore, in a packaging structure (2.5D Interposer) applying through-silicon vias (TSV) interposer, a relatively large number of capacitor trenches (DTC) and TSVs need to be integrated.

[0003] The TSV-based 2.5D / 3D integration technology has been widely regarded as the leading technology in the field of future high-density packaging and an effective way to break through Moore's Law. Compared with traditional 2D packaging, the 2.5D packaging based on TSV interposer enables multiple chips to be directly interconnected on the interposer, greatly shortening the wiring length, reducing signal delay and loss, and its relative bandwidth can reach 8 - 50 times that of traditional packaging. The silicon-based interposer can fabricate interconnections with smaller line widths, greatly improving the wiring density to meet the requirements of high-performance chips. Both the silicon-based interposer and the chip use silicon as the substrate material, with a smaller mismatch in the coefficient of thermal expansion between them, greatly reducing the thermal stress borne by the chip and improving the reliability. The shorter interconnection lines between the chip and the substrate can improve the system electrical performance. Therefore, the packaging form in which multiple functional chips are interconnected through TSV interposer has attracted more and more attention from major semiconductor companies and research institutions around the world.

[0004] However, the existing formation quality of TSV is poor, which greatly affects the product yield. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, including: a substrate including opposite first and second surfaces; a through-silicon via penetrating the substrate; a first electrode layer located on the surface of the first surface and the sidewall surface of the through-silicon via, a dielectric layer located on the surface of the first electrode layer, and a second electrode layer located on the surface of the dielectric layer; an isolation layer located on the surface of the second electrode layer within the through-silicon via; a conductive layer located on the surface of the isolation layer within the through-silicon via, the conductive layer filling the through-silicon via, and the second surface exposing the conductive layer.

[0007] Optionally, it further includes: a capacitive trench located in the substrate, the capacitive trench being recessed with respect to the first surface, and the depth of the capacitive trench being less than the thickness of the substrate; a first electrode layer, a dielectric layer, and a second electrode layer are further sequentially located on the inner wall surface of the capacitive trench.

[0008] Optionally, the isolation layer is further located on the surface of the second electrode layer in the capacitive trench, and the isolation layer fills the capacitive trench.

[0009] Optionally, the isolation layer is further located on a partial surface of the second electrode layer on the first surface.

[0010] Optionally, it further includes: an interlayer dielectric layer located on the surface of the conductive layer, the surface of the isolation layer, and the exposed partial surfaces of the first electrode layer and the second electrode layer; a plurality of conductive posts located in the interlayer dielectric layer, and the plurality of conductive posts are respectively electrically connected to the first electrode layer, the second electrode layer, and the conductive layer.

[0011] Optionally, it further includes: a redistribution layer located on the surface of the interlayer dielectric layer, the redistribution layer having a conductive structure therein, and the conductive structure is electrically connected to the plurality of conductive posts.

[0012] Optionally, it further includes: a plurality of discrete first bumps located on the surface of the redistribution layer; a carrier wafer located on the surface of the first bumps.

[0013] Optionally, it further includes: a passivation layer located on the second surface and the surface of the conductive layer, the passivation layer having an opening therein, and the opening exposes the surface of the conductive layer; a second bump located in the opening.

[0014] Correspondingly, the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including opposite first and second surfaces; forming mutually discrete capacitive trenches and through-vias in the substrate, both the capacitive trenches and the through-vias being recessed with respect to the first surface, and the depth of the capacitive trenches being less than the depth of the through-vias; forming a first electrode layer, a dielectric layer located on the surface of the first electrode layer, and a second electrode layer located on the surface of the dielectric layer on the surface of the first surface, the inner wall surface of the capacitive trenches, and the inner wall surface of the through-vias; forming an isolation layer on the surface of the second electrode layer in the capacitive trenches and in the through-vias, the isolation layer filling the capacitive trenches, and the isolation layer in the through-vias having a via opening; forming a conductive layer filling the via opening; thinning the substrate, the first electrode layer, the dielectric layer, the second electrode layer, and the isolation layer from the second surface until the conductive layer is exposed.

[0015] Optionally, the method for forming the capacitor trenches and the via holes includes: forming a first mask layer and a second mask layer on the surface of the first side, the height of the first mask layer being higher than that of the second mask layer; forming a pattern layer on the surfaces of the first mask layer and the second mask layer; etching the substrate using the pattern layer as a mask to form discrete capacitor trenches and via holes in the substrate, both the capacitor trenches and the via holes being recessed with respect to the first side, and the depth of the capacitor trenches being less than the depth of the via holes.

[0016] Optionally, the method for forming the isolation layer and the conductive layer includes: forming an initial isolation layer on the surface of the second electrode layer, the initial isolation layer filling the capacitor trenches; forming an initial conductive layer on the surface of the initial isolation layer; planarizing the initial conductive layer until the surface of the initial isolation layer is exposed, and forming a conductive layer within the via opening.

[0017] Optionally, it further includes etching the initial isolation layer until a part of the surface of the first electrode layer and the second electrode layer on the surface of the first side is exposed to form the isolation layer.

[0018] Optionally, after forming the conductive layer and the isolation layer, it further includes: forming an interlayer dielectric layer on the surface of the conductive layer, the surface of the isolation layer, and the exposed parts of the first electrode layer and the second electrode layer; forming a plurality of conductive posts within the interlayer dielectric layer, the plurality of conductive posts being electrically connected to the first electrode layer, the second electrode layer, and the conductive layer respectively.

[0019] Optionally, it further includes: forming a redistribution layer on the surface of the interlayer dielectric layer, the redistribution layer having a conductive structure, the conductive structure being electrically connected to the plurality of conductive posts.

[0020] Optionally, it further includes: forming a plurality of discrete first bumps on the surface of the redistribution layer.

[0021] Optionally, the method for thinning the substrate, the first electrode layer, the dielectric layer, the second electrode layer, and the isolation layer from the second side includes forming a carrier on the surface of the first bump, flipping the substrate, and planarizing the substrate from the second side until the conductive layer is exposed.

[0022] Optionally, after the thinning process, it further includes forming a passivation layer on the surface of the second side and the exposed surface of the conductive layer, forming an opening within the passivation layer that exposes the surface of the conductive layer; and forming a second bump within the opening.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0024] In the semiconductor structure of the technical solution of the present invention, the first electrode layer, the dielectric layer, the second electrode layer, and the isolation layer are simultaneously located in the through-interconnection via, and the conductive layer is located on the surface of the isolation layer within the through-interconnection via; on the one hand, a capacitor is jointly constructed in the capacitor trench and the through-interconnection via subsequently, which greatly reduces the preparation steps of the semiconductor structure and improves the capacitance density and capacity of the semiconductor structure integration; at the same time, the presence of the first electrode layer, the dielectric layer, and the second electrode layer reduces the formation space of the isolation layer within the through-interconnection via, thereby reducing the formation thickness of the isolation layer within the through-interconnection via and improving the processing efficiency; on the other hand, after the through-interconnection via penetrates the substrate, a passivation layer is formed on the second surface and the surface of the conductive layer, avoiding the risk of cracking of the conductive layer on the second surface and greatly improving the yield of the semiconductor structure. Description of the Drawings

[0025] Figures 1 to 4 are schematic structural diagrams of each step of a semiconductor structure and a method for forming the same in an embodiment;

[0026] Figures 5 to 13 are schematic structural diagrams of each step of a semiconductor structure and a method for forming the same in an embodiment of the present invention. Detailed Description of the Embodiment

[0027] As in the background art, in combination with Figures 1 to 4 the formation process of the existing TSV is described.

[0028] First, please refer to Figure 1 , which includes a silicon substrate 100; a TSV deep trench 100a located in the silicon substrate 100; a silicon oxide layer 101 located on the sidewalls and bottom of the TSV deep trench 100a; a conductive layer 102 located on the surface of the silicon oxide layer 101, the conductive layer 102 fills the TSV deep trench, and the conductive layer 102 and the silicon oxide layer 101 form a TSV structure 106; a redistribution layer 103 located on the surfaces of the silicon substrate 100 and the conductive layer 102; discrete bumps 104 located on the surface of the redistribution layer 103; a silicon carrier or a glass carrier 105 located on the surface of the bumps 104.

[0029] Please refer to Figure 2 , the silicon substrate 100 is planarized and etched and thinned to expose the ends of a part of the TSV structure 106.

[0030] Please refer to Figure 3 , a passivation layer 107 is formed at the exposed ends of the TSV structure 106.

[0031] Please refer to Figure 4 , the exposed ends of the TSV structure 106 are planarized to be flush with the surface of the silicon substrate 100.

[0032] The inventors found that during the planarization process, the TSV structure 106 protruded from the surface of the silicon substrate 100, resulting in slight cracking at the ends of the TSV structure 106 due to local mechanical stress and crystal defects during the planarization process, which greatly affected the yield of the product.

[0033] On this basis, the present invention provides a semiconductor structure. The first electrode layer, the dielectric layer, the second electrode layer, and the isolation layer are simultaneously located in the through-interconnection holes, and the conductive layer is located on the surface of the isolation layer in the through-interconnection holes. On the one hand, capacitors are jointly constructed in the capacitor trenches and the through-interconnection holes subsequently, greatly reducing the preparation steps of the semiconductor structure and improving the capacitance density and capacity of the semiconductor structure integration. At the same time, the presence of the first electrode layer, the dielectric layer, and the second electrode layer reduces the formation space of the isolation layer in the through-interconnection holes, thereby reducing the formation thickness of the isolation layer in the through-interconnection holes and improving the processing efficiency. On the other hand, after the through-interconnection holes penetrate the substrate, a passivation layer is formed on the second surface and the surface of the conductive layer, avoiding the risk of cracking of the conductive layer on the second surface and greatly improving the yield of the semiconductor structure.

[0034] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0035] First, please refer to Figure 5 , a substrate 200 is provided, and the substrate 200 includes opposite first surface 200a and second surface 200b.

[0036] Please continue to refer to Figure 5 , mutually discrete capacitor trenches 201 and through-interconnection holes 202 are formed in the substrate 200. The capacitor trenches 201 and the through-interconnection holes 202 are both recessed with respect to the first surface 200a, and the depth of the capacitor trenches 201 is less than the depth of the through-interconnection holes 202.

[0037] In this embodiment, the formation method of the capacitor trenches 201 and the through-interconnection holes 202 includes: forming a first mask layer and a second mask layer on the surface of the first surface 200a, the height of the first mask layer being higher than that of the second mask layer; forming a pattern layer on the surfaces of the first mask layer and the second mask layer; etching the substrate 200 using the pattern layer as a mask to form mutually discrete capacitor trenches 201 and through-interconnection holes 202 in the substrate 200. The capacitor trenches 201 and the through-interconnection holes 202 are both recessed with respect to the first surface 200a, and the depth of the capacitor trenches 201 is less than the depth of the through-interconnection holes 202.

[0038] In this embodiment, the first mask layer and the second mask layer are removed after the capacitor trenches 201 and the through-interconnection holes 202 are formed.

[0039] Please refer to Figure 6, a first electrode layer 204, a dielectric layer 205 located on the surface of the first electrode layer 204, and a second electrode layer 206 located on the surface of the dielectric layer 205 are formed on the surface of the first side 200a, the inner wall surface of the capacitor trench 201, and the inner wall surface of the interconnection via 202.

[0040] In this embodiment, before forming the first electrode layer 204, an oxide layer 203 is formed on the inner wall surface of the capacitor trench 201 and the inner wall surface of the interconnection via 202.

[0041] In this embodiment, the material of the oxide layer 203 is silicon oxide.

[0042] In this embodiment, the thickness of the oxide layer 203 is 100 Å to 200 Å.

[0043] In this embodiment, the process for forming the oxide layer 203 is atomic layer deposition process.

[0044] In other embodiments, the process for forming the oxide layer 203 can also be physical vapor deposition process, chemical vapor deposition process, etc.

[0045] In this embodiment, the material of the first electrode layer 204 is titanium nitride, and the thickness of the first electrode layer 204 is 200 Å to 300 Å.

[0046] In this embodiment, the process for forming the first electrode layer 204 is atomic layer deposition process.

[0047] In other embodiments, the process for forming the first electrode layer 204 can also be physical vapor deposition process, chemical vapor deposition process, etc.

[0048] In this embodiment, the dielectric layer 205 includes a ZAZ structure of zirconia with a thickness of 20 Å to 60 Å, alumina with a thickness of 20 Å, and zirconia with a thickness of 20 Å to 60 Å.

[0049] In this embodiment, the material of the second electrode layer 206 is titanium nitride, and the thickness of the first electrode layer 204 is 200 Å to 300 Å.

[0050] Please refer to Figure 7 , an initial isolation layer 207 is formed on the surface of the second electrode layer 206 in the capacitor trench 201 and the interconnection via 202. The initial isolation layer 207 fills the capacitor trench 201; there is a via opening 207a in the initial isolation layer 207 in the interconnection via 202.

[0051] In this embodiment, the material of the initial isolation layer 207 is silicon oxide.

[0052] In this embodiment, the thickness of the initial isolation layer 207 is 0.5 μm to 1.5 μm.

[0053] In this embodiment, the formation process of the initial isolation layer 207 is an atomic layer deposition process.

[0054] Please refer to Figure 8 , an initial conductive layer 208 is formed on the surface of the initial isolation layer 207, and the initial conductive layer 208 fills the via opening 207a.

[0055] In this embodiment, the material of the initial conductive layer 208 is copper.

[0056] In this embodiment, the process of forming the initial conductive layer 208 is an electroless plating process.

[0057] In other embodiments, the process of forming the initial conductive layer 208 can also be physical vapor deposition or the like.

[0058] Please refer to Figure 9 , the initial conductive layer 208 is planarized until the surface of the initial isolation layer 207 is exposed, and a conductive layer 209 is formed in the via opening 207a.

[0059] In this embodiment, during the process of planarizing the initial conductive layer 208, a part of the initial isolation layer 207 with a certain thickness is also planarized, so that the thickness range of the initial isolation layer 207 is between 200 angstroms and 800 angstroms.

[0060] In this embodiment, the process of planarizing the initial conductive layer 208 is a chemical mechanical polishing process.

[0061] Please refer to Figure 10 , the initial isolation layer 207 is etched until the surfaces of a part of the first electrode layer 204 and the second electrode layer 206 on the surface of the first side 200a are exposed, and an isolation layer 210 is formed.

[0062] In this embodiment, a lithography etching method is used to expose the surfaces of a part of the first electrode layer 204 and the second electrode layer 206 on the surface of the first side 200a.

[0063] In this embodiment, the surfaces of a part of the first electrode layer 204 and the second electrode layer 206 on the surface of the first side 200a are exposed as the upper and lower electrode plate ports.

[0064] Please refer to Figure 11 , an interlayer dielectric layer 211 is formed on the surface of the conductive layer 209, the surface of the isolation layer 210, and the exposed surfaces of a part of the first electrode layer 204 and the second electrode layer 206; a plurality of conductive pillars 213 are formed in the interlayer dielectric layer 211, and the plurality of conductive pillars 213 are electrically connected to the first electrode layer 204, the second electrode layer 206, and the conductive layer 209 respectively.

[0065] Please continue to refer to Figure 11, a redistribution layer 212 is formed on the surface of the interlayer dielectric layer 211. The redistribution layer 212 has a conductive structure 214 therein, and the conductive structure 214 is electrically connected to a plurality of conductive posts 213.

[0066] In this embodiment, it further includes: forming a plurality of discrete first bumps 215 on the surface of the redistribution layer 212.

[0067] Please refer to Figure 12 , the substrate 200, the first electrode layer 204, the dielectric layer 205, the second electrode layer 206, and the isolation layer 210 are thinned from the second surface 200b until the conductive layer 209 is exposed.

[0068] In this embodiment, the method of thinning the substrate 200, the first electrode layer 204, the dielectric layer 205, the second electrode layer 206, and the isolation layer 210 from the second surface 200b includes forming a carrier wafer 216 on the surface of the first bump 215, flipping the substrate 200, and planarizing the substrate 200 from the second surface 200b until the conductive layer 209 is exposed.

[0069] Please refer to Figure 13 , after the thinning process, it further includes forming a passivation layer 217 on the surface of the second surface 200b and the exposed surface of the conductive layer 209, forming an opening 218 in the passivation layer 217 that exposes the surface of the conductive layer 209; forming a second bump 219 in the opening 218.

[0070] In this embodiment, the first electrode layer 204, the dielectric layer 205, the second electrode layer 206, and the isolation layer 210 are simultaneously located in the through-interconnection hole 202, and the conductive layer 209 is located on the surface of the isolation layer 210 in the through-interconnection hole 202; on the one hand, the capacitor trench 201 and the through-interconnection hole 202 are formed simultaneously, and the capacitor trench 201 and the through-interconnection hole 202 jointly construct a capacitor, greatly reducing the manufacturing steps of the semiconductor structure and improving the capacitance density and capacity of the semiconductor structure integration; at the same time, the presence of the first electrode layer 204, the dielectric layer 205, and the second electrode layer 206 reduces the formation space of the isolation layer 210 in the through-interconnection hole 202, thereby reducing the formation thickness of the isolation layer 210 in the through-interconnection hole 202 and improving the processing efficiency; on the other hand, after the through-interconnection hole 202 penetrates the substrate 200, a passivation layer 217 is formed on the surface of the second surface 200b and the conductive layer 209, avoiding the risk of cracking of the conductive layer 209 on the second surface 200b and greatly improving the yield of the semiconductor structure.

[0071] Using the above formation method, correspondingly, the present invention further provides a semiconductor structure. Please refer to Figure 13, including a substrate 200, including opposite first and second surfaces 200a and 200b; an interconnection through-hole 202 penetrating the substrate 200; a first electrode layer 204 on the surface of the first surface 200a and the sidewall surface of the interconnection through-hole 202, a dielectric layer 205 on the surface of the first electrode layer 204, and a second electrode layer 206 on the surface of the dielectric layer 205; an isolation layer 210 on the surface of the second electrode layer 206 within the interconnection through-hole 202; a conductive layer 209 on the surface of the isolation layer 210 within the interconnection through-hole 202, the conductive layer 209 filling the interconnection through-hole 202, and the second surface 200b exposing the conductive layer 209.

[0072] In this embodiment, it further includes a capacitive trench 201 within the substrate 200, the capacitive trench 201 being recessed relative to the first surface 200a, and the depth of the capacitive trench 201 being less than the thickness of the substrate 200; the first electrode layer 204, the dielectric layer 205, and the second electrode layer 206 are also sequentially on the inner wall surface of the capacitive trench 201.

[0073] In this embodiment, the isolation layer 210 is also on the surface of the second electrode layer 206 within the capacitive trench 201, and the isolation layer 210 fills the capacitive trench 201.

[0074] In this embodiment, the isolation layer 210 is also on a partial surface of the second electrode layer 206 on the first surface 200a.

[0075] In this embodiment, it further includes: an interlayer dielectric layer 211 on the surface of the conductive layer 209, the surface of the isolation layer 210, and the exposed partial surfaces of the first electrode layer 204 and the second electrode layer 206; a plurality of conductive pillars 213 within the interlayer dielectric layer 211, the plurality of conductive pillars 213 being electrically connected to the first electrode layer 204, the second electrode layer 206, and the conductive layer 209 respectively.

[0076] In this embodiment, it further includes: a redistribution layer 212 on the surface of the interlayer dielectric layer 211, the redistribution layer 212 having a conductive structure 214, the conductive structure 214 being electrically connected to the plurality of conductive pillars 213.

[0077] In this embodiment, it further includes: a plurality of discrete first bumps 215 on the surface of the redistribution layer 212; a carrier wafer 216 on the surface of the first bumps 215.

[0078] In this embodiment, it further includes: a passivation layer 217 on the second surface 200b and the surface of the conductive layer 209, the passivation layer 217 having an opening 218, the opening 218 exposing the surface of the conductive layer 209; a second bump 219 within the opening 218.

[0079] In this embodiment, the first electrode layer 204, the dielectric layer 205, the second electrode layer 206, and the isolation layer 210 are simultaneously located within the through-interconnection via 202, and the conductive layer 209 is located on the surface of the isolation layer 210 within the through-interconnection via 202. On the one hand, the capacitor trench 201 and the through-interconnection via 202 jointly construct a capacitor, greatly reducing the manufacturing steps of the semiconductor structure and improving the capacitance density and capacity of the semiconductor structure integration. At the same time, the presence of the first electrode layer 204, the dielectric layer 205, and the second electrode layer 206 reduces the formation space of the isolation layer 210 within the through-interconnection via 202, thereby reducing the formation thickness of the isolation layer 210 within the through-interconnection via 202 and improving the processing efficiency. On the other hand, after the through-interconnection via 202 penetrates the substrate 200, a passivation layer 217 is formed on the surface of the second surface 200b and the conductive layer 209, avoiding the risk of cracking of the conductive layer 209 on the second surface 200b and greatly improving the yield of the semiconductor structure.

[0080] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, including opposite first and second surfaces; Mutually connected through-holes penetrating the substrate; A first electrode layer located on the surface of the first surface and the side wall surface of the mutually connected through-holes, a dielectric layer located on the surface of the first electrode layer, and a second electrode layer located on the surface of the dielectric layer; An isolation layer located on the surface of the second electrode layer within the mutually connected through-holes; A conductive layer located on the surface of the isolation layer within the mutually connected through-holes, the conductive layer filling the mutually connected through-holes, and the second surface exposing the conductive layer.

2. The semiconductor structure according to claim 1, characterized in that, Further comprising: Capacitor trenches within the substrate, the capacitor trenches being recessed relative to the first surface, and the depth of the capacitor trenches being less than the thickness of the substrate; The first electrode layer, the dielectric layer, and the second electrode layer are also sequentially located on the inner wall surface of the capacitor trenches.

3. The semiconductor structure according to claim 2, wherein, The isolation layer is also located on the surface of the second electrode layer within the capacitor trenches, and the isolation layer fills the capacitor trenches.

4. The semiconductor structure according to claim 1, wherein The isolation layer is also located on a partial surface of the second electrode layer on the first surface.

5. The semiconductor structure according to claim 1, characterized in that, Further comprising: An interlayer dielectric layer located on the surface of the conductive layer, the surface of the isolation layer, and the exposed partial surfaces of the first electrode layer and the second electrode layer; A plurality of conductive pillars located within the interlayer dielectric layer, the plurality of conductive pillars being electrically connected to the first electrode layer, the second electrode layer, and the conductive layer respectively.

6. The semiconductor structure according to claim 5, wherein, Further comprising: A redistribution layer located on the surface of the interlayer dielectric layer, the redistribution layer having a conductive structure therein, the conductive structure being electrically connected to the plurality of conductive pillars.

7. The semiconductor structure according to claim 6, wherein, Further comprising: A plurality of discrete first bumps located on the surface of the redistribution layer; A carrier wafer located on the surface of the first bumps.

8. The semiconductor structure according to claim 1, wherein, Further comprising: A passivation layer located on the second surface and the surface of the conductive layer, the passivation layer having an opening therein, the opening exposing the surface of the conductive layer; A second bump located within the opening.

9. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including opposite first and second surfaces; Forming mutually discrete capacitor trenches and mutually connected through-holes within the substrate, both the capacitor trenches and the mutually connected through-holes being recessed relative to the first surface, and the depth of the capacitor trenches being less than the depth of the mutually connected through-holes; Forming a first electrode layer, a dielectric layer located on the surface of the first electrode layer, and a second electrode layer located on the surface of the dielectric layer on the surface of the first surface, the inner wall surface of the capacitor trenches, and the inner wall surface of the mutually connected through-holes; Forming an isolation layer on the surface of the second electrode layer within the capacitor trenches and within the mutually connected through-holes, the isolation layer filling the capacitor trenches, and having a via opening within the isolation layer within the mutually connected through-holes; Forming a conductive layer filling the via opening; Thinning the substrate, the first electrode layer, the dielectric layer, the second electrode layer, and the isolation layer from the second surface until the conductive layer is exposed.

10. The method for forming a semiconductor structure according to claim 9, wherein, The forming method of the capacitance trench and the interconnection via includes: forming a first mask layer and a second mask layer on the surface of the first face, the height of the first mask layer being higher than that of the second mask layer; forming a pattern layer on the surfaces of the first mask layer and the second mask layer; etching the substrate using the pattern layer as a mask to form discrete capacitance trenches and interconnection vias in the substrate, both the capacitance trenches and the interconnection vias being recessed relative to the first face, and the depth of the capacitance trenches being less than the depth of the interconnection vias.

11. The method for forming a semiconductor structure as described in claim 9, wherein, The forming method of the isolation layer and the conductive layer includes: forming an initial isolation layer on the surface of the second electrode layer, the initial isolation layer filling the capacitance trenches; forming an initial conductive layer on the surface of the initial isolation layer; planarizing the initial conductive layer until the surface of the initial isolation layer is exposed, and forming a conductive layer in the via opening.

12. The method for forming a semiconductor structure according to claim 11, wherein, It further includes etching the initial isolation layer until the surfaces of part of the first electrode layer and the second electrode layer on the surface of the first face are exposed to form the isolation layer.

13. The method for forming a semiconductor structure according to claim 12, wherein After forming the conductive layer and the isolation layer, it further includes: forming an interlayer dielectric layer on the surface of the conductive layer, the surface of the isolation layer, and the exposed surfaces of part of the first electrode layer and the second electrode layer; forming a plurality of conductive posts in the interlayer dielectric layer, the plurality of conductive posts being electrically connected to the first electrode layer, the second electrode layer, and the conductive layer respectively.

14. The method for forming a semiconductor structure according to claim 13, wherein, It further includes: forming a redistribution layer on the surface of the interlayer dielectric layer, the redistribution layer having a conductive structure therein, the conductive structure being electrically connected to the plurality of conductive posts.

15. The method for forming a semiconductor structure according to claim 14, wherein, It further includes: forming a plurality of discrete first bumps on the surface of the redistribution layer.

16. The method for forming a semiconductor structure as described in claim 15, wherein, The method of thinning the substrate, the first electrode layer, the dielectric layer, the second electrode layer, and the isolation layer from the second face includes forming a carrier on the surface of the first bump, flipping the substrate, and planarizing the substrate from the second face until the conductive layer is exposed.

17. The method for forming a semiconductor structure according to claim 16, wherein, After the thinning process, it further includes forming a passivation layer on the surface of the second face and the exposed surface of the conductive layer, forming an opening in the passivation layer that exposes the surface of the conductive layer; and forming a second bump in the opening.

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