Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a bottom wafer which comprises a bottom substrate and a bottom interconnection structure disposed on the bottom substrate; a top wafer including a top substrate having a front surface and a back surface, and a top interconnect structure disposed on the front surface of the top substrate, where the top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer; an oxide-nitride-oxide (ONO) dielectric layer covering the rear surface of the top substrate; and a plurality of conductive vias disposed on the rear surface and extending into the ONO dielectric layer and the top substrate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an improved semiconductor structure applicable to the field of wafer hybrid bonding technology. Background Art

[0002] Three-dimensional integrated circuits (3D ICs) are the next-generation semiconductor technology, with advantages such as small size, high performance, low power consumption, and high-density integration. Through-silicon vias (TSVs) and stacked bonding are the core technologies for realizing 3D integrated vertical interconnections.

[0003] Chip-to-wafer and wafer-to-wafer hybrid bonding can connect chips through direct copper-to-copper bonding, enabling the combined components to operate as a whole. Hybrid bonding is the most advanced production technology in the industry, which improves component performance by introducing more wiring into a smaller space and reducing the distance that signals need to travel.

[0004] TSVs are vertical wires used to precisely connect stacked chips. They are formed by etching trenches in a silicon substrate and then filling the trenches with an insulating liner and metal wires. As designers continue to integrate more logic, memory, and application-specific chips into advanced 2.5D and 3D packages, the number of TSV interconnections has expanded from hundreds per package to more than thousands. To integrate more interconnections and accommodate higher chip stacks, designers need to make the vias narrower and taller, which leads to deposition uniformity variations, thereby reducing performance and increasing resistance and power consumption. Summary of the Invention

[0005] The main objective of the present invention is to provide an improved semiconductor structure and its manufacturing method applicable to the field of wafer hybrid bonding technology to address the deficiencies or drawbacks of the prior art.

[0006] The present invention provides a semiconductor structure on the one hand, comprising: a bottom wafer, including a bottom substrate and a bottom interconnect structure located on the bottom substrate; a top wafer, including a top substrate having a front surface and a back surface, and a top interconnect structure disposed on the front surface of the top substrate, wherein the top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer; an oxide-nitride-oxide (ONO) dielectric layer covering the back surface of the top substrate; and a plurality of conductive vias disposed on the back surface and extending into the ONO dielectric layer and the top substrate.

[0007] According to an embodiment of the present invention, the top substrate comprises a silicon substrate with a thickness of 3 to 5 microns.

[0008] According to an embodiment of the present invention, the plurality of conductive vias are electrically connected to the top interconnect structure disposed on the front surface of the top substrate.

[0009] According to an embodiment of the present invention, the plurality of conductive vias comprise copper or aluminum.

[0010] According to an embodiment of the present invention, the top surfaces of the plurality of conductive vias are coplanar with the top surface of the ONO dielectric layer.

[0011] According to an embodiment of the present invention, the bottom wafer has a first vertical sidewall, and the top wafer has a second vertical sidewall, wherein the first vertical sidewall is flush with the second vertical sidewall.

[0012] According to an embodiment of the present invention, the bottom wafer has an edge portion protruding from the first vertical sidewall.

[0013] According to an embodiment of the present invention, the first vertical sidewall and the second vertical sidewall are covered with a protective layer.

[0014] According to an embodiment of the present invention, the protective layer extends onto the upper surface of the edge portion.

[0015] According to an embodiment of the present invention, the protective layer comprises silicon oxide.

[0016] Another aspect of the present invention provides a method of forming a semiconductor structure, comprising: providing a bottom wafer comprising a bottom substrate and a bottom interconnect structure disposed on the bottom substrate; providing a top wafer comprising a top substrate having a front surface and a back surface, and a top interconnect structure disposed on the front surface of the top substrate, wherein the top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer; forming an oxide-nitride-oxide (ONO) dielectric layer covering the back surface of the top substrate; and after forming the ONO dielectric layer, forming a plurality of conductive vias on the back surface, the plurality of conductive vias extending into the ONO dielectric layer and the top substrate.

[0017] According to an embodiment of the present invention, the top substrate comprises a silicon substrate with a thickness of 3 to 5 microns.

[0018] According to an embodiment of the present invention, the plurality of conductive vias are electrically connected to the top interconnect structure disposed on the front surface of the top substrate.

[0019] According to an embodiment of the present invention, the plurality of conductive vias comprise copper or aluminum.

[0020] According to an embodiment of the present invention, the top surfaces of the plurality of conductive vias are coplanar with the top surface of the ONO dielectric layer.

[0021] According to an embodiment of the present invention, the bottom wafer has a first vertical sidewall, and the top wafer has a second vertical sidewall, wherein the first vertical sidewall is flush with the second vertical sidewall.

[0022] According to an embodiment of the present invention, the bottom wafer has an edge portion protruding from the first vertical sidewall.

[0023] According to an embodiment of the present invention, a protective layer covers the first vertical sidewall and the second vertical sidewall. According to an embodiment of the present invention, the protective layer extends onto the upper surface of the edge portion. According to an embodiment of the present invention, the protective layer comprises silicon oxide. Description of the Drawings

[0024] Figure 1 A schematic cross-sectional view of a semiconductor structure illustrated for an embodiment of the present invention;

[0025] Figures 2 to 10 A schematic diagram illustrating a method of forming a semiconductor structure.

[0026] Description of the Reference Numerals

[0027] 1 Semiconductor structure

[0028] 10 Bottom wafer

[0029] 12 Edge portion

[0030] 100 Bottom substrate

[0031] 110 Bottom interconnect structure

[0032] 111 Dielectric layer

[0033] 112 Metal layer

[0034] 113 Dielectric layer

[0035] 114 Bonding copper pad

[0036] 115 Bonding dielectric layer

[0037] 20 Top wafer

[0038] 200 Top substrate

[0039] 210 Top interconnect structure

[0040] 211 Dielectric layer

[0041] 212 Metal layer

[0042] 213 Dielectric layer

[0043] 214 Bonding copper pad

[0044] 215 Bonding dielectric layer

[0045] 220 Conductive vias

[0046] 310 Oxide-nitride-oxide (ONO) dielectric layer

[0047] 410 Metal wiring structure

[0048] 412 Metal wire layer

[0049] 413 Dielectric layer

[0050] 413a Opening

[0051] 510 Protective layer

[0052] S1 Front surface

[0053] S2 Back surface

[0054] S3 Top surface

[0055] S4 Top surface

[0056] S5 Upper surface

[0057] S6 Top surface

[0058] SW1 First vertical sidewall

[0059] SW2 Second vertical sidewall

[0060] d Width

[0061] w Depth

[0062] t1 First thickness

[0063] t2 Second thickness

[0064] t3 Third thickness

[0065] t4 Fourth thickness

[0066] SB Conductive part Detailed implementation mode

[0067] In the following, details will be described with reference to the accompanying drawings, the content of which also constitutes a part of the detailed description of the specification and is shown in a specific description manner for implementing the embodiment. The following embodiments have described sufficient details for those of ordinary skill in the art to implement accordingly.

[0068] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as a limitation. Instead, the embodiments included therein will be defined by the appended claims.

[0069] Please refer to Figure 1 , which is a schematic cross-sectional view of a semiconductor structure shown according to an embodiment of the present invention. As Figure 1 shown, the semiconductor structure 1 includes a bottom wafer 10 and a top wafer 20, and the bottom wafer 10 and the top wafer 20 are directly bonded together. According to an embodiment of the present invention, the bottom wafer 10 includes a bottom substrate 100 and a bottom interconnect structure 110 located on the bottom substrate 100. According to an embodiment of the present invention, the bottom substrate 100 is, for example, a silicon substrate, but is not limited thereto. According to an embodiment of the present invention, the top wafer 20 includes a top substrate 200, wherein the top substrate 200 has a front surface S1 and a back surface S2, and a top interconnect structure 210 provided on the front surface S1 of the top substrate 200. According to an embodiment of the present invention, the top substrate 200 is, for example, a silicon substrate, but is not limited thereto. According to an embodiment of the present invention, the thickness of the top substrate 200 is 3 to 5 microns.

[0070] According to an embodiment of the present invention, for example, the bottom interconnect structure 110 may include, but is not limited to, a dielectric layer 111, a metal layer 112, a dielectric layer 113, a bonding copper pad 114, and a bonding dielectric layer 115. According to an embodiment of the present invention, for example, the dielectric layers 111, 113 may include a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a low dielectric constant material layer, or an ultra-low dielectric constant layer, etc. According to an embodiment of the present invention, for example, the dielectric layer 115 may include a silicon oxide layer, but is not limited thereto. According to an embodiment of the present invention, for example, the metal layer 112 may include copper, tungsten, titanium, tantalum, aluminum, gold, etc., but is not limited thereto.

[0071] Those skilled in the art should understand that circuit elements, such as transistors, etc., may be formed in the bottom substrate 100. For simplicity of illustration, these circuit elements are not shown in the figure.

[0072] According to an embodiment of the present invention, for example, the top interconnect structure 210 may include, but is not limited to, a dielectric layer 211, a metal layer 212, a dielectric layer 213, a bonding copper pad 214, and a bonding dielectric layer 215. According to an embodiment of the present invention, for example, the dielectric layers 211, 213 may include a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a low dielectric constant material layer, or an ultra-low dielectric constant layer, etc. According to an embodiment of the present invention, for example, the dielectric layer 215 may include a silicon oxide layer, but is not limited thereto. According to an embodiment of the present invention, for example, the metal layer 212 may include copper, tungsten, titanium, tantalum, aluminum, gold, etc., but is not limited thereto.

[0073] Those skilled in the art should understand that circuit elements, such as transistors, etc., may also be formed in the bottom substrate 200. For simplicity of illustration, these circuit elements are not shown in the figure.

[0074] According to an embodiment of the present invention, the bottom wafer 10 and the top wafer 20 can be bonded together by hybrid bonding technology. According to an embodiment of the present invention, the top interconnect structure 210 of the top wafer 20 is directly bonded to the bottom interconnect structure 110 of the bottom wafer 10. More specifically, the direct bonding of the bottom wafer 10 to the top wafer 20 is accomplished by aligning and bonding the bonding copper pads 114 and the bonding copper pads 214 and directly bonding the bonding dielectric layer 115 to the bonding dielectric layer 215.

[0075] According to an embodiment of the present invention, the semiconductor structure 1 further includes an oxide-nitride-oxide (ONO) dielectric layer 310 covering the back surface S2 of the top substrate 200. According to an embodiment of the present invention, a metal wiring structure 410 is formed on the ONO dielectric layer 310. According to an embodiment of the present invention, for example, the metal wiring structure 410 may include a metal wire layer 412 and a dielectric layer 413. According to an embodiment of the present invention, for example, the metal wire layer 412 may include metal pads, and the dielectric layer 413 may include an opening 413a exposing a portion of the metal wire layer 412.

[0076] According to an embodiment of the present invention, the semiconductor structure 1 further includes a plurality of conductive vias 220 disposed on the back surface S2 of the top substrate 200, electrically connected to the metal wire layer 412, and extending downward into the ONO dielectric layer 310 and the top substrate 200. According to an embodiment of the present invention, the plurality of conductive vias 220 are electrically connected to the top interconnect structure 210 disposed on the front surface S1 of the top substrate 200. According to an embodiment of the present invention, the plurality of conductive vias 220 include copper or aluminum. According to an embodiment of the present invention, the top surface S3 of the plurality of conductive vias 220 is coplanar with the top surface S4 of the ONO dielectric layer 310.

[0077] According to an embodiment of the present invention, the bottom wafer 10 has a first vertical sidewall SW1, and the top wafer 20 has a second vertical sidewall SW2, wherein the first vertical sidewall SW1 and the second vertical sidewall SW2 are flush in the vertical direction. According to an embodiment of the present invention, the bottom wafer 10 has an edge portion 12 protruding from the first vertical sidewall SW1. According to an embodiment of the present invention, the first vertical sidewall SW1 and the second vertical sidewall SW2 are covered with a protective layer 510. According to an embodiment of the present invention, the protective layer 510 extends onto the upper surface S5 of the edge portion 12. According to an embodiment of the present invention, the protective layer 510 includes, for example, silicon oxide, but is not limited thereto. According to an embodiment of the present invention, the ONO dielectric layer 310 can directly contact the top surface S6 of the protective layer 510.

[0078] Please refer to Figures 2 to 10 which illustrates a method of forming the semiconductor structure 1 according to the present invention. As Figure 2As shown, first, a bottom wafer 10 and a top wafer 20 are provided, and the bottom wafer 10 and the top wafer 20 are directly bonded together using hybrid bonding technology. According to an embodiment of the present invention, the bottom wafer 10 includes a bottom substrate 100 and a bottom interconnect structure 110 located on the bottom substrate. According to an embodiment of the present invention, the bottom substrate 100 is, for example, a silicon substrate, but is not limited thereto. According to an embodiment of the present invention, the top wafer 20 includes a top substrate 200, wherein the top substrate 200 has a front surface S1 and a back surface S2, and a top interconnect structure 210 provided on the front surface S1 of the top substrate 200. At this time, the top substrate 200 has a first thickness t1, for example, 700 to 800 microns. Through-silicon vias (TSVs) are not formed in the top substrate 200.

[0079] According to an embodiment of the present invention, for example, the bottom interconnect structure 110 may include, but is not limited to, a dielectric layer 111, a metal layer 112, a dielectric layer 113, a bonding copper pad 114, and a bonding dielectric layer 115. According to an embodiment of the present invention, for example, the dielectric layers 111, 113 may include a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a low dielectric constant material layer, or an ultra-low dielectric constant layer, etc. According to an embodiment of the present invention, for example, the dielectric layer 115 may include a silicon oxide layer, but is not limited thereto. According to an embodiment of the present invention, for example, the metal layer 112 may include copper, tungsten, titanium, tantalum, aluminum, gold, etc., but is not limited thereto.

[0080] According to an embodiment of the present invention, for example, the top interconnect structure 210 may include, but is not limited to, a dielectric layer 211, a metal layer 212, a dielectric layer 213, a bonding copper pad 214, and a bonding dielectric layer 215. According to an embodiment of the present invention, for example, the dielectric layers 211, 213 may include a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a low dielectric constant material layer, or an ultra-low dielectric constant layer, etc. According to an embodiment of the present invention, for example, the dielectric layer 215 may include a silicon oxide layer, but is not limited thereto. According to an embodiment of the present invention, for example, the metal layer 212 may include copper, tungsten, titanium, tantalum, aluminum, gold, etc., but is not limited thereto.

[0081] As Figure 3 shown, then, a first wafer grinding manufacturing process is performed on the back surface S2 of the top substrate 200. At this time, the ground top substrate 200 has a second thickness t2, for example, 200 to 300 microns, for example, 250 microns.

[0082] As Figure 4As shown, a photolithography process and an etching process are then carried out to remove the entire thickness of the bottom wafer 10 and a part of the thickness of the top wafer 20 within the annular peripheral region. According to an embodiment of the present invention, for example, the width d of the above-mentioned annular peripheral region is about 2.8 mm, and the depth w is about 290 microns. According to an embodiment of the present invention, the bottom wafer 100 has a first vertical sidewall SW1, and the top wafer 20 has a second vertical sidewall SW2, wherein the first vertical sidewall SW1 and the second vertical sidewall SW2 are flush in the vertical direction. In addition, the bottom wafer has an annular edge portion 12 protruding from the first vertical sidewall SW1.

[0083] As Figure 5 shown, a chemical vapor deposition process can then be carried out to conformally deposit a protective layer 510 on the back surface S2 of the top substrate 200, on the first vertical sidewall SW1 of the bottom wafer 100, on the second vertical sidewall SW2 of the top wafer 20, and on the upper surface S5 of the annular edge portion 12. According to an embodiment of the present invention, the protective layer 510 includes, for example, silicon oxide, but is not limited thereto.

[0084] As Figure 6 shown, a second wafer grinding process is then carried out on the back surface S2 of the top substrate 200. At this time, the ground top substrate 200 has a third thickness t3, for example, 10 - 30 microns. The protective layer 510 originally located on the back surface S2 of the top substrate 200 will also be removed, leaving only the protective layer 510 on the first vertical sidewall SW1 of the bottom wafer 100, on the second vertical sidewall SW2 of the top wafer 20, and on the upper surface S5 of the annular edge portion 12.

[0085] As Figure 7 shown, a chemical mechanical polishing process is carried out to thin the thickness of the top substrate 200 to a fourth thickness t4, for example, 3 - 5 microns. Then, a chemical vapor deposition process is carried out to conformally deposit an oxide-nitride-oxide (ONO) dielectric layer 310 on the top substrate 200 and on the protective layer 510.

[0086] As Figure 8 shown, after the ONO dielectric layer 310 is formed, a plurality of conductive vias 220 are formed on the back surface S2 of the top substrate 200, and the plurality of conductive vias 220 extend into the ONO dielectric layer 310 and the top substrate 200. According to an embodiment of the present invention, the plurality of conductive vias 220 are electrically connected to a top interconnect structure 210 provided on the front surface S1 of the top substrate 200. According to an embodiment of the present invention, the plurality of conductive vias 220 include, for example, copper or aluminum, but are not limited thereto. According to an embodiment of the present invention, at this time, the top surface S3 of the plurality of conductive vias 220 is coplanar with the top surface S4 of the ONO dielectric layer 310.

[0087] As shown Figure 9 Next, a metallization process is performed to form a metal wiring structure 410 on the ONO dielectric layer 310. According to an embodiment of the present invention, for example, the metal wiring structure 410 may include a metal wire layer 412 and a dielectric layer 413. According to an embodiment of the present invention, for example, the metal wire layer 412 may include a metal pad, and the dielectric layer 413 may include an opening 413a that exposes a portion of the metal wire layer 412.

[0088] Finally, as shown Figure 10 in the figure, a conductive member SB, such as a solder ball, a bump, or a micro-bump, but not limited thereto, may be formed on the metal wiring structure 410.

[0089] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A semiconductor structure comprising: a bottom wafer comprising a bottom substrate and a bottom interconnect structure disposed on the bottom substrate; A top wafer comprising a top substrate having a front surface and a back surface, and a top interconnect structure disposed on the front surface of the top substrate, wherein: The top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer; an oxide-nitride-oxide (ONO) dielectric layer covering the rear surface of the top substrate; as well as A plurality of conductive vias are disposed on the rear surface and extend into the ONO dielectric layer and the top substrate.

2. The semiconductor structure according to claim 1, wherein: The top substrate comprises a silicon substrate and has a thickness of 3 to 5 microns.

3. The semiconductor structure according to claim 1, wherein: The plurality of conductive vias are electrically connected to the top interconnect structure disposed on the front surface of the top substrate.

4. The semiconductor structure according to claim 1, wherein: The plurality of conductive vias include copper or aluminum.

5. The semiconductor structure according to claim 1, wherein: Top surfaces of the plurality of conductive vias are coplanar with a top surface of the ONO dielectric layer.

6. The semiconductor structure of claim 1, wherein: The bottom wafer has a first vertical sidewall and the top wafer has a second vertical sidewall, wherein the first vertical sidewall is flush with the second vertical sidewall.

7. The semiconductor structure according to claim 6, wherein: The bottom wafer has an edge portion protruding from the first vertical sidewall.

8. The semiconductor structure of claim 7, wherein: The first vertical side wall and the second vertical side wall are covered with a protection layer.

9. The semiconductor structure of claim 8, wherein: The protective layer extends onto the upper surface of the edge portion.

10. The semiconductor structure of claim 8, wherein: The protective layer includes silicon oxide.

11. A method of forming a semiconductor structure, comprising: providing a bottom wafer comprising a bottom substrate and a bottom interconnect structure located on the bottom substrate; A top wafer is provided, comprising a top substrate having a front surface and a back surface, and a top interconnect structure disposed on the front surface of the top substrate, wherein: The top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer; forming an oxide-nitride-oxide (ONO) dielectric layer covering the rear surface of the top substrate; as well as After forming the ONO dielectric layer, a plurality of conductive vias are formed on the rear surface such that the plurality of conductive vias extend into the ONO dielectric layer and the top substrate.

12. The method of claim 11, wherein: The top substrate comprises a silicon substrate and has a thickness of 3 to 5 microns.

13. The method of claim 11, wherein: The plurality of conductive vias are electrically connected to the top interconnect structure disposed on the front surface of the top substrate.

14. The method of claim 11, wherein: The plurality of conductive vias include copper or aluminum.

15. The method of claim 11, wherein: Top surfaces of the plurality of conductive vias are coplanar with a top surface of the ONO dielectric layer.

16. The method of claim 11, wherein: The bottom wafer has a first vertical sidewall and the top wafer has a second vertical sidewall, wherein the first vertical sidewall is flush with the second vertical sidewall.

17. The method of claim 16, wherein: The bottom wafer has an edge portion protruding from the first vertical sidewall.

18. The method of claim 17, wherein: The first vertical side wall and the second vertical side wall are covered with a protection layer.

19. The method of claim 18, wherein: The protective layer extends onto the upper surface of the edge portion.

20. The method of claim 18, wherein: The protective layer includes silicon oxide.

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