Packaging structure and packaging method of 3D integrated circuit

Abstract

The invention belongs to the technical field of integrated circuit packaging, and provides a packaging structure and packaging method of a 3D integrated circuit, and the packaging structure comprises a multi-layer chip stacking body, an inter-chip interconnection layer, a power distribution network, a heat dissipation module, and a packaging substrate. The multi-layer chip stacking body comprises integrated circuit chips, the integrated circuit chips are arranged in a three-dimensional stacking mode, and the integrated circuit chips are electrically connected through vertical interconnection structures; the inter-chip interconnection layer is configured between adjacent integrated circuit chips, comprises multiple layers of metal interconnection circuits, is made of a high-density and low-resistance metal material, and is integrated with a signal isolation structure; the power distribution network is configured to be integrated in the packaging substrate, and the power supply voltage of the integrated circuit chip is adjusted through the programmable switch matrix; the heat dissipation module is connected with the multi-layer chip stacking body; the package substrate is disposed at the bottom of the multi-layer chip stack for supporting the entire package structure. According to the invention, miniaturization and lightweight application of an integrated circuit is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a packaging structure and a packaging method for a 3D integrated circuit. Background Art

[0002] As electronic devices continue to develop towards miniaturization and high performance, the requirements for the integration and performance of integrated circuits are becoming increasingly higher. In the face of growing functional requirements, traditional two-dimensional integrated circuit packaging methods have gradually exposed many limitations. The interconnection distance between chips is long, resulting in large signal transmission delays and increased power consumption. In addition, due to the limitations of planar layout, it is difficult to achieve higher integration.

[0003] Therefore, three-dimensional integrated circuit packaging structures and packaging methods came into being, aiming to shorten the interconnection distance between chips by vertically stacking chips, thereby increasing signal transmission speed and reducing power consumption. This packaging method can not only effectively improve the integration level, but also meet the stringent requirements of high-performance electronic devices for integrated circuits. In the three-dimensional packaging structure, each chip is connected through a vertical interconnection channel, achieving a more compact layout, while also providing a more efficient path for collaborative work between chips.

[0004] Although some current packaging technologies have improved integration to a certain extent, they still have problems such as low data transmission efficiency, uneven power distribution, and heat dissipation difficulties. For example, in some multi-layer packaging structures, the interconnection technology used between chips cannot meet the needs of high-speed data transmission. Signals are prone to attenuation and interference during transmission, affecting circuit performance. At the same time, due to the difference in power consumption of chips with different functions, it is difficult to achieve accurate and efficient power distribution, resulting in performance limitations or even damage to some chips due to insufficient power supply or overvoltage. In addition, with the increase in integration, the heat generated by the chip accumulates in large quantities, and the heat dissipation problem seriously affects the stability and reliability of the chip.

[0005] Therefore, it is necessary to provide a packaging structure and a packaging method for a 3D integrated circuit. Summary of the invention

[0006] The present invention provides a packaging structure and packaging method for a 3D integrated circuit, aiming to overcome the shortcomings of the prior art, effectively reducing the packaging volume through three-dimensional stacking, using an inter-chip interconnection layer made of a high-density, low-resistance metal material, improving the signal transmission speed and stability, and reducing energy consumption. The application of a programmable switch matrix in a power distribution network allows the power supply voltage to be flexibly adjusted according to actual needs, further optimizing the performance of the integrated circuit, and the effective connection of the heat dissipation module ensures good heat dissipation of the multi-layer chip stack during operation, thereby extending the service life of the integrated circuit.

[0007] The present invention provides a packaging structure for a 3D integrated circuit, comprising: a multi-layer chip stack, an inter-chip interconnect layer, a power distribution network, a heat dissipation module, and a packaging substrate; The multi-layer chip stack includes a plurality of integrated circuit chips with different functions or processes. The integrated circuit chips are closely arranged in a three-dimensional stacking manner, and electrical connections between the integrated circuit chips are achieved through a vertical interconnect structure; The inter-chip interconnect layer is disposed between adjacent integrated circuit chips, includes multi-layer metal interconnect lines, is made of a high-density and low-resistance metal material, and is integrated with a signal isolation structure; The power distribution network is configured to be integrated in the packaging substrate, and adjusts the supply voltage of the integrated circuit chips through a programmable switch matrix; The heat dissipation module is connected to the multi-layer chip stack; The packaging substrate is disposed at the bottom of the multi-layer chip stack and is used to support the entire packaging structure.

[0008] Further, the vertical interconnect structure includes through-silicon vias and a micro-bump array. The inner wall of the through-silicon vias is plated with a copper-titanium composite layer; the micro-bump array is made of a copper-tin alloy material, the surface is covered with a nano-scale insulating coating, and is arranged in an asymmetric layout.

[0009] Further, the power distribution network includes a multi-phase voltage regulation module, a three-dimensional stacked distributed capacitor array, a power supply topology mode adjustment module, and an adaptive feedback control module; The multi-phase voltage regulation module includes a plurality of parallel buck converters, each buck converter is independently controlled, and the buck converter supports dynamic adjustment of the output voltage in the range of 0.5V to 3.3V with a 10mV step; The three-dimensional stacked distributed capacitor array is vertically integrated by a metal-insulator-metal (MIN) capacitor and an embedded spiral inductor; The power supply topology mode adjustment module is used to adjust and switch the power supply topology mode based on the real-time monitoring data of the current flowing through the chip load; The adaptive feedback control module is used to adjust the output voltage of the multi-phase voltage regulation module through a proportional-integral-derivative (PID) controller.

[0010] Further, the power supply topology mode adjustment module includes a current signal acquisition unit, a load fluctuation prediction unit, and a power supply topology mode switching implementation unit; The current signal acquisition unit is used to acquire the current signal of the chip load by using a Hall sensor array; The load fluctuation prediction unit is used to predict the current fluctuation data of the chip load within a future set period according to the current signal by using a long short-term memory network; A power supply topology mode switching implementation unit is used to dynamically switch the power supply topology mode according to the corresponding matching relationship between the set current fluctuation data and the switching strategy, so as to achieve the minimum power supply path impedance; the power supply topology modes include star topology mode, mesh topology mode or hybrid topology mode.

[0011] Furthermore, the heat dissipation module includes heat dissipation fins and heat dissipation channels; the heat dissipation fins are made of boron nitride or silicon carbide materials, and the heat dissipation channels are filled with a heat dissipation medium, and the heat dissipation medium is a phase change heat dissipation material or a liquid metal heat dissipation material.

[0012] Furthermore, the packaging substrate is a multi-layer organic interposer, configured with high-frequency signal transmission lines, embedded passive devices, interfaces connected to external circuits, and impedance matching circuits; the embedded passive devices include resistors, capacitors and filters.

[0013] Furthermore, it also includes an electromagnetic shielding layer and a stress buffer layer; the electromagnetic shielding layer is composed of a copper-ferrite composite material and is configured to cover the periphery of the integrated circuit chip; the stress buffer layer is configured at the multi-layer chip stacking interface and between the chip stack and the packaging substrate, and is composed of a polyimide-silica gel mixture.

[0014] A packaging method for a 3D integrated circuit includes: S1: Perform preprocessing operations such as cleaning and passivation on the integrated circuit chip to obtain a preprocessed integrated circuit chip; S2: Stack the preprocessed integrated circuit chips three-dimensionally to obtain a multi-layer chip stack; S3: Fabricate an inter-chip interconnect layer between adjacent integrated circuit chips in the multi-layer chip stack to form multi-layer metal interconnect lines and signal isolation structures; S4: Generate a power distribution network in the packaging structure through photolithography and electroplating processes; S5: Connect the heat dissipation module to the multi-layer chip stack and fill the heat dissipation medium; S6: Connect the bottom of the packaging substrate to the multi-layer chip stack, and configure and fabricate high-frequency signal transmission lines, embedded passive devices, interfaces connected to external circuits, and impedance matching circuits on the packaging substrate; S7: Perform electrical performance testing and reliability testing on the packaged 3D integrated circuit.

[0015] Furthermore, in step S2, a microelectromechanical system positioning technology is used for chip alignment to control the distance between chips.

[0016] Furthermore, in step S4, a dual-damascene process is used to form copper interconnects, and the programmable switch matrix is integrated through a post-metalization process.

[0017] Compared with the prior art, the present invention has the following advantages and beneficial effects: By means of three-dimensional stacking, the packaging volume is effectively reduced. The inter-chip interconnect layer made of high-density and low-resistance metal materials improves the signal transmission speed and stability, reduces energy consumption. The application of the programmable switch matrix in the power distribution network enables the power supply voltage to be flexibly adjusted according to actual needs, further optimizing the performance of the integrated circuit. The effective connection of the heat dissipation module ensures good heat dissipation during the operation of the multi-layer chip stack, extending the service life of the integrated circuit.

[0018] Other features and advantages of the present invention will be described in the following specification, and some of them will become obvious from the specification, or can be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the structure specifically pointed out in the written specification and the drawings.

[0019] The technical solution of the present invention will be further described in detail below through the drawings and embodiments. Description of the Drawings

[0020] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In the drawings: Figure 1 It is a schematic structural diagram of a packaging structure module of a 3D integrated circuit; Figure 2 It is a schematic structural diagram of a power distribution network; Figure 3 It is a schematic diagram of the steps of a packaging method of a 3D integrated circuit. Detailed Embodiments

[0021] The following describes the preferred embodiments of the present invention with reference to the drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0022] The present invention provides a packaging structure of a 3D integrated circuit, as Figure 1 shown, including: A multi-layer chip stack, an inter-chip interconnect layer, a power distribution network, a heat dissipation module, and a packaging substrate; The multi-layer chip stack includes multiple integrated circuit chips with different functions or processes. The integrated circuit chips are closely arranged in a three-dimensional stacking manner, and electrical connections are achieved between the integrated circuit chips through a vertical interconnect structure; The inter-chip interconnect layer is disposed between adjacent integrated circuit chips, includes multiple layers of metal interconnect lines, is made of high-density and low-resistance metal materials, and is integrated with a signal isolation structure; The power distribution network is configured to be integrated in the package substrate and regulate the power supply voltage of the integrated circuit chip through a programmable switch matrix; The heat dissipation module is connected to the multi-layer chip stack; The package substrate is configured at the bottom of the multi-layer chip stack to support the entire package structure.

[0023] The working principle of this technical solution is as follows: To implement a packaging structure for 3D integrated circuits, the present invention proposes a multi-layer chip stack, an inter-chip interconnect layer, a power distribution network, a heat dissipation module, and a package substrate; these components work together to jointly achieve an efficient and stable 3D integrated circuit package; the multi-layer chip stack realizes electrical connections between different chips through a vertical interconnect structure, thus greatly improving the integration degree and data transmission speed; the inter-chip interconnect layer is made of a high-density and low-resistance metal material, ensuring high-speed and low-loss signal transmission, and at the same time, the integrated signal isolation structure effectively avoids signal interference and improves the stability of the system; the power distribution network flexibly regulates the power supply voltage of each integrated circuit chip through a programmable switch matrix, not only meeting the power consumption requirements of different chips, but also improving the energy utilization efficiency; the heat dissipation module is tightly connected to the multi-layer chip stack, effectively dissipating the heat generated when the chip works and ensuring the stable operation of the chip; the package substrate serves as the support of the entire package structure, providing a stable mechanical support and electrical connection interface.

[0024] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment, the performance and reliability of the 3D integrated circuit package can be significantly improved; First, through the multi-layer chip stack and the vertical interconnect structure, efficient electrical connections between chips are realized, significantly improving the integration degree and data transmission speed, thus meeting the requirements of high-performance computing and low-power applications; Second, the high-density and low-resistance metal material and the integrated signal isolation structure adopted by the inter-chip interconnect layer ensure high-speed and low-loss signal transmission and effectively avoid signal interference, further enhancing the stability and reliability of the system; Third, the flexible regulation function of the power distribution network not only meets the power consumption requirements of different chips, but also improves the energy utilization efficiency by optimizing energy distribution; In addition, the tight connection between the heat dissipation module and the multi-layer chip stack effectively solves the chip heat dissipation problem and ensures the long-term stable operation of the chip; Finally, the package substrate serves as the support of the entire package structure, providing a stable mechanical support and electrical connection interface, ensuring the overall performance and reliability of the package structure.

[0025] In one embodiment, the vertical interconnect structure includes through-silicon vias and a micro-bump array. The inner wall of the through-silicon vias is plated with a copper-titanium composite layer; the micro-bump array is made of a copper-tin alloy material, the surface is covered with a nano-scale insulating coating, and is arranged in an asymmetric layout.

[0026] The working principle of this technical solution is as follows: The multi-layer chip stack forms a vertical interconnection structure through through-silicon vias and micro-bump arrays, which can achieve efficient electrical connection between chips; The through-silicon via, as a vertical channel inside and outside the chip, is plated with a copper-titanium composite layer on its inner wall, which can improve the electrical conductivity and enhance the stability and reliability of the structure; The micro-bump array uses a copper-tin alloy material and is covered with a nanoscale insulating coating. This design can ensure high-speed signal transmission, effectively avoid signal interference, and improve the overall performance of the system.

[0027] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment, through the design of the vertical interconnection structure, the electrical connection path between chips is effectively shortened, thereby reducing the signal transmission delay and increasing the data transmission rate; The copper-titanium composite layer plated on the inner wall of the through-silicon via not only enhances the electrical conductivity but also improves the stability and reliability of the structure, ensuring the reliability of the packaging structure during long-term operation; The micro-bump array uses a copper-tin alloy material and is covered with a nanoscale insulating coating, improving the signal transmission quality, effectively avoiding signal interference, and enhancing the packaging efficiency and performance of 3D integrated circuits.

[0028] In one embodiment, as Figure 2 shown, the power distribution network includes a multi-phase voltage regulation module, a three-dimensional stacked distributed capacitor array, a power supply topology mode adjustment module, and an adaptive feedback control module; The multi-phase voltage regulation module includes multiple parallel buck converters, each buck converter is independently controlled, and the buck converter supports dynamic adjustment of the output voltage in the range of 0.5V to 3.3V with a 10mV step. The three-dimensional stacked distributed capacitor array is vertically integrated by metal-insulator-metal (MIN) capacitors and embedded spiral inductors. The power supply topology mode adjustment module is used to adjust and switch the power supply topology mode based on the real-time monitoring data of the current flowing through the chip load. The adaptive feedback control module is used to adjust the output voltage of the multi-phase voltage regulation module through a proportional-integral-derivative (PID) controller.

[0029] The working principle of this technical solution is as follows: The buck converter in the multi-phase voltage regulation module independently controls the output voltage according to the preset or dynamically adjusted output voltage range (0.5V to 3.3V, with a 10mV step), providing a stable and flexible power supply for the 3D integrated circuit; The three-dimensional stacked distributed capacitor array can improve the capacitance density and response speed, stabilize the power supply voltage, and reduce voltage fluctuations through the vertical integration of MIN capacitors and embedded spiral inductors; The power supply topology mode adjustment module monitors the current flowing through the chip load in real time and dynamically adjusts the power supply topology mode according to the current change to adapt to different load requirements, which can improve the power usage efficiency and the stability of the system; The adaptive feedback control module precisely adjusts the output voltage of the multi-phase voltage regulation module through a PID controller to ensure that the output voltage always remains within the set target range, and can quickly respond even in the case of load mutation or power supply voltage fluctuation, maintaining the stability and reliability of the system.

[0030] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment, the multi-phase voltage regulation module can flexibly and stably provide the required output voltage range, meeting the precise requirements of different 3D integrated circuits for the power supply voltage; The design of the three-dimensional stacked distributed capacitor array effectively improves the capacitance density and response speed, further stabilizes the power supply voltage, and significantly reduces voltage fluctuations; The real-time monitoring and dynamic adjustment functions of the power supply topology mode adjustment module enable the power supply system to better adapt to different load requirements, improve the power usage efficiency, and enhance the stability of the system at the same time; The precise adjustment ability of the adaptive feedback control module ensures that the output voltage always remains within the set target range, and can maintain the stability and reliability of the system even under complex working conditions.

[0031] In one embodiment, the power supply topology mode adjustment module includes a current signal acquisition unit, a load fluctuation prediction unit, and a power supply topology mode switching implementation unit; The current signal acquisition unit is used to acquire the current signal of the chip load by using a Hall sensor array; The load fluctuation prediction unit is used to predict the current fluctuation data of the chip load within a future set period according to the current signal by using a long short-term memory network; The power supply topology mode switching implementation unit is used to dynamically switch the power supply topology mode according to the corresponding matching relationship between the set current fluctuation data and the switching strategy to achieve the minimum power supply path impedance; The power supply topology modes include a star topology mode, a mesh topology mode, or a hybrid topology mode.

[0032] The working principle of this technical solution is as follows: The current signal acquisition unit monitors the current changes of the chip load in real time through a high-precision Hall sensor array, and transmits the acquired current signal to the load fluctuation prediction unit; after receiving the current signal, the load fluctuation prediction unit uses the advanced long short-term memory network algorithm to perform deep learning and analysis on the current data, predicts the chip load current fluctuation trend within a set future period, and generates accurate current fluctuation prediction data, which provide a decision-making basis for the power supply topology mode switching implementation unit; according to the prediction data provided by the load fluctuation prediction unit, the power supply topology mode switching implementation unit combines the preset corresponding matching relationship between the current fluctuation data and the power supply topology mode switching strategy, makes an intelligent judgment and dynamically switches to the optimal power supply topology mode. When the load is light, it may select the star topology mode to reduce energy consumption; when the load is heavy or fluctuates greatly, it may switch to the mesh topology mode or the hybrid topology mode to ensure the stability and efficiency of power supply. Through this dynamic adjustment, the impedance of the power supply path is minimized, thereby improving the overall performance and reliability of the power supply system.

[0033] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment, the current fluctuation trend of the chip load can be monitored and predicted in real time, and the power supply topology mode can be intelligently switched according to the prediction results, thereby effectively improving the flexibility and response speed of the power supply system; in addition, by dynamically adjusting the power supply path, the impedance is minimized, which not only reduces energy consumption but also enhances the stability and efficiency of power supply.

[0034] In one embodiment, the heat dissipation module includes heat dissipation fins and heat dissipation channels; the heat dissipation fins are made of boron nitride or silicon carbide materials, and the heat dissipation channels are filled with a heat dissipation medium, which is a phase change heat dissipation material or a liquid metal heat dissipation material.

[0035] The working principle of this technical solution is as follows: The heat dissipation fins are made of high thermal conductivity materials such as boron nitride or silicon carbide, which can effectively absorb and conduct the heat generated in the 3D integrated circuit. These heat dissipation fins are designed to be compact and reasonably distributed to ensure that the heat can be quickly dispersed and transferred to the heat dissipation channels; the heat dissipation medium filled inside the heat dissipation channels, whether it is a phase change heat dissipation material or a liquid metal heat dissipation material, has excellent heat conduction performance. When the heat absorbed by the heat dissipation fins is transferred to the heat dissipation channels, these heat dissipation media will quickly respond, absorb and disperse the heat, preventing the heat from accumulating locally; the phase change heat dissipation material will undergo a phase change from solid to liquid at a specific temperature, absorbing a large amount of heat, while the liquid metal heat dissipation material, with its high fluidity and high thermal conductivity, can more effectively transfer the heat from the heat dissipation fins to the outside of the package structure and dissipate the heat to the surrounding environment through natural convection or forced convection.

[0036] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment, the design of the heat dissipation module improves the heat dissipation efficiency of the 3D integrated circuit, ensures the stability and reliability of the packaging structure, and extends the service life of the integrated circuit.

[0037] In one embodiment, the packaging substrate is a multi-layer organic interposer, which is configured with high-frequency signal transmission lines, embedded passive devices, interfaces connected to external circuits, and impedance matching circuits; the embedded passive devices include resistors, capacitors, and filters.

[0038] The working principle of this technical solution is as follows: As the core component of the 3D integrated circuit, the multi-layer organic interposer design of the packaging substrate not only provides good mechanical support but also integrates high-frequency signal transmission lines to ensure the high-speed and stable transmission of signals inside the integrated circuit; the configuration of embedded passive devices such as resistors, capacitors, and filters further optimizes the circuit performance, reduces the dependence on external components, and improves the integration and reliability of the package. The precise layout and interconnection of these passive devices on the packaging substrate significantly enhance the overall performance of the circuit; the design of the high-frequency signal transmission lines fully considers signal attenuation and interference issues, and uses low-loss materials and advanced transmission line structures to ensure the integrity and stability of signals during transmission; at the same time, the setting of the impedance matching circuit effectively avoids the generation of signal reflection and standing waves, further improving the quality of signal transmission; the design of the interfaces connected to external circuits focuses on compatibility and ease of use, enabling the 3D integrated circuit to be conveniently connected and communicate with other electronic devices. These interfaces not only support high-speed data transmission but also have good anti-interference capabilities, ensuring the stable operation of the circuit in complex environments.

[0039] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment, the design of the packaging substrate not only optimizes the packaging structure of the 3D integrated circuit but also significantly improves its electrical performance and reliability, laying a solid foundation for the wide application of 3D integrated circuits.

[0040] In one embodiment, it further includes an electromagnetic shielding layer and a stress buffer layer; the electromagnetic shielding layer is composed of a copper-ferrite composite material and is configured to cover the periphery of the integrated circuit chip; the stress buffer layer is configured at the multi-layer chip stacking interface and between the chip stack and the packaging substrate and is composed of a polyimide-silica gel mixture.

[0041] The working principle of this technical solution is as follows: The main function of the electromagnetic shielding layer is to prevent the influence of external electromagnetic interference on the integrated circuit chip and reduce the interference of electromagnetic radiation generated during the operation of the chip on the surrounding environment. The copper-ferrite composite material is selected because it has good conductivity and magnetic permeability, and can effectively absorb and shield electromagnetic waves, thus protecting the normal operation of the integrated circuit; the stress buffer layer plays a role in relieving the stress generated by the mismatch of the thermal expansion coefficients between the multi-layer chip stack and between the chip and the packaging substrate. The polyimide-silica gel mixture is used because it has good flexibility and elasticity, and can effectively absorb and disperse stress, avoiding damage to the chip due to excessive stress during the packaging process.

[0042] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment, through this structure, the electromagnetic shielding layer and the stress buffer layer cooperate together, not only improving the anti-interference ability of the 3D integrated circuit, but also enhancing the stability and reliability of its packaging structure, providing a strong guarantee for the high-performance application of the 3D integrated circuit.

[0043] A packaging method for a 3D integrated circuit, as Figure 3 shown, includes: S1: Perform preprocessing operations such as cleaning and passivation on the integrated circuit chip to obtain a preprocessed integrated circuit chip; S2: Stack the preprocessed integrated circuit chips three-dimensionally to obtain a multi-layer chip stack; S3: Fabricate an inter-chip interconnect layer between adjacent integrated circuit chips in the multi-layer chip stack to form multi-layer metal interconnect lines and signal isolation structures; S4: Generate a power distribution network in the packaging structure through photolithography and electroplating processes; S5: Connect the heat dissipation module to the multi-layer chip stack and fill the heat dissipation medium; S6: Connect the bottom of the packaging substrate to the multi-layer chip stack, and configure and fabricate high-frequency signal transmission lines, embedded passive devices, interfaces connected to external circuits, and impedance matching circuits on the packaging substrate; S7: Perform electrical performance testing and reliability testing on the packaged 3D integrated circuit.

[0044] The working principle of this technical solution is as follows: To achieve the efficient packaging of 3D integrated circuits, the present invention first preprocesses the integrated circuit chips, including operations such as cleaning and passivation, to ensure the cleanliness and good electrical performance of the chip surface; then, the preprocessed integrated circuit chips are stacked three-dimensionally to form a multi-layer chip stack, thereby improving the integration and performance of the circuit; in the multi-layer chip stack, adjacent integrated circuit chips are connected through an inter-chip interconnect layer to form multi-layer metal interconnect lines and signal isolation structures, and these interconnect lines and signal isolation structures ensure the accurate transmission of signals between chips while avoiding signal interference and leakage; to further improve the reliability and performance of the circuit, a power distribution network is generated in the packaging structure through photolithography and electroplating processes, and the power distribution network provides a stable power supply for the circuit to ensure the normal operation of the circuit; in addition, a heat dissipation module is also connected to the multi-layer chip stack and a heat dissipation medium is filled, which can effectively reduce the temperature of the circuit during operation and improve the reliability and stability of the circuit; on the packaging substrate, high-frequency signal transmission lines, embedded passive devices, interfaces connected to external circuits, and impedance matching circuits are configured, and these configurations enable the 3D integrated circuit to better connect and communicate with external circuits while improving the transmission efficiency and performance of the circuit; finally, electrical performance tests and reliability tests are carried out on the packaged 3D integrated circuit to ensure that it meets the design requirements and usage requirements, and through these tests, potential problems in the circuit can be discovered and repaired in a timely manner, thereby improving the reliability and stability of the circuit.

[0045] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment, the integration and performance of 3D integrated circuits can be significantly improved, while ensuring the stability and reliability of the circuits. First, through the pre-treatment of the integrated circuit chips, the cleanliness and good electrical performance of the chip surfaces are ensured, laying a solid foundation for the subsequent packaging work. The three-dimensional stacking design not only improves the integration of the circuits but also significantly enhances the performance of the circuits. The setting of the inter-chip interconnect layer ensures the accurate transmission of signals between chips, avoiding signal interference and leakage, thereby improving the transmission efficiency and performance of the circuits. The generation of the power distribution network provides a stable power supply for the circuits, ensuring the normal operation of the circuits and further improving the reliability of the circuits. The connection of the heat dissipation module to the multi-layer chip stack and the filling of the heat dissipation medium effectively reduce the temperature of the circuits during operation, further improving the reliability and stability of the circuits. The high-frequency signal transmission lines, embedded passive devices, interfaces connected to external circuits, and impedance matching circuits configured on the packaging substrate enable the 3D integrated circuits to better connect and communicate with external circuits, further improving the transmission efficiency and performance of the circuits. The conduct of electrical performance tests and reliability tests ensures that the packaged 3D integrated circuits meet the design requirements and usage requirements, improving the reliability and stability of the circuits.

[0046] In one embodiment, in step S2, microelectromechanical system (MEMS) positioning technology is used to align the chips to control the distance between the chips.

[0047] The working principle of this technical solution is as follows: Using MEMS positioning technology, through high-precision sensors and micro-actuators, the positions of the chips are precisely adjusted. This technology can ensure that the distance between the chips meets the design requirements, avoiding signal transmission problems or degradation of electrical performance caused by too large or too small distances. At the same time, MEMS positioning technology also has high stability and repeatability, which can greatly improve the efficiency and accuracy of the packaging process.

[0048] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment and calibrating the chips through this technology, a solid foundation is laid for the subsequent packaging steps, thereby ensuring the packaging quality and performance of the entire 3D integrated circuit.

[0049] In one embodiment, in step S4, a dual-damascene process is used to form copper interconnects, and the programmable switch matrix is integrated through a post-metalization process.

[0050] The working principle of this technical solution is as follows: The dual-damascene process is adopted. First, vias and trenches are etched in the dielectric layer formed between chips, and then copper material is filled to form interconnect lines. This process can ensure the conductivity and stability of the interconnect lines while reducing the loss of signal transmission. The subsequent metallization process is to deposit a metal layer and form a programmable switch matrix thereon, which can be connected and disconnected as needed to achieve flexible circuit configuration.

[0051] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment, the integration method not only improves the functionality and flexibility of 3D integrated circuits, but also provides strong support for their applications in fields such as high-performance computing and big data processing.

[0052] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A packaging structure of a 3D integrated circuit, characterized in that: include: Multi-layer chip stack, chip interconnect layer, power distribution network, heat dissipation module and packaging substrate; The multi-layer chip stack includes a plurality of integrated circuit chips with different functions or processes, the integrated circuit chips are closely arranged in a three-dimensional stack, and the integrated circuit chips are electrically connected through a vertical interconnection structure; The inter-chip interconnect layer is arranged between adjacent integrated circuit chips, and includes a multi-layer metal interconnect line, made of high-density, low-resistance metal material, and integrated with a signal isolation structure; The power distribution network is configured to be integrated in the package substrate and adjust the power supply voltage of the integrated circuit chip through a programmable switch matrix; The heat dissipation module is connected to the multi-layer chip stack; The packaging substrate is arranged at the bottom of the multi-layer chip stack to support the entire packaging structure.

2. The packaging structure of a 3D integrated circuit according to claim 1, characterized in that: The vertical interconnect structure includes through silicon vias and micro bump arrays. The inner wall of the through silicon via is plated with a copper-titanium composite layer; the micro bump array is made of copper-tin alloy material, the surface is covered with a nano-scale insulating coating, and is arranged asymmetrically.

3. The packaging structure of a 3D integrated circuit according to claim 1, characterized in that: The power distribution network includes a multi-phase voltage regulation module, a three-dimensional stacked distributed capacitor array, a power supply topology mode adjustment module and an adaptive feedback control module; A multi-phase voltage regulation module, including multiple buck converters connected in parallel, each buck converter is independently controlled, and the buck converter supports dynamic adjustment of output voltage in 10mV steps within the range of 0.5V to 3.3V; Three-dimensional stacked distributed capacitor arrays, vertically integrated with metal-insulator-metal (MIN) capacitors and embedded spiral inductors; A power supply topology mode adjustment module, used to adjust and switch the power supply topology mode based on real-time monitoring data of the current flowing through the chip load; An adaptive feedback control module is used to adjust the output voltage of the multi-phase voltage regulation module through a proportional-integral-derivative (PID) controller.

4. The packaging structure of a 3D integrated circuit according to claim 3, characterized in that: The power supply topology mode adjustment module includes a current signal acquisition unit, a load fluctuation prediction unit and a power supply topology mode switching implementation unit; A current signal acquisition unit, used to acquire the current signal of the chip load using a Hall sensor array; A load fluctuation prediction unit is used to predict the current fluctuation data of the chip load within a future set period according to the current signal by using a long short-term memory network; A power supply topology mode switching implementation unit, used to dynamically switch the power supply topology mode according to the corresponding matching relationship between the set current fluctuation data and the switching strategy, so as to achieve a minimized power supply path impedance; The power supply topology modes include star topology mode, mesh topology mode or hybrid topology mode.

5. The packaging structure of a 3D integrated circuit according to claim 1, characterized in that: The heat dissipation module includes heat dissipation fins and heat dissipation channels; the heat dissipation fins are made of boron nitride or silicon carbide materials, and the heat dissipation channels are filled with heat dissipation medium, which is phase change heat dissipation material or liquid metal heat dissipation material.

6. The packaging structure of a 3D integrated circuit according to claim 1, characterized in that: The packaging substrate is a multi-layer organic interposer, configured with high-frequency signal transmission lines, embedded passive devices, interfaces connected to external circuits, and impedance matching circuits; the embedded passive devices include resistors, capacitors, and filters.

7. The packaging structure of a 3D integrated circuit according to claim 1, characterized in that: It also includes an electromagnetic shielding layer and a stress buffer layer; the electromagnetic shielding layer is composed of a copper-ferrite composite material and is configured to cover the periphery of the integrated circuit chip; the stress buffer layer is configured at the multi-layer chip stacking interface and between the chip stack and the packaging substrate, and is composed of a polyimide-silicone mixture.

8. A packaging method for a 3D integrated circuit, characterized in that: include: S1: performing pretreatment operations such as cleaning and passivation on the integrated circuit chip to obtain a pretreated integrated circuit chip; S2: three-dimensionally stacking the pre-processed integrated circuit chips to obtain a multi-layer chip stack; S3: Fabricating an inter-chip interconnection layer between adjacent integrated circuit chips in the multi-layer chip stack to form a multi-layer metal interconnection line and a signal isolation structure; S4: Generate a power distribution network in the package structure through photolithography and electroplating processes; S5: connecting the heat dissipation module to the multi-layer chip stack and filling it with heat dissipation medium; S6: connecting the packaging substrate to the bottom of the multi-layer chip stack, and configuring and manufacturing a high-frequency signal transmission line, an embedded passive device, an interface connected to an external circuit, and an impedance matching circuit on the packaging substrate; S7: Conduct electrical performance test and reliability test on the packaged 3D integrated circuit.

9. The packaging method of a 3D integrated circuit according to claim 8, characterized in that: In step S2 , the chips are aligned using a micro-electromechanical system positioning technology to control the distance between the chips.

10. The packaging method of a 3D integrated circuit according to claim 8, characterized in that: In step S4, a dual damascene process is used to form copper interconnects, and the programmable switch matrix is ​​integrated through a back-end metallization process.

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