A packaging structure and packaging method for 3D integrated circuit

Abstract

The present invention belongs to the field of integrated circuit packaging technology and provides a packaging structure and packaging method for a 3D integrated circuit. The packaging structure includes: a multi-layer chip stack, an inter-chip interconnect layer, a power distribution network, a heat dissipation module, and a packaging substrate. The multi-layer chip stack includes integrated circuit chips arranged in a three-dimensional stack, and the integrated circuit chips are electrically connected via a vertical interconnect structure. The inter-chip interconnect layer is arranged between adjacent integrated circuit chips and includes multiple layers of metal interconnect lines made of high-density, low-resistance metal materials and integrated with a signal isolation structure. The power distribution network is configured to be integrated into the packaging substrate, and the supply voltage of the integrated circuit chips is adjusted via a programmable switch matrix. The heat dissipation module is connected to the multi-layer chip stack. The packaging substrate is arranged at the bottom of the multi-layer chip stack to support the entire packaging structure. The present invention facilitates the miniaturization and lightweight application of integrated circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a packaging structure and a packaging method for a 3D integrated circuit. Background Art

[0002] As electronic devices continue to develop towards miniaturization and high performance, the requirements for the integration and performance of integrated circuits are becoming increasingly higher. In the face of growing functional demands, traditional two-dimensional integrated circuit packaging methods have gradually exposed many limitations. The interconnection distance between chips is long, resulting in large signal transmission delays and increased power consumption. Due to the limitations of planar layout, it is difficult to achieve higher integration.

[0003] Therefore, three-dimensional integrated circuit packaging structures and packaging methods came into being, aiming to shorten the interconnection distance between chips by vertically stacking chips, thereby increasing signal transmission speed and reducing power consumption. This packaging method can not only effectively improve the integration level, but also meet the stringent requirements of high-performance electronic devices for integrated circuits. In the three-dimensional packaging structure, each chip is connected through vertical interconnection channels, achieving a more compact layout, while also providing a more efficient path for collaborative work between chips.

[0004] While some current packaging technologies have improved integration to a certain extent, they still face issues such as low data transmission efficiency, uneven power distribution, and heat dissipation difficulties. For example, in some multi-layer packaging structures, the interconnect technology used between chips cannot meet the requirements of high-speed data transmission. Signals are prone to attenuation and interference during transmission, affecting circuit performance. Furthermore, due to the varying power consumption of chips with different functions, accurate and efficient power distribution is difficult to achieve. As a result, some chips suffer performance limitations or even damage due to insufficient power or overvoltage. Furthermore, as integration increases, the heat generated by the chips accumulates significantly, and heat dissipation issues seriously affect chip stability and reliability.

[0005] Therefore, it is necessary to provide a packaging structure and packaging method for a 3D integrated circuit. Summary of the Invention

[0006] The present invention provides a packaging structure and packaging method for a 3D integrated circuit, aiming to overcome the shortcomings of the existing technology. The packaging volume is effectively reduced through three-dimensional stacking. The chip interconnection layer is made of high-density, low-resistance metal materials, which improves the signal transmission speed and stability and reduces energy consumption. The application of a programmable switch matrix in the power distribution network enables the supply voltage to be flexibly adjusted according to actual needs, further optimizing the performance of the integrated circuit. The effective connection of the heat dissipation module ensures good heat dissipation of the multi-layer chip stack during operation, extending the service life of the integrated circuit.

[0007] The present invention provides a packaging structure for a 3D integrated circuit, comprising:

[0008] Multi-layer chip stack, inter-chip interconnect layer, power distribution network, heat dissipation module and packaging substrate;

[0009] The multi-layer chip stack includes multiple integrated circuit chips with different functions or processes. The integrated circuit chips are closely arranged in a three-dimensional stack, and the integrated circuit chips are electrically connected through vertical interconnect structures.

[0010] The inter-chip interconnect layer is configured between adjacent integrated circuit chips and includes multi-layer metal interconnect lines made of high-density, low-resistance metal materials and integrated with signal isolation structures;

[0011] The power distribution network is configured to be integrated into the package substrate and regulate the power supply voltage of the integrated circuit chip through a programmable switch matrix;

[0012] The heat dissipation module is connected to the multi-layer chip stack;

[0013] The packaging substrate is arranged at the bottom of the multi-layer chip stack to support the entire packaging structure.

[0014] Furthermore, the vertical interconnect structure includes through-silicon vias and micro-bump arrays. The inner wall of the through-silicon via is plated with a copper-titanium composite layer; the micro-bump array is made of a copper-tin alloy material, the surface is covered with a nano-scale insulating coating, and is arranged asymmetrically.

[0015] Furthermore, the power distribution network includes a multi-phase voltage regulation module, a three-dimensional stacked distributed capacitor array, a power supply topology mode adjustment module, and an adaptive feedback control module;

[0016] A multi-phase voltage regulator module, including multiple buck converters connected in parallel, each independently controlled, with the buck converters supporting dynamic output voltage adjustment in 10mV steps from 0.5V to 3.3V;

[0017] A three-dimensional stacked distributed capacitor array consisting of metal-insulator-metal (MIN) capacitors vertically integrated with embedded spiral inductors;

[0018] A power supply topology mode adjustment module is used to adjust and switch the power supply topology mode based on real-time monitoring data of the current flowing through the chip load;

[0019] An adaptive feedback control module is used to adjust the output voltage of the multiphase voltage regulation module through a proportional-integral-derivative (PID) controller.

[0020] Furthermore, the power supply topology mode adjustment module includes a current signal acquisition unit, a load fluctuation prediction unit and a power supply topology mode switching implementation unit;

[0021] A current signal acquisition unit, used to acquire the current signal of the chip load using a Hall sensor array;

[0022] A load fluctuation prediction unit is used to predict the current fluctuation data of the chip load within a future set period based on the current signal using a long short-term memory network;

[0023] The power supply topology mode switching implementation unit is used to dynamically switch the power supply topology mode according to the corresponding matching relationship between the set current fluctuation data and the switching strategy to achieve minimized power supply path impedance; the power supply topology mode includes a star topology mode, a mesh topology mode or a hybrid topology mode.

[0024] Furthermore, the heat dissipation module includes heat dissipation fins and heat dissipation channels; the heat dissipation fins are made of boron nitride or silicon carbide material, and the heat dissipation channels are filled with heat dissipation medium, which is phase change heat dissipation material or liquid metal heat dissipation material.

[0025] Furthermore, the packaging substrate is a multi-layer organic interposer, configured with high-frequency signal transmission lines, embedded passive components, interfaces connected to external circuits, and impedance matching circuits; the embedded passive components include resistors, capacitors, and filters.

[0026] Furthermore, it also includes an electromagnetic shielding layer and a stress buffer layer; the electromagnetic shielding layer is composed of a copper-ferrite composite material and is configured to cover the periphery of the integrated circuit chip; the stress buffer layer is configured at the multi-layer chip stacking interface and between the chip stack and the packaging substrate, and is composed of a polyimide-silicone mixture.

[0027] A packaging method for a 3D integrated circuit, comprising:

[0028] S1: performing pretreatment operations such as cleaning and passivation on the integrated circuit chip to obtain a pretreated integrated circuit chip;

[0029] S2: three-dimensionally stacking the pre-processed integrated circuit chips to obtain a multi-layer chip stack;

[0030] S3: Fabricating an inter-chip interconnection layer between adjacent integrated circuit chips in the multi-layer chip stack to form a multi-layer metal interconnection line and signal isolation structure;

[0031] S4: Generate a power distribution network in the package structure through photolithography and electroplating processes;

[0032] S5: Connect the heat dissipation module to the multi-layer chip stack and fill it with heat dissipation medium;

[0033] S6: Connecting the package substrate to the bottom of the multi-layer chip stack, and configuring and manufacturing high-frequency signal transmission lines, embedded passive components, interfaces for connecting to external circuits, and impedance matching circuits on the package substrate;

[0034] S7: Conduct electrical performance and reliability tests on the packaged 3D integrated circuits.

[0035] Furthermore, in step S2 , the chips are aligned using a micro-electromechanical system positioning technology to control the distance between the chips.

[0036] Furthermore, in step S4, a dual damascene process is used to form copper interconnects, and the programmable switch matrix is ​​integrated through a back-end metallization process.

[0037] Compared with the existing technology, the present invention has the following advantages and beneficial effects: the package volume is effectively reduced through three-dimensional stacking; the chip interconnection layer is made of high-density, low-resistance metal materials, which improves the signal transmission speed and stability and reduces energy consumption; the application of programmable switch matrix in the power distribution network enables the supply voltage to be flexibly adjusted according to actual needs, further optimizing the performance of the integrated circuit; the effective connection of the heat dissipation module ensures good heat dissipation of the multi-layer chip stack during operation, extending the service life of the integrated circuit.

[0038] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0039] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0041] Figure 1 This is a schematic diagram of a 3D integrated circuit packaging module structure;

[0042] Figure 2 This is a schematic diagram of the power distribution network structure;

[0043] Figure 3 A schematic diagram of the steps of a packaging method for a 3D integrated circuit. DETAILED DESCRIPTION

[0044] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0045] The present invention provides a packaging structure for a 3D integrated circuit, such as Figure 1 Shown, including:

[0046] Multi-layer chip stack, inter-chip interconnect layer, power distribution network, heat dissipation module and packaging substrate;

[0047] The multi-layer chip stack includes multiple integrated circuit chips with different functions or processes. The integrated circuit chips are closely arranged in a three-dimensional stack, and the integrated circuit chips are electrically connected through vertical interconnect structures.

[0048] The inter-chip interconnect layer is configured between adjacent integrated circuit chips and includes multi-layer metal interconnect lines made of high-density, low-resistance metal materials and integrated with signal isolation structures;

[0049] The power distribution network is configured to be integrated into the package substrate and regulate the power supply voltage of the integrated circuit chip through a programmable switch matrix;

[0050] The heat dissipation module is connected to the multi-layer chip stack;

[0051] The packaging substrate is arranged at the bottom of the multi-layer chip stack to support the entire packaging structure.

[0052] The working principle of this technical solution is as follows: In order to realize a packaging structure of a 3D integrated circuit, the present invention proposes a multi-layer chip stack, an inter-chip interconnection layer, a power distribution network, a heat dissipation module and a packaging substrate; these components work together to realize efficient and stable 3D integrated circuit packaging; the multi-layer chip stack realizes electrical connection between different chips through a vertical interconnection structure, thereby greatly improving the integration and data transmission speed; the inter-chip interconnection layer is made of high-density, low-resistance metal material, ensuring high-speed and low-loss transmission of signals, while the integrated signal isolation structure effectively avoids signal interference and improves the stability of the system; the power distribution network flexibly adjusts the power supply voltage of each integrated circuit chip through a programmable switch matrix, which not only meets the power consumption requirements of different chips, but also improves energy utilization efficiency; the heat dissipation module is tightly connected to the multi-layer chip stack, effectively dissipating the heat generated by the chip during operation, ensuring the stable operation of the chip; the packaging substrate serves as a support for the entire packaging structure, providing stable mechanical support and electrical connection interface.

[0053] The beneficial effects of the above technical solution are as follows: the solution provided in this embodiment can significantly improve the performance and reliability of 3D integrated circuit packaging; first, through the multi-layer chip stack and vertical interconnection structure, efficient electrical connection between chips is achieved, which significantly improves the integration and data transmission speed, thereby meeting the needs of high-performance computing and low-power applications; secondly, the high-density, low-resistance metal materials and integrated signal isolation structure used in the chip interconnection layer ensure high-speed, low-loss transmission of signals, and effectively avoid signal interference, further improving the stability and reliability of the system; thirdly, the flexible adjustment function of the power distribution network not only meets the power consumption requirements of different chips, but also improves energy utilization efficiency by optimizing energy distribution; in addition, the close connection between the heat dissipation module and the multi-layer chip stack effectively solves the chip heat dissipation problem and ensures the long-term stable operation of the chip; finally, the packaging substrate, as the support of the entire packaging structure, provides stable mechanical support and electrical connection interface, ensuring the overall performance and reliability of the packaging structure.

[0054] In one embodiment, the vertical interconnect structure includes a through silicon via (TSV) and a microbump array. The inner wall of the TSV is plated with a copper-titanium composite layer. The microbump array is made of a copper-tin alloy material, the surface of which is covered with a nano-scale insulating coating and is arranged asymmetrically.

[0055] The working principle of this technical solution is as follows: the vertical interconnection structure formed by the multi-layer chip stack through silicon vias and micro-bump arrays can achieve efficient electrical connection between chips; the silicon via serves as a vertical channel between the inside and outside of the chip, and the copper-titanium composite layer plated on its inner wall can improve the conductivity and enhance the stability and reliability of the structure; while the micro-bump array uses a copper-tin alloy material with a nano-scale insulating coating on the surface. This design can ensure high-speed signal transmission, effectively avoid signal interference, and improve the overall performance of the system.

[0056] The beneficial effects of the above technical solution are as follows: by adopting the solution provided in this embodiment, the electrical connection path between chips is effectively shortened through the design of the vertical interconnection structure, thereby reducing the delay of signal transmission and improving the data transmission rate; the copper-titanium composite layer plated on the inner wall of the silicon through-hole not only enhances the conductive performance, but also improves the stability and reliability of the structure, ensuring the reliability of the packaging structure in long-term operation; the micro-bump array adopts copper-tin alloy material and is covered with a nano-level insulating coating, which improves the signal transmission quality, effectively avoids signal interference, and improves the packaging efficiency and performance of 3D integrated circuits.

[0057] In one embodiment, Figure 2 As shown, the power distribution network includes a multi-phase voltage regulation module, a three-dimensional stacked distributed capacitor array, a power supply topology mode adjustment module and an adaptive feedback control module;

[0058] A multi-phase voltage regulator module, including multiple buck converters connected in parallel, each independently controlled, with the buck converters supporting dynamic output voltage adjustment in 10mV steps from 0.5V to 3.3V;

[0059] A three-dimensional stacked distributed capacitor array consisting of metal-insulator-metal (MIN) capacitors vertically integrated with embedded spiral inductors;

[0060] A power supply topology mode adjustment module is used to adjust and switch the power supply topology mode based on real-time monitoring data of the current flowing through the chip load;

[0061] An adaptive feedback control module is used to adjust the output voltage of the multiphase voltage regulation module through a proportional-integral-derivative (PID) controller.

[0062] The technical solution works as follows: The buck converter in the multi-phase voltage regulation module independently controls the output voltage within a preset or dynamically adjusted output voltage range (0.5V to 3.3V, in 10mV steps), providing a stable and flexible power supply for 3D integrated circuits. The three-dimensional stacked distributed capacitor array, through the vertical integration of MIN capacitors and embedded spiral inductors, can improve capacitance density and response speed, stabilize the power supply voltage, and reduce voltage fluctuations. The power supply topology mode adjustment module monitors the current flowing through the chip load in real time and dynamically adjusts the power supply topology mode based on current changes to adapt to different load requirements, thereby improving power efficiency and system stability. The adaptive feedback control module uses a PID controller to precisely adjust the output voltage of the multi-phase voltage regulation module, ensuring that the output voltage always remains within the set target range. Even in the event of sudden load changes or power supply voltage fluctuations, it can respond quickly to maintain system stability and reliability.

[0063] The beneficial effects of the above technical solution are as follows: by adopting the solution provided in this embodiment, the multi-phase voltage regulation module can flexibly and stably provide the required output voltage range to meet the precise requirements of different 3D integrated circuits for power supply voltage; the design of the three-dimensional stacked distributed capacitor array effectively improves the capacitance density and response speed, further stabilizes the power supply voltage, and significantly reduces voltage fluctuations; the real-time monitoring and dynamic adjustment functions of the power supply topology mode adjustment module enable the power supply system to better adapt to different load requirements, improve power supply efficiency, and also enhance the stability of the system; the precise adjustment capability of the adaptive feedback control module ensures that the output voltage is always maintained within the set target range, and the stability and reliability of the system can be maintained even under complex working conditions.

[0064] In one embodiment, the power supply topology mode adjustment module includes a current signal acquisition unit, a load fluctuation prediction unit, and a power supply topology mode switching implementation unit;

[0065] A current signal acquisition unit, used to acquire the current signal of the chip load using a Hall sensor array;

[0066] A load fluctuation prediction unit is used to predict the current fluctuation data of the chip load within a future set period based on the current signal using a long short-term memory network;

[0067] The power supply topology mode switching implementation unit is used to dynamically switch the power supply topology mode according to the corresponding matching relationship between the set current fluctuation data and the switching strategy to achieve minimized power supply path impedance; the power supply topology mode includes a star topology mode, a mesh topology mode or a hybrid topology mode.

[0068] The working principle of this technical solution is as follows: the current signal acquisition unit uses a high-precision Hall sensor array to monitor the current changes of the chip load in real time and transmits the collected current signal to the load fluctuation prediction unit; after receiving the current signal, the load fluctuation prediction unit uses an advanced long-short-term memory network algorithm to perform deep learning and analysis on the current data, predict the chip load current fluctuation trend within the future set period, and generate accurate current fluctuation prediction data. This data provides a decision-making basis for the power supply topology mode switching implementation unit; the power supply topology mode switching implementation unit intelligently judges and dynamically switches to the optimal power supply topology mode based on the prediction data provided by the load fluctuation prediction unit, combined with the corresponding matching relationship between the preset current fluctuation data and the power supply topology mode switching strategy. When the load is light, the star topology mode may be selected to reduce energy consumption; when the load is heavy or the fluctuation is large, it may switch to the mesh topology mode or the hybrid topology mode to ensure the stability and efficiency of the power supply. Through this dynamic adjustment, the power supply path impedance is minimized, thereby improving the overall performance and reliability of the power supply system.

[0069] The beneficial effects of the above technical solution are: by adopting the solution provided in this embodiment, the current fluctuation trend of the chip load can be monitored and predicted in real time, and the power supply topology mode can be intelligently switched according to the prediction results, thereby effectively improving the flexibility and response speed of the power supply system; in addition, by dynamically adjusting the power supply path, the impedance is minimized, which not only reduces energy consumption but also enhances the stability and efficiency of the power supply.

[0070] In one embodiment, the heat dissipation module includes heat dissipation fins and heat dissipation channels; the heat dissipation fins are made of boron nitride or silicon carbide material, and the heat dissipation channels are filled with heat dissipation medium, which is phase change heat dissipation material or liquid metal heat dissipation material.

[0071] The working principle of this technical solution is as follows: the heat sink fins are made of high thermal conductivity materials such as boron nitride or silicon carbide, which can effectively absorb and conduct the heat generated in the 3D integrated circuit. These heat sink fins are designed to be compact and reasonably distributed to ensure that the heat can be quickly dispersed and transferred to the heat dissipation channel; the heat dissipation medium filled in the heat dissipation channel, whether it is a phase change heat dissipation material or a liquid metal heat dissipation material, has excellent thermal conductivity. When the heat absorbed by the heat sink fins is transferred to the heat dissipation channel, these heat dissipation media will respond quickly, absorb and disperse the heat, and prevent heat from accumulating locally; the phase change heat dissipation material will undergo a phase change when it reaches a specific temperature, from solid to liquid, absorbing a large amount of heat, while the liquid metal heat dissipation material, with its high fluidity and high thermal conductivity, can more effectively transfer heat from the heat sink fins to the outside of the packaging structure, and dissipate the heat to the surrounding environment through natural convection or forced convection.

[0072] The beneficial effects of the above technical solution are: by adopting the solution provided in this embodiment, the design of the heat dissipation module improves the heat dissipation efficiency of the 3D integrated circuit, ensures the stability and reliability of the packaging structure, and extends the service life of the integrated circuit.

[0073] In one embodiment, the packaging substrate is a multi-layer organic interposer, configured with high-frequency signal transmission lines, embedded passive components, interfaces connected to external circuits, and impedance matching circuits; the embedded passive components include resistors, capacitors, and filters.

[0074] The working principle of this technical solution is as follows: The packaging substrate, as the core component of the 3D integrated circuit, features a multi-layer organic interposer design that not only provides excellent mechanical support but also integrates high-frequency signal transmission lines, ensuring high-speed and stable signal transmission within the integrated circuit. The configuration of embedded passive components such as resistors, capacitors, and filters further optimizes circuit performance, reduces reliance on external components, and improves the integration and reliability of the package. The precise layout and interconnection of these passive components on the packaging substrate significantly enhances the overall performance of the circuit. The design of the high-frequency signal transmission lines fully considers signal attenuation and interference, utilizing low-loss materials and advanced transmission line structures to ensure signal integrity and stability during transmission. Simultaneously, the provision of impedance matching circuits effectively avoids signal reflections and standing waves, further improving signal transmission quality. The interface design for connecting to external circuits focuses on compatibility and ease of use, enabling the 3D integrated circuit to easily connect and communicate with other electronic devices. These interfaces not only support high-speed data transmission but also have excellent anti-interference capabilities, ensuring stable operation of the circuit in complex environments.

[0075] The beneficial effects of the above technical solution are: by adopting the solution provided in this embodiment, the design of the packaging substrate not only optimizes the packaging structure of the 3D integrated circuit, but also significantly improves its electrical performance and reliability, laying a solid foundation for the widespread application of 3D integrated circuits.

[0076] In one embodiment, it also includes an electromagnetic shielding layer and a stress buffer layer; the electromagnetic shielding layer is composed of a copper-ferrite composite material and is configured to cover the periphery of the integrated circuit chip; the stress buffer layer is configured at the multi-layer chip stacking interface and between the chip stack and the packaging substrate, and is composed of a polyimide-silicone mixture.

[0077] The working principle of this technical solution is as follows: The electromagnetic shielding layer's primary function is to prevent external electromagnetic interference from affecting the integrated circuit chip and to reduce the impact of electromagnetic radiation generated by the chip during operation on the surrounding environment. The copper-ferrite composite material was chosen for its excellent electrical conductivity and magnetic permeability, effectively absorbing and shielding electromagnetic waves, thereby protecting the normal operation of the integrated circuit. The stress buffer layer mitigates stress caused by thermal expansion mismatches between the multi-layer chip stack and between the chip and the packaging substrate. A polyimide-silicone blend was used for its excellent flexibility and elasticity, effectively absorbing and dissipating stress, preventing damage to the chip due to excessive stress during the packaging process.

[0078] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, through this structure, the electromagnetic shielding layer and the stress buffer layer work together, which not only improves the anti-interference ability of the 3D integrated circuit, but also enhances the stability and reliability of its packaging structure, providing a strong guarantee for the high-performance application of the 3D integrated circuit.

[0079] A packaging method for a 3D integrated circuit, such as Figure 3 Shown, including:

[0080] S1: performing pretreatment operations such as cleaning and passivation on the integrated circuit chip to obtain a pretreated integrated circuit chip;

[0081] S2: three-dimensionally stacking the pre-processed integrated circuit chips to obtain a multi-layer chip stack;

[0082] S3: Fabricating an inter-chip interconnection layer between adjacent integrated circuit chips in the multi-layer chip stack to form a multi-layer metal interconnection line and signal isolation structure;

[0083] S4: Generate a power distribution network in the package structure through photolithography and electroplating processes;

[0084] S5: Connect the heat dissipation module to the multi-layer chip stack and fill it with heat dissipation medium;

[0085] S6: Connecting the package substrate to the bottom of the multi-layer chip stack, and configuring and manufacturing high-frequency signal transmission lines, embedded passive components, interfaces for connecting to external circuits, and impedance matching circuits on the package substrate;

[0086] S7: Conduct electrical performance and reliability tests on the packaged 3D integrated circuits.

[0087] The working principle of this technical solution is as follows: in order to achieve efficient packaging of 3D integrated circuits, the present invention first pre-processes the integrated circuit chips, including operations such as cleaning and passivation, to ensure the cleanliness of the chip surface and good electrical performance; then, the pre-processed integrated circuit chips are three-dimensionally stacked to form a multi-layer chip stack, thereby improving the integration and performance of the circuit; in the multi-layer chip stack, adjacent integrated circuit chips are connected through inter-chip interconnection layers, forming multi-layer metal interconnection lines and signal isolation structures, which ensure the accurate transmission of signals between chips while avoiding signal interference and leakage; in order to further improve the reliability and performance of the circuit, a power distribution network is generated in the packaging structure through photolithography and electroplating processes, and the power distribution network is connected to the chip by the chip interconnection layer. The distribution network provides a stable power supply for the circuit, ensuring the normal operation of the circuit; in addition, the heat dissipation module is connected to the multi-layer chip stack and filled with heat dissipation medium, which can effectively reduce the temperature of the circuit during operation and improve the reliability and stability of the circuit; on the packaging substrate, high-frequency signal transmission lines, embedded passive components, interfaces for connecting to external circuits, and impedance matching circuits are configured. These configurations enable the 3D integrated circuit to better connect and communicate with external circuits, while improving the transmission efficiency and performance of the circuit; finally, the packaged 3D integrated circuit is subjected to electrical performance testing and reliability testing to ensure that it meets the design requirements and usage requirements. Through these tests, potential problems in the circuit can be discovered and repaired in a timely manner, thereby improving the reliability and stability of the circuit.

[0088] The beneficial effects of the above technical solution are as follows: the solution provided by this embodiment can significantly improve the integration and performance of 3D integrated circuits, while ensuring the stability and reliability of the circuit; first, by pre-processing the integrated circuit chip, the cleanliness of the chip surface and good electrical performance are ensured, laying a solid foundation for subsequent packaging work; the three-dimensional stacking design not only improves the integration of the circuit, but also significantly improves the performance of the circuit; the setting of the interconnection layer between chips ensures the accurate transmission of signals between chips, avoids signal interference and leakage, and thus improves the transmission efficiency and performance of the circuit; the generation of the power distribution network provides a stable power supply for the circuit The connection between the heat dissipation module and the multi-layer chip stack, as well as the filling of the heat dissipation medium, effectively reduces the temperature of the circuit during operation, further improving the reliability and stability of the circuit; the high-frequency signal transmission lines, embedded passive components, interfaces connected to external circuits, and impedance matching circuits configured on the packaging substrate enable the 3D integrated circuit to better connect and communicate with external circuits, further improving the transmission efficiency and performance of the circuit; the electrical performance test and reliability test ensure that the packaged 3D integrated circuit meets the design requirements and usage requirements, thereby improving the reliability and stability of the circuit.

[0089] In one embodiment, in step S2 , the chips are aligned using a micro-electromechanical system positioning technology to control the distance between the chips.

[0090] The working principle of this technical solution is as follows: using micro-electromechanical system positioning technology, the position of the chip is precisely adjusted through high-precision sensors and micro-actuators. This technology can ensure that the spacing between chips meets the design requirements and avoid signal transmission problems or electrical performance degradation caused by excessive or insufficient spacing. At the same time, micro-electromechanical system positioning technology also has high stability and repeatability, which can greatly improve the efficiency and accuracy of the packaging process.

[0091] The beneficial effect of the above technical solution is: by adopting the solution provided by this embodiment, the chip is calibrated through this technology, which lays a solid foundation for the subsequent packaging steps, thereby ensuring the packaging quality and performance of the entire 3D integrated circuit.

[0092] In one embodiment, in step S4, a dual damascene process is used to form copper interconnects, and the programmable switch matrix is ​​integrated through a back-end metallization process.

[0093] The working principle of this technical solution is as follows: using a dual-damascene process, through holes and wire grooves are first etched in the dielectric layer formed between the chips, and then filled with copper material to form interconnects. This process can ensure the conductivity and stability of the interconnects while reducing signal transmission losses; the back-end metallization process deposits a metal layer and forms a programmable switch matrix on it. The matrix can be connected and disconnected as needed, thereby achieving flexible circuit configuration.

[0094] The beneficial effect of the above technical solution is: by adopting the solution provided by this embodiment, the integration method not only improves the functionality and flexibility of 3D integrated circuits, but also provides strong support for their application in high-performance computing, big data processing and other fields.

[0095] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A packaging structure for a 3D integrated circuit, characterized in that: include: Multi-layer chip stack, inter-chip interconnect layer, power distribution network, heat dissipation module and packaging substrate; The multi-layer chip stack includes multiple integrated circuit chips with different functions or processes. The integrated circuit chips are closely arranged in a three-dimensional stack, and the integrated circuit chips are electrically connected through vertical interconnect structures. The inter-chip interconnect layer is configured between adjacent integrated circuit chips and includes multi-layer metal interconnect lines made of high-density, low-resistance metal materials and integrated with signal isolation structures; The power distribution network is configured to be integrated into the package substrate and regulate the power supply voltage of the integrated circuit chip through a programmable switch matrix; The power distribution network includes a multi-phase voltage regulation module, a three-dimensional stacked distributed capacitor array, a power supply topology mode adjustment module, and an adaptive feedback control module; A multi-phase voltage regulator module, including multiple buck converters connected in parallel, each independently controlled, with the buck converters supporting dynamic output voltage adjustment in 10mV steps from 0.5V to 3.3V; A three-dimensional stacked distributed capacitor array consisting of vertically integrated metal-insulator-metal (MIM) capacitors and embedded spiral inductors; A power supply topology mode adjustment module is used to adjust and switch the power supply topology mode based on real-time monitoring data of the current flowing through the chip load; an adaptive feedback control module for adjusting the output voltage of the multiphase voltage regulation module through a proportional-integral-derivative (PID) controller; The heat dissipation module is connected to the multi-layer chip stack; The packaging substrate is arranged at the bottom of the multi-layer chip stack to support the entire packaging structure.

2. The packaging structure of a 3D integrated circuit according to claim 1, wherein: The vertical interconnect structure includes through-silicon vias and micro-bump arrays. The inner wall of the through-silicon via is plated with a copper-titanium composite layer; the micro-bump array is made of copper-tin alloy material, the surface is covered with a nano-scale insulating coating, and is arranged asymmetricly.

3. The packaging structure of a 3D integrated circuit according to claim 1, wherein: The power supply topology mode adjustment module includes a current signal acquisition unit, a load fluctuation prediction unit and a power supply topology mode switching implementation unit; A current signal acquisition unit, used to acquire the current signal of the chip load using a Hall sensor array; A load fluctuation prediction unit is used to predict the current fluctuation data of the chip load within a future set period based on the current signal using a long short-term memory network; A power supply topology mode switching implementation unit is used to dynamically switch the power supply topology mode according to the corresponding matching relationship between the set current fluctuation data and the switching strategy to achieve minimized power supply path impedance; The power supply topology modes include star topology mode, mesh topology mode or hybrid topology mode.

4. The packaging structure of a 3D integrated circuit according to claim 1, wherein: The heat dissipation module includes heat dissipation fins and heat dissipation channels; the heat dissipation fins are made of boron nitride or silicon carbide materials, and the heat dissipation channels are filled with heat dissipation medium, which is phase change heat dissipation material or liquid metal heat dissipation material.

5. The packaging structure of a 3D integrated circuit according to claim 1, wherein: The packaging substrate is a multi-layer organic interposer, equipped with high-frequency signal transmission lines, embedded passive components, interfaces for connecting to external circuits, and impedance matching circuits; the embedded passive components include resistors, capacitors, and filters.

6. The packaging structure of a 3D integrated circuit according to claim 1, wherein: It also includes an electromagnetic shielding layer and a stress buffer layer; the electromagnetic shielding layer is composed of a copper-ferrite composite material and is configured to cover the periphery of the integrated circuit chip; the stress buffer layer is configured at the multi-layer chip stacking interface and between the chip stack and the packaging substrate, and is composed of a polyimide-silicone mixture.

7. A packaging method for manufacturing the packaging structure of a 3D integrated circuit according to any one of claims 1 to 6, characterized in that: include: S1: performing pretreatment operations such as cleaning and passivation on the integrated circuit chip to obtain a pretreated integrated circuit chip; S2: three-dimensionally stacking the pre-processed integrated circuit chips to obtain a multi-layer chip stack; S3: Fabricating an inter-chip interconnection layer between adjacent integrated circuit chips in the multi-layer chip stack to form a multi-layer metal interconnection line and signal isolation structure; S4: Generate a power distribution network in the package structure through photolithography and electroplating processes; S5: Connect the heat dissipation module to the multi-layer chip stack and fill it with heat dissipation medium; S6: Connecting the package substrate to the bottom of the multi-layer chip stack, and configuring and manufacturing high-frequency signal transmission lines, embedded passive components, interfaces for connecting to external circuits, and impedance matching circuits on the package substrate; S7: Perform electrical performance and reliability tests on the packaged 3D integrated circuits.

8. The packaging method of a 3D integrated circuit according to claim 7, characterized in that: In step S2 , the chips are aligned using a micro-electromechanical system positioning technology to control the distance between the chips.

9. The packaging method of a 3D integrated circuit according to claim 7, wherein: In step S4, a dual damascene process is used to form copper interconnects, and the programmable switch matrix is ​​integrated through a back-end metallization process.

Images