3D integrated circuit device

Abstract

In one aspect, a 3D IC device is provided, comprising: a package routing plane comprising a global VDD voltage node and a global VSS voltage node; a die stack disposed on the package wiring plane and including a plurality of stacked dies stacked on each other; a metal interconnect layer disposed atop a top stacked die in the die stack; and a through interconnect extending vertically through each stacked die in the stack of dies and connecting the metal interconnect layer to a global VDD voltage node; wherein each stacked die in the die stack has a bottom surface and a top surface, a local VDD voltage contact on the top surface thereof, and a local VSS voltage contact on the bottom surface thereof, and wherein the stacked dies in the die stack are voltage stacked between a global VDD voltage node and a global VSS voltage node.

Description

Technical Field

[0001] This disclosure relates to a 3D integrated circuit device. This disclosure also relates to a method for forming a 3D integrated circuit device. Background Technology

[0002] The semiconductor industry has been striving to shrink device size to achieve higher density and performance circuits. Scaling up by reducing feature size has become increasingly challenging and costly. Therefore, there is growing interest in the design and integration techniques of 3D integrated circuits (3D ICs), which consist of multiple dies stacked on top of each other. For example, a system-on-a-chip (SoC) implemented as a 3D IC can include multiple stacked dies, each configured to perform a given circuit function (e.g., logic or memory).

[0003] However, one problem with 3D ICs is that power density increases with the number of dies in the stack, which in turn can increase IR drop and require more power bump resources in the package proportional to the number of dies. Summary of the Invention

[0004] The object of this invention is to provide an improved 3D IC device that allows for an increase in the number of stacked dies (i.e., the number of die layers in a 3DIC) and a reduction in current density and the number of package power bumps. Another object is to enable 3DICs with a larger number of die layers to be implemented at a lower cost compared to conventional 3D IC designs.

[0005] According to a first aspect of the present invention, a 3D integrated circuit (IC) device is provided, comprising:

[0006] The package routing plane includes the global VDD voltage node and the global VSS voltage node;

[0007] Die stacks, which are arranged on the package wiring plane and include multiple stacked dies stacked on top of each other;

[0008] A metal interconnect layer is disposed on top of the top stacked die in the die stack; and

[0009] A through interconnect extends vertically through each stacked die in the die stack and connects the metal interconnect layer to the global VDD voltage node;

[0010] Each of the stacked dies in the die stack has a bottom surface and a top surface, a local VDD voltage contact on its top surface and a local VSS voltage contact on its bottom surface.

[0011] In this die stack, the local VSS voltage contact of the bottom stacked die is connected to the global VSS voltage node, the local VSS voltage contact of each other stacked die is connected to the local VDD voltage contact of the adjacent stacked die below it, and the local VDD voltage contact of the top stacked die is connected to the through interconnect via a metal interconnect layer, so that the stacked dies in the die stack are voltage-stacking between the global VDD voltage node and the global VSS voltage node.

[0012] Thus, each stacked die in the die stack can be associated with or included in a corresponding voltage domain in the voltage stack, i.e., powered by the corresponding local VDD and VSS voltages. The package voltage (i.e., the voltage difference between the global VDD and VSS voltages) can therefore be divided in series across the stacked dies so that each die sees a portion of the package voltage, much like a voltage divider.

[0013] Therefore, this 3D IC can use a higher package voltage at a lower current, which allows for a reduction in the voltage drop across the power transmission network (PDN), as it is proportional to the current and the PDN resistance. This reduces the voltage drop across the PDN, which leads to footprint and financial penalties, without increasing the number of package bumps.

[0014] Voltage stacking can be implemented using an interconnect structure with relatively low overall complexity (i.e., a metal interconnect layer on top of the top die and a through interconnect that extends through each die in the die stack to directly connect the metal interconnect layer to the global VDD voltage node (thus electrically bypassing the local connections within each die).

[0015] The metal interconnect layer can be simply configured to short through interconnects to local VDD contacts of the top stacked die. The metal interconnect layer can be implemented, for example, as a redistribution layer (e.g., a single metal layer), which can be formed on top of the top stacked die using a low-complexity and low-cost process after the die stack is formed.

[0016] Through-silicon interconnects may include, for example, multiple through-silicon vias (TSVs) that are vertically stacked on top of each other and each extends through a corresponding die in the die stack. In this disclosure, the term "TSV" refers to a via structure (i.e., a vertical electrical interconnect) extending through a die substrate, regardless of the type of semiconductor material of the substrate, and is consistent with its typical use in the semiconductor industry.

[0017] In some embodiments, each stacked die in the die stack has a front side and a back side, and includes a front-end line (FEOL) structure and a front-end back-end line (BEOL) interconnect structure disposed on the FEOL structure, wherein the stacked dies are stacked such that the front-end BEOL interconnect structures face the same direction. The stacked dies can therefore be stacked on top of each other in a conventional manner (face-to-back).

[0018] In some embodiments, the front side is the bottom surface of the stacked dies. Therefore, the stacked dies can be arranged such that their respective front sides and front BEOL structures face the package routing plane. This can be particularly advantageous in embodiments where the 3D IC also includes a substrate die as discussed below, which includes a backside power distribution network disposed thereon facing the package routing plane. The backside PDN of the substrate die can then be conveniently connected to the associated VSS and VDD power supply voltage nodes of the package routing plane, while the bottom stacked dies can be arranged face-to-face with the substrate die.

[0019] In some embodiments, the front side corresponds to the top surface of the stacked dies. Therefore, the stacked dies can alternatively be arranged with their respective back sides facing the package wiring plane. This can facilitate the rational fabrication of die stacks because the metal interconnect layers can be formed at the wafer level on top of the stacked dies before the dies are cut and stacked to form the die stack.

[0020] In some embodiments, stacked dies are essentially the same die.

[0021] Configuring stacked dies to be (essentially) identical further contributes to the low-cost and low-complexity implementation of 3D ICs. Furthermore, stacked dies can be fabricated in a reasonable manner using (essentially) the same set of designs and masks. Additionally, identical stacked dies facilitate the uniform distribution of package voltage (and therefore power) across the stacked dies. This, in turn, reduces the need to incorporate voltage regulation circuitry into each stacked die (although in some implementations, a simple voltage regulation circuit can be useful, as discussed below).

[0022] In some embodiments, the stacked die is a memory die.

[0023] 3DIC can therefore implement memory circuits with multiple stacked memory dies. The base die (and thus the control and / or I / O die of concern to the memory) discussed below can implement the peripheral circuitry of the memory circuit. Memory arrays are a very suitable type of circuit for stacking implementation because they can be divided into multiple subarrays with the same layout. Therefore, each stacked die can implement a corresponding subarray of the memory array, where optionally, the stacked dies / subarrays can have (substantially) identical layouts. Furthermore, implementing stacked dies as memory dies can facilitate power balancing, for example by distributing read / write activity across all stacked (memory) dies, or by implementing redundant read / write operations.

[0024] In some embodiments, the stacked dies are logic dies.

[0025] 3DICs can therefore implement logic on logic circuits. The base die discussed below can implement a set of primary logic functions and / or act as a control and / or I / O die for stacked logic dies, and the stacked dies can implement auxiliary logic functions, wherein optionally, the stacked dies can have (substantially) the same layout and be configured to implement the same logic functions. Stacked dies can, for example, implement accelerators (e.g., for accelerating matrix multiplication or other complex computational tasks). The activity of accelerators tends to be more deterministic than the activity of general logic circuits, and thus can facilitate power balancing.

[0026] In some embodiments, the die stack further includes a base die and the stacked dies are stacked on top of the base die.

[0027] The base die is configured as a control and / or I / O die in the die stack and is connected to each stacked die.

[0028] The substrate die is connected between a second VSS voltage node and a local VDD voltage node in the package wiring plane. The local VDD voltage node is configured to supply a lower VDD voltage than the global VDD voltage node, and the second VSS voltage node is either a global VSS voltage node or a local VSS voltage node.

[0029] In addition to stacked dies (e.g., memory or logic dies, optionally the same), die stacks may include base dies that are disposed at the bottom of the die stack and configured as controllers or master units for the stacked dies above.

[0030] By connecting the base die between the local VDD voltage node and the global / local (i.e., "second") VSS voltage node, the base die can be designed with greater freedom and less concern about power consumption and voltage drop relative to the stacked dies, because the base die does not need to be included in the voltage stack. Therefore, it is not necessary to customize the global VDD and VSS voltages and the stacked dies so that the VSS voltage at the local VSS voltage contact of the bottom stacked die matches the VDD supply voltage requirements of the base die.

[0031] In some embodiments, the 3D IC further includes:

[0032] A set of output signal routing structures, extending through the die stack and configured to route output signals from the base die to each stacked die, and

[0033] A set of input signal routing structures configured to route input signals from stacked dies to base dies.

[0034] Input and output signals can therefore be routed using respective sets of signal routing structures that extend through the die stack (e.g., between the base die and each corresponding stacked die). Thus, the base die can exchange control and / or I / O signals with the stacked dies, for example, to achieve the intended circuit function.

[0035] Optionally, in some embodiments, the set of input and output signal routing structures may terminate on the top surface of the top stacked die, and the metal interconnect layer may be arranged to disconnect from the output signal routing structure and short-circuit the input signal routing structure to a local VDD voltage contact of the top stacked die.

[0036] Therefore, the floating of the input of the top stacked die (on which there are no other stacked dies) can be avoided, as the input can be fixed to the local VDD supply voltage of the top stacked die (which corresponds to the global VDD supply voltage).

[0037] This also prevents a short circuit between the output signal routing structure and the local VDD supply voltage of the top stacked die. Otherwise, this could lead to incorrect data and / or increased power consumption, for example, by causing a race between the output signal and the drive buffer / logic of the stacked die.

[0038] In some embodiments, the substrate die has a front side facing the stacked die and a back side facing the package wiring plane, and includes an FEOL structure, a front (BEOL) interconnect structure disposed on the FEOL structure (on the front side of the substrate die), and a back-side power distribution network disposed on the back side of the substrate die and connected to a local VDD voltage node and a second VSS voltage node.

[0039] The back-side PDN of the substrate die can therefore be easily connected to the local VDD voltage node and the second (i.e., global or local) VSS voltage node of the package routing plane. Simultaneously, contention between power routing sources and signal routing sources in the front-side interconnect structure of the substrate die can be reduced. As discussed above, this configuration of the substrate die can also be beneficial when combined with stacked dies arranged so that their respective front sides face the package routing plane.

[0040] In some embodiments, the local VSS voltage contacts of the bottom stacked die are connected to the global VSS power voltage node via the front interconnect structure and the back power distribution network of the base die.

[0041] In some embodiments, the stacked dies are configured to have substantially uniform power consumption in the operating devices. This can contribute to stable and consistent operation of the circuitry of each stacked die and to a uniform distribution of package voltage across the stacked dies.

[0042] According to a second aspect of the present invention, a method for forming a 3D IC device is provided, the method comprising:

[0043] A die stack consisting of multiple stacked dies stacked on top of each other is arranged on the package routing plane, which includes the global VDD voltage node and the global VSS voltage node.

[0044] Each of the stacked dies in the die stack has a bottom surface and a top surface, a local VDD voltage contact on its top surface and a local VSS voltage contact on its bottom surface.

[0045] The local VSS voltage contact of the bottom stacked die in the die stack is connected to the global VSS voltage node, and the local VSS voltage contact of each other stacked die is connected to the local VDD voltage contact of the adjacent stacked die below it.

[0046] The die stack includes a through interconnect that extends vertically through each stacked die in the die stack and connects to the global VDD voltage node; and

[0047] A metal interconnect layer is formed on top of the top stacked die to connect the through interconnect to the local VDD voltage contact of the top stacked die.

[0048] The second aspect of the method thus enables the manufacture of a 3DIC according to the first aspect, which has the effects discussed above. Specifically, the voltage stack can be implemented using a process with relatively low overall complexity; through interconnects are shorted to local VDD contacts of the top stack die by forming a metal interconnect layer on top of the top stack die. The metal interconnect layer can be implemented, for example, as a redistribution layer (e.g., a single metal layer).

[0049] Die stacks can be formed by stacking multiple wafers on top of each other to form a wafer stack and then dicing the wafer stack to form individual / diced die stacks, each wafer comprising a corresponding stacked die.

[0050] A metal interconnect layer can be formed on top of the stacked dies before the die stack is arranged on the package wiring plane. For example, the metal interconnect layer can be formed on the top die in the aforementioned wafer stack before dicing.

[0051] Unless otherwise stated, any other features, effects, and examples discussed in this disclosure with respect to the first aspect generally apply to the second aspect. Attached Figure Description

[0052] The foregoing contents, additional features, embodiments, characteristics, and advantages of this disclosure can be better understood through the following illustrative and non-limiting detailed description with reference to the accompanying drawings.

[0053] Figure 1 This is a schematic cross-sectional view of a 3D IC.

[0054] Figure 2 This is a schematic cross-sectional view of another 3DIC.

[0055] Figure 3 This is a flowchart of a method for forming 3D ICs. Detailed Implementation

[0056] In the accompanying drawings, unless otherwise specified, the same reference numerals will be used for the same or corresponding elements. The drawings are schematic only, and unless otherwise specified, the relative dimensions of the elements shown (such as layers or other structures) may be exaggerated and not drawn to scale. Instead, dimensions may be adjusted to make the illustration clear and easy to understand. When appearing in the drawings, the indicated axes X and Y point to the horizontal and vertical directions, respectively.

[0057] In this disclosure, the term "horizontal" refers to a direction parallel to the package wiring plane of the 3D IC. The term "lateral" may be used interchangeably with the term "horizontal." The term "vertical" refers to a direction perpendicular to or laterally to the package wiring plane. Therefore, terms indicating the relative vertical arrangement of components, such as "top," "bottom," "above," "above," "below," etc., should be understood in relation to the vertical direction Y. For example, a "top" die is farther from the package wiring plane than a "bottom" die, an "above" feature is farther from the package wiring plane than other features, and so on. Typically, the vertical direction Y corresponds to the direction in which the 3DIC die stack is above the package wiring plane.

[0058] In this disclosure, when an element (e.g., a layer or other structure) is referred to as being “on” another element, it can be directly on the other element or on one or more intermediate elements on the other element. Conversely, when an element is referred to as being “directly on another element,” there are no intermediate elements, and thus the element forms physical contact or adjacency with the other element.

[0059] In this disclosure, when two elements are referred to as “connection” or “interconnection”, unless otherwise stated, this means that the elements are electrically connected or coupled directly or via one or more intermediate conductive structures (e.g., interconnections).

[0060] Figure 1 This is a schematic cross-sectional view of the 3D IC 100. The 3D IC 100 includes a package wiring plane 102 and a die stack 104. The package wiring plane is... Figure 1 The package wiring plane 102 is schematically depicted in height by box 102. Only a few non-limiting examples are given; the package wiring plane 102 may be included in or defined by the wiring structure of the 3DIC 100's package substrate, bottom redistribution layer (RDL), or inserter. Furthermore, the package wiring plane 102 includes a global VDD voltage node VDD-G and a global VSS voltage node VSS-G.

[0061] In this disclosure, the terms "VDD voltage node" and "VSS voltage node" refer to the respective power supply voltage nodes of the 3DIC 100, or synonymous power or power rails. More specifically, "VDD" refers to a higher (positive) power supply voltage, and "VSS" refers to a lower power supply voltage, such as a reference power supply voltage, like ground level (GND). A VDD voltage node may correspond to a pull-up power supply voltage node / rail, and a VSS voltage node may correspond to a pull-down power supply voltage node / rail. In this disclosure, "global" and "local" VDD / VSS voltage nodes are also mentioned, where "global" is used to specify the higher VDD / VSS voltage domain of the 3DIC, which may be distributed across the die stack 104 as described herein. Meanwhile, "local" is used to specify the lower VDD / VSS voltage domain that is local to one die in the die stack 104.

[0062] Die stack 104 is arranged on package wiring plane 102 and includes a plurality of stacked dies 110 stacked on top of each other in the vertical direction Z. Hereinafter, reference numeral 110 will be used as a general designation for any one of the stacked dies 110 in the die stack 110, while suffixes “a,” “b,” etc., will be used to designate a specific stacked die in the die stack 104. Therefore, reference numeral 110 will generally be used when discussing the features and examples applied to each stacked die 110a-d in the die stack 104. In the example shown, four stacked dies 110 are shown, including a bottom stacked die 110a, a top (i.e., the uppermost) stacked die 110d, and two additional intermediate stacked dies 110b and 110c. However, the number of die stacks 110 shown is only a non-limiting example, and the number of stacked dies 110 can vary between different applications and configurations of the 3DIC 100, and can typically be much greater than four. For example, in memory applications, the number of stacked dies can be 32, 64 or more. In any case, the die stack 110 includes at least a bottom stacked die 110a and a top stacked die 110d, as well as a number of other intermediate stacked dies typically between the bottom and top stacked dies 110a, 110d.

[0063] The label “stacked” in “stacked die” serves both as a descriptive label for the stacked die 110, since each die 110 is stacked on the package wiring plane 102 and forms part of the die stack 104, and as a distinguishing label to differentiate it from the other optional base die 120 of the die stack 204, which will be discussed further below. The stacked die 110 and the base die 120 may also be referred to as the auxiliary die 110 and the main die 120.

[0064] In this disclosure, the term "die" is used to refer to a die structure or chip. For example... Figure 1 As shown, each stacked (auxiliary) die 110 has a front side 111 and a back side 112 and includes a front end line (FEOL) structure 113 and a front end line (BEOL) interconnect structure 114 disposed on the FEOL structure 113. Therefore, the front BEOL interconnect structure 114 is disposed on or defines the front side 111 of the stacked die 110.

[0065] In this disclosure, the term "FEOL structure" is used to refer to a portion of a die / chip that implements an active device, such as a front-end transistor (FMT) on a die / wafer. Therefore, the FEOL structure may include an active semiconductor layer (i.e., an active region or pattern including the FMT), a gate layer (i.e., the gate including the FMT), and local contacts or interconnect layers (i.e., source / drain (S / D) contacts including the FMT) of the FMT) of die 110. The active region may include the S / D region and channel region of the FMT. The active layer may be formed in a semiconductor substrate layer of the die. The semiconductor substrate layer may be formed or contained in any conventional CMOS-compatible substrate, such as Si, Ge, or SiGe substrates. Other non-limiting examples include silicon-on-insulator (SOI) substrates, GeOI substrates, or SiGeOI substrates. The FMT may include, for example, NMOSFETs and PMOSFETs (e.g., implemented as FinFETs, nanosheet FETs, or nanowire FETs). However, the die of the 3D IC according to this disclosure is not limited to transistor devices, but may additionally include capacitors, non-transistor-based selectors, diodes, volatile or non-volatile memory devices, magnetoresistive memory devices or other types of spintronic devices, depending on the specific circuit function and implementation of the die.

[0066] Furthermore, in this disclosure, the term "BEOL structure" (or simply "interconnect structure") is used to refer to the vertical stacking of interconnect layers of a die / chip, each interconnect layer including a dielectric layer with embedded conductive elements (typically metal), such as horizontal interconnects (traces or lines in the metal wiring layer, such as M0, M1, etc.) or vertical interconnects ("vias" in the via layer, such as V0, V1, etc.), for providing vertical wiring for signals between different metal wiring layers or between the wiring layers and the conductive elements of the FEOL structure 113. The "front" BEOL / interconnect structure of the die refers to the interconnect structure disposed on the front side of the die, such as on the FEOL structure of the die. The "back" BEOL / interconnect structure of the die refers to the interconnect structure disposed on the back side of the die.

[0067] The FEOL structure 113 and the front interconnect structure 114 together define the circuitry 116 of each stacked die 110. The stacked die 110 may be, for example, a stacked memory die, where the circuitry 116 of each memory die 110 can implement a subarray of memory cells. In another example, the stacked die 110 may be a logic die, where the circuitry 116 may include logic circuitry, such as sequential and / or combinational logic. As a specific example, the stacked die 116 may be configured to implement computational tasks for a hardware accelerator.

[0068] The circuit 116 of each stacked die 110 is connected to the local VDD voltage contact of the corresponding stacked die. Figure 1VDD (hereinafter referred to as "partial VDD contact" for simplicity) and partial VSS voltage contact ( Figure 1 The VSS (hereinafter referred to as "local VSS contact" for brevity) is located between the stacked dies 110. The local VDD and VSS contacts of each stacked die 110 are respectively arranged on the back side 112 and the front side 111 of the stacked die 110. As further described below, the local VDD and VSS contacts are configured to provide the associated stacked die 110 with substrate VDD and VSS voltages distributed by voltage stacking.

[0069] exist Figure 1 In this configuration, the stacked dies 110 are oriented such that their respective front faces 111 and BEOL structures 114 face the same direction. Therefore, the stacked dies 110 are arranged face-to-back. More specifically, the front faces 111 of the stacked dies 110 all face the package wiring plane 102 (i.e., in the negative Z direction). The front face 111 of each stacked die 110 corresponds to the bottom surface of the die 110, and the back face 112 corresponds to the top surface of the die 110. Referring to the illustrated example, reference numeral 111 can therefore be used to refer to the front and bottom surfaces of the die 110, while reference numeral 112 can be used to refer to the back and top surfaces of the die 110.

[0070] Although Figure 1 The partial VDD and VSS contacts are schematically shown as a single corresponding contact of each stacked die 110, but it will be understood that each partial VDD and VSS contact may generally be a contact structure or arrangement comprising a set of contact portions distributed on the respective die surfaces (i.e., front or back) of the stacked die 110.

[0071] The VSS and VDD contacts can be arranged in a matching or corresponding pattern so that the VSS and VDD contacts of adjacent stacked dies 110 can be electrically connected to each other. However, the VDD and VSS contacts can also be arranged in different patterns, provided that some intermediate interconnect structures (e.g., inserters and / or RDLs) are provided as interfaces between adjacent stacked dies 110.

[0072] Implementing the local VDD and VSS contacts as a contact arrangement comprising a set of multiple contact portions can be advantageous because the local VDD and VSS voltages can then be directly supplied to multiple locations of the circuitry 116 in each stacked die 110. This reduces the need for routing resources in each stacked die 110 for planar routing of the local VDD and VSS voltages from the local VDD and VSS contacts across the stacked dies 110.

[0073] The local VDD contacts of the stacked die 110 can be implemented as back-side contacts (e.g., multiple sets of back-side contacts) exposed at each back side 112 of the stacked die 110. Figure 1 As shown, the back contact can be provided in the form of a TSV 108 extending through the substrate of each stacked die 110. However, the local VDD contact of the stacked die 110 can also be implemented by contacts (e.g., vias) of a (local) back-side power transmission network (BSPDN) optionally disposed on the back side 112 of each stacked die 110.

[0074] Local VSS contacts of the stacked die 110 can be implemented as front contacts (e.g., multiple sets of front contacts) arranged in the respective front interconnect structures 114 of the stacked die 110. The front contacts can be arranged in the top layer of the front interconnect structure 114, more specifically at the interface of the front wiring structure 114 toward the back face 112 of the adjacent stacked die 110 (or, for the bottom stacked die 110a, at the interface toward the front face 121 of the base die 120). The front contacts can be provided in the front interconnect structure 114, for example, in the form of metal vias, islands, or pads.

[0075] like Figure 1 As schematically indicated, the front and back contacts of adjacent stacked dies 110 can be connected via interlayer interconnects in the form of conductive bumps 118 disposed between the respective front 111 and back 112 of the stacked dies 110. The conductive bumps 118 can be implemented as microbumps, solder balls, conductive pillars, etc. When the back and front contacts are formed by pads, the interlayer interconnects can also be formed by hybrid bonding pads, i.e., a hybrid bonding of the pads forming the back and front contacts.

[0076] As described above, the die stack 104 further includes a base die or a main die 120. A stacked (auxiliary) die 110 is stacked on top of the base (main) die 120. The base die 120 thus defines the lowermost die of the die stack 104.

[0077] like Figure 1 As shown, the substrate die 120 has a structure generally similar to that of each stacked die 110. Therefore, the substrate die 120 has a front side 121 and a back side 122. The substrate die 120 includes a FEOL structure 123 and a front side (BEOL) interconnect structure 124 disposed on the FEOL structure 123.

[0078] The front side 121 and front interconnect structure 124 of the substrate die 120 are arranged back-to-back with the package wiring plane 102 (i.e., in the +Z direction). Therefore, as Figure 1As shown, the base die 120 is arranged face-to-face with the bottom stacked die 110a (i.e., front to front), while the stacked dies 110 are arranged back-to-back with each other (i.e., front to back). The front face 121 of the base die 120 corresponds to the top surface of the base die 120, and the back face 122 of the base die 120 corresponds to the bottom surface of the base die 120. Referring to the example shown, reference numeral 121 can therefore be used to refer to the front and top surfaces of the base die 120, while reference numeral 122 can be used to refer to the back and bottom surfaces of the base die 120.

[0079] The FEOL structure 123 and the front interconnect structure 124 together define the circuitry 126 of the substrate die 120. As discussed further below, the substrate die 120 is configured as a control and / or I / O die of the die stack 104. Thus, the circuitry 126 enables the control and / or I / O functionality of the substrate die 120.

[0080] Circuit 126 is connected to the local VDD contact ( Figure 1 The VDD is specified in the middle and the VSS contact is in the middle. Figure 1 The VDD and VSS contacts of the substrate die 120 are arranged in the back-side power transmission network (BSPDN) of the back-side interconnect structure 125 of the substrate die 120.

[0081] Similar to the discussion above regarding the local VDD and VSS contacts of the stacked die 110, the local VDD and VSS contacts of the base die 120 can be implemented as a local VDD and VSS contact arrangement comprising a set of contact portions. However, in contrast to the stacked die 110, the base die 120 does not form part of a voltage stack, as further described below. Instead, the local VDD and VSS contacts of the base die 120 are configured to supply local VDD and VSS voltages directly via the corresponding voltage nodes of the package wiring plane 102.

[0082] The local VDD contact VDD of the substrate die 120 is connected to the local VDD voltage node VDD-L of the package wiring plane 102, as shown in the figure. The local VDD voltage node VDD-L is typically configured to supply a lower VDD voltage than the global VDD voltage node VDD-G.

[0083] The local VSS contact of the base die 120 is connected to the global VSS voltage node VSS-G as shown in the figure. Therefore, the base die 120 and the bottom stacked die 110 can have a common VSS voltage.

[0084] Alternatively, the local VSS contacts of the substrate die 120 can be (as shown by the dashed line) connected to an optional local VSS voltage node VSS-L of the package wiring plane 102. This allows the local VSS voltage of the substrate die 120 to be set independently of the global VSS voltage, which can promote noise isolation (especially where the substrate die 120 includes dense analog and / or high-speed I / O circuitry).

[0085] Therefore, in summary, the substrate die 120 is connected between the local VDD voltage node VDD-L and the second VSS voltage node of the package wiring plane 102, wherein the second VSS voltage node can be the global VSS voltage node VSS-G of the package wiring plane 102 or a separate local VSS voltage node VSS-L.

[0086] As shown in the figure, the substrate die 120 may further include a set of interlayer interconnects 128 configured to interconnect the bottom stacked die 110a (e.g., the front contacts of the front interconnect structure 114 of the bottom stacked die 110a) with the substrate die 120 (e.g., the front contacts of the front interconnect structure 124 of the substrate die 120, such as metal vias, islands, or pads). This interlayer interconnect can be implemented in the same manner as described for interlayer interconnects 118.

[0087] The 3D IC 100 also includes a metal interconnect layer 130 disposed on top of the top stacked die 110d of the die stack 104. The 3D IC 100 also includes a through interconnect 106 that extends vertically (along the Z direction) through each stacked die 110 in the die stack 104 to connect the metal interconnect layer 130 to the global VDD voltage node VDD-G.

[0088] The metal interconnect layer 130 can be implemented, for example, as a redistribution layer (RDL), such as aluminum or any other conventional metal typically used for RDLs. Alternatively, the metal interconnect layer 130 can be implemented as a metal wiring layer embedded within a dielectric layer, similar to a metal routing layer in a BEOL structure. While this is somewhat more complex and expensive than an RDL from a manufacturing perspective, it allows for more flexible interconnection between the through interconnect 106 and the local VDD contacts VDD of the top stacked die 110d. This can be particularly advantageous when the local VDD contacts VDD of the stacked die 110 include multiple distributed contact portions.

[0089] A through-connect 106 refers to an interconnect structure with a basic vertical wiring. The through-connect 106 is configured to connect the metal interconnect layer 130 to the global VDD voltage node VDD-G, while electrically bypassing each stacked die 110 and the base die 120. That is, there is no direct electrical connection between any portion of the through-connect 106 and the circuits 116, 126 of the stacked die 110 and the base die 120. Therefore, the portion of the through-connect 106 extending through the respective stacked die 110 (or base die 116) extends through the respective die 110 (or 116) without connecting to another circuit 116 (or circuit 126) of the respective die 110 (or 116).

[0090] The through-connect 106 may, for example, include multiple TSVs 108 stacked vertically to each other, each TSV extending through a corresponding stacked die 110 in the die stack 104. Figure 1 In this configuration, the TSVs of the stacked dies 110 are indicated to extend only through the lower portion of each stacked die 110. In this case, the TSVs 108 of the stacked dies 110 may extend through the substrate of the stacked dies 110 and (e.g., via abutment connections) connect to contact structures disposed in the interconnect structure 114 and optional FEOL structure 113 of the stacked dies 110, depending on the vertical extension (i.e., height) of the TSVs 108. When contact structures are included in the interconnect structure 114 and optional FEOL structure 113, it should be noted that such contact structures do not form part of or define the aforementioned circuit 116, but are electrically disconnected from the circuit 116 within the respective die 110. The contact structure may include a combination of vias in the interconnect structure 114 and optional intermediate metal islands. The contact structure can be arranged to extend through the interconnect structure 114 of the stacked die 110, so as to define a front contact in the top layer of the front interconnect structure 114, more specifically at the interface of the front interconnect structure 114 toward the back side 112 of the adjacent stacked die 110 (or, for the bottom stacked die 110a, toward the front side 121 of the base die 120), (e.g., in the form of a metal via, island, or pad). The front contact can then be connected to the TSV 108 of the underlying stacked die 110 via interlayer interconnects (e.g., conductive bumps 118).

[0091] A TSV 108 may also be formed for each respective stacked die 110 included in the through interconnect 106 to extend completely through the stacked die 110 from the back side 112 to the front side 111. Thus, each TSV 108 of the through interconnect 106 may define a front contact and a back contact adjacent to the TSV 108 of the adjacent stacked die 110 on its bottom and top surfaces.

[0092] Although it was mentioned above that the through interconnect 106 includes a single TSV 108 for each stacked die 110, it should be noted that the through interconnect may include multiple TSVs 108 for each stacked die 110. This allows the through interconnect 106 to have an increased cross-sectional size and thus a reduced IR drop.

[0093] Although not in Figure 1 As explicitly shown, the through-connect 106 may include a set of corresponding TSVs and optionally contact structures extending through the substrate die 120 to contact the global VDD voltage node VDD-G. However, the specific implementation of the connection to the global VDD voltage node VDD-G can vary. For example, the through-connect 106 may not need to extend through the substrate die 120, but instead terminate at and adjacent to a subset of the contact structures 128 of the substrate die 120, which may then be connected to the global VDD voltage node VDD-G via a combination of vertical and (optionally) horizontal wiring interconnects of the front interconnect structure 124, the FEOL structure 123, and (if present) the back interconnect structure 125 of the substrate die 120.

[0094] Still refer to Figure 1 It begins at the bottom stacked die 110a, whose local VSS contact is connected to the global VSS voltage node VSS-G via the base die 120, as schematically indicated by a downward arrow extending between the local VSS contact of the bottom stacked die 110a and the global VSS voltage node VSS-G.

[0095] For example, a local VSS contact of the bottom stacked die 110a can be connected to a corresponding contact (or contact arrangement) of the front interconnect structure 124 of the base die 120, and further connected to the global VSS voltage node VSS-G in the package wiring plane 102 via the circuit 126 of the base die 120 and the BSDPN of the back interconnect structure 125. When the base die 120 and the bottom stacked die 110 are configured to have a common VSS voltage supply, the local VSS contact of the bottom stacked die 110a can be connected to the local VSS contact VSS of the base die 120.

[0096] Moving upwards within the die stack 104, each of the other stacked dies 110 (e.g., stacked dies 110b, 110c, 110d) connects its respective local VSS contact VSS to the local VDD contact VDD of the adjacent stacked die below it (e.g., stacked dies 110a, 110b, 110c). Finally, the local VDD contact VDD of the top stacked die 110d is connected to the through interconnect 106 via the metal interconnect layer 130. Thus, the stacked dies 110 of the die stack 104 are connected in series between the global VDD and VSS voltage nodes VDD-G, VSS-G to stack voltages therebetween. That is, the stacked dies 110 are voltage-stacked such that the voltage between the global VDD voltage node VDD-G and the global VSS voltage node VSS-G (i.e., the package voltage) is divided across each stacked die 110.

[0097] As an example, assuming the global VDD voltage provided by the global VDD voltage node VDD-G is 4V and the global VSS voltage node VSS-G is 0V, and further assuming the voltage drop across each stacked die 110 is substantially the same, then the voltage across each stacked die 110 will be approximately 1V. That is:

[0098] -The local VDD and VSS voltages of the bottom-stacked die 110a will be approximately 1V and 0V, respectively.

[0099] - The local VDD and VSS voltages of another stacked die 110b will be approximately 2V and 1V, respectively.

[0100] - The local VDD and VSS voltages of another stacked die 110c will be approximately 3V and 2V, respectively.

[0101] - The local VDD and VSS voltages of the top-stacked die 110d will be approximately 4V and 3V, respectively.

[0102] Those skilled in the art will understand that different global VDD and VSS voltages, as well as different numbers of stacked dies 110, will result in different voltage distributions.

[0103] Generally, the global VDD and VSS voltages can be selected based on factors such as the number of stacked dies 110, power requirements, and the expected voltage drop of each stacked die 110.

[0104] The local VDD and VSS supply voltages of the substrate die 120 can be, for example, approximately 0.7-1V and 0V, respectively, thus making it suitable for core logic and I / O circuits.

[0105] The stacked dies 110 can be configured to provide a substantially consistent voltage drop between their respective local VDD and VSS contacts. In other words, the stacked dies 110 can be configured to have a substantially consistent power dissipation during operation or runtime. This contributes to stable and consistent operation of the circuitry 116 of each stacked die 110. It also reduces the need to incorporate voltage regulation circuitry in each stacked die 110 to adapt to the voltage supplied by adjacent stacked dies 110.

[0106] One way to promote consistent voltage drop / power dissipation of the stacked dies 110 is to configure the stacked dies 110 as substantially identical dies. That is, the circuits 116 of the stacked dies 110 may have substantially identical layouts. Here, "layout" refers to the combined layout of the FEOL structure 113 and the front interconnect structure 114 (and the back interconnect structure, if present) (e.g., the layout of the active semiconductor layer, gate layer, and local interconnect layers). Therefore, two or more circuits 116 with substantially identical layouts can be defined by the same netlist and planar diagram and can be fabricated using the same combination of masks and process steps. Consequently, the impedance between the respective local VDD and VSS contacts of the stacked dies 110 can be substantially consistent or equal for the stacked dies 110.

[0107] An alternative or complementary approach is to implement a power balancing circuit in circuitry 126 of the substrate die 120. This power balancing circuit can be configured to balance or evenly distribute the power allocated to each stacked die 110 during operation. The power balancing circuit can monitor circuit activity and distribute activity substantially uniformly or evenly across the stacked dies 110. Where functional operation is required only in one or a subset of the stacked dies 110, the power balancing circuit can be configured to operate redundantly with similar power consumption in the other stacked dies 110.

[0108] The identical stacked dies 110 and power balancing may be particularly suitable for memory applications, where the stacked dies 110 can be configured to implement identical subarrays of the memory array. Read / write activities and / or redundant read / write operations can then be distributed directly among the stacked dies 110. Another application suitable for implementations with identical stacked dies 110 and / or power balancing is hardware accelerators, where the stacked dies 110 can be configured to implement the same computational tasks of the accelerator.

[0109] As described above, the base die 120, namely its circuitry 126, is configured to implement control and / or I / O functions. Circuitry 126 is connected to each stacked die 110. Therefore, base die 126 can provide control signals to the stacked dies and receive and process signals (e.g., data) from the stacked dies. For example, if the stacked die 110 is a memory die, circuitry 126 of base die 120 can be configured to implement a memory and I / O controller for the stacked memory die 110. As another example, if the stacked die 110 is a logic die, circuitry 126 of base die 120 can be configured to implement the main control and logic functions and distribute tasks among the stacked logic dies 110. To facilitate signal exchange with the stacked dies 110, the 3D IC device 100 includes a set of output signal routing structures 150 extending through the die stack 104 and configured to route output signals from circuit 126 of substrate die 120 to corresponding circuit 116 of each of the stacked dies 110. The 3D IC device 100 also includes a set of input signal routing structures 152 configured to route input signals from corresponding circuit 116 of each of the stacked dies 110 to circuit 126 of substrate die 120. For example, in memory applications, the input signal routing structure 152 may route read data signals from the stacked memory die 110 to substrate die 120, while the output signal routing structure 150 may route write data signals from substrate die 110 to the stacked memory die 110.

[0110] Each of the sets of input and output signal routing structures 150, 152 may include a combination of the following: TSV 108, interlayer interconnects (e.g., conductive bumps 118), metal wires and vias of the interconnect structure 114 of the stacked die 110, and any other circuitry (e.g., level shifters 140) connecting the circuitry 126 of the base die 120 and the corresponding inputs / outputs (e.g., input / output buffers) of the stacked die 110. Therefore, although Figure 1 The set of input and output signal routing structures 150, 152, separated from and shifted relative to the outline of circuit 116, is schematically shown. However, it should be understood that the set of input and output signal routing structures 150, 152 included in each respective stacked die 110 may be included in or form part of the circuit 116 of the stacked die 110. Thus, while the through interconnect 106 is configured to supply the global VDD voltage along a substantially strictly vertical path, the set of input and output signal routing structures 150, 152 may be configured to allow signal propagation to / from the substrate die 120 in a generally vertical direction, including vertically and horizontally oriented segments.

[0111] As shown, the set of input and output signal routing structures 150, 152 can terminate at the top surface 112 of the top stacked die 110d. To prevent the output signal routing structure 150 (and therefore the corresponding input buffer of the circuit 116 of the stacked die 110) from shorting the through interconnect 106 (and therefore the global VDD voltage node VDD-G), the metal interconnect layer 130 can be arranged to be disconnected from the output signal routing structure 150. For example, if the metal interconnect layer 130 is an RDL, the RDL can be arranged so that it does not cover the top surface 112 of the top stacked die 110d in the area exposing the output signal routing structure 150. On the other hand, to prevent the input terminals of the top stacked die 110d from floating (in the lower stacked dies 110a-c, these input terminals are connected to the output terminals of the upper stacked die 110b), the metal interconnect layer 130 can be arranged to short the input signal routing structure 152, more specifically, the input node of the input signal routing structure 152 at the top surface 112 of the top stacked die 110d, to the local VDD voltage contact VDD of the top stacked die 110d. In other words, the input signal routing structure 152 can be shorted at the top surface 112 of the top stacked die 110d to the through interconnect 106 (and thus to the global VDD voltage node VDD-G). For example, if the metal interconnect layer 130 is an RDL, the RDL can be arranged to extend continuously between the area exposing the input node of the input signal routing structure 152 and the local VDD voltage contact VDD of the top stacked die 110d.

[0112] To control the signal flow between the substrate die 120 and the stacked dies 110, the circuitry 116 of each stacked die 110 may include a multiplexer connected to the input and output signal routing structures 150, 152. The multiplexer of the stacked die 110 may, for example, be configurable (e.g., in response to a control signal provided by the substrate die 120 via the output signal routing structure 150) to output data generated by its circuitry 116, or data generated by and received from the circuitry 116 of the adjacent stacked die 110 above it via the input signal routing structure 152.

[0113] To ensure that logic signals routed via input and output signal routing structures 150, 152 are represented by voltage levels suitable for the corresponding voltage domain of each stacked die 110, each stacked die 110 may further include a level shifter, including an up shifter and a down shifter. The down shifter can be configured to shift a logic low or logic high voltage received by the first stacked die 110 (e.g., 110a) from its adjacent second stacked die 110 (e.g., 110b) down into the voltage domain of the first stacked die 110. The logic low or logic high voltage received from the second stacked die 110 (e.g., 110b) corresponds to the local VSS and VDD of the second stacked die 110, respectively. Therefore, as an example, if the stacked die 110b is powered by local VDD and VSS voltages of 2V and 1V respectively, then in the circuit 116 of the stacked die 110a, a logic high level ("1") can be represented by 2V and a logic low level ("0") can be represented by 1V. Conversely, if the stacked die 110a is powered by local VDD and VSS voltages of 1V and 0V respectively, then in the circuit 116 of the stacked die 110a, a logic high level ("1") can be represented by 1V and a logic low level ("0") can be represented by 0V. Therefore, if the stacked die 110a receives 1V from the stacked die 110b, it will be incorrectly interpreted as logic 1. By using a level-down shifter, the 2V and 1V input voltages received from the stacked die 110b can be shifted to 1V and 0V, respectively, so that they are correctly represented as logic 1 and 0 in the circuit 116 of the stacked die 110a. The level shifter can be configured in a similar manner to shift up a logic low or logic high voltage received by the second stacked die 110 (e.g., 110b) from the adjacent first stacked die 110 (e.g., 110a) below.

[0114] Figure 2This is a schematic cross-sectional view of another 3D IC 200. Like 3D IC 100, 3D IC 200 includes a die stack 104 comprising a base die 120 and a plurality of stacked dies 110 stacked on top of the base die 20. The above description of 3D IC 100 generally applies to 3D IC 200 accordingly. However, 3D IC 200 differs from 3D IC 100 in that the stacked dies 110 here are arranged such that their respective front faces 111 and FEOL structures 113 face away from the package wiring plane 102 (i.e., in the +Z direction), that is, in the same direction as the base die 120. The front face 111 of each stacked die 110 corresponds to the top surface of die 110, and the back face 112 corresponds to the bottom surface of die 110. Referring to the example shown, reference numeral 111 can therefore be used to refer to the front and top surfaces of die 110, while reference numeral 112 can be used to refer to the back and bottom surfaces of die 110.

[0115] Therefore, in both 3D IC 100 and 3D IC 200, the stacked dies 110 are arranged face-to-back. However, in 3D IC 100, the front side 111 of the stacked die 110 faces the package wiring plane 102 and the substrate die 120, while in 3D IC 200, the front side 111 of the stacked die 110 faces away from the package wiring plane 102 and the substrate die 120. Therefore, as... Figure 2 As shown, die 120 and bottom stacked die 110a are arranged face to back.

[0116] Due to the "face-up" orientation of the stacked die 110, the metal interconnect layer 130 is disposed here on top of the front side 111 of the top stacked die 110d. More specifically, the metal interconnect layer 130 is disposed on top of the front interconnect structure 114 of the top stacked die 110d.

[0117] Figure 3 It is used to form 3D ICs (such as in...) Figure 1 and Figure 2 The flowchart of method 300 (3D IC 100 or 200) is shown below. Therefore, for ease of understanding, in... Figure 3 In the description, similar reference numerals will be used to refer to Figure 1 and Figure 2 Similar characteristics.

[0118] Method 300 includes, in S301, forming dies to be stacked to form a die stack. The dies may include a “stacked” die 110 and a substrate die 120. The stacked die 110, as discussed above, can be formed with substantially the same layout. Therefore, the stacked die 110 can be formed using a substantially identical set of circuit layouts, designs, netlists, and masks. The substrate die 120 will typically have a different layout than the stacked die 110 and can therefore be formed using a different set of circuit layouts, designs, netlists, and masks. The fabrication of the stacked dies may include conventional CMOS processing techniques including FEOL and BEOL processes. The dies may be formed on multiple different wafers, which will be stacked and bonded to each other in subsequent steps. Thus, multiple wafers comprising multiple stacked dies 110 and another “substrate” wafer comprising multiple substrate dies 120 can be formed.

[0119] In S302, the dies 110 and 120 formed in S301 are stacked on top of each other to form a die stack, such as die stack 104. Forming die stack 104 may include performing wafer-level stacking of the dies 110 and 120 formed in step S301. Thus, multiple wafers, each including a plurality of stacked dies 110, can be stacked together with a substrate wafer including a plurality of substrate dies 120.

[0120] In step S303, a local VDD voltage contact VDD of the top-stacked die 110d is connected to a through-through interconnect by forming a metal interconnect layer 130 (e.g., RDL) on top of the top-stacked die 110d. In the case of a wafer-level stack of dies 110, 120 in step S302, the metal interconnect layer 130 may be formed on a top-stacked die (top-stacked die refers to a die comprising multiple top-stacked dies 110ds) in the wafer stack, such that the corresponding local VD voltage contact VDD of each top-stacked die 110d is connected to a corresponding through-through interconnect extending through the corresponding die stack. Therefore, the formed wafer stack can then be diced to form multiple individual die stacks 104, each die stack including a corresponding metal interconnect layer 130.

[0121] In step S304, a die stack 104 (i.e., each die stack 104 in the case of cutting multiple die stacks 104 from a wafer stack) is arranged on the package wiring plane 102 of the (corresponding) chip package, such that a through interconnect is connected to the global VDD voltage contact VDD-G of the package wiring plane, and the stacked dies 110 in the die stack 104 are voltage-stacking between the global VDD voltage node VDD-G and the global VSS voltage node VSS-G of the package wiring plane 102.

[0122] As an alternative to forming the metal interconnect layer 130 before dicing, the corresponding metal interconnect layer 130 may also be formed on top of the top stacked die 110d in each corresponding die stack 104 after dicing.

[0123] Those skilled in the art will recognize that the invention is by no means limited to the examples described above. Rather, many modifications and variations are possible within the scope of the appended claims. For example, while both 3DIC devices 100 and 200 include a base die 120 as the bottom die of a die stack 104, it is conceivable that this disclosure is also applicable to other configurations. For instance, instead of arranging the base die 120 below the stacked dies 110, a base die having a function corresponding to the base die 120 may be arranged above the package wiring plane 102 but adjacent to the die stack 104. The base die can then be connected to the die stack 104 using an inserter and / or an RDL.

Claims

1. A 3D integrated circuit (IC) device, comprising: The package routing plane includes a global VDD voltage node and a global VSS voltage node; Die stack, the die stack being arranged on the package wiring plane and comprising a plurality of stacked dies stacked on top of each other; A metal interconnect layer is disposed on top of the top stacked die in the die stack; as well as A through interconnect that extends vertically through each stacked die in the die stack and connects the metal interconnect layer to the global VDD voltage node; Each of the stacked dies in the die stack has a bottom surface and a top surface, a local VDD voltage contact on its top surface and a local VSS voltage contact on its bottom surface. The local VSS voltage contact of the bottom stacked die in the die stack is connected to the global VSS voltage node, the local VSS voltage contact of each other stacked die is connected to the local VDD voltage contact of the adjacent stacked die below it, and the local VDD voltage contact of the top stacked die is connected to the through interconnect through the metal interconnect layer, such that the stacked dies in the die stack are voltage-stacking between the global VDD voltage node and the global VSS voltage node.

2. The 3DIC of claim 1, wherein each stacked die in the die stack has a front side and a back side, and includes a front end line (FEOL) structure and a front end line (BEOL) interconnect structure disposed on the FEOL structure, and wherein the stacked dies are stacked such that the front BEOL interconnect structures face the same direction.

3. The 3D IC of claim 2, wherein the front side is the bottom surface of the stacked die.

4. The 3D IC of claim 2, wherein the front side is the top surface of the stacked die.

5. The 3DIC of claim 1, wherein the stacked dies are substantially identical dies.

6. The 3D IC of claim 1, wherein the stacked die is a memory die.

7. The 3D IC of claim 1, wherein the stacked die is a logic die.

8. The 3D IC as described in claim 1, The die stack also includes a base die, and the stacked dies are stacked on top of the base die. The base die is configured as the control and / or I / O die of the die stack and is connected to each stacked die. The substrate die is connected between a second VSS voltage node and a local VDD voltage node in the package wiring plane. The local VDD voltage node is configured to supply a lower VDD voltage than the global VDD voltage node, and the second VSS voltage node is either the global VSS voltage node or the local VSS voltage node.

9. The 3D IC of claim 8, further comprising: A set of output signal routing structures extends through the die stack and is configured to route output signals from the base die to each stacked die, and A set of input signal routing structures is configured to route input signals from the stacked die to the base die.

10. The 3D IC of claim 9, wherein the set of input and output signal routing structures terminates on the top surface of the top stacked die, and wherein the metal interconnect layer is arranged to be disconnected from the output signal routing structure and to short the input signal routing structure to a local VDD voltage contact of the top stacked die.

11. The 3DIC as claimed in any one of claims 8-10, wherein the substrate die has a front side facing the stacked die and a back side facing the package wiring plane, and includes a front-end line FEOL structure, a front-end back-end line BEOL interconnect structure disposed on the FEOL structure, and a back-end power distribution network connected to the local VDD voltage node and the second VSS voltage node.

12. The 3D IC of claim 11, wherein the local VSS voltage contacts of the bottom stacked die are connected to the global VSS power voltage node via the front interconnect structure of the base die and the rear power distribution network.

13. The 3D IC of claim 11, wherein the metal interconnect layer is a redistribution layer.

14. A method for forming a 3D integrated circuit (IC) device, the method comprising: A die stack consisting of multiple stacked dies stacked on top of each other is arranged on the package routing plane, which includes the global VDD voltage node and the global VSS voltage node. Each of the stacked dies in the die stack has a bottom surface and a top surface, a local VDD voltage contact on its top surface and a local VSS voltage contact on its bottom surface. The local VSS voltage contact of the bottom stacked die in the die stack is connected to the global VSS voltage node, and the local VSS voltage contact of each other stacked die is connected to the local VDD voltage contact of the adjacent stacked die below it. The die stack includes a through interconnect that extends vertically through each stacked die in the die stack and connects to the global VDD voltage node; as well as A metal interconnect layer is formed on top of the top stacked die to connect the through interconnect to the local VDD voltage contact of the top stacked die.

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