3D integrated circuit device
By introducing global VDD and VSS voltage nodes into the package routing plane and through interconnects in 3D ICs, the problems of power density and IR voltage drop are solved, enabling low-cost and high-efficiency 3D IC design and reducing voltage drop and packaging complexity.
CN121665588APending Publication Date: 2026-03-13INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
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Patent Information
- Application Number
- CN202511237468.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-09-02
- Filing Date
- 2025-09-01
- Publication Date
- 2026-03-13
AI Technical Summary
Technical Problem
In existing 3D IC designs, as the number of dies increases, power density rises, and IR voltage drop increases, resulting in the need for more power bump resources in the package, which is costly.
Method used
The package routing plane uses global VDD and VSS voltage nodes, and the metal interconnect layer is connected to the global VDD voltage node through through interconnects to achieve voltage stacking, reduce current density and the number of package power bumps, and use the same die design to reduce complexity and cost.
Benefits of technology
Using higher package voltage at lower current reduces voltage drop across the PDN, minimizing footprint and financial penalties, enabling low-cost and high-efficiency 3D IC design.
✦ Generated by Eureka AI based on patent content.
Abstract
In one aspect, a 3D IC device is provided, comprising: a package routing plane comprising a global VDD voltage node and a global VSS voltage node; a die stack disposed on the package wiring plane and including a plurality of stacked dies stacked on each other; a metal interconnect layer disposed atop a top stacked die in the die stack; and a through interconnect extending vertically through each stacked die in the stack of dies and connecting the metal interconnect layer to a global VDD voltage node; wherein each stacked die in the die stack has a bottom surface and a top surface, a local VDD voltage contact on the top surface thereof, and a local VSS voltage contact on the bottom surface thereof, and wherein the stacked dies in the die stack are voltage stacked between a global VDD voltage node and a global VSS voltage node.
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