Method of using connections between 3D transistor stacks to make a six-transistor SRAM cell

Abstract

A method for fabricating a semiconductor device is disclosed, the method comprising: forming a first stack of a first transistor structure on a substrate; and forming a second stack of a second transistor structure adjacent to the first stack on the substrate. The second stack is formed adjacent to the first stack such that a stacked S / D region at one end of the first stack faces a corresponding stacked S / D region at one end of the second stack. A first pair of facing S / D regions of the first stack and the second stack are connected by forming an interconnect structure extending horizontally to physically connect the first pair of facing S / D regions to each other. Second pairs of facing S / D regions of the first stack and the second stack are maintained as a pair of physically separated facing S / D regions. A first metal interconnect structure and a second metal interconnect structure are connected to corresponding S / D regions in the second pair of facing S / D regions.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit on the filing dates of U.S. Provisional Patent Application No. 62 / 956,038, filed December 31, 2019, and U.S. Non-Provisional Patent Application No. 17 / 090,501, filed November 5, 2020, which are incorporated herein by reference in their entirety. Background of the Invention Technical Field

[0004] This disclosure pertains to the fabrication of integrated circuits and 3D microelectronic devices.

[0005] In the fabrication of semiconductor devices (especially at the microscale), various fabrication processes are performed, such as film deposition, etch mask generation, patterning, material etching and removal, and doping. These processes are repeated to form the desired semiconductor device elements on a substrate. Historically, microfabrication has been used to create transistors in a plane, with wiring / metallization layers formed above the active device plane, and thus these transistors are characterized as two-dimensional (2D) circuits or 2D fabrications. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, but scaling efforts are facing greater challenges as scaling enters single-digit nanometer semiconductor device fabrication nodes. The contact gate pitch for 2D transistor density scaling reaches its scaling limit due to fabrication variability and electrostatic device constraints. New transistor designs, such as vertical-channel full-around-gate transistors, can overcome some contact gate pitch scaling limitations; however, resistance, capacitance, and reliability issues limit line pitch scaling, thus limiting the density at which transistors can be wired into circuits. Semiconductor device manufacturers have expressed aspirations for three-dimensional (3D) semiconductor circuits with transistors stacked on top of each other. Summary of the Invention

[0006] Note that the Summary of this invention does not specify every embodiment and / or additional novel aspect of the invention disclosed herein or claimed. Rather, the Summary provides only a preliminary discussion of different embodiments and corresponding novel points that outperform conventional techniques. For additional details and / or possible perspectives regarding the invention and embodiments, the reader should focus on the Detailed Description of the Invention and the accompanying drawings, which are further discussed below.

[0007] Aspect (1) includes a method of fabricating a semiconductor device. The method includes forming a first stack of first transistor structures on a substrate, each first transistor structure including a channel extending horizontally along a surface of the substrate and a pair of S / D regions formed at opposite ends of the channel. The first transistor structures are stacked vertically along the thickness direction of the substrate such that the channel regions of the first stack are positioned above each other and the S / D regions of the first stack are positioned above each other. A second stack of second transistor structures is formed adjacent to the first stack on the substrate, each second transistor structure including a channel extending horizontally and a pair of S / D regions formed at opposite ends of the channel, wherein the second transistor structures are stacked vertically such that the channel regions of the second stack are positioned above each other and the S / D regions of the second stack are positioned above each other. The second stack is formed adjacent to the first stack such that a stacked S / D region at one end of the first stack faces a corresponding stacked S / D region at one end of the second stack. A first pair of facing S / D regions of the first stack and the second stack are connected by forming a connection structure that extends in the horizontal direction to physically connect the first pair of facing S / D regions to each other. The second pair of facing S / D regions of the first stack and the second stack are maintained as a pair of physically separated facing S / D regions. A first metal interconnect structure and a second metal interconnect structure are connected to the corresponding S / D regions in the second pair of facing S / D regions.

[0008] Aspect (2) includes the method of aspect (1), wherein forming the first stack and the second stack includes: forming a channel of the first stack; forming a channel of the second stack adjacent to the first stack; forming an S / D region of the first stack while covering a region of the second stack with a protective material; and forming an S / D region of the second stack while covering a region of the first stack with a protective material.

[0009] Aspect (3) includes the method of aspect (2), wherein forming the S / D region of the first stack body includes forming S / D regions of the same conductivity type on all channels of the first stack body.

[0010] Aspect (4) includes the method of aspect (3), wherein forming the S / D region of the second stack comprises: forming an S / D region of a first conductivity type in one of the channels of the second stack while covering the other channels of the second stack with a protective material; and forming an S / D region of a second conductivity type in another channel of the second stack while covering the S / D region of the first conductivity type with a protective material.

[0011] Aspect (5) includes the method of aspect (1), wherein connecting the first pair of facing S / D regions includes growing connecting material from each of the first pair toward each other S / D region of the first pair of facing S / D regions.

[0012] Aspect (6) includes the method of aspect (5), wherein the growth includes growing connecting material from each S / D region in the first pair toward each other S / D region facing each other in the first pair until the connecting material joins to physically connect the S / D regions of the first pair facing each other.

[0013] Aspect (7) includes the method of aspect (6), further comprising forming a metal on the connecting material.

[0014] Aspect (8) includes the method of aspect (5), wherein the growth includes growing a connecting material from each of the S / D regions in the first pair toward each other S / D region in the S / D regions facing each other in the first pair, without joining the connecting material.

[0015] Aspect (9) includes the method of aspect (8), further comprising forming a metal on the connecting material such that the metal engages the connecting material to physically connect the S / D regions of the first pair of facing S / D regions to each other.

[0016] Aspect (10) includes a three-dimensional (3D) semiconductor device comprising a first stack of first transistor structures formed on a substrate, each first transistor structure including a channel extending horizontally along the surface of the substrate and a pair of S / D regions formed at opposite ends of the channel. The first transistor structures are stacked vertically along the thickness direction of the substrate such that the channel regions of the first stack are positioned above each other and the S / D regions of the first stack are positioned above each other. A second stack of second transistor structures is formed adjacent to the first stack on the substrate, each second transistor structure including a channel extending in the horizontal direction and a pair of S / D regions formed at opposite ends of the channel. The second transistor structures are stacked vertically such that the channel regions of the second stack are positioned above each other and the S / D regions of the second stack are positioned above each other, and the second stack is formed adjacent to the first stack such that a stacked S / D region at one end of the first stack faces a corresponding stacked S / D region at one end of the second stack. The connection structure extends horizontally to physically connect the first pair of facing S / D regions to each other. A first metal interconnect structure and a second metal interconnect structure are connected to corresponding S / D regions in the second pair of facing S / D regions of the first and second stacks, which are physically separated into a pair of physically separated facing S / D regions.

[0017] Aspect (11) includes the device of aspect (10), wherein at least one of the first stack and the second stack has an S / D region of the same conductivity type.

[0018] Aspect (12) includes the device of aspect (10), wherein at least one of the first stack and the second stack has an S / D region with a different conductivity type.

[0019] Aspect (13) includes the device of aspect (10), wherein the connection structure includes an epitaxially grown connection material that physically connects the S / D regions of the first pair of facing S / D regions to each other.

[0020] Aspect (14) includes the device of aspect (10), wherein the connection structure includes: an epitaxially grown connection material that is not connected to the S / D regions of the first pair of facing S / D regions; and a metal formed on the connection material such that the metal engages the connection material to physically connect the S / D regions of the first pair of facing S / D regions to each other.

[0021] Aspect (15) includes a method of fabricating a semiconductor device. The method includes: forming a first stack of transistor channels adjacent to a second stack of transistor channels, the stacks of transistor channels being horizontally extending and vertically aligned all-around gate transistor channels, wherein the transistor channels are positioned above each other; and forming a first source / drain region on the transistor channel of the first stack, while covering the transistor channel of the second stack. The source / drain region is formed on the transistor channel of the second stack, while covering the source / drain region on the first stack, wherein, during the formation of the source / drain region on the transistor channel of the second stack, channel ends are progressively exposed to selectively form N-doped or P-doped source / drain regions. A first adjacent source / drain region is grown together between the first stack and the second stack, while second adjacent source / drain regions are maintained physically separated from each other. The transistors in the first stack and the second stack are electrically connected to form an SRAM cell.

[0022] Aspect (16) includes the method of aspect (15), wherein first adjacent source / drain regions are grown together to form a source / drain connection for a pair of inverting transistors for an SRAM cell.

[0023] Aspect (17) includes the method of aspect (16), wherein second adjacent source / drain regions are maintained as physically separated from each other to form pass transistors for SRAM cells.

[0024] Aspect (18) includes the method of aspect (17), wherein the SRAM cell is a six-transistor SRAM cell, the method further comprising growing a third first adjacent source / drain region together between the first stack and the second stack to form another pair of inverting transistors for the SRAM cell, while maintaining the second adjacent source / drain regions physically separated from each other.

[0025] Aspect (19) includes the method of aspect (18), further including forming a pass transistor positioned as a top channel of the first stack and the second stack.

[0026] Aspect (20) includes the method of aspect (18), further including forming a pass transistor positioned as a bottom channel of the first stack and the second stack.

[0027] The general description of the illustrative embodiments above and the detailed description below are merely exemplary aspects of the teaching content of this disclosure and are not restrictive. Attached Figure Description

[0028] The invention becomes better understood by referring to the following specific embodiments, taken in conjunction with the accompanying drawings, in which a more complete understanding of the invention and its many incidental advantages will be readily obtained:

[0029] Figure 1 This is a cross-section of a substrate segment of an example 3D semiconductor device according to an embodiment of this disclosure.

[0030] Figure 2 This is a flowchart for forming a 3D semiconductor device according to an embodiment of this disclosure.

[0031] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3J , Figure 3K , Figure 3L , Figure 3M , Figure 3M' and 3N It is formed Figure 1 A cross-sectional view of an intermediate structure in an example process for an SRAM cell.

[0032] Figure 4 This is a cross-section of a substrate segment of an example 3D semiconductor device according to another embodiment of this disclosure.

[0033] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5E' and Figure 5F It is formed Figure 4 A cross-sectional view of an intermediate structure in an example process for an SRAM cell.

[0034] Figure 6 The circuit diagram of the SRAM cell is depicted. Detailed Implementation

[0035] In the accompanying drawings, similar reference numerals refer to the same or corresponding parts in all these views. Furthermore, as used herein, unless otherwise stated, the words "a / an" and the like generally mean "one or more". Unless otherwise specified or showing a schematic structure or flowchart, the drawings are generally not drawn to scale.

[0036] In addition, the terms “approximately,” “about,” “about,” and similar terms generally refer to a range of identified values ​​that include a margin of 20%, 10%, or preferably 5%, as well as any values ​​in between.

[0037] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” “upper,” and “top” may be used herein to describe the relationship between an element or feature as shown in the accompanying drawings and (multiple) other elements or features. In addition to the orientations depicted in the accompanying drawings, the spatially related terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0038] Throughout this specification, references to "one embodiment" or "embodiment" mean that a particular feature, structure, material, or property described in conjunction with an embodiment is included in at least one embodiment, but does not imply that they are present in every embodiment. Therefore, the phrase "in one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, a particular feature, structure, material, or property may be combined in any suitable manner.

[0039] As described in the background section, semiconductor device manufacturers have expressed a desire for three-dimensional (3D) semiconductor circuits with transistors stacked on top of each other. 3D integration is one option for overcoming the inevitable saturation in critical size scaling. 3D integration (i.e., vertical stacking of multiple devices) can overcome these scaling limitations by increasing transistor density in volume rather than area. While the flash memory industry has successfully demonstrated and implemented vertical stacking with the adoption of 3D NAND, applying vertical stacking to random logic designs is much more difficult. For example, mainstream CMOS VLSI scaling in CPU or GPU products is exploring 3D integration as a primary means of advancing semiconductor blueprints, and therefore requires enabling technologies.

[0040] The techniques presented in this paper overcome significant challenges that make 3D logic integration feasible by eliminating connections and simplifying layout and transistor wiring, for example. This results in a reduced 3D layout size due to the reduced connection space. Furthermore, all transistors in the 3D stack can be used for logic cells and memory, including static random access memory (SRAM).

[0041] The SRAM cell comprises two pairs of inverter transistors, M2 / M1 and M4 / M3. The techniques described in this paper include methods and designs for connecting the source / drain regions of these devices. Several advantages are achieved. Two connections can be eliminated. A reduced layout size is realized due to the reduced connection space. Furthermore, the via transistors can be separated, and buried power rails can be integrated.

[0042] This disclosure describes various aspects of 3D logic devices with inverted planes, such as SRAM (Static Random Access Memory) cells. The methods described herein include process flows for growing epitaxial interconnects for SRAM scaling. One embodiment includes growing silicon interconnects between 3D transistor stacks having SRAM access transistors and NMOS access transistors on the top. Another embodiment includes growing silicon interconnects between 3D transistor stacks having SRAM access transistors and NMOS access transistors on the bottom.

[0043] Figure 6 This is a circuit diagram of an SRAM cell. The SRAM cell has two inverters (M1 and M2 in series, and M3 and M4 in series) and two pass transistors (M5 and M6) that comprise the SRAM cell. WL stands for "word line," and BL stands for "bit line." BL! represents a bit line with the same value as BL but opposite polarity. Note that the gates of pass transistors M5 and M6 are connected to the word line WL, while the gates of M1 and M2 are in series and connected to the bit line BL. The gate of M2 inverts the signal from the bit line BL (when M6 allows the signal from WL to pass through), thus turning on either M1 or M2 depending on the polarity of the signal on BL. Similarly, the gates of M3 and M4 are in series and connected to the bit line BL!. The gate of M4 inverts the signal from the bit line BL (when M5 allows the signal from WL to pass through), thus turning on either M3 or M4 depending on the polarity of the signal on BL!. VDD and ground will be connected to the cell via buried power rails (BPR) within the SRAM cell. Note that M2 and M4 are PMOS devices, while M1, M3, M5, and M6 are NMOS devices. However, this configuration can be reversed so that M2 and M4 are NMOS devices, while M1, M3, M5, and M6 are PMOS devices.

[0044] Figure 1 This is a cross-section illustrating a substrate segment of an example 3D semiconductor device according to an embodiment of this disclosure. This example is implemented using a parallel 6T SRAM cell. Figure 6 SRAM cells. In Figure 1In this embodiment, the access transistor is located on top of the cell, and the bit lines (BL and BL!) and word lines (WL) are wired from the top to the cell. Buried power rails for Vdd and GND are wired from the bottom of the cell. Buried power rails are power rails positioned below the active device. Buried power rails can be formed in the bulk silicon region.

[0045] like Figure 1 As seen, the 3D SRAM cell includes a stack 110 of transistors M1, M3, and M5 positioned above each other, and a stack 120 of transistors M2, M4, and M6 positioned above each other. Each transistor M1 to M6 includes a channel extending horizontally along the surface of the substrate, and a pair of S / D regions formed on opposite ends of the channel. As seen, stack 110 includes a transistor having an N+ epitaxial S / D region 115, while stack 120 includes both a P+ epitaxial S / D region 114 and an N+ epitaxial S / D region. Figure 1 In this embodiment, the transistor is implemented as a nanochannel. A nanochannel refers to a nanosheet or nanowire. These are semiconductor channels that are part of a field-effect transistor (FET), which is a gate-all-around (GAA) device in which the gate material is formed or will be formed around the cross-section of the channel. A gate-all-around (GAA) FET is a non-planar 3D transistor that is conceptually similar to a FinFET, except that the gate material surrounds the channel region on all sides. Depending on the design, a GAA FET can have two or more active gates. A GAA FET can utilize a silicon nanowire stack in which the gate completely surrounds the stack. The channel can be circular, square, rectangular, or other shapes. The nanochannel can be formed by epitaxial growth. For example, a first epitaxial stack can be formed on the top side surface of a first substrate. For example, post-nano-stack epitaxial growth can be performed after a CFET (Complementary FET) process flow.

[0046] Such as Figure 1 As seen, stacks 110 and 120 are formed adjacent to each other, such that the stacked S / D region at one end of stack 110 faces the corresponding stacked S / D region at one end of stack 120. A connecting structure 111a extends horizontally to physically connect the first pair of facing S / D regions of stacks M1 and M2 to each other. Similarly, a connecting structure 111b extends horizontally to physically connect the second pair of facing S / D regions of stacks M3 and M4 to each other. The connecting structure 111a and... Figure 6 The Q! corresponds to, and the connection structure 111b is with Figure 6 The Q corresponds to this. The facing S / D regions of M5 and M6 remain separated. A local metal interconnect structure electrically connects the transistors to form SRAM cells, where the electrical connections are represented by node 101. Figure 1In one embodiment, the first metal interconnect structure 131a and the second metal interconnect structure 131b contact the facing S / D regions of M5 and M6, which are maintained as physically separated from each other.

[0047] Figure 2 It is used to form such as Figure 1 The flowchart illustrates a 3D semiconductor device such as an SRAM cell. In step 201, the process begins by forming a first stack of first transistor structures on a substrate. Each first transistor structure includes a channel extending horizontally along the surface of the substrate and a pair of S / D regions formed at opposite ends of the channel. The first transistor structures are stacked vertically along the thickness direction of the substrate such that the channel regions of the first stack are positioned above each other and the S / D regions of the first stack are positioned above each other.

[0048] In step 203, a second stack of transistor structures is formed adjacent to the first stack on the substrate. Each second transistor structure includes a channel extending horizontally along the surface of the substrate and a pair of S / D regions formed at opposite ends of the channel. The second transistor structures are stacked vertically along the thickness direction of the substrate such that the channel regions of the first stack are positioned above each other and the S / D regions of the first stack are positioned above each other. The second stack of transistor structures is formed adjacent to the first stack such that the stacked S / D regions at one end of the first stack face the corresponding stacked S / D regions at one end of the second stack.

[0049] In step 205, a connecting structure is formed to connect the first opposing S / D regions of the first stack and the second stack, the connecting structure extending horizontally to physically connect the first opposing S / D regions to each other. This connection is performed while maintaining the second opposing S / D regions of the first stack and the second stack as a pair of physically separated opposing S / D regions.

[0050] In step 207, the first metal interconnect structure and the second metal interconnect structure are connected to the corresponding S / D regions in the second pair of facing S / D regions, while keeping these facing regions separate from each other.

[0051] Figures 3A to 3N In the production Figure 2 The cross-section of the intermediate structure formed during the process of 3D SRAM. Figure 3A It shows the formation Figure 2The cross-section of the stacked nanochannel SRAM cells of transistors M1 to M6 is shown. Note that the initial stack can be formed using alternating layers of epitaxially grown semiconductor material that can be selectively removed and replaced. In one example embodiment, up to about 12 or more alternating silicon-germanium (SiGe) and silicon single-plane stacks are formed. Note that fewer than 12 layers can be formed. Next, the epitaxial stack can be diced into a fin structure using an etching mask. The SiGe material can be optionally removed and replaced with a dielectric. The channel material doping can be performed before or after the formation of the source / drain. As a result, a vertical stack of GAA channels can be formed on a substrate, such as... Figure 3A As shown in the diagram. Gate protection material 117 is shown as a protection channel (M1 to M6). Future S / D regions are shown, but these S / D regions have not yet been formed. Channels M1, M3, M5, and M6 have future N+ regions 113, while channels M4 and M2 have future P+ regions 112. Buried power lines (not shown) can be used to form Vdd and ground connections.

[0052] although Figure 3A Only two adjacent stacks are shown, but multiple stacks formed by the processes described in this disclosure may exist. For example, a second set of stacks may exist extending behind and / or to the right and / or left of the first set of stacks. For clarity, Figures 3A to 3N The processing of two adjacent stacks is shown, but is not to be construed as limiting the number of stacks that can be formed and processed on a substrate by the methods disclosed herein.

[0053] Each channel may have a different material composition and doping, or may have a uniform material. The channels may have a gate protection material 117 formed on these channels for subsequent replacement with a functional gate that completely surrounds each nanochannel. In a non-limiting example, the gate protection material may be a high-k dielectric. In a non-limiting example, the high-k dielectric may be selected from the group consisting of: hafnium silicon oxide (HfSiO), hafnium oxide (HfO2), hafnium chromium oxide (HfCrO), aluminum oxide (Al2O3), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), scandium(III)Sc2O3, lanthanum oxide (La2O3), lutetium oxide (Lu2O3), niobium(V)Nb2O5, tantalum pentoxide (Ta2O5), or combinations thereof.

[0054] Internal spacers 119 separate each corresponding nanochannel from its adjacent nanochannels (i.e., M1 and M3, M3 and M5, M2 and M4, and M4 and M6). The spaces between the nanochannel stacks can be filled with oxide-filled materials or other dielectrics. In non-limiting examples, the filler material can be SiO, SiO2, silicon nitride, oxide nitride, or other dielectrics. These other dielectrics can be low-k or high-k dielectrics, where K ranges from 1.5 to 3.0. Some examples are: oxide derivatives, such as fluorine (F)-doped oxides, carbon (C)-doped oxides, hafnium (H)-doped oxides; or vapor-deposited organic materials, such as polyimide; or porous oxides, such as hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), and barium titanate (BaTiO3).

[0055] exist Figure 3B In the middle, oxide 118 (silicon oxide or other dielectric) is deposited and polished downwards to the top of the transistor stack. An etching mask 122 (photoresist) is formed above the right-side stack 120, as shown... Figure 3C As shown, the exposed oxide is then etched (removed) in a directional manner. Figure 3C In the process, while the photoresist etching mask 122 covers the right stack 120, the oxide 118 covering the left stack 110 has been removed by directional etching. The directional etching exposes the future N+S / D regions 113 of channels M1, M3, and M5.

[0056] exist Figure 3D In the process, the photoresist etching mask 122 has been removed, while oxide 118 remains to cover the sides of the stack 120. Oxide 118 can be any protective material such as nitride. Following this, N+ epitaxial growth is performed on the left-side stack 110 to form each S / D region 115. Epitaxial growth refers to a type of crystal growth or material deposition in which a new crystalline layer is formed with a defined orientation relative to a crystalline substrate. N+ indicates silicon doped with a high concentration of dopants such as phosphorus, arsenic, or antimony. P+ indicates silicon doped with a high concentration of dopants such as boron atoms. Boron, arsenic, phosphorus, and occasionally gallium are used to dope silicon. Boron is the preferred p-type dopant in silicon integrated circuit production because its diffusion rate allows for easy control of junction depth. Phosphorus is typically used for bulk doping of silicon wafers, while arsenic is used for diffusion junctions because arsenic diffuses more slowly and is therefore more controllable than phosphorus. High concentrations can be "degenerate," or greater than 10 at room temperature. 18 atoms / cm 3 This causes the material to behave like a metal. The doping concentration of silicon semiconductors can range from 10... 13 / cm 3 Up to 10 18 / cm 3Any value. Degraded doped silicon contains impurities in a ratio of approximately a few parts per thousand of silicon. N+ or P+ epitaxial growth of the S / D region is performed using vapor phase epitaxy (VPE), a modification of chemical vapor deposition. During deposition, depending on whether an N+ or P+ S / D region is being formed, the epitaxial layer is doped by adding impurities (such as arsine, phosphine, or diborane) to the source gas.

[0057] like Figure 3E As shown, the newly grown N+ S / D regions 115 are then selectively covered with a protective film 116. For example, selective high-k deposition is performed to cover the N+ regions on the left-side stack 110. Alternatively, low-temperature oxide growth can be performed to protect the exposed S / D regions. The protective film (e.g., a high-k layer) 116 can be selected from the group consisting of: HfO2, Al2O3, Y2O3, ZrO2, HfZrO4, TiO2, Sc2O3, La2O3, Lu2O3, Nb2O5, and Ta2O5.

[0058] Next, a portion of the second nanochannel stack 120 is exposed from top to bottom, while one or more nanochannels positioned below this portion remain covered. This step can be performed by reactive ion etching (RIE) that directionally etches the oxide until the channels are exposed. The exposed portion can reveal the ends of one or more nanochannels. Figure 3F In the example, channel M6 is exposed while channels M4 and M2 remain covered. Then, an N+ epitaxial S / D region 115 is grown over channel M6. Following this, a protective film 116 (e.g., a high-k film) can be selectively deposited over the N+ S / D region of the right-side stack 120, such as... Figure 3G As shown in the image.

[0059] The remaining oxide covering the end of the second nanochannel stack 120 on the right side was removed by reactive ion etching, exposing the future P+ S / D region 112. Then, a P+ epitaxial S / D region 114 was grown on the right-side stack 120, as shown... Figure 3H As shown in the diagram. These are the final products to be formed by the S / D regions, therefore a protective film does not need to be deposited on these P+S / D regions. Figure 3I The protective film removed from all S / D regions is shown, where both stacks are completed and each stack has a different S / D formation. At this point, all S / D regions have been formed for the 3D SRAM.

[0060] Then, oxide or insulator is deposited on the substrate to cover all S / D regions of the 6T 3D cell, and back polishing is performed, such as... Figure 3JAs shown in the diagram. In step 3K, an etching step is performed to expose M5 and M6, after which a protective material (e.g., a high-K material) 116 is selectively deposited on the S / D regions of these transistors to protect them from subsequent processes. Then, another etching step is performed to expose the S / D edges 140 of M3 / M4 and the S / D edges 150 of M1 / M2, as shown in the diagram. Figure 3L The edge shown in the image.

[0061] exist Figure 3M In this process, interconnect material 160 is epitaxially grown to connect regions M3 and M4 together, and regions M1 and M2 together. Note that regions M5 and M6 will not be grown together because they are covered by a high-k material or other protective agent. These transistors remain separated to become pass transistors. Figure 3M' It shows Figure 3M An alternative is to leave small gaps between areas M3 and M4, and between areas M1 and M2. Figure 3M or Figure 3M' The diagram shows that after the interconnect structure is formed, wet oxide etching is used to expose the remaining edges of the N+ and P+ regions of transistors M1 to M4. Then, a metal 170 such as Ru is deposited on the interconnect structure and the exposed edges. Figure 3N As seen in [the diagram], a connecting material 160 is partially grown, as shown in [the diagram], and metal 170 fills the gap to complete the connection structure. Ru can be polished, and then silicide self-alignment can be performed, followed by stripping to form a good connection. At this point, the S / D regions of paired inverted SRAM cells are formed, and the S / D regions of the pass transistors are not connected and can be accessed individually in the SRAM circuit.

[0062] Further steps for completing the SRAM circuitry include forming local interconnects, replacing the gate, and performing additional metallization (not shown) after gate dicing. These steps may include: TiN, TaN, TiAl deposition; removal of the replacement gate P-type work function metal (RMG PWFM); RMG termination; gate dicing (CMG); and forming horizontal and vertical connections between dual damascene metal layers M0 and M1, where M0 refers to the lower metal layer of the stack and M1 refers to the upper metal layer of the stack. Vertical vias can be used to connect wiring to the M0 and M1 layers, as known in the art.

[0063] Depending on the device type (PFET or NFET), the work function metal layer can be a p-type work function layer or an n-type work function layer. A p-type work function layer includes metals selected from, but not limited to, the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. An n-type work function layer includes metals selected from, but not limited to, the group consisting of: titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon carbide (TaSiN), titanium silicon carbide (TiSiN), or combinations thereof. The metal filler layer may include aluminum (Al), tungsten (W), cobalt (Co), and / or other suitable materials.

[0064] In the dual damascene process, the structure undergoes a diffusion barrier etching step, followed by the deposition of via dielectric. Then, an etching step forms a spacing in which lines and vias are formed.

[0065] Thin barrier layers of tantalum (Ta) and tantalum nitride (TaN) were deposited using physical vapor deposition (PVD). Ta was used to form a pad, while TaN was used as the barrier in the structure. The barrier layer was then coated with a copper seed barrier via PVD. Finally, the structure was electroplated with copper and planar polished using chemical mechanical polishing (CMP).

[0066] Figure 4 This is a cross-section illustrating a substrate segment of an example 3D semiconductor device according to another embodiment of this disclosure. This example is implemented using a parallel 6T SRAM cell. Figure 6 SRAM cells. In Figure 4 In this embodiment, the access transistor is located at the bottom of the cell, and the bit lines (B and B!) and word lines (WL) are wired to the cell from the bottom. The power rails for Vdd and GND are wired from the top of the cell.

[0067] Figure 4 The formation of two vertically stacked bodies with fully surrounding gate channels (where gate protection material surrounds channels M1 to M6) is shown. As can be seen, the 3D SRAM cell includes... Figure 1 The stacked structures are similar to stacked structures 410 and 420. Figure 4 In the middle, like Figure 1 Channels M1, M3, M5 and M6 have future N+ zones, of which channels M2 and M4 have future P+ zones. Figure 4One difference is that channels M2 and M4 are positioned as top and middle channels of the right-side stack, rather than bottom and middle channels of the right-side stack. Connecting structure 411a extends horizontally to physically connect the first opposing S / D regions of stacks M1 and M2 to each other. Similarly, connecting structure 411b extends horizontally to physically connect the second opposing S / D regions of stacks M3 and M4 to each other. Connecting structure 411a and... Figure 6 The Q! corresponds to, and the connection structure 411b and Figure 6 The Q corresponds to this. The facing S / D regions of M5 and M6 remain separated. A local metal interconnect structure electrically connects the transistors to form SRAM cells, where the electrical connections are represented by node 101. Figure 1 In one embodiment, the first metal interconnect structure 131a and the second metal interconnect structure 131b contact the facing S / D regions of M5 and M6, which are maintained as physically separated from each other.

[0068] Figures 5A to 5F In the production Figure 4 A cross-section of an intermediate structure formed during the fabrication process of 3D SRAM. Used to form Figure 4 The initial processing steps of the device are performed to form Figure 1 The similarities in those steps of the device are as follows: first, an S / D region is formed in one stack while protecting other stacks, and then the channel ends of another stack are progressively exposed to form a corresponding S / D region on the second stack (the right-hand stack). This is used to form... Figure 4 The initial processing steps of the device and Figures 3A to 3E Similarly, and produce Figure 5A The structure, Figure 5A The N+S / D region covered by a protective film 416 and the stack 420 protected by oxide 418 are shown.

[0069] Next, a portion of the second nanochannel stack 420 is exposed from top to bottom, while one or more nanochannels positioned below this portion remain covered. This step can be performed by reactive ion etching (RIE) that directionally etches the oxide until the channels are exposed. The exposed portion can reveal the ends of one or more nanochannels. Figure 5B In the example shown, channels M4 and M2 are exposed, while channel M6 remains covered. Then, P+ epitaxial S / D regions 415 are grown for channels M4 and M2, followed by selective deposition of a protective film 416, such as a high-k film, over the P+ S / D regions of the right-side stack 420. Figure 5B It is displayed in the middle.

[0070] The remaining oxide covering the end of the right-hand vertical stack 420 is removed by reactive ion etching, exposing the future N+ S / D region 413. Then, N+ epitaxial S / D regions 114 are grown on the right-hand stack 120, after which the protective film is removed from all S / D regions, where both stacks are completed and each stack has a different S / D formation. At this point, all S / D regions are formed for the 3D SRAM, as shown below. Figure 5C As shown in the image.

[0071] Then, an oxide or insulator is deposited on the substrate to cover all the S / D regions of the 6T 3D cell, and back polishing is performed, followed by an etching step to expose the S / D edges 440 of M3 / M4 and the S / D edges 450 of M1 / M2, as shown. Figure 5D As shown in the image.

[0072] exist Figure 5E In this process, interconnect material 460 is grown to connect regions M3 and M4 together, and regions M1 and M2 together. Note that regions M5 and M6 will not grow together because they are covered by oxide 418. These transistors remain separate to become pass transistors. Figure 5E' It shows Figure 5E An alternative. As can be seen, small gaps can be left between areas M3 and M4, and between areas M1 and M2. This forms a... Figure 5E or Figure 5E' Following the interconnect structure shown, wet oxide etching is used to expose the remaining edges of the N+ and P+ regions of transistors M1 to M4. Then, a metal 470 such as Ru is deposited on the interconnect structure and the exposed edges. Figure 5F As seen in the text. Among them, such as Figure 5E' As shown, a connection material 460 is partially grown, and metal 470 fills the gap to complete the connection structure. Ru can be polished, and then silicide self-alignment can be performed, followed by stripping to form a good connection. At this point, the S / D regions of paired inverted SRAM cells are formed, and the S / D regions of the pass transistors are not connected and can be accessed individually in the SRAM circuit.

[0073] Further steps for completing the SRAM circuitry include forming local interconnects, replacing the gate, and performing additional metallization (not shown) after gate dicing. These steps may include: TiN, TaN, TiAl deposition; removal of the replacement gate p-type work function metal (RMG PWFM); RMG termination; gate dicing (CMG); and forming horizontal and vertical connections between dual damascene metal layers M0 and M1, where M0 refers to the lower metal layer of the stack and M1 refers to the upper metal layer of the stack. Vertical vias can be used to connect wiring to the M0 and M1 layers, as known in the art.

[0074] Depending on the device type (PFET or NFET), the work function metal layer can be a p-type work function layer or an n-type work function layer. A p-type work function layer includes metals selected from, but not limited to, the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. An n-type work function layer includes metals selected from, but not limited to, the group consisting of: titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon carbide (TaSiN), titanium silicon carbide (TiSiN), or combinations thereof. The metal filler layer may include aluminum (Al), tungsten (W), cobalt (Co), and / or other suitable materials.

[0075] In the dual damascene process, the structure undergoes a diffusion barrier etching step, followed by the deposition of via dielectric. Then, an etching step forms a spacing in which lines and vias are formed.

[0076] Thin barrier layers of tantalum (Ta) and tantalum nitride (TaN) were deposited using physical vapor deposition (PVD). Ta was used to form a pad, while TaN was used as the barrier in the structure. The barrier layer was then coated with a copper seed barrier via PVD. Finally, the structure was electroplated with copper and planar polished using chemical mechanical polishing (CMP).

[0077] For clarity, the order in which the different steps described herein are discussed has been presented. These steps can typically be performed in any suitable order. Furthermore, although each different feature, technique, configuration, etc., may be discussed in different places within this disclosure, it is intended that each concept can be implemented independently of or in combination with each other. Accordingly, aspects of this disclosure can be embodied and viewed in many different ways.

[0078] In the foregoing description, specific details, such as the particular geometry of the processing system and the description of the various components and processes used therein, have been set forth. However, it should be understood that the techniques described herein may be practiced in other embodiments departing from these specific details, and such details are for illustrative purposes and not for limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been set forth for illustrative purposes to provide a thorough understanding. However, embodiments may be practiced without such specific details. Components having substantially the same functional construction are indicated by similar reference numerals, and therefore any redundant description may be omitted.

[0079] Various techniques have been described as multiple discontinuous operations to aid in understanding the various embodiments. The order of the description should not be construed as implying that these operations are necessarily order-dependent. In fact, these operations do not need to be performed in the presented order. The described operations may be performed in a different order than the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0080] As used herein, "substrate" or "target substrate" generally refers to the object being processed according to the invention. A substrate may include any material portion or structure of a device (especially a semiconductor or other electronic device) and may be, for example, a base substrate structure (such as a semiconductor wafer, photomask), or a layer on or overlying a base substrate structure (such as a thin film). Therefore, a substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0081] Those skilled in the art will also understand that many changes can be made to the technical operations described above, while still achieving the same objectives of the invention. The scope of this disclosure is intended to cover these changes. Therefore, the foregoing description of embodiments of the invention is not intended to be limiting. Rather, any limitations on embodiments of the invention are set forth in the appended claims.

Claims

1. A method of fabricating a semiconductor device, the method comprising: forming a first stack of first transistor structures on a substrate, each first transistor structure including a channel extending in a horizontal direction along a surface of the substrate and a pair of S / D regions formed on opposite ends of the channel, wherein the first transistor structures are stacked in a vertical direction along a thickness of the substrate such that channel regions of the first stack are positioned above one another and S / D regions of the first stack are positioned above one another; forming a second stack of second transistor structures on the substrate adjacent to the first stack, each second transistor structure including a channel extending in the horizontal direction and a pair of S / D regions formed on opposite ends of the channel, wherein the second transistor structures are stacked in the vertical direction such that channel regions of the second stack are positioned above one another and S / D regions of the second stack are positioned above one another, the second stack being formed adjacent to the first stack such that a stacked S / D region at one end of the first stack faces a corresponding stacked S / D region at one end of the second stack; connecting a first pair of facing S / D regions of the first stack and the second stack by forming a connection structure extending in the horizontal direction to physically connect the first pair of facing S / D regions to one another; maintaining a second pair of facing S / D regions of the first stack and the second stack as a pair of separate facing S / D regions physically separated from one another; and forming first and second metal interconnect structures connected to respective S / D regions of the second pair of facing S / D regions.

2. The method of claim 1, wherein, forming the first and second stacks includes: forming channels of the first stack; forming channels of the second stack adjacent to the first stack; forming S / D regions of the first stack while covering regions of the second stack with a protective material; and forming S / D regions of the second stack while covering regions of the first stack with a protective material.

3. The method of claim 2, wherein, forming the S / D regions of the first stack includes simultaneously forming S / D regions of a same conductivity type on all channels of the first stack.

4. The method of claim 3, wherein, forming the S / D regions of the second stack includes: forming S / D regions of a first conductivity type on one of the channels of the second stack while covering other channels of the second stack with a protective material; and forming S / D regions of a second conductivity type on another of the channels of the second stack while covering the S / D regions of the first conductivity type with a protective material.

5. The method of claim 1, wherein, connecting the first pair of facing S / D regions includes growing a connection material from each S / D region of the first pair toward each other S / D region of the first pair of facing S / D regions.

6. The method of claim 5, wherein, the growing includes growing the connection material from each S / D region of the first pair toward each other S / D region of the first pair of facing S / D regions until the connection material bonds to physically connect the S / D regions of the first pair of facing S / D regions to one another.

7. The method of claim 6, further comprising forming a metal on the connection material.

8. The method of claim 5, wherein, The growing includes growing the connection material from each S / D region of the first pair toward each other S / D region of the first pair facing S / D regions without joining the connection material.

9. The method of claim 8, further comprising forming a metal on the connection material such that the metal joins the connection material to physically connect S / D regions of the first pair facing S / D regions to each other.

10. A three-dimensional (3D) semiconductor device, comprising: a first stack of first transistor structures formed on a substrate, each first transistor structure including a channel extending in a horizontal direction along a surface of the substrate and a pair of S / D regions formed on opposite ends of the channel, wherein the first transistor structures are stacked along a vertical direction along a thickness direction of the substrate such that channel regions of the first stack are positioned above each other and S / D regions of the first stack are positioned above each other; a second stack of second transistor structures formed on the substrate adjacent to the first stack, each second transistor structure including a channel extending in the horizontal direction and a pair of S / D regions formed on opposite ends of the channel, wherein the second transistor structures are stacked along the vertical direction such that channel regions of the second stack are positioned above each other and S / D regions of the second stack are positioned above each other, the second stack being formed adjacent to the first stack such that stacked S / D regions at one end of the first stack face corresponding stacked S / D regions at one end of the second stack; a connection structure extending in the horizontal direction to physically connect a first pair of facing S / D regions to each other; and first and second metal interconnect structures connected to respective S / D regions of a second pair of facing S / D regions of the first and second stacks, the second pair of facing S / D regions of the first and second stacks being physically separated from each other into a pair of separate facing S / D regions physically separated from each other.

11. The 3D semiconductor device of claim 10, wherein, At least one of the first and second stacks has S / D regions that are all of a same conductivity type.

12. The 3D semiconductor device of claim 10, wherein, At least one of the first and second stacks has S / D regions of different conductivity types.

13. The 3D semiconductor device of claim 10, wherein, The connection structure includes an epitaxially grown connection material that physically connects S / D regions of the first pair of facing S / D regions to each other.

14. The 3D semiconductor device of claim 10, wherein, The connection structure includes: an epitaxially grown connection material that does not connect S / D regions of the first pair of facing S / D regions; and a metal formed on the connection material such that the metal joins the connection material to physically connect S / D regions of the first pair of facing S / D regions to each other.

15. A method of fabricating a semiconductor device, the method comprising: forming a first stack of transistor channels adjacent to a second stack of transistor channels, the stacks of transistor channels being horizontally extending and vertically aligned full wraparound gate transistor channels, wherein transistor channels are positioned above each other; forming first source / drain regions on the transistor channels of the first stack while covering the transistor channels of the second stack; forming source / drain regions on the transistor channels of the second stack while covering the source / drain regions on the first stack, wherein forming source / drain regions on the transistor channels of the second stack is performed by stepwise exposing channel ends to selectively form N-doped source / drain regions or P-doped source / drain regions; growing first adjacent source / drain regions together between the first and second stacks while maintaining second adjacent source / drain regions physically separated from each other; and electrically connecting the transistors in the first and second stacks to form an SRAM cell.

16. The method of claim 15, wherein, growing the first adjacent source / drain regions together forms source / drain connections for a pair of inverter transistors of the SRAM cell.

17. The method of claim 16, wherein, maintaining the second adjacent source / drain regions physically separated from each other forms pass transistor transistors of the SRAM cell.

18. The method of claim 17, wherein, The SRAM cell is a six-transistor SRAM cell, the method further comprising growing third first adjacent source / drain regions together between the first and second stacks to form another pair of inverter transistors for the SRAM cell while maintaining the second adjacent source / drain regions physically separated from each other.

19. The method of claim 18, further comprising forming the pass transistor transistors positioned as top channels of the first and second stacks.

20. The method of claim 18, further comprising forming the pass transistor transistors positioned as bottom channels of the first and second stacks.

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