Gate oxide layer electrical thickness monitoring structure, method, device and computer equipment

Abstract

The present application provides a gate oxide layer electrical thickness monitoring structure, method, device and computer equipment, the structure comprising: a first MOS structure and a second MOS structure arranged at intervals, wherein in the first MOS structure, a first plate is formed above the source and drain regions, a second plate is formed above the channel region, and the gate on the second plate has a first overlapping region with the source and drain regions; in the second MOS structure, a third plate is formed above the source and drain regions, a fourth plate is formed above the channel region, and the gate on the fourth plate has a second overlapping region with the source and drain regions; along the channel direction, the distance between any point on the first plate and the second plate is the same as the distance between the corresponding point on the third plate and the fourth plate, the first overlapping region and the second overlapping region have the same area, and the gate region on the second plate has the same gate width and different gate length compared to the gate region on the fourth plate. Through the present application, the accurate electrical thickness of the gate oxide layer can be calculated.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor design and production technology, and in particular relates to a gate oxide layer electrical thickness monitoring structure, method, device and computer equipment. Background Art

[0002] With the development of semiconductor manufacturing technology, device size continues to shrink, and the thickness of the gate oxide layer is also getting smaller and smaller. This parameter has a great impact on device performance. Therefore, the process requires precise control of the physical thickness of the gate oxide layer. Corresponding effective and accurate monitoring is particularly important for judging process capabilities.

[0003] Typically, the method for monitoring the thickness of the gate oxide layer is generally to use optical methods to measure the thickness after the gate oxide layer deposition process is completed. In the actual process, the gate oxide layer may re-grow during other process steps after deposition, resulting in the final gate oxide layer being thicker than when it was just deposited. Therefore, this measurement method cannot characterize the final gate oxide layer thickness because it can only be measured directly after deposition.

[0004] Another method for monitoring the thickness of the gate oxide layer is to measure the capacitance of the MOS device in the strong inversion state and calculate the equivalent thickness of the gate oxide layer, that is, the electrical thickness of the gate oxide layer. This measurement is performed after all processes are completed, so it can truly reflect the final thickness of the gate oxide layer. However, since MOS devices have parasitic capacitance in addition to the gate oxide capacitance, the measured gate oxide capacitance will be biased, resulting in inaccurate calculation results of the electrical thickness of the gate oxide layer.

[0005] Currently, no effective solution has been proposed for the problem of the influence of parasitic capacitance on the measurement accuracy of gate oxide thickness in related technologies. Summary of the Invention

[0006] The present application provides a gate oxide layer electrical thickness monitoring structure, method, device and computer equipment to accurately monitor the electrical thickness of the gate oxide layer.

[0007] To achieve the above objectives, the present application provides a gate oxide layer electrical thickness monitoring structure, comprising: a first MOS structure and a second MOS structure arranged at intervals, wherein, in the first MOS structure, a first plate is formed above the source and drain regions, a second plate is formed above the channel region, and a gate on the second plate has a first overlapping region with the source and drain regions;

[0008] In the second MOS structure, a third plate is formed above the source and drain regions, a fourth plate is formed above the channel region, and the gate on the fourth plate has a second overlapping region with the source and drain regions;

[0009] Along the channel direction, the distance between any point on the first plate and the second plate is the same as the distance between the corresponding point on the third plate and the fourth plate, the area of ​​the first overlapping region is the same as the area of ​​the second overlapping region, and the gate region on the second plate has the same gate width and different gate length compared to the gate region on the fourth plate.

[0010] In some embodiments, the first MOS structure includes:

[0011] A first source electrode and a first drain electrode are connected to a first metal line through a first contact hole, respectively; and a first gate electrode is connected to a second metal line through a second contact hole;

[0012] The second MOS structure includes:

[0013] The second source and the second drain are respectively connected to the third metal line through the third contact hole; and the second gate is connected to the fourth metal line through the fourth contact hole;

[0014] The distance between the first metal line and the second metal line is the same as the distance between the third metal line and the fourth metal line; the distance between the first contact hole and the second contact hole is the same as the distance between the third contact hole and the fourth contact hole; the distance between the first contact hole and the first gate is the same as the distance between the third contact hole and the second gate;

[0015] The width of the first gate is equal to the width of the second gate, the length of the first gate is greater than the length of the second gate, and the number of the second contact holes is greater than the number of the fourth contact holes.

[0016] In some embodiments, the first gate has overlapping areas A1 and A2 with the first source and the first drain, respectively, and the second gate has overlapping areas B1 and B2 with the second source and the second drain, respectively; the overlapping areas A1 and B1 are the same in area, and the overlapping areas A2 and B2 are the same in area;

[0017] The width of the first gate is the same as that of the second gate, and the length of the first gate is greater than that of the second gate.

[0018] The present application also provides a gate oxide layer electrical thickness monitoring method, which is applied to the gate oxide layer electrical thickness monitoring structure described above, comprising:

[0019] Determining an area of ​​a first gate oxide layer below a gate region on the second electrode plate and an area of ​​a second gate oxide layer below a gate region on the fourth electrode plate;

[0020] determining a first total capacitance of the first MOS structure and a second total capacitance of the second MOS structure;

[0021] The electrical thicknesses of the gate oxide layers of the first MOS structure and the second MOS structure are calculated based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area.

[0022] In some embodiments, determining a first total capacitance of the first MOS structure includes:

[0023] Acquiring a current signal of a first MOS structure, wherein a scan voltage is applied above the gate of the first MOS structure and the source and drain regions are grounded;

[0024] integrating the current signal with respect to time to determine the amount of charge;

[0025] A first total capacitance is calculated according to the scan voltage and the charge amount.

[0026] In some embodiments, determining a second total capacitance of the second MOS structure includes:

[0027] Acquiring a current signal of a second MOS structure, wherein a scan voltage is applied above the gate of the second MOS structure and the source and drain regions are grounded;

[0028] integrating the current signal with respect to time to determine the amount of charge;

[0029] A second total capacitance is obtained by calculation according to the scan voltage and the charge amount.

[0030] In some embodiments, calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area includes:

[0031] determining a third equivalent capacitance based on the first total capacitance and the second total capacitance, wherein the third equivalent capacitance does not include parasitic capacitance;

[0032] Determining a third equivalent gate oxide layer area according to the first gate oxide layer area and the second gate oxide layer area, wherein the third equivalent gate oxide layer has the same thickness as the first gate oxide layer and the second gate oxide layer;

[0033] Based on the third equivalent capacitance, the third equivalent gate oxide layer area and the capacitance formula, the electrical thickness of the gate oxide layer of the first MOS structure and the second MOS structure is calculated.

[0034] In some embodiments, calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area includes:

[0035] Determining a first parasitic capacitance and a second parasitic capacitance based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area;

[0036] The electrical thickness of the gate oxide layer of the first MOS structure is determined based on the first total capacitance, the first gate oxide layer area and the first parasitic capacitance, or the electrical thickness of the gate oxide layer of the second MOS structure is determined based on the second total capacitance, the second gate oxide layer area and the second parasitic capacitance.

[0037] The present application also provides a gate oxide layer electrical thickness monitoring device, comprising:

[0038] a gate oxide layer area determining unit, configured to determine an area of ​​a first gate oxide layer below the gate region on the second electrode plate and an area of ​​a second gate oxide layer below the gate region on the fourth electrode plate;

[0039] a total capacitance determining unit, configured to determine a first total capacitance of the first MOS structure and a second total capacitance of the second MOS structure;

[0040] The gate oxide layer electrical thickness calculation unit is used to calculate the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance and the second gate oxide layer area.

[0041] The present application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0042] The above-mentioned gate oxide layer electrical thickness monitoring structure, method, device and computer equipment, by arranging the first MOS structure and the second MOS structure at intervals, so that the height of each process section of the first MOS structure and the second MOS structure is consistent; along the channel direction, the distance between any point on the first electrode plate and the second electrode plate is the same as the distance between the corresponding point on the third electrode plate and the fourth electrode plate, and the gate on the second electrode plate and the source and drain region have a first overlapping area, the gate on the fourth electrode plate and the source and drain region have a second overlapping area, and the area of ​​the first overlapping area and the second overlapping area are the same, so that the parasitic capacitance in the first MOS structure and the second MOS structure is consistent, including the capacitance C between the gate and the source and drain. of , capacitance C between the contact hole and the gate c2p, capacitance C between contact holes c2c , the capacitance C between the metal line and the contact hole m2c , C of metal line and gate m2p , the capacitance C between metal lines m2m And the gate over-coverage capacitance C ov .

[0043] By setting the gate region on the second plate to have the same gate width and different gate lengths as the gate region on the fourth plate, the first MOS structure and the second MOS structure differ only in gate length. This allows the parasitic capacitance to be offset by the capacitance measurement results of the first and second MOS structures, thereby accurately calculating the electrical thickness of the gate oxide layer. This monitoring structure requires no additional process steps and is highly compatible with actual semiconductor manufacturing processes. By monitoring the capacitance value, the final thickness of the gate oxide layer can be effectively monitored, improving the accuracy and efficiency of process monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 Schematic diagram of capacitance distribution of MOS structure in related technology.

[0046] Figure 2 This is a schematic diagram of the structure of the gate oxide layer electrical thickness monitoring structure provided in Example 1 of the present application.

[0047] Figure 3 This is a top view of the first MOS structure in the gate oxide layer electrical thickness monitoring structure provided in Example 1 of the present application.

[0048] Figure 4 This is a top view of the second MOS structure in the gate oxide layer electrical thickness monitoring structure provided in Example 1 of the present application.

[0049] Figure 5 This is a flow chart of a method for monitoring the electrical thickness of a gate oxide layer provided in the second embodiment of the present application. DETAILED DESCRIPTION

[0050] The aforementioned and other technical aspects, features, and functions of this application are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are merely references to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit this application.

[0051] Example 1

[0052] See also Figures 2 to 4 The present application provides a gate oxide layer electrical thickness monitoring structure, including a first MOS structure, the first MOS structure is provided with: a substrate, a source-drain region (including a first source and a first drain arranged in the active region) is provided on the substrate; a channel region is provided between the first source and the first drain; a first gate oxide layer and a first gate are provided above the channel region in sequence, and a contact hole CT is provided above the first gate, the first source and the first drain, for respectively connecting the first gate, the first source and the first drain to the metal layer located on the contact hole CT. Specifically, the first source and the first drain are respectively connected to the first metal wire through the first contact hole, and the first gate is connected to the second metal wire through the second contact hole. By applying a voltage signal to the second metal wire connected to the first gate, the conductive state of the channel region can be controlled, thereby measuring the capacitance of the first MOS device in the strong inversion state, and then calculating the electrical thickness of the first gate oxide layer.

[0053] In the first MOS structure, a first electrode plate is formed above the source-drain region. The first electrode plate may include a first source, a first contact hole above the first source, and a first metal line above the first contact hole, or may include a first drain, a first contact hole, and a first metal line. A second electrode plate is formed above the channel region. The second electrode plate includes a first gate oxide layer, and a first gate, a second contact hole, and a second metal line sequentially disposed above the first gate oxide layer. The first gate has a first overlapping region with the source-drain region. Specifically, the first gate has overlapping regions A1 and A2 with the first source and the first drain, respectively.

[0054] In this embodiment, the gate oxide layer electrical thickness monitoring structure further includes a second MOS structure spaced apart from the first MOS structure. The configuration of the second MOS structure can refer to the above embodiment. For the sake of simplicity, any details not mentioned in the configuration of the second MOS structure can be referred to the corresponding contents of the first MOS structure. The first MOS structure and the second MOS structure can be provided in one or more forms. The second MOS structure differs from the first MOS structure in that:

[0055] In the second MOS structure, a third electrode plate is formed above the source-drain region. The third electrode plate may include a second source electrode, a third contact hole above the second source electrode, and a third metal line above the third contact hole. The third electrode plate may also include a second drain electrode, a third contact hole above the second drain electrode, and a third metal line above the third contact hole. A fourth electrode plate is formed above the channel region. The fourth electrode plate includes a second gate oxide layer, and a second gate electrode, a fourth contact hole, and a fourth metal line sequentially disposed above the second gate oxide layer. The second gate electrode has a second overlapping region with the source-drain region. Specifically, the second gate electrode has overlapping region B1 and overlapping region B2 with the second source electrode and the second drain electrode, respectively.

[0056] During semiconductor manufacturing, when a first MOS structure and a second MOS structure are arranged alternately on the same wafer, careful design and strict control of process conditions can ensure that the two structures achieve consistent process quality across all process steps. Specifically, the manufacture of MOS structures involves multiple process steps, including photolithography, etching, ion implantation, deposition, and annealing. To achieve high process consistency, precise control measures are required in each process step. For example, during photolithography, strict control of wafer alignment accuracy and light dose can ensure consistent pattern dimensions between the first and second MOS structures. During etching, optimizing etching parameters (such as etching gas flow, power, and time) can ensure consistent etch depth and shape between the two structures. During ion implantation, precise control of implant dose and energy can ensure consistent doping concentration between the two structures. Furthermore, regular equipment calibration, process parameter optimization, and real-time monitoring of process conditions (such as deposition rate, temperature profile, and annealing time) are key to achieving high process consistency. In this embodiment, by arranging the first and second MOS structures alternately, consistent process quality across all stages of the first and second MOS structures can be achieved.

[0057] like Figures 1-4 As shown, in this embodiment, along the channel direction, the distance between any point on the first electrode plate and the second electrode plate is the same as the distance between the corresponding point on the third electrode plate and the fourth electrode plate. Specifically, the distance between the first metal wire and the second metal wire is the same as the distance between the third metal wire and the fourth metal wire (D m2m ); the distance between the first contact hole and the second contact hole is the same as the distance between the third contact hole and the fourth contact hole (D c2c The distance between the first contact hole and the first gate is the same as the distance between the third contact hole and the second gate (D c2p). In this arrangement, since the height of each section of the process of the first MOS structure and the second MOS structure is consistent, the distance between any point on the first plate and the second plate along the channel direction is the same as the distance between the corresponding point on the third plate and the fourth plate, so that the parasitic capacitance in the first MOS structure and the second MOS structure includes the capacitance C between the contact hole and the gate. c2p , contact hole and contact hole C c2c , the capacitance C between the metal line and the contact hole m2c , the capacitance C between the metal line and the gate m2p , the capacitance C between metal lines m2m And the gate and source-drain capacitance C of In addition, since the area of ​​the first overlapping region is the same as that of the second overlapping region, the over-coverage capacitance C of the gate in the first MOS structure and the second MOS structure is ov In this way, all parasitic capacitances in the first MOS structure and the second MOS structure remain consistent.

[0058] In this embodiment, the overlapping area A1 is the same as the overlapping area B1, and the overlapping area A2 is the same as the overlapping area B2. In this way, since the process heights of the first MOS structure and the second MOS structure are consistent, the gate over-coverage capacitance C ov Stay consistent.

[0059] In this embodiment, the gate region on the second plate has the same gate width and different gate lengths as the gate region on the fourth plate. In some embodiments, the width of the first gate is the same as the width of the second gate, and the length of the first gate is greater than the length of the second gate. By setting the gate region on the second plate to have the same gate width and different gate lengths as the gate region on the fourth plate, the difference between the first MOS structure and the second MOS structure is only the gate length, so that the parasitic capacitance can be offset by the capacitance measurement results of the first MOS structure and the second MOS structure, and then the accurate electrical thickness of the gate oxide layer can be calculated. This monitoring structure does not require additional process steps and has good compatibility with actual semiconductor manufacturing processes. By monitoring the capacitance value, the final thickness of the gate oxide layer can be effectively monitored, thereby improving the accuracy and efficiency of process monitoring.

[0060] It should be noted that, along the channel direction, in order to ensure that the distance between any point on the first plate and the second plate is the same as the distance between the corresponding point on the third plate and the fourth plate, the length of the first gate is greater than the length of the second gate, and the number of the second contact holes is greater than the number of the fourth contact holes. In some embodiments, the number of second contact holes is at least 2, and the number of fourth contact holes is at least 1. In this way, when the length of the first gate is greater than the length of the second gate, the distance between the first contact hole and the nearest second contact hole is the same as the distance between the third contact hole and the nearest fourth contact hole, ensuring that the distance between any point on the first plate and the second plate is the same as the distance between the corresponding point on the third plate and the fourth plate, so that the parasitic capacitance in the first MOS structure and the second MOS structure remains consistent.

[0061] Of course, in other embodiments, the number of the second contact holes and the fourth contact holes can be adaptively set according to the specific settings of the first MOS structure and the second MOS structure, and the present application does not limit this.

[0062] Example 2

[0063] like Figure 5 As shown, this embodiment provides a gate oxide layer electrical thickness monitoring method, which is applied to the gate oxide layer electrical thickness monitoring structure as described in Example 1. For matters not mentioned in this embodiment, please refer to the relevant content of Example 1, and this embodiment will not be repeated. The gate oxide layer electrical thickness monitoring method can be executed by a computer, specifically, by one or more processors in the computer, and includes the following steps S101-S103.

[0064] Step S101 : determining an area of ​​a first gate oxide layer below a gate region on a second electrode plate and an area of ​​a second gate oxide layer below a gate region on a fourth electrode plate.

[0065] In this embodiment, the area A1 of the first gate oxide layer below the gate region on the second electrode can be calculated by multiplying the length L1 of the first gate in the channel direction by the width W1 perpendicular to the channel direction: A1=L1*W1; the area A2 of the second gate oxide layer below the gate region on the fourth electrode can be calculated by multiplying the length L2 of the second gate in the channel direction by the width W2 perpendicular to the channel direction: A2=L2*W2.

[0066] Step S102 : determining a first total capacitance of the first MOS structure and a second total capacitance of the second MOS structure.

[0067] In this embodiment, the first total capacitance of the first MOS structure and the second total capacitance of the second MOS structure are both capacitances of the corresponding MOS structures in a strong inversion state.

[0068] In this embodiment, determining the first total capacitance C1 of the first MOS structure includes: connecting the metal wire connected to the first gate to a voltage source and applying a scan voltage, grounding or floating the metal wires connected to the first source and the first drain, and collecting a current signal. Integrating the collected current over time to calculate the charge dt. Then, the first total capacitance is calculated based on the relationship between the scan voltage U1 and the charge Q1. .

[0069] Determining the second total capacitance C2 of the second MOS structure includes: connecting the metal wire connected to the second gate to a voltage source and applying a scan voltage, grounding or floating the metal wires connected to the second source and the second drain, and collecting a current signal. Integrating the collected current over time to calculate the charge Then, the first total capacitance is calculated based on the relationship between the scan voltage U2 and the charge Q2. .

[0070] It can be understood that the first total capacitance of the first MOS structure and the second total capacitance of the second MOS structure can also be obtained by analyzing the CV characteristic curve through the CV measurement method or measured by other methods. They can be adaptively selected according to the measurement frequency range, accuracy requirements and equipment availability, and this application is not limited thereto.

[0071] In this embodiment, the first total capacitance C1 of the first MOS structure includes the first gate oxide layer capacitance C ox1 and the first parasitic capacitance C x1 , the first parasitic capacitance C x1 Including the capacitance C between the contact hole and the gate in the first MOS structure c2p , contact hole and contact hole C c2c , the capacitance C between the metal line and the contact hole m2c , the capacitance C between the metal line and the gate m2p , the capacitance C between metal lines m2m And the gate and source-drain capacitance C of And the gate over-coverage capacitance C ov The second total capacitance C2 of the second MOS structure includes the second gate oxide layer capacitance C ox2 and the second parasitic capacitance C x2 , the second parasitic capacitance C x2 Including the capacitance C between the contact hole and the gate in the second MOS structure c2p , contact hole and contact hole C c2c , the capacitance C between the metal line and the contact hole m2c , the capacitance C between the metal line and the gate m2p, the capacitance C between metal lines m2m And the gate and source-drain capacitance C of And the gate over-coverage capacitance C ov .

[0072] Since the process heights of the first MOS structure and the second MOS structure are consistent, along the channel direction, the distance between any point on the first plate and the second plate is the same as the distance between the corresponding point on the third plate and the fourth plate, and the area of ​​the first overlapping region and the second overlapping region are the same, so that the first parasitic capacitance C x1 Equal to the second parasitic capacitance C x2 .

[0073] Step S103 : calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance C1 , the first gate oxide layer area A1 , the second total capacitance C2 , and the second gate oxide layer area A2 .

[0074] In this embodiment, using the gate oxide layer electrical thickness monitoring structure, based on the first total capacitance C1, the first gate oxide layer area A1, the second total capacitance C2, the second gate oxide layer area A2 and the gate oxide layer thickness calculation formula, the gate oxide layer electrical thickness of the first MOS structure and the second MOS structure in the gate oxide layer electrical thickness monitoring structure can be calculated.

[0075] In some embodiments, the gate oxide thickness is calculated as follows:

[0076] , where C (1)

[0077] in, is the gate oxide thickness, is the dielectric constant of vacuum, is the relative dielectric constant of the gate oxide layer, A is the gate area, C is the total capacitance, is the gate oxide capacitance, is the parasitic capacitance.

[0078] In this embodiment, the gate oxide layer capacitance calculation formula (1) is known, and the first gate oxide layer capacitance can be set as C ox1 , the first parasitic capacitance is C x1 , substituting the first total capacitance C1 and the first gate oxide layer area A1 into the above formula, we can obtain:

[0079] (2)

[0080] Let the second gate oxide capacitance be C ox2 , the second parasitic capacitance is Cx2，将第二总电容C2 , Substituting the area of ​​the second gate oxide layer A2 into the above formula, we can get:

[0081] (3)

[0082] Since the thickness of the first gate oxide layer The thickness of the second gate oxide layer Equal, the first parasitic capacitance C x1 and the second parasitic capacitance C x2 If they are equal,

[0083] And C x1 =C x2 （4）

[0084] According to equations (2)-(3), the first parasitic capacitance C of the first MOS structure can be calculated as x1 , C x1 Substituting into formula (2), the electrical thickness of the gate oxide layer of the first MOS structure is obtained .

[0085] In some other embodiments, calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure includes the following steps:

[0086] In step S1031 , a third equivalent capacitance C3 may be determined according to the first total capacitance C1 and the second total capacitance C2 , where the third equivalent capacitance C3 does not include parasitic capacitance.

[0087] Step S1032 : determining a third equivalent gate oxide area A3 according to the first gate oxide area A1 and the second gate oxide area A2 , wherein the third equivalent gate oxide has the same thickness as the first gate oxide and the second gate oxide.

[0088] Step S1033 , calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the third equivalent capacitance C3 , the third equivalent gate oxide layer area A3 and the capacitance formula.

[0089] In this embodiment, C3 = C1 - C2 and A3 = A1 - A2 (5)

[0090] Combining equations (1), (4) and (5), we can get C3=C ox1 -C ox2 (6)

[0091] Since the first gate oxide layer area A1 and the first gate oxide layer area A2 are:

[0092] A1=L1*W A2=L2*W (7)

[0093] Where W is the width of the first gate and the width of the second gate, then from equations (5) and (7) we can get:

[0094] ( - )*W (8)

[0095] Substituting equations (6) and (8) into equation (1), we can obtain the electrical thickness of the gate oxide layer:

[0096]

[0097] In this embodiment, the gate oxide layer capacitance The third equivalent capacitance C3 is proportional to the area A of the gate oxide layer. The third equivalent capacitance C3 is the difference between the first total capacitance C1 and the second total capacitance C2. The third equivalent gate oxide layer area A3 is the difference between the first gate oxide layer area A1 and the second gate oxide layer area A2. Therefore, the third equivalent capacitance C3 is proportional to the third equivalent gate oxide layer area A3. The third equivalent gate oxide layer has the same thickness as the first gate oxide layer and the second gate oxide layer, and the third equivalent capacitance C3 does not include parasitic capacitance and is the capacitance of the third equivalent gate oxide layer. Therefore, the third equivalent capacitance C3 and the third equivalent gate oxide layer area A3 are applied to the capacitance formula (4) to calculate the accurate gate oxide layer thickness. .

[0098] By the above steps, the capacitance measurement results of the first MOS structure and the second MOS structure offset the parasitic capacitance, thereby calculating the accurate electrical thickness of the gate oxide layer. This monitoring structure does not require additional process steps and has good compatibility with actual semiconductor manufacturing processes. By monitoring the capacitance value, the final thickness of the gate oxide layer can be effectively monitored, thereby improving the accuracy and efficiency of process monitoring. It should be understood that although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless clearly stated herein, the execution of these steps does not have strict order restrictions, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of the steps or stages in other steps.

[0099] Based on the same inventive concept, an embodiment of the present application further provides a gate oxide layer electrical thickness monitoring device for implementing the aforementioned gate oxide layer electrical thickness method. The implementation solution provided by this device is similar to the implementation solution described in the aforementioned method. Therefore, the specific limitations of one or more gate oxide layer electrical thickness monitoring device embodiments provided below can be referred to the limitations of the gate oxide layer electrical thickness monitoring method above, and will not be repeated here.

[0100] In one embodiment, a gate oxide layer electrical thickness monitoring device is provided, comprising: a gate oxide layer area determination unit, a total capacitance determination unit, and a gate oxide layer electrical thickness calculation unit.

[0101] a gate oxide layer area determining unit, configured to determine an area of ​​a first gate oxide layer below the gate region on the second electrode plate and an area of ​​a second gate oxide layer below the gate region on the fourth electrode plate;

[0102] a total capacitance determining unit, configured to determine a first total capacitance of the first MOS structure and a second total capacitance of the second MOS structure;

[0103] The gate oxide layer electrical thickness calculation unit is used to calculate the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance and the second gate oxide layer area.

[0104] In some embodiments, the total capacitance determination unit includes: a first current acquisition unit, a first charge amount determination unit, and a first calculation unit.

[0105] a first current acquisition unit, configured to acquire a current signal of a first MOS structure, wherein a scan voltage is applied above the gate of the first MOS structure and the source and drain regions are grounded;

[0106] a first charge amount determining unit, configured to integrate the current signal with respect to time to determine the charge amount;

[0107] The first calculation unit is configured to calculate a first total capacitance according to the scanning voltage and the charge amount.

[0108] In some embodiments, the total capacitance determination unit further includes: a second current acquisition unit, a second charge determination unit, and a second calculation unit.

[0109] a second current acquisition unit, configured to acquire a current signal of a second MOS structure, wherein a scan voltage is applied above the gate of the second MOS structure and the source and drain regions are grounded;

[0110] a second charge amount determining unit, configured to integrate the current signal with respect to time to determine the charge amount;

[0111] The second calculation unit is configured to calculate a second total capacitance according to the scanning voltage and the charge amount.

[0112] In some embodiments, the gate oxide layer electrical thickness calculation unit includes: an equivalent capacitance determination unit, an equivalent gate oxide layer area determination unit, and a first thickness calculation unit.

[0113] an equivalent capacitance determining unit, configured to determine a third equivalent capacitance based on the first total capacitance and the second total capacitance, wherein the third equivalent capacitance does not include parasitic capacitance;

[0114] an equivalent gate oxide layer area determining unit, configured to determine a third equivalent gate oxide layer area according to the first gate oxide layer area and the second gate oxide layer area;

[0115] The first thickness calculation unit is used to calculate the electrical thickness of the gate oxide layer of the first MOS structure and the second MOS structure based on the third equivalent capacitance, the third equivalent gate oxide layer area and the capacitance formula.

[0116] In some embodiments, the gate oxide layer electrical thickness calculation unit includes: a parasitic capacitance calculation unit and a second thickness calculation unit.

[0117] a parasitic capacitance calculation unit, configured to determine a first parasitic capacitance and a second parasitic capacitance based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area;

[0118] A second thickness calculation unit is used to determine the electrical thickness of the gate oxide layer of the first MOS structure based on the first total capacitance, the first gate oxide layer area and the first parasitic capacitance, or to determine the electrical thickness of the gate oxide layer of the second MOS structure based on the second total capacitance, the second gate oxide layer area and the second parasitic capacitance.

[0119] In one embodiment, a computer device is provided, which may be a server or a terminal device. The computer device includes a processor, a memory, and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the above-mentioned gate oxide layer electrical thickness monitoring method is implemented.

[0120] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A gate oxide layer electrical thickness monitoring structure, characterized in that: include: A first MOS structure and a second MOS structure are arranged at intervals, wherein: In the first MOS structure, a first plate is formed above the source and drain regions, a second plate is formed above the channel region, and the gate on the second plate has a first overlapping region with the source and drain regions; In the second MOS structure, a third plate is formed above the source and drain regions, a fourth plate is formed above the channel region, and the gate on the fourth plate has a second overlapping region with the source and drain regions; Along the channel direction, the distance between any point on the first plate and the second plate is the same as the distance between the corresponding point on the third plate and the fourth plate, the area of ​​the first overlapping region is the same as the area of ​​the second overlapping region, and the gate region on the second plate has the same gate width and different gate length compared to the gate region on the fourth plate; the number of contact holes above the gate in the first MOS structure is greater than the number of contact holes above the gate in the second MOS structure.

2. The gate oxide layer electrical thickness monitoring structure according to claim 1, wherein: The first MOS structure includes: A first source electrode and a first drain electrode are connected to a first metal line through a first contact hole, respectively; and a first gate electrode is connected to a second metal line through a second contact hole; The second MOS structure includes: The second source and the second drain are respectively connected to the third metal line through the third contact hole; and the second gate is connected to the fourth metal line through the fourth contact hole; The distance between the first metal line and the second metal line is the same as the distance between the third metal line and the fourth metal line; the distance between the first contact hole and the second contact hole is the same as the distance between the third contact hole and the fourth contact hole; the distance between the first contact hole and the first gate is the same as the distance between the third contact hole and the second gate; The width of the first gate is equal to the width of the second gate, the length of the first gate is greater than the length of the second gate, and the number of the second contact holes is greater than the number of the fourth contact holes.

3. The gate oxide layer electrical thickness monitoring structure according to claim 2, wherein: The first gate has overlapping areas A1 and A2 with the first source and the first drain, respectively; the second gate has overlapping areas B1 and B2 with the second source and the second drain, respectively; the overlapping areas A1 and B1 are the same in area, and the overlapping areas A2 and B2 are the same in area; The width of the first gate is the same as that of the second gate, and the length of the first gate is greater than that of the second gate.

4. A gate oxide layer electrical thickness monitoring method, applied to the gate oxide layer electrical thickness monitoring structure according to any one of claims 1 to 3, characterized in that: include: Determining an area of ​​a first gate oxide layer below a gate region on the second electrode plate and an area of ​​a second gate oxide layer below a gate region on the fourth electrode plate; determining a first total capacitance of the first MOS structure and a second total capacitance of the second MOS structure; The electrical thicknesses of the gate oxide layers of the first MOS structure and the second MOS structure are calculated based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area.

5. The method for monitoring the electrical thickness of a gate oxide layer according to claim 4, wherein: Determining a first total capacitance of the first MOS structure includes: Acquiring a current signal of a first MOS structure, wherein a scan voltage is applied above the gate of the first MOS structure and the source and drain regions are grounded; integrating the current signal with respect to time to determine the amount of charge; A first total capacitance is calculated according to the scan voltage and the charge amount.

6. The method for monitoring the electrical thickness of a gate oxide layer according to claim 4, wherein: Determining a second total capacitance of the second MOS structure includes: Acquiring a current signal of a second MOS structure, wherein a scan voltage is applied above the gate of the second MOS structure and the source and drain regions are grounded; integrating the current signal with respect to time to determine the amount of charge; A second total capacitance is calculated according to the scan voltage and the charge amount.

7. The method for monitoring the electrical thickness of a gate oxide layer according to claim 4, wherein: Calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area includes: determining a third equivalent capacitance according to the first total capacitance and the second total capacitance, wherein the third equivalent capacitance does not include parasitic capacitance; Determining a third equivalent gate oxide layer area according to the first gate oxide layer area and the second gate oxide layer area, wherein the third equivalent gate oxide layer has the same thickness as the first gate oxide layer and the second gate oxide layer; Based on the third equivalent capacitance, the third equivalent gate oxide layer area and the capacitance formula, the electrical thickness of the gate oxide layer of the first MOS structure and the second MOS structure is calculated.

8. The method for monitoring the electrical thickness of a gate oxide layer according to claim 4, wherein: Calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area includes: Determining a first parasitic capacitance and a second parasitic capacitance based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area; The electrical thickness of the gate oxide layer of the first MOS structure is determined based on the first total capacitance, the first gate oxide layer area and the first parasitic capacitance, or the electrical thickness of the gate oxide layer of the second MOS structure is determined based on the second total capacitance, the second gate oxide layer area and the second parasitic capacitance.

9. A gate oxide layer electrical thickness monitoring device, applied to the gate oxide layer electrical thickness monitoring structure according to any one of claims 1 to 3, characterized in that: include: a gate oxide layer area determining unit, configured to determine an area of ​​a first gate oxide layer below the gate region on the second electrode plate and an area of ​​a second gate oxide layer below the gate region on the fourth electrode plate; a total capacitance determining unit, configured to determine a first total capacitance of the first MOS structure and a second total capacitance of the second MOS structure; The gate oxide layer electrical thickness calculation unit is used to calculate the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance and the second gate oxide layer area.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 4 to 8 are implemented.

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