Anti-mis-triggering electrostatic discharge clamp circuit

Abstract

The application discloses a mistaken trigger prevention electrostatic discharge clamping circuit, and belongs to the technical field of integrated circuit electrostatic discharge protection, which comprises a control transistor, a PMOS current mirror resistance branch, an NMOS current mirror capacitance branch, an inverter and a clamping transistor; through feedback control and voltage division design, the RC structure composed of the PMOS current mirror resistance branch and the NMOS current mirror capacitance branch has different RC time constants in electrostatic discharge events and normal or fast power-on, and has good mistaken trigger prevention characteristics; the application also amplifies small capacitance and small resistance through two groups of current mirror structures, and based on equivalent large resistance and large capacitance, greatly reduces the layout area occupied by the resistance and capacitance. The application solves the problems of easy mistaken trigger of the electrostatic discharge clamping transistor and large layout area occupied by the resistance and capacitance in the existing integrated circuit.

Description

Technical Field

[0001] This invention belongs to the field of strain measurement technology, and in particular relates to an electrostatic discharge clamping circuit to prevent accidental triggering. Background Technology

[0002] Electrostatic discharge (ESD) is an extremely common phenomenon in daily life. ESD can generate voltages of thousands of volts, which can produce enormous currents in integrated circuits (ICs), causing problems such as gate oxide breakdown, metal interconnect melting, and PN junction breakdown. This potential damage becomes even more pronounced as ICs move into the deep submicron stage, where they can only withstand voltages of a few to tens of volts. Therefore, ESD protection is crucial for ICs, and almost all current ICs incorporate ESD protection structures. In on-chip ESD protection, the ESD power supply clamping circuit is a vital component. Its primary purpose is to provide ESD protection between power supply pins, preventing ESD current from damaging the power supply pins and internal circuitry.

[0003] Traditional RC-triggered clamping circuits consist of an RC detection network, an inverter, and a clamping transistor. The RC detection branch typically comprises resistors and capacitors, and different RC time constants can be set by adjusting parameters. The inverter usually acts as the driver circuit for the clamping transistor, pulling the level of the detection branch high or low to control the transistor's turn-on and turn-off. When the clamping transistor is on, a large current can flow, thus dissipating ESD energy. However, traditional RC detection branches with fixed RC time constants are easily confused with ESD events during rapid power-on detection, posing a significant risk of false triggering. Furthermore, in some manufacturing processes, due to the very small resistance or capacitance per unit area, achieving a sufficiently long RC time constant requires sacrificing a large layout area, which is unacceptable in integrated circuit designs that prioritize good anti-false triggering characteristics, high integration, and low cost. Summary of the Invention

[0004] In view of the above-mentioned shortcomings in the prior art, the present invention provides an electrostatic discharge clamping circuit to prevent false triggering, which solves the problem that electrostatic discharge clamping tubes in existing integrated circuits are prone to false triggering.

[0005] To achieve the above-mentioned objectives, the technical solution adopted by this invention is as follows:

[0006] The present invention provides an electrostatic discharge clamping circuit for preventing accidental triggering, comprising a control transistor, a PMOS current mirror resistor branch, an NMOS current mirror capacitor branch, an inverter, and a clamping transistor;

[0007] The control transistor is connected to the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch respectively, and is externally connected to the power supply voltage VDD; the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch are connected, and are externally connected to the power supply voltage VDD and the ground level VSS respectively; the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch form an RC structure; the NMOS current mirror capacitor branch is connected to the inverter and is externally connected to the ground level VSS; the inverter is connected to the clamping transistor and is externally connected to the power supply voltage VDD and the ground level VSS respectively; the clamping transistor is externally connected to the power supply voltage VDD and the ground level VSS respectively.

[0008] The beneficial effects of this invention are as follows: In the electrostatic discharge clamping circuit for preventing false triggering provided by this invention, an RC structure is formed by a PMOS current mirror resistor branch and an NMOS current mirror capacitor branch. The RC structure provides feedback control for the control transistor. Through feedback control and voltage divider design, the RC structure formed by the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch has different RC time constants during electrostatic discharge events and normal power-on or rapid power-on, thus exhibiting good anti-false triggering characteristics. Furthermore, by setting the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch, this invention achieves equivalent amplification of the capacitor and resistor based on two sets of current mirror structures. Based on the equivalent large resistance and large capacitance, the layout area required by the resistor and capacitor is significantly reduced.

[0009] Furthermore, the control transistor is a feedback-controlled PMOS transistor Mp0, which serves as the switching transistor for the PMOS current mirror resistor branch and also as a voltage divider transistor for normal power-on and fast power-on.

[0010] The source and substrate of the PMOS transistor Mp0 are both externally connected to a power supply voltage VDD; the gate of the PMOS transistor Mp0 is connected to both the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch to receive the detection signal V from the RC structure. RC This forms a feedback structure; the drain of the PMOS transistor Mp0 is connected to the PMOS current mirror resistor branch.

[0011] Furthermore, the PMOS current mirror resistor branch includes PMOS transistor Mp1, PMOS transistor Mp2, and resistor R;

[0012] The substrate of PMOS transistor Mp1 is connected to an external power supply voltage VDD; the source of PMOS transistor Mp1 is connected to the drain of PMOS transistor Mp0; the gate of PMOS transistor Mp1 is connected to the drain, one end of resistor R, and the gate of PMOS transistor Mp2; the other end of resistor R is grounded to a voltage level VSS; the source and substrate of PMOS transistor Mp2 are both connected to an external power supply voltage VDD; the drain of PMOS transistor Mp2 is connected to the NMOS current mirror capacitor branch to generate the detection signal V of the RC structure. RC .

[0013] Furthermore, the NMOS current mirror capacitor branch includes a PMOS transistor Mp3, an NMOS transistor Mn0, and an NMOS transistor Mn1 connected in a capacitor configuration;

[0014] The source of the PMOS transistor Mp3 is connected to its drain, the substrate, the drain of the PMOS transistor Mp2, the gate of the PMOS transistor Mp0, the drain of the NMOS transistor Mn1, and an inverter, respectively, to generate the detection signal V of the RC structure. RC The gate of the PMOS transistor Mp3 is connected to the gate of the NMOS transistor Mn1, the drain and the gate of the NMOS transistor Mn0, respectively; the source and substrate of the NMOS transistor Mn0 are both externally grounded at a voltage level VSS; the source and substrate of the NMOS transistor Mn1 are both externally grounded at a voltage level VSS.

[0015] Furthermore, the inverter includes a PMOS transistor Mp4 and an NMOS transistor Mn2;

[0016] The gate of the PMOS transistor Mp4 is connected to the gate of the NMOS transistor Mn2 and the drain of the NMOS transistor Mn1, respectively; the source of the PMOS transistor Mp4 and the substrate are connected to an external power supply voltage VDD; the source of the NMOS transistor Mn2 and the substrate are connected to an external ground level VSS; the drain of the PMOS transistor Mp4 is connected to the drain of the NMOS transistor Mn2 and a clamping transistor, respectively, to generate a driving voltage V. G And input clamping transistor.

[0017] Furthermore, the clamping transistor is an NMOS transistor Mn3;

[0018] The gate of the NMOS transistor Mn3 is connected to the drain of the PMOS transistor Mp4 and the drain of the NMOS transistor Mn2, respectively, to receive the drive voltage V. G The drain of the NMOS transistor Mn3 is connected to an external power supply voltage VDD; the source and substrate of the NMOS transistor Mn3 are both grounded to an external ground level VSS.

[0019] Other advantages of the present invention will be analyzed in more detail in the following embodiments. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a block diagram of an electrostatic discharge clamping circuit for preventing accidental triggering, as described in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of an electrostatic discharge clamping circuit for preventing accidental triggering, as described in an embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of a conventional RC-triggered clamping circuit in an embodiment of the present invention.

[0024] Figure 4 The diagram shows the node voltage waveforms of the circuit according to the present invention under electrostatic discharge event simulation in an embodiment of the present invention.

[0025] Figure 5 The waveform diagram shows the ability of the clamping transistor to discharge electrostatic discharge current in an electrostatic discharge event, comparing the circuit of the present invention with that of a conventional RC-triggered clamping circuit in an embodiment of the present invention.

[0026] Figure 6 The diagram shows the node voltage waveforms of the circuit of the present invention and the conventional RC-triggered clamping circuit under normal power-on event simulation in the embodiments of the present invention.

[0027] Figure 7 The image shows the leakage current waveform of the clamping transistor under normal power-on event simulation of the circuit of the present invention and the conventional RC-triggered clamping circuit in the embodiments of the present invention.

[0028] Figure 8 The diagram shows the node voltage waveforms of the circuit of the present invention and the conventional RC-triggered clamping circuit under a rapid power-on event simulation in the embodiments of the present invention.

[0029] Figure 9 This is a size comparison diagram between the clamping circuit of the present invention and a conventional clamping circuit in an embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0031] like Figure 1 As shown, in one embodiment of the present invention, the present invention provides an electrostatic discharge clamping circuit to prevent accidental triggering, including a control transistor, a PMOS current mirror resistor branch, an NMOS current mirror capacitor branch, an inverter, and a clamping transistor.

[0032] The control transistor is connected to the PMOS current mirror resistor branch, the NMOS current mirror capacitor branch, and the inverter, and is externally connected to the power supply voltage VDD; the PMOS current mirror resistor branch is connected to the NMOS current mirror capacitor branch and the inverter, and is externally connected to the power supply voltage VDD and the ground level VSS, respectively; the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch form an RC structure; the NMOS current mirror capacitor branch is connected to the inverter and is externally connected to the ground level VSS; the inverter is connected to the clamping transistor and is externally connected to the power supply voltage VDD and the ground level VSS, respectively; the clamping transistor is externally connected to the power supply voltage VDD and the ground level VSS, respectively.

[0033] like Figure 2 As shown, the control transistor is a feedback-controlled PMOS transistor Mp0, which serves as the switching transistor for the PMOS current mirror resistor branch and also as a voltage divider transistor for normal power-on and fast power-on.

[0034] In this scheme, when the PMOS transistor Mp0 is used as the switching transistor of the PMOS current mirror resistor branch, it can control the leakage current. When the PMOS transistor Mp0 is used as the voltage divider transistor for normal power-on and fast power-on, it can change the RC time constant to prevent false triggering. The RC structure refers to the resistor-capacitor structure formed by connecting the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch.

[0035] When the internal circuit of the integrated circuit is working normally, the detection signal V of the RC structure RC When the voltage is high, the gate voltage of the PMOS transistor Mp0 is controlled by feedback, so that the PMOS transistor Mp0 is in the off state and acts as the switching transistor of the PMOS current mirror resistor branch to control the leakage current.

[0036] During normal and rapid power-up, because PMOS transistor Mp0 acts as a voltage divider transistor, PMOS transistor Mp1 will be in a subthreshold conducting state, while PMOS transistor Mp2 will be in a fully conducting state. At this time, the on-resistance of PMOS transistor Mp2 will form a new RC structure with the NMOS current mirror capacitor branch. Compared with the large RC time constant during electrostatic discharge events, the duration of the new RC structure is very small, within a few nanoseconds, which has a sensitive detection capability and can accurately prevent false triggering.

[0037] The source and substrate of the PMOS transistor Mp0 are both externally connected to a power supply voltage VDD; the gate of the PMOS transistor Mp0 is connected to both the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch to receive the detection signal V from the RC structure. RC This forms a feedback structure; the drain of the PMOS transistor Mp0 is connected to the PMOS current mirror resistor branch.

[0038] The PMOS current mirror resistor branch includes PMOS transistor Mp1, PMOS transistor Mp2 and resistor R;

[0039] The substrate of PMOS transistor Mp1 is connected to an external power supply voltage VDD; the source of PMOS transistor Mp1 is connected to the drain of PMOS transistor Mp0; the gate of PMOS transistor Mp1 is connected to the drain, one end of resistor R, and the gate of PMOS transistor Mp2; the other end of resistor R is grounded to a voltage level VSS; the source and substrate of PMOS transistor Mp2 are both connected to an external power supply voltage VDD; the drain of PMOS transistor Mp2 is connected to the NMOS current mirror capacitor branch to generate the detection signal V of the RC structure. RC In this scheme, V A V is the node voltage between PMOS transistors Mp0 and Mp1, and V B This represents the common gate voltage of PMOS transistors Mp1 and Mp2 in the PMOS current mirror resistor branch.

[0040] In this scheme, the PMOS current mirror resistor branch is equivalent to a large resistor, and its current is reduced by a factor of two, thereby charging the capacitor. The set of current mirrors in the PMOS current mirror resistor branch that amplifies the resistor R uses a PMOS structure. Through the ratio of the MOSFET width to length, the large current flowing through the resistor is reduced by approximately nine times after passing through the current mirror composed of PMOS transistors Mp1 and Mp2, thus charging the capacitor. Therefore, the capacitor requires a longer time to reach the inverter's reversal threshold voltage. Thus, the PMOS current mirror resistor branch provided by this invention is equivalent to a large resistor. Furthermore, this invention controls the leakage current of the PMOS current mirror resistor branch through PMOS transistor Mp0, and the gate of PMOS transistor Mp0 is connected to the intermediate node of the RC structure.

[0041] The NMOS current mirror capacitor branch includes a PMOS transistor Mp3, an NMOS transistor Mn0, and an NMOS transistor Mn1 connected in a capacitor configuration.

[0042] The source of the PMOS transistor Mp3 is connected to its drain, the substrate, the drain of the PMOS transistor Mp2, the gate of the PMOS transistor Mp0, the drain of the NMOS transistor Mn1, and an inverter, respectively, to generate the detection signal V of the RC structure. RC The gate of the PMOS transistor Mp3 is connected to the gate of the NMOS transistor Mn1, the drain and the gate of the NMOS transistor Mn0, respectively; the source and substrate of the NMOS transistor Mn0 are both externally grounded at a voltage level VSS; the source and substrate of the NMOS transistor Mn1 are both externally grounded at a voltage level VSS.

[0043] In this scheme, the NMOS current mirror capacitor branch can amplify the capacitance value of the PMOS transistor Mp3 in a capacitor-connected configuration by a factor of two, effectively making it equivalent to a large capacitor. The NMOS current mirror capacitor branch uses an inverted current mirror structure to amplify the impedance, achieving an impedance amplification of approximately 45 times through the ratio of the MOSFET width-to-length ratio, effectively increasing the capacitor's resistance. Furthermore, because this scheme uses an inverted current mirror structure, based on the relationship between the NMOS transistor's current-to-voltage and its width-to-length ratio, it can be observed that at the same voltage, the smaller the width-to-length ratio of the NMOS transistor, the smaller the current, thereby reducing the circuit's leakage current.

[0044] The inverter includes a PMOS transistor Mp4 and an NMOS transistor Mn2;

[0045] The gate of the PMOS transistor Mp4 is connected to the gate of the NMOS transistor Mn2 and the drain of the NMOS transistor Mn1, respectively; the source of the PMOS transistor Mp4 and the substrate are connected to an external power supply voltage VDD; the source of the NMOS transistor Mn2 and the substrate are connected to an external ground level VSS; the drain of the PMOS transistor Mp4 is connected to the drain of the NMOS transistor Mn2 and a clamping transistor, respectively, to generate a driving voltage V. G And input clamping transistor.

[0046] In this scheme, the inverter is composed of a PMOS transistor Mp4 and an NMOS transistor Mn2 to generate a drive voltage V. G And input clamping transistor; in order to make the PMOS transistor Mp4 have sufficient driving capability, its size is selected to be 1 / 20 of the clamping transistor. The driving capability of the NMOS transistor Mn2 is better than that of the PMOS transistor Mp4, and it further affects the circuit delay time. Therefore, in this scheme, the size of the NMOS transistor Mn2 is selected to be 1 / 4 of that of the PMOS transistor Mp4.

[0047] The clamping transistor is an NMOS transistor Mn3;

[0048] The gate of the NMOS transistor Mn3 is connected to the drain of the PMOS transistor Mp4 and the drain of the NMOS transistor Mn2, respectively, to receive the drive voltage V. G The drain of the NMOS transistor Mn3 is connected to an external power supply voltage VDD; the source and substrate of the NMOS transistor Mn3 are both grounded to an external ground level VSS.

[0049] In this scheme, the clamping transistor is a large-size NMOS transistor Mn3, used to clamp according to the driving voltage V. G It is turned on during electrostatic discharge to discharge electrostatic discharge energy; the size of the NMOS transistor Mn3 determines the human body mode (HBM) protection level of the design. In this embodiment, the channel width / length of the selected NMOS transistor Mn3 is 1000μm / 180nm, which can achieve a failure current withstand capability of 1.8A, and its HBM protection level is about 2700V.

[0050] The circuit structure in this scheme is illustrated using a 0.18-micron, 1.8V complementary metal-oxide-semiconductor (CMOS) process as an example. The resistor R is the POLY resistor with the largest resistance per unit area under this CMOS process, and the capacitor is an active MOSFET capacitor.

[0051] The working principle of this invention is as follows:

[0052] (1) When an electrostatic discharge event occurs, the power-on speed is very fast, usually within 10 ns, while the voltage across the capacitor does not change abruptly. The node voltage of the large-resistance, large-capacitor RC structure composed of the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch, i.e. the detection signal V RC It cannot change rapidly with the power supply voltage VDD; therefore, when an electrostatic discharge event occurs, the detection signal V... RC The initial voltage is low, while the detection signal V of the RC structure is low. RC Furthermore, as the gate control voltage of the PMOS transistor Mp0, it ensures that the PMOS transistor Mp0 is fully turned on during an electrostatic discharge event, causing the current in the PMOS current mirror resistor branch to decrease significantly and be transferred to the NMOS current mirror capacitor branch for charging. Detection signal V RC This will create a voltage difference with the source voltage of PMOS transistor Mp4, causing PMOS transistor Mp4 to turn on and transmit the drive voltage V. G The voltage is pulled up to the power supply voltage VDD, which turns on the NMOS transistor Mn3 and discharges the electrostatic discharge energy.

[0053] In electrostatic discharge (ESD) events, the power-on time ranges from 100 ps to 60 ns, while the duration of HBM ESD is typically between 500 ns and 1 μs. Based on the requirements for discharge time and rapid, accurate detection in ESD events, the RC time constant is usually set to 500 ns. This requires large resistors and capacitors, which, in some processes, result in a large layout area due to the small resistance and capacitance values ​​per unit area. Furthermore, a single RC time constant design often weakens the anti-false triggering performance during rapid power-on. However, in the circuit of this invention, the equivalent amplification of resistors and capacitors is achieved through a current mirror structure. A larger RC time constant can be achieved with only smaller resistors and capacitors, freeing the choice of RC time constant from the limitations of resistor and capacitor selection and effectively saving layout area. Moreover, this solution introduces a feedback-controlled transistor that acts as a voltage divider during normal and rapid power-on. This results in a new RC structure with a small RC time constant during both normal and rapid power-on, providing excellent anti-false triggering characteristics within a few nanoseconds.

[0054] (2) During normal power-on, the power supply voltage VDD on the power line rises from 0 to the operating voltage within a relatively long time (usually 1μs to 1ms). In this embodiment, the operating voltage is 1.8V. Due to the slow power-on speed, the node voltage of the large-resistance, large-capacitor RC network composed of the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch, i.e., the detection signal V RC It will change with the power supply voltage VDD. Therefore, PMOS transistor Mp0 is in the off state, and the gate-source voltage V of PMOS transistor Mp1 is... BThe voltage will also fall below its turn-on threshold, and PMOS transistor Mp2 will be fully on. Its on-resistance will form a new low-constant RC structure with the NMOS current mirror capacitor branch. Since the source and gate voltages of PMOS transistor Mp4 change synchronously, the maximum gate-source voltage is 0, so PMOS transistor Mp4 is turned off. NMOS transistor Mn2 turns on as the gate voltage increases, and the drive voltage V... G When the value is pulled down to 0, the NMOS transistor Mn3 is turned off, and the entire circuit is in a closed state.

[0055] (3) When other special rapid power-up events occur, the power supply voltage VDD will rise from 0 to the operating voltage in a very short time (usually tens to hundreds of nanoseconds). This situation is similar to that of an electrostatic discharge event, and there may be instances of electrostatic discharge pulse confusion causing false triggering. In the detection of rapid power-up in this invention's circuit, the power supply voltage VDD is 1.8V. Due to the voltage division of the control transistor, PMOS transistor Mp1, and resistor R, V... A With V B The voltage difference between the two transistors is less than the turn-on threshold of PMOS transistor Mp1, so PMOS transistor Mp1 is in a subthreshold conducting state. Meanwhile, the gate voltage of PMOS transistor Mp2 is only a few millivolts, and its source is connected to the external power supply VDD, so it is fully conducting. At this time, a new RC structure is mainly formed by the fully conducting PMOS transistor Mp2 and the NMOS current mirror capacitor branch. Because the on-resistance of PMOS transistor Mp2 is very small, the overall RC time constant of the new RC structure becomes smaller. Therefore, the detection signal of the corresponding new RC structure closely follows the power supply voltage VDD, causing PMOS transistor Mp4 in the inverter to not turn on, and NMOS transistor Mn2 to turn on, realizing the pull-down drive voltage V. G This shuts down the NMOS transistor Mn3, putting the entire circuit in a closed state, thus effectively preventing false triggering during rapid power-up.

[0056] In a practical example of the present invention, the present invention simulates the voltage and current characteristics of nodes in an electrostatic discharge event based on the electrostatic discharge clamping circuit for preventing false triggering provided by the present invention, and compares and verifies it with the traditional RC-triggered clamping circuit under the same conditions.

[0057] like Figure 3 As shown, a traditional RC-triggered clamping circuit includes an RC detection network, an inverter, and a clamping transistor;

[0058] The RC detection network includes a resistor R1 and a capacitor C1; one end of the resistor R1 is connected to an external power supply VDD; the other end of the resistor R1 is connected to one end of the capacitor C1 and an inverter, and a node RC0 is formed at the connection between the RC detection network and the directional controller. The corresponding node voltage serves as the detection signal V of a traditional RC-triggered clamping circuit. RC0 The other end of capacitor C1 is grounded to a voltage level VSS; the inverter includes a PMOS transistor Mp10 and an NMOS transistor Mn10; the source and substrate of the PMOS transistor Mp10 are both externally connected to a power supply VDD; the gate of the PMOS transistor Mp10 is connected to the other end of resistor R1 and the gate of the NMOS transistor Mn10, respectively; the drain of the PMOS transistor Mp10 is connected to the drain of the NMOS transistor Mn10 and the clamping transistor, respectively, and transmits a drive voltage V to the clamping transistor. G0 The source and substrate of the NMOS transistor Mn10 are both externally grounded; the clamping transistor is an NMOS transistor Mn11; the gate of the NMOS transistor Mn11 is connected to the drain of the NMOS transistor Mn10; the source and substrate of the NMOS transistor Mn11 are externally grounded at a level of VSS; the drain of the NMOS transistor Mn11 is connected to an external power supply VDD.

[0059] like Figure 4 As shown, during the simulation, the rise time of the power supply voltage VDD from 0V to 4V was set to 10ns, and the detection signal V in the circuit of this invention was also tested. RC (This invention V) RC ), driving voltage V G (This invention V) G The node voltage V between PMOS transistors Mp0 and Mp1 A (This invention V) A ), and the common gate voltage V of PMOS transistors Mp1 and Mp2 in the PMOS current mirror resistor branch. B (This invention V) B Simulation observation was conducted: Under an electrostatic discharge event, the PMOS transistor Mp0 was fully turned on, causing the present invention V... A Approximately to the power supply voltage VDD, the present invention V B Maintain a voltage of approximately 2.8V to ensure both components can be fully activated. This invention V RC In the first 1-2 ns after power-on at power supply voltage VDD, it can follow the changes in power supply voltage VDD. (This is from the invention V...) RC After rising to 1.2V, the power supply voltage VDD powers on quickly. This invention's V... RCIt cannot follow the change of the power supply voltage VDD, and a voltage difference appears between the two. The voltage difference changes from 2.8V to 0.4V. During this change, the duration of the voltage difference being greater than the threshold voltage of the PMOS transistor Mp4 is approximately 600ns. The gate voltage V of the NMOS transistor Mn3 is also greater. G During this period, the voltage changed from 3.6V to below 0.4V, ensuring that the NMOS transistor Mn3 had enough time to discharge electrostatic discharge energy.

[0060] like Figure 5 As shown, under simulation conditions where the rise time of the power supply voltage VDD from 0V to 4V is 10ns, the conventional electrostatic discharge circuit can continuously discharge an electrostatic discharge current of about 1.8A, that is, the conventional i_clamp is about 1.8A. Under the same conditions, the circuit of the present invention can continuously discharge an electrostatic discharge current of about 1.6A, that is, the i_clamp of the present invention is about 1.6A.

[0061] In another practical embodiment of the present invention, the circuit of the present invention was simulated under the condition that the integrated circuit is normally powered on, and compared and verified with the traditional RC-triggered clamping circuit under the same conditions.

[0062] like Figure 6 and Figure 7 As shown, during the simulation, the rise time of the power supply voltage VDD from 0V to 1.8V was set to 10ns, and the detection signal V in the circuit of this invention was also measured. RC (This invention V) RC The node voltage V between PMOS transistors Mp0 and Mp1 A (This invention V) A The common gate voltage V of PMOS transistors Mp1 and Mp2 in the PMOS current mirror resistor branch. B (This invention V) B The electrostatic discharge current of the circuit of this invention (i_clamp of this invention), and the detection signal V of the conventional RC-triggered clamping circuit. RC0 (Traditional V) RC0 Simulation observation of the electrostatic discharge current (traditional i_clamp) in the conventional discharge circuit during the entire power-on process: The present invention V... RC Compared to traditional V RC0 To more closely follow changes in the power supply voltage VDD, the present invention V RC The voltage difference between the transistor and the power supply voltage is always less than the turn-on threshold voltage of the PMOS transistor Mp0, thus controlling the transistor to be in the off state. This invention V A The present invention varies with the voltage around 0.4V. BWith voltage fluctuations around 0V, PMOS transistor Mp1 is in subthreshold conduction, and PMOS transistor Mp2 is turned on. In the inverter, PMOS transistor Mp4 is turned off, and NMOS transistor Mn2 is turned on. This invention's V... G Pulled down to 0V, and in the present invention V G When pulled down to 0V, the NMOS transistor Mn3 is not turned on, so the maximum value of i_clamp in this invention is about 250nA, and it stabilizes at about 70nA.

[0063] In another practical embodiment of the present invention, the circuit of the present invention was simulated under the condition of rapid power-up of integrated circuit, and compared and verified with the traditional RC-triggered clamping circuit under the same conditions.

[0064] like Figure 8 As shown, during the simulation, the rise time of the power supply voltage VDD from 0V to 1.8V was set to 100ns, and the detection signal V in the circuit of this invention was also measured. RC (This invention V) RC The node voltage V between PMOS transistors Mp0 and Mp1 A (This invention V) A The common gate voltage V of PMOS transistors Mp1 and Mp2 in the PMOS current mirror resistor branch. B (This invention V) B ), and the detection signal V of the traditional RC-triggered clamping circuit. RC0 (Traditional V) RC0 Simulation observations were conducted: Compared to normal power-on, rapid power-on has a very short power-up time, which is easily confused with electrostatic discharge events. In this invention, due to the control of the PMOS transistor Mp0 under rapid power-up conditions, V... A The voltage stabilizes at around 0.4V. (This invention's V...) B Stable at around 0V, the subthreshold conduction of PMOS transistor Mp1 and the on-resistance of PMOS transistor Mp2 are very small, and the overall equivalent RC time constant is also small. Within a range of several nanoseconds, it can effectively handle rapid power-up events. This invention V RC The voltage difference between the two voltages closely follows the changes in the power supply VDD, remaining below 0.4V, which is less than the transistor's turn-on threshold voltage, thus the NMOS transistor Mn3 remains off. In contrast, the traditional RC-triggered clamping circuit... RC0 Under these simulation conditions, the voltage difference between the two transistors does not closely follow VDD. Within 1µs after power-on from 0V, the voltage difference remains greater than 0.4V, which is greater than the transistor's turn-on threshold voltage. Consequently, the PMOS transistor Mp10 turns on, pulling up the gate voltage V of the NMOS transistor Mn11. G0If this happens, the NMOS transistor Mn11 will be falsely triggered. In contrast, this invention can better handle fast power-up events of 100ns, and has better fast power-up event handling capability and good anti-false triggering characteristics.

[0065] like Figure 9 As shown, because the circuit of this invention has almost the same ESD protection capability as the traditional RC-triggered clamping circuit, except for the different RC network structure, the inverter circuit and clamping transistor are the same size. However, according to Figure 4 The ability of the clamping transistor to discharge electrostatic discharge current is evident. Although traditional solutions use resistors and capacitors with the highest resistance and capacitance per unit area in the manufacturing process, they still occupy more than half of the layout area, resulting in significant area waste. The solution proposed in this invention, through an optimized RC structure, significantly reduces the layout area. The clamping circuit size of this invention (53µm × 27µm) achieves approximately 60% area optimization compared to the traditional clamping circuit size (100µm × 39µm).

[0066] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An electrostatic discharge clamping circuit for preventing accidental triggering, characterized in that, This includes control transistors, PMOS current mirror resistor branches, NMOS current mirror capacitor branches, inverters, and clamping transistors; The control transistor is connected to the PMOS current mirror resistor branch, the NMOS current mirror capacitor branch, and the inverter, and is externally connected to the power supply voltage VDD; the PMOS current mirror resistor branch is connected to the NMOS current mirror capacitor branch and the inverter, and is externally connected to the power supply voltage VDD and the ground level VSS, respectively; the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch form an RC structure; the NMOS current mirror capacitor branch is connected to the inverter and is externally connected to the ground level VSS; the inverter is connected to the clamping transistor and is externally connected to the power supply voltage VDD and the ground level VSS, respectively; the clamping transistor is externally connected to the power supply voltage VDD and the ground level VSS, respectively. The control transistor is a feedback-controlled PMOS transistor Mp0, which serves as the switching transistor for the PMOS current mirror resistor branch and also as a voltage divider transistor for normal power-on and fast power-on. The source and substrate of the PMOS transistor Mp0 are both externally connected to a power supply voltage VDD; the gate of the PMOS transistor Mp0 is connected to both the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch to receive the detection signal V from the RC structure. RC This forms a feedback structure; the drain of the PMOS transistor Mp0 is connected to the PMOS current mirror resistor branch. The PMOS current mirror resistor branch includes PMOS transistor Mp1, PMOS transistor Mp2 and resistor R; The substrate of PMOS transistor Mp1 is connected to an external power supply voltage VDD; the source of PMOS transistor Mp1 is connected to the drain of PMOS transistor Mp0; the gate of PMOS transistor Mp1 is connected to the drain, one end of resistor R, and the gate of PMOS transistor Mp2; the other end of resistor R is grounded to a voltage level VSS; the source and substrate of PMOS transistor Mp2 are both connected to an external power supply voltage VDD; the drain of PMOS transistor Mp2 is connected to the NMOS current mirror capacitor branch to generate the detection signal V of the RC structure. RC ; The NMOS current mirror capacitor branch includes a PMOS transistor Mp3, an NMOS transistor Mn0, and an NMOS transistor Mn1 connected in a capacitor configuration. The source of the PMOS transistor Mp3 is connected to its drain, the substrate, the drain of the PMOS transistor Mp2, the gate of the PMOS transistor Mp0, the drain of the NMOS transistor Mn1, and an inverter, respectively, to generate the detection signal V of the RC structure. RC The gate of the PMOS transistor Mp3 is connected to the gate of the NMOS transistor Mn1, the drain and the gate of the NMOS transistor Mn0, respectively; the source and substrate of the NMOS transistor Mn0 are both externally grounded at a voltage level VSS; the source and substrate of the NMOS transistor Mn1 are both externally grounded at a voltage level VSS.

2. The electrostatic discharge clamping circuit for preventing accidental triggering according to claim 1, characterized in that, The inverter includes a PMOS transistor Mp4 and an NMOS transistor Mn2; The gate of the PMOS transistor Mp4 is connected to the gate of the NMOS transistor Mn2 and the drain of the NMOS transistor Mn1, respectively; the source of the PMOS transistor Mp4 and the substrate are connected to an external power supply voltage VDD; the source of the NMOS transistor Mn2 and the substrate are connected to an external ground level VSS; the drain of the PMOS transistor Mp4 is connected to the drain of the NMOS transistor Mn2 and a clamping transistor, respectively, to generate a driving voltage V. G And input clamping transistor.

3. The electrostatic discharge clamping circuit for preventing accidental triggering according to claim 2, characterized in that, The clamping transistor is an NMOS transistor Mn3; The gate of the NMOS transistor Mn3 is connected to the drain of the PMOS transistor Mp4 and the drain of the NMOS transistor Mn2, respectively, to receive the drive voltage V. G The drain of the NMOS transistor Mn3 is connected to an external power supply voltage VDD; the source and substrate of the NMOS transistor Mn3 are both grounded to an external ground level VSS.

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