A data acquisition and processing method for a multi-core single-chip power distribution intelligent terminal

Abstract

The present invention discloses a data acquisition and processing method for a multi-core single-chip power distribution intelligent terminal, which relates to the field of data acquisition and processing technology. The present invention significantly optimizes the real-time response and data processing capabilities of the multi-core power distribution terminal through dynamic priority scheduling and intelligent memory management; the dynamic priority model integrates task type, core load and time attenuation factor to achieve intelligent queue-jumping processing of emergency interruptions, effectively alleviating the timing conflict between periodic sampling and sudden interruptions; the shared memory sharding design isolates real-time data streams and historical caches, combines independent access channels with a conflict arbitration mechanism, and reduces the risk of inter-core communication blockage; the adaptive sampling frequency tracks power grid fluctuations, and combines an improved compression algorithm to take into account both high-frequency signal acquisition efficiency and storage resource optimization.

Description

Technical Field

[0001] The present invention relates to the technical field of data acquisition and processing, and in particular to a data acquisition and processing method for a multi-core single-chip power distribution intelligent terminal. Background Art

[0002] In the power distribution system, multi-core single-chip terminals undertake the core tasks of data acquisition, fault diagnosis and real-time control. Typical application scenarios include the need to simultaneously process periodic sampling data and non-periodic emergency events, such as collecting voltage and current waveforms and handling circuit breaker tripping, grounding and other faults. Traditional architectures mostly adopt a division of labor mode between data processing cores and microprocessor cores: the former is responsible for high-frequency analog quantity acquisition, and the latter performs protocol parsing and logic control.

[0003] Existing systems mostly use static priority scheduling or polling mechanisms to deal with timing conflicts. For periodic sampling tasks, most of them trigger ADC conversion with a fixed time window and store the data in shared memory. Non-periodic interrupts rely on hardware trigger signals to preempt processing resources. This mode can still be maintained in low-load scenarios, but it is less effective in complex working conditions such as feeder automation and frequent transient faults. The interrupt response delay increases nonlinearly with the increase of system load, and critical fault signals will miss the optimal processing time due to queuing. In addition, the continuity of periodic sampling tasks can be easily destroyed by high-frequency interrupts, resulting in waveform data loss or phase distortion.

[0004] To alleviate the above problems, some solutions introduce a hybrid priority mechanism in the task scheduling layer to perform hierarchical management of non-periodic interrupts; use double buffering technology in the data storage layer to isolate the data flow of periodic sampling and interrupt processing; optimize the granularity of mutex locks in the inter-core communication layer to reduce resource sharing conflicts. However, these methods are essentially local optimizations under static rules. Faced with dynamically changing load characteristics and event distribution, traditional solutions lack the ability to quantitatively evaluate task urgency and cannot achieve flexible allocation of processing resources. Summary of the Invention

[0005] In view of the above existing problems, the present invention is proposed.

[0006] The present invention provides a data acquisition and processing method for a multi-core single-chip power distribution intelligent terminal to solve the problem that traditional multi-core terminals use static priority scheduling and fixed timing windows, which have inherent problems such as interrupt response delay, data aliasing and memory access conflicts, and are difficult to meet the real-time requirements under dynamic loads.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] The embodiment of the present invention provides a data collection and processing method for a multi-core single-chip power distribution intelligent terminal, which includes:

[0009] Step S1: Configure a periodic sampling task in the data processing core, set a sampling time window synchronized with the grid fundamental frequency, and trigger analog-to-digital conversion through a hardware timer;

[0010] Step S2: deploying a non-periodic interrupt monitoring module in the microprocessor core to capture circuit breaker trip signals, ground fault signals and communication protocol interrupt requests in real time;

[0011] Step S3: Based on the dynamic priority calculation model, the priorities of the periodic sampling tasks and the non-periodic interrupt tasks are quantified. The model dynamically adjusts the weights according to the task type, the current core load rate, and the data timeliness attenuation factor.

[0012] Step S4, dividing the storage area into a real-time data area, a history buffer area, and an interrupt event queue through a shared memory shard management unit, with each area using an independent memory access channel;

[0013] Step S5, after the data processing core completes the sample data preprocessing, the data packet is written into the corresponding memory area according to the priority weight, and the inter-core communication flag is triggered at the same time;

[0014] Step S6: After the microprocessor core responds to the communication flag, it processes the memory data in descending order of timeliness weight and outputs the processing result to the communication interface;

[0015] The triggering conditions of the inter-core communication flag in step S6 include:

[0016] The real-time data area write volume reaches 80% of its capacity;

[0017] There are tasks in the interrupt event queue whose waiting time exceeds the set threshold;

[0018] The current load rate of the microprocessor core is less than 30%.

[0019] As a preferred solution of the data acquisition and processing method of the multi-core single-chip power distribution intelligent terminal described in the present invention, the configuration of the periodic sampling task in step S1 includes:

[0020] The sampling frequency is set to 2N times the integer multiple of the fundamental frequency, where N is a natural number greater than or equal to 10;

[0021] The sampling time window length is adaptively adjusted according to the grid frequency fluctuation range, with an adjustment step of 1ms.

[0022] As a preferred solution of the data acquisition and processing method of the multi-core single-chip power distribution intelligent terminal described in the present invention, wherein: in step S1, a periodic sampling task is configured in the data processing core, a sampling time window synchronized with the grid fundamental frequency is set, and analog-to-digital conversion is triggered by a hardware timer;

[0023] In step S1, the sampling frequency is defined as ,in, represents the sampling frequency, Indicates the sampling index, the value range is a natural number greater than or equal to 10, Indicates the fundamental frequency of the power grid, Indicates integer multiple sampling coefficient;

[0024] For the highest signal bandwidth ,satisfy ,in, Indicates the maximum bandwidth of the signal;

[0025] When the fundamental frequency deviates When dynamic sampling interval is introduced :

[0026] ,

[0027] in, represents the dynamic sampling interval, Indicates fundamental frequency deviation;

[0028] The baseline sampling interval and its correction amount are defined as:

[0029] , ,

[0030] in, represents the baseline sampling interval, Indicates the sampling interval correction amount.

[0031] As a preferred solution of the data acquisition and processing method of the multi-core single-chip power distribution intelligent terminal described in the present invention, the construction method of the dynamic priority calculation model in step S3 includes:

[0032] A basic weight coefficient K1 is assigned to the periodic sampling task, and its value is positively correlated with the number of sampling channels;

[0033] An emergency weight coefficient K2 is assigned to non-periodic interruption tasks, and its value matches the grid security level associated with the interruption type;

[0034] A time decay factor is introduced, whose value decays exponentially with the task waiting time.

[0035] As a preferred solution of the data acquisition and processing method of the multi-core single-chip power distribution intelligent terminal described in the present invention, in which: in step S3, the step of dynamically adjusting the weight according to the task type, the current core load rate and the data timeliness attenuation factor is:

[0036] For the task Calculate the dynamic priority. In each scheduling cycle, the priority is updated as follows:

[0037] ,in, Indicates a task Dynamic priority, Indicates a task The basic weight coefficient of Represents the current core load regulation function, Indicates a task The time decay factor of

[0038] Then define each sub-item separately, including:

[0039] The core load regulation function is defined as:

[0040] ,

[0041] in, Indicates the current core load rate, the value range is , Represents the load influence coefficient, which is used to control the load weight attenuation rate.

[0042] As a preferred solution of the data acquisition and processing method of the multi-core single-chip power distribution intelligent terminal described in the present invention, in step S3, each sub-item further includes:

[0043] Time decay factor, comprehensive task waiting time The decay effect on priority is defined as:

[0044] ,in, Indicates a task The time decay factor, Indicates a task The decay rate, Indicates a task The cumulative waiting time;

[0045] Make the task urgent Discretize into four levels, 1-4, and map to the minimum and maximum decay rates on the linear interval:

[0046] ,

[0047] in, Indicates a task The decay rate, Indicates the minimum decay rate corresponding to the lowest urgency, Indicates the highest decay rate corresponding to the highest urgency, Indicates a task The urgency level is 1-4;

[0048] The update and calculation of the above functions and factors are performed once in each scheduling cycle, and the update cycle is set to ,in, Indicates the period of dynamic priority calculation and decay update.

[0049] As a preferred solution of the data acquisition and processing method of the multi-core single-chip power distribution intelligent terminal described in the present invention, the operation of the shared memory shard management unit in step S4 includes:

[0050] The real-time data area stores the original sampling data within the last two cycles, using a cyclic overwriting writing strategy;

[0051] The historical buffer stores compressed feature data in a paged storage structure, with each page of data appended with a timestamp.

[0052] The interrupt event queue uses a double buffer structure, allowing high-priority tasks to write directly into the active buffer.

[0053] As a preferred solution of the data acquisition and processing method of the multi-core single-chip power distribution intelligent terminal described in the present invention, the shared memory shard management unit further includes:

[0054] Memory access conflict arbitration mechanism, which comprehensively sorts simultaneous read and write requests based on task priority and timeliness;

[0055] Data integrity check module, which adds a 2-byte CRC check code after each memory write operation;

[0056] Access timestamp recording function, attaching a write time stamp accurate to microseconds to each memory block.

[0057] As a preferred solution of the data acquisition and processing method of the multi-core single-chip power distribution intelligent terminal described in the present invention, the data preprocessing in step S5 includes:

[0058] Implement sliding window feature extraction on the sampled data, with the window length equal to the grid fundamental wave period;

[0059] Improved run-length encoding is used to compress feature data losslessly, and the compression block size is fixed at 64 bytes.

[0060] As a preferred solution of the data acquisition and processing method of the multi-core single-chip power distribution intelligent terminal of the present invention, in step S5, the step of using improved run-length encoding to losslessly compress the feature data is:

[0061] Adopting a two-stage lossless compression process of differential encoding and run-length encoding;

[0062] For length Characteristic sequence of Take first-order differences:

[0063] ,in, Indicates the Item difference value, Indicates the Item eigenvalue, As the initial reference value, take or 0;

[0064] For the difference sequence Perform run-length encoding to obtain a sequence of encoding pairs:

[0065] ,

[0066] in, Indicates the The difference value of the run, Indicates the length of the run, the length is the same continuously The number of represents the total number of run pairs;

[0067] Pack run-length pairs into fixed-size blocks byte: ;

[0068] The number of bits occupied by each pair of codes is: ,

[0069] in, For all The maximum value of plus 1, The maximum allowed run length plus 1, is the difference value field width, The width of the run length field;

[0070] The maximum number of encoding pairs per block is:

[0071] ,

[0072] when When the number of blocks is insufficient, it is stored in sequence in multiple blocks. If the number of blocks is insufficient, it is filled with zero value pairs until the block is full.

[0073] The beneficial effects of the present invention are as follows: the present invention significantly optimizes the real-time response and data processing capabilities of multi-core power distribution terminals through dynamic priority scheduling and intelligent memory management; the dynamic priority model integrates task type, core load and time attenuation factor to achieve intelligent queue-jumping processing of emergency interruptions, effectively alleviating the timing conflict between periodic sampling and sudden interruptions; the shared memory sharding design isolates real-time data streams and historical caches, combines independent access channels with conflict arbitration mechanisms, and reduces the risk of inter-core communication blockage; the adaptive sampling frequency tracks power grid fluctuations, combined with an improved compression algorithm, taking into account both high-frequency signal acquisition efficiency and storage resource optimization.

[0074] While maintaining hardware compatibility, it systematically solves the response delay, data loss and memory contention problems caused by rigid scheduling in traditional methods, providing highly reliable algorithm-level support for distribution automation under complex working conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0076] Figure 1 This is a flow chart of the data collection and processing method of the multi-core single-chip power distribution intelligent terminal in Example 1. DETAILED DESCRIPTION

[0077] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0078] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0079] Secondly, the term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive of other embodiments.

[0080] Example 1, reference Figure 1 This embodiment provides a data collection and processing method for a multi-core single-chip power distribution intelligent terminal, including:

[0081] Step S1: Configure a periodic sampling task in the data processing core, set a sampling time window synchronized with the grid fundamental frequency, and trigger analog-to-digital conversion through a hardware timer;

[0082] The configuration of the periodic sampling task in step S1 includes:

[0083] The sampling frequency is set to 2N times the integer multiple of the fundamental frequency, where N is a natural number greater than or equal to 10;

[0084] The sampling time window length is adaptively adjusted according to the grid frequency fluctuation range, with an adjustment step of 1ms;

[0085] In step S1, a periodic sampling task is configured in the data processing core, a sampling time window synchronized with the grid fundamental frequency is set, and analog-to-digital conversion is triggered by a hardware timer;

[0086] In step S1, the sampling frequency is defined as ,in, represents the sampling frequency, Indicates the sampling index, the value range is a natural number greater than or equal to 10, Indicates the fundamental frequency of the power grid, Indicates integer multiple sampling coefficient;

[0087] For the highest signal bandwidth ,satisfy ,in, Indicates the maximum bandwidth of the signal;

[0088] When the fundamental frequency deviates When dynamic sampling interval is introduced :

[0089] ,

[0090] in, represents the dynamic sampling interval, Indicates fundamental frequency deviation;

[0091] The baseline sampling interval and its correction amount are defined as:

[0092] , ,

[0093] in, represents the baseline sampling interval, Indicates the sampling interval correction amount;

[0094] Specifically, by setting the sampling frequency to Combined with the highest signal bandwidth Under the premise of satisfying the Nyquist sampling theorem, the sampling index N can be flexibly selected, thereby taking into account the time domain resolution and system resource consumption, and the dynamic sampling interval The design allows real-time frequency deviation Accurate compensation keeps the sampling window synchronized with the grid fundamental wave, reduces the impact of aliasing and time base drift, and the reference interval and correction amount The introduction of ,achieves rapid response to frequency mutations, improving the robustness and sampling accuracy of data processing core to power grid changes;

[0095] Step S2: deploying a non-periodic interrupt monitoring module in the microprocessor core to capture circuit breaker trip signals, ground fault signals and communication protocol interrupt requests in real time;

[0096] Step S3: Based on the dynamic priority calculation model, the priorities of the periodic sampling tasks and the non-periodic interrupt tasks are quantified. The model dynamically adjusts the weights according to the task type, the current core load rate, and the data timeliness attenuation factor.

[0097] The construction method of the dynamic priority calculation model in step S3 includes:

[0098] A basic weight coefficient K1 is assigned to the periodic sampling task, and its value is positively correlated with the number of sampling channels;

[0099] An emergency weight coefficient K2 is assigned to non-periodic interruption tasks, and its value matches the grid security level associated with the interruption type;

[0100] Introduce a time decay factor, whose value decays exponentially with the task waiting time;

[0101] In step S3, the steps for dynamically adjusting the weights based on the task type, current core load rate, and data timeliness attenuation factor are as follows:

[0102] For the task Calculate the dynamic priority. In each scheduling cycle, the priority is updated as follows:

[0103] ,in, Indicates a task Dynamic priority, Indicates a task The basic weight coefficient of Represents the current core load regulation function, Indicates a task The time decay factor of

[0104] Then define each sub-item separately, including:

[0105] The core load regulation function is defined as:

[0106] ,

[0107] in, Indicates the current core load rate, the value range is , Represents the load influence coefficient, which is used to control the load weight attenuation rate;

[0108] In step S3, each sub-item also includes:

[0109] Time decay factor, comprehensive task waiting time The decay effect on priority is defined as:

[0110] ,in, Indicates a task The time decay factor, Indicates a task The decay rate, Indicates a task The cumulative waiting time;

[0111] Make the task urgent Discretize into four levels, 1-4, and map to the minimum and maximum decay rates on the linear interval:

[0112] ,

[0113] in, Indicates a task The decay rate, Indicates the minimum decay rate corresponding to the lowest urgency, Indicates the highest decay rate corresponding to the highest urgency, Indicates a task The urgency level can be 1-4;

[0114] The update and calculation of the above functions and factors are performed once in each scheduling cycle, and the update cycle is set to ,in, Indicates the cycle of dynamic priority calculation and attenuation update;

[0115] Specifically, through the above model, the basic weight of the task, the current core load and the time decay are closely combined to achieve dynamic priority adjustment of different types of tasks, and the core load adjustment function The weight of new tasks can be automatically lowered according to the busyness of the processing unit to avoid overload and time attenuation factor Reflects the task waiting time in exponential form. The more urgent the task, the faster it decays. The larger the value, the faster the priority can be restored, thus quickly responding to security-related interruptions, while low-urgency tasks are naturally postponed. The method of linearly mapping urgency and decay rate takes into account both simple implementation and controllable parameter adjustment.

[0116] Step S4, dividing the storage area into a real-time data area, a history buffer area, and an interrupt event queue through a shared memory shard management unit, with each area using an independent memory access channel;

[0117] The operations of the shared memory shard management unit in step S4 include:

[0118] The real-time data area stores the original sampling data within the last two cycles, using a cyclic overwriting writing strategy;

[0119] The historical buffer stores compressed feature data in a paged storage structure, with each page of data appended with a timestamp.

[0120] The interrupt event queue adopts a double buffer structure, allowing high priority tasks to directly write to the activation buffer;

[0121] The shared memory shard management unit also includes:

[0122] Memory access conflict arbitration mechanism, which comprehensively sorts simultaneous read and write requests based on task priority and timeliness;

[0123] Data integrity check module, which adds a 2-byte CRC check code after each memory write operation;

[0124] Access timestamp recording function, which adds a write time stamp accurate to microseconds to each memory block;

[0125] Step S5, after the data processing core completes the sample data preprocessing, the data packet is written into the corresponding memory area according to the priority weight, and the inter-core communication flag is triggered at the same time;

[0126] The data preprocessing in step S5 includes:

[0127] Implement sliding window feature extraction on the sampled data, with the window length equal to the grid fundamental wave period;

[0128] Improved run-length encoding is used to compress feature data losslessly, and the compression block size is fixed at 64 bytes;

[0129] In step S5, the steps of using improved run-length encoding to losslessly compress the feature data are as follows:

[0130] Adopting a two-stage lossless compression process of differential encoding and run-length encoding;

[0131] For length Characteristic sequence of Take the first-order difference:

[0132] ,in, Indicates the Item difference value, Indicates the Item eigenvalue, As the initial reference value, take or 0;

[0133] For the difference sequence Perform run-length encoding to obtain a sequence of encoding pairs:

[0134] ,

[0135] in, Indicates the The difference value of the run, Indicates the length of the run, the length is the same continuously The number of represents the total number of run pairs;

[0136] Pack run-length pairs into fixed-size blocks byte: ;

[0137] The number of bits occupied by each pair of codes is: ,

[0138] in, For all The maximum value of plus 1, The maximum allowed run length plus 1, is the difference value field width, The run length field bit width;

[0139] The maximum number of encoding pairs per block is:

[0140] ,

[0141] when When the number of blocks is insufficient, it is stored in sequence in multiple blocks. If the number of blocks is insufficient, it is filled with zero value pairs until the block is full.

[0142] Specifically, differential coding is introduced to condense the changes of adjacent eigenvalues into , significantly improves the aggregation of the same value segment, creates a longer constant segment for subsequent run encoding, and thus reduces the total number of run pairs , reduce the encoding header overhead, differential mapping to the unsigned domain and combine the bit width calculation , ensuring the optimal ratio of symbol and length fields, making fixed Maximize the utilization of byte blocks;

[0143] Step S6: After the microprocessor core responds to the communication flag, it processes the memory data in descending order of timeliness weight and outputs the processing result to the communication interface;

[0144] The triggering conditions of the inter-core communication flag in step S6 include:

[0145] The real-time data area write volume reaches 80% of its capacity;

[0146] There are tasks in the interrupt event queue whose waiting time exceeds the set threshold;

[0147] The current load rate of the microprocessor core is less than 30%.

[0148] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A data acquisition and processing method for a multi-core single-chip power distribution intelligent terminal, characterized in that: include, Step S1: Configure a periodic sampling task in the data processing core, set a sampling time window synchronized with the grid fundamental frequency, and trigger analog-to-digital conversion through a hardware timer; Step S2: deploying a non-periodic interrupt monitoring module in the microprocessor core to capture circuit breaker trip signals, ground fault signals and communication protocol interrupt requests in real time; Step S3: Based on the dynamic priority calculation model, the priorities of the periodic sampling tasks and the non-periodic interrupt tasks are quantified. The model dynamically adjusts the weights according to the task type, the current core load rate, and the data timeliness attenuation factor. Step S4, dividing the storage area into a real-time data area, a history buffer area, and an interrupt event queue through a shared memory shard management unit, with each area using an independent memory access channel; Step S5, after the data processing core completes the sample data preprocessing, the data packet is written into the corresponding memory area according to the priority weight, and the inter-core communication flag is triggered at the same time; Step S6: After the microprocessor core responds to the communication flag, it processes the memory data in descending order of timeliness weights and outputs the processing results to the communication interface.

2. The data collection and processing method of a multi-core single-chip power distribution intelligent terminal according to claim 1, characterized in that: The configuration of the periodic sampling task in step S1 includes: The sampling frequency is set to 2N times the integer multiple of the fundamental frequency, where N is a natural number greater than or equal to 10; The length of the sampling time window is adaptively adjusted according to the grid frequency fluctuation range, with an adjustment step of 1ms.

3. The data collection and processing method of a multi-core single-chip power distribution intelligent terminal according to claim 2, characterized in that: In step S1, a periodic sampling task is configured in the data processing core, a sampling time window synchronized with the grid fundamental frequency is set, and analog-to-digital conversion is triggered by a hardware timer; In step S1, the sampling frequency is defined as ,in, represents the sampling frequency, Indicates the sampling index, the value range is a natural number greater than or equal to 10, Indicates the fundamental frequency of the power grid, Indicates integer multiple sampling coefficient; For the highest signal bandwidth ,satisfy ,in, Indicates the maximum bandwidth of the signal; When the fundamental frequency deviates When dynamic sampling interval is introduced : ， in, represents the dynamic sampling interval, Indicates fundamental frequency deviation; The baseline sampling interval and its correction amount are defined as: ， ， in, represents the baseline sampling interval, Indicates the sampling interval correction amount.

4. The data collection and processing method of a multi-core single-chip power distribution intelligent terminal according to claim 1, characterized in that: The construction method of the dynamic priority calculation model in step S3 includes: A basic weight coefficient K1 is assigned to the periodic sampling task, and its value is positively correlated with the number of sampling channels; An emergency weight coefficient K2 is assigned to non-periodic interruption tasks, and its value matches the grid security level associated with the interruption type; A time decay factor is introduced, whose value decays exponentially with the task waiting time.

5. The data collection and processing method of a multi-core single-chip power distribution intelligent terminal according to claim 4, characterized in that: In step S3, the steps of dynamically adjusting the weight according to the task type, the current core load rate and the data timeliness attenuation factor are as follows: For the task Calculate the dynamic priority. In each scheduling cycle, the priority is updated as follows: ,in, Indicates a task Dynamic priority, Indicates a task The basic weight coefficient of Represents the current core load regulation function, Indicates a task The time decay factor of Then define each sub-item separately, including: The core load regulation function is defined as: ， in, Indicates the current core load rate, the value range is , Represents the load influence coefficient, which is used to control the load weight attenuation rate.

6. The data collection and processing method of a multi-core single-chip power distribution intelligent terminal according to claim 5, characterized in that: In step S3, each sub-item also includes: Time decay factor, comprehensive task waiting time The decay effect on priority is defined as: ,in, Indicates a task The time decay factor, Indicates a task The decay rate, Indicates a task The cumulative waiting time; Determine the urgency of the task Discretize into four levels, 1-4, and map to the minimum and maximum decay rates on the linear interval: ， in, Indicates a task The decay rate, Indicates the minimum decay rate corresponding to the lowest urgency, Indicates the highest decay rate corresponding to the highest urgency, Indicates a task The urgency level can be 1-4; The update and calculation of the above functions and factors are performed once in each scheduling cycle, and the update cycle is set to ,in, Indicates the period of dynamic priority calculation and decay update.

7. The data collection and processing method of a multi-core single-chip power distribution intelligent terminal according to claim 1, characterized in that: The operations of the shared memory shard management unit in step S4 include: The real-time data area stores the original sampling data within the last two cycles, using a cyclic overwriting writing strategy; The historical buffer stores compressed feature data in a paged storage structure, with each page of data appended with a timestamp. The interrupt event queue uses a double buffer structure, allowing high-priority tasks to write directly into the active buffer.

8. The data collection and processing method of a multi-core single-chip power distribution intelligent terminal according to claim 7, characterized in that: The shared memory fragment management unit further comprises: Memory access conflict arbitration mechanism, which comprehensively sorts simultaneous read and write requests based on task priority and timeliness; Data integrity check module, which adds a 2-byte CRC check code after each memory write operation; Access timestamp recording function, attaching a write time stamp accurate to microseconds to each memory block.

9. The data collection and processing method of a multi-core single-chip power distribution intelligent terminal according to claim 1, characterized in that: The data preprocessing in step S5 includes: Implement sliding window feature extraction on the sampled data, with the window length equal to the grid fundamental wave period; Improved run-length encoding is used to compress feature data losslessly, and the compression block size is fixed at 64 bytes.

10. The data collection and processing method of a multi-core single-chip power distribution intelligent terminal according to claim 9, characterized in that: In step S5, the step of using improved run-length encoding to losslessly compress the feature data is as follows: Adopting a two-stage lossless compression process of differential encoding and run-length encoding; For length Characteristic sequence of Take the first-order difference: ,in, Indicates the Item difference value, Indicates the Item eigenvalue, As the initial reference value, take or 0; For the difference sequence Perform run-length encoding to obtain a sequence of encoding pairs: ， in, Indicates the The difference value of the run, Indicates the length of the run, the length is the same continuously The number of represents the total number of run pairs; Pack run-length pairs into fixed-size blocks byte: ; The number of bits occupied by each pair of codes is: , in, For all The maximum value of plus 1, The maximum allowed run length plus 1, is the difference value field width, The width of the run length field; The maximum number of encoding pairs per block is: ， when When the number of blocks is insufficient, it is stored in sequence in multiple blocks. If the number of blocks is insufficient, it is filled with zero value pairs until the block is full.

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