Parallel carrier synchronization method, inverter device, system and storage medium

Abstract

The present application relates to the field of new energy technology, and in particular to a parallel carrier synchronization method, inverter device, system and storage medium. The parallel carrier synchronization method includes: sampling the output current of the inverter device at the first moment and the second moment of each preset carrier adjustment period, respectively, to obtain the current value at the first moment and the current value at the second moment; the difference between the current value at the first moment and the current value at the second moment is input as an error value to the proportional integral controller, and the carrier count cycle value is adjusted by the proportional integral controller; and the corresponding carrier signal is output based on the adjusted carrier count cycle value. In the method of the present application, the slave does not need to communicate with the host, which is not only simple in design and low in cost, but also does not rely on hardware accuracy and communication speed, and has high flexibility and reliability.

Description

Technical Field

[0001] The present application relates to the field of new energy technology, and in particular to a parallel carrier synchronization method, inverter equipment, system and storage medium. Background Art

[0002] With the development of society, electricity has become indispensable in our daily life and work, but we often encounter a series of problems such as outdoor electricity use, equipment power outage, and excessive load. Portable energy storage power supplies, due to their flexibility, can be connected in parallel or in series, and have become one of the options to solve these problems.

[0003] When multiple inverters are connected in parallel, if their PWM (Pulse Width Modulation) carriers are out of sync, this can cause severe high-frequency circulating currents within the system, reducing efficiency and harmonic characteristics. To prevent this, carrier synchronization technology is required to suppress it.

[0004] Traditional parallel carrier synchronization technology is implemented via wired connections, with the master transmitting carrier information to the slaves via synchronization signal lines and communication cables for synchronous control. This solution is not only complex and costly, but also, because the clock reference signals for multiple inverters are typically generated independently by multiple crystal oscillators, which inherently have clock errors, it's difficult for the clock frequencies of the individual processors to be identical, and carrier synchronization can still occur. Summary of the Invention

[0005] The embodiments of the present application aim to provide a parallel carrier synchronization method, inverter device, system and storage medium to solve the problems of complex design, high cost and low reliability of parallel carrier synchronization technology in the prior art.

[0006] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a parallel carrier synchronization method, which is applied to an inverter device, and the method includes:

[0008] Sampling the output current of the inverter device at a first moment and a second moment of each preset carrier adjustment period to obtain a current value at the first moment and a current value at the second moment;

[0009] The difference between the current value at the first moment and the current value at the second moment is input as an error value to a proportional-integral controller, and the carrier counting period value is adjusted by the proportional-integral controller;

[0010] A corresponding carrier signal is output based on the adjusted carrier count period value.

[0011] Optionally, the phase difference between the first moment and the second moment is 180 degrees.

[0012] Optionally, the waveform of the carrier signal is a triangular wave, the first moment is the moment when the carrier count value is zero, and the second moment is the moment when the carrier count value is a carrier count period value.

[0013] Optionally, sampling the output current of the inverter device at a first moment and a second moment of each preset carrier adjustment period to obtain the current value at the first moment and the current value at the second moment includes:

[0014] When the carrier count value of each preset carrier adjustment period is zero, a first sampling signal is triggered, and the output current of the inverter device is sampled based on the first sampling signal to obtain the current value at the first moment;

[0015] When the carrier count value of each preset adjusted carrier period is the carrier count period value, a second sampling signal is triggered, and the output current of the inverter device is sampled based on the second sampling signal to obtain the current value at the second moment.

[0016] Optionally, the adjusted carrier cycle is a carrier cycle selected from all carrier cycles included in a power frequency cycle according to a preset period interval.

[0017] Optionally, adjusting the carrier count period value by the proportional-integral controller includes:

[0018] When the error value is positive, increasing the carrier counting period value based on a first adjustment strategy;

[0019] When the error value is negative, the carrier count period value is reduced based on a second adjustment strategy.

[0020] In the second aspect, an embodiment of the present application provides a parallel carrier synchronization method, which is applied to a multi-machine parallel inverter system, wherein the multi-machine parallel inverter system includes a host and at least one slave, and the method includes: controlling each of the at least one slave to execute the method described above.

[0021] In a third aspect, an embodiment of the present application provides an inverter device, which includes at least one processor and a memory communicatively connected to the at least one processor, the memory storing instructions executable by the at least one processor, and the instructions being executed by the at least one processor so that the at least one processor can execute the method described above.

[0022] In a third aspect, an embodiment of the present application provides a multi-machine parallel inverter system, which includes a master machine and at least one slave machine, and controls each of the at least one slave machine to execute the method described above.

[0023] In a fourth aspect, an embodiment of the present application provides a computer storage medium, which stores instructions or programs. When the instructions or programs are executed by at least one processor, the at least one processor executes any one of the methods described above.

[0024] The beneficial effects of the embodiments of the present application are as follows: Different from the prior art, the embodiments of the present application provide a method for synchronizing a parallel-type carrier wave. First, the output current of the inverter device is sampled at the first moment and the second moment of each preset carrier adjustment period to obtain the current value at the first moment and the current value at the second moment. Then, the difference between the current value at the first moment and the current value at the second moment is input as an error value to the proportional-integral controller, and the carrier counting period value is adjusted by the proportional-integral controller. Based on the adjusted carrier counting period value, a corresponding carrier signal is output. In the method of the present application, the slave does not need to communicate with the master. A closed-loop control method is used to control the current difference between the first moment and the second moment of the carrier cycle to zero, thereby suppressing high-frequency circulating current and achieving carrier synchronization. The method is not only simple in design and low in cost, but also independent of hardware accuracy and communication speed, and has high flexibility and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0026] Figure 1 A topological structure diagram of a multi-machine parallel inverter system is shown as an example;

[0027] Figure 2 An example is shown Figure 1 Simplified circuit diagram of parallel output;

[0028] Figure 3 The following example shows the high-frequency voltage difference waveforms corresponding to the carrier phase differences of the two inverter devices when they are 0 degrees, 90 degrees, and 180 degrees respectively;

[0029] Figure 4 The structure diagram of the inverter device is shown as an example;

[0030] Figure 5 A flowchart of a parallel carrier synchronization method is exemplarily shown;

[0031] Figure 6 The schematic diagram of current sampling time is shown as an example;

[0032] Figure 7 The schematic diagram of the execution process of the PI control algorithm is shown as an example. DETAILED DESCRIPTION

[0033] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0034] In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0035] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0036] Please refer to Figure 1 , Figure 1 The topological structure diagram of the multi-machine parallel inverter system is shown in FIG. Figure 1 As shown, the multi-machine parallel inverter system includes an inverter device 10 and an inverter device 20. Specifically, the inverter device 10 and the inverter device 20 are bidirectional PCS (Power Conversion System) power supplies, using an LC topology (L refers to the inductor and C refers to the capacitor). After the inverter device 10 and the inverter device 20 are connected in parallel, the output interface becomes an LCCL structure, and the output voltage of the inverter device is at the end of capacitor C. Since the PWM signal contains the power frequency signal and the carrier signal, the input of the inductor L It includes power frequency voltage and high frequency voltage. Among them, the high frequency voltage is attenuated by the LC low-pass filter, and a weak high frequency voltage still exists at the output of capacitor C. This voltage signal is the high frequency ripple voltage, which is usually in the range of several volts.

[0037] Please refer to Figure 2 , Figure 2 Shown Figure 1 Simplified circuit diagram of parallel output. is the output voltage of the inverter device 10, is the output voltage of the inverter device 20, is the line impedance of the inverter device 10, is the line impedance of the inverter device 20, is the load impedance. In steady state, the load power is evenly distributed, or The load impedance of the loop is twice the impedance, so, and Current at both ends and The calculation formula is:

[0038]

[0039] Due to the current and Same, the following only According to From the calculation formula, we can see that the output current contains the power frequency current component and high-frequency circulation components .because , so the power frequency current component is mainly composed of Determine. Among the high-frequency circulation components, and Contains power frequency voltage signal and high frequency voltage signal respectively. When the power frequency signal is synchronized, The power frequency signals can cancel each other out. The high frequency signal depends on whether the carrier is synchronized. When the carrier is not synchronized, it will inevitably lead to The output voltage is not zero, and The line impedance of the two inverter devices, that is, the resistance value of the transmission cable, is generally only a few tens of milliohms. Therefore, if the high-frequency voltages of the two inverter devices are not synchronized, a large high-frequency circulating current will be generated. Figure 3 As shown in the figure, when the carrier phase difference between the two inverter devices is 0 degrees (i.e., carrier synchronization), the triangle waves are in an overlapping state and the high-frequency voltage difference is zero. When the carrier phase difference between the two inverter devices is 90 degrees or 180 degrees, a high-frequency voltage difference is formed.

[0040] Please refer to Figure 4 , Figure 4 FIG. 4 is a diagram showing a structure of the inverter device 40. Figure 4 As shown, the inverter device 40 includes at least one processor 41 and a memory 42, wherein the memory 42 can be built into the inverter device 40 or externally located outside the inverter device 40. The memory 42 can also be a remotely set memory connected to the inverter device 40 via a network.

[0041] The memory 42 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs, and modules. The memory 42 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal, etc. In addition, the memory 42 may include a high-speed random access memory and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 42 may optionally include a memory remotely located relative to the processor 41, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0042] The processor 41 performs various functions of the terminal and processes data by running or executing software programs and / or modules stored in the memory 42, and calling data stored in the memory 42, thereby monitoring the terminal as a whole, for example, implementing the parallel carrier synchronization method described in any embodiment of the present application.

[0043] The processor 41 may be one or more, Figure 4 In the figure, a processor 41 is used as an example. The processor 41 and the memory 42 may be connected via a bus or other means. The processor 41 may include a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a controller, a field-programmable gate array (FPGA), etc. The processor 41 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0044] Please refer to Figure 5 , Figure 5 A flow chart of a parallel carrier synchronization method is shown, which is applied to an inverter device. The inverter device may include: Figure 1 and Figure 4 The structure shown.

[0045] like Figure 5 As shown, the parallel carrier synchronization method applied to the inverter device includes:

[0046] Step S501 : sampling the output current of the inverter device at the first moment and the second moment of each preset carrier adjustment period to obtain the current value at the first moment and the current value at the second moment.

[0047] In order to better suppress high-frequency circulating current and more efficiently achieve carrier synchronization, the phase difference between the first moment and the second moment is about 180 degrees, preferably 180 degrees.

[0048] In one embodiment, the current sampling at the first moment and the second moment is triggered based on a timer. For example, assuming that the start time of the carrier cycle is t0, the first moment is t0+ , the carrier period is T, if the second time is later than the first time, then the second time t2 can be t0+ +T / 2. Specifically, the timer is started at the start time t0 of the carrier cycle, and when the timing time is When the current sampling at the first moment is triggered, when the timing time is At +T / 2, the current sampling at the second moment is triggered.

[0049] In a more preferred embodiment, current sampling at the first and second moments is triggered based on the carrier count value. For example, if the carrier signal waveform is a triangular wave (where the carrier counter counts from zero to the carrier count period and then decrements from the carrier count period to zero), assuming the carrier count period is Arr and the carrier count value corresponding to the first moment is A1, then if the second moment is later than the first, the carrier count value A2 corresponding to the second moment may be Arr-A1.

[0050] Generally, the chip supports triggering current sampling when the carrier count value is zero and the carrier count cycle value. To simplify the design, the first moment can be set to the moment when the carrier count value is zero, and the second moment can be set to the moment when the carrier count value is the carrier count cycle value. Specifically, when the carrier count value of each preset adjusted carrier cycle is zero, the first sampling signal is triggered, and the output current of the inverter device is sampled based on the first sampling signal to obtain the current value at the first moment. When the carrier count value of each preset adjusted carrier cycle is the carrier count cycle value, the second sampling signal is triggered, and the output current of the inverter device is sampled based on the second sampling signal to obtain the current value at the second moment.

[0051] In one embodiment, the adjusted carrier period is each carrier period included in the power frequency period. In other embodiments, the adjusted carrier period is a carrier period selected from all carrier periods included in a power frequency period according to a preset period interval. Taking a 50Hz sine wave as an example, the power frequency period is 20ms. Assuming that the carrier frequency is 20KHz, the carrier period is 50us, that is, each power frequency period contains 400 carrier periods. In the former embodiment, all 400 carrier periods are adjusted carrier periods; in the latter embodiment, a certain number of carrier periods are uniformly selected from the 400 carrier periods as adjusted carrier periods. For example, if 10 carrier periods are selected as adjusted carrier periods, the adjusted carrier periods are the 40th carrier period, the 80th carrier period, the 120th carrier period, ..., the 400th carrier period.

[0052] Step S502 : The difference between the current value at the first moment and the current value at the second moment is input as an error value into a proportional-integral controller, and the carrier counting period value is adjusted by the proportional-integral controller.

[0053] Below is Figure 6 Taking the current sampling moments shown as an example, the principle of suppressing high-frequency circulating current by controlling the difference between the current value at the first moment and the current value at the second moment to zero is discussed. Figure 6 In the example, the first moment is when the carrier count value is zero, and the second moment is when the carrier count value is the carrier count cycle value. The carrier count value is zero as point a, and the current value at the first moment obtained by sampling the output current is , the carrier count value is recorded as point b when the carrier count cycle value is the carrier count cycle value, and the current value at the second moment obtained by sampling the output current is Based on the above The calculation formula of is known, and The calculation formula is:

[0054]

[0055] Based on the above description, we can see that and It also includes the power frequency current part and the high frequency circulating current part. and By performing a subtraction operation, the power frequency current part can be filtered out and the high-frequency circulating current part can be extracted, specifically:

[0056]

[0057] Simplifying the above formula, we can get:

[0058]

[0059] in, is the peak-to-peak voltage of one carrier cycle, is the peak-to-peak value of the power frequency current, It is the peak-to-peak value of the high-frequency current.

[0060] Typically, this is a few volts. Assuming a peak-to-peak voltage of 5V, at no load, the load impedance is infinite, and the peak-to-peak power frequency current approaches zero. At full load, assuming a 120V / 2400W load condition and a load impedance of 12 ohms, the peak-to-peak power frequency current is 0.5A. In summary, the peak-to-peak power frequency current is between 0 and 0.5A.

[0061] The expression of the high-frequency current peak-to-peak value is: , the numerator is the peak-to-peak voltage error of the two inverter devices, and the denominator is the impedance of the output wire (usually in milliohms). Assuming the wire impedance is 50mΩ, the peak-to-peak value of the high-frequency current is completely determined by the peak-to-peak voltage error of the two inverter devices. If the peak-to-peak voltage error of the two inverter devices is 5V, the peak-to-peak value of the high-frequency current will reach 100A. Figure 3 As shown in the figure, when the carrier phase difference between the two inverter devices is 90 degrees or 180 degrees, a high-frequency peak-to-peak voltage difference (i.e. ), at 180 degrees, the high-frequency peak-to-peak voltage difference reaches its maximum value.

[0062] In summary, the peak-to-peak value of the power frequency current is much smaller than the peak-to-peak value of the high frequency current. The peak-to-peak value of the power frequency current can be ignored. The calculation formula can be simplified as:

[0063]

[0064] in, It represents the difference between the peak current and the valley current in one carrier cycle. By controlling it to zero, the high-frequency circulating current can be suppressed and carrier synchronization can be achieved.

[0065] In one embodiment, adjusting the carrier count cycle value using a proportional-integral controller includes: when the error value is positive, increasing the carrier count cycle value based on a first adjustment strategy; when the error value is negative, decreasing the carrier count cycle value based on a second adjustment strategy; and when the error value is zero, maintaining the carrier count cycle value unchanged. Specifically, the first adjustment strategy and the second adjustment strategy can be set based on the time interval and error value between adjacent adjusted carrier cycles. For example, when the time interval and / or error value between adjacent adjusted carrier cycles is small, the adjustment amplitude value obtained based on the first adjustment strategy and the second adjustment strategy is small; when the time interval and / or error value between adjacent adjusted carrier cycles is large, the adjustment amplitude value obtained based on the first adjustment strategy and the second adjustment strategy is large.

[0066] In other embodiments, adjusting the carrier count period value by a proportional-integral controller includes increasing the carrier count period value by a fixed adjustment amplitude when the error value is positive, and decreasing the carrier count period value by a fixed adjustment amplitude when the error value is negative. Generally, since the time interval between adjacent carrier period adjustments is relatively short, the fixed adjustment amplitude value can be set to 1.

[0067] Please refer to Figure 7 , Figure 7 The execution process of the PI control algorithm is shown in Figure 1. and are the sampling currents at the first and second moments of each preset carrier adjustment period, respectively. - The value is input into the error regulator (i.e., proportional-integral controller) to obtain the initial value of the adjustment amplitude of the carrier calculation period value, the initial value of the adjustment amplitude is limited to output the final value of the adjustment amplitude, and the final value of the adjustment amplitude is added to the carrier count period value to obtain a new carrier count period value.

[0068] Step S503: outputting a corresponding carrier signal based on the adjusted carrier counting period value.

[0069] When the carrier counting cycle value of the inverter device is adjusted, the carrier signal it outputs is also adjusted accordingly. The driving signal obtained based on the adjusted carrier signal is used to drive the transistor of the inverter device, thereby achieving carrier synchronization.

[0070] The embodiment of the present application also provides a parallel carrier synchronization method applied to a multi-machine parallel inverter system, wherein the multi-machine parallel inverter system includes a master and at least one slave, wherein the master and the slave adopt Figure 1 The topology shown is connected in parallel. The parallel carrier synchronization method includes: controlling each of at least one slave to execute the parallel carrier synchronization method applied to an inverter device in any embodiment of the present application.

[0071] from The calculation formula shows that the high-frequency circulation component is , theoretically, it is also possible to control The high-frequency circulating current is suppressed by setting the carrier period to zero. However, due to the very short carrier period, for example, the 20KHz PWM period is 50us. Within 50us, both voltage acquisition and communication between two inverter devices must be achieved. This places high demands on the sensitivity of the devices and the real-time performance of communication, making it difficult to implement. In contrast, the method of the present application does not require the slave to communicate with the master. Instead, a closed-loop control method is used to control the current difference between the first and second moments of the carrier period to zero, thereby suppressing the high-frequency circulating current and achieving carrier synchronization. This method is not only simple in design and low in cost, but also independent of hardware accuracy and communication speed, and has high flexibility and reliability.

[0072] An embodiment of the present application further provides a computer storage medium storing instructions or programs, which are executed by one or more processors, enabling the one or more processors to execute the parallel carrier synchronization method in any of the above method embodiments.

[0073] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the relevant technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or certain portions of the embodiments.

[0074] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of variations or substitutions within the technical scope disclosed in the present application. Therefore, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for synchronizing a parallel carrier wave, characterized in that: Applied to an inverter device, the method includes: Sampling the output current of the inverter device at a first moment and a second moment of each preset carrier adjustment period, respectively, to obtain a current value at the first moment and a current value at the second moment, wherein a phase difference between the first moment and the second moment is 180 degrees; The difference between the current value at the first moment and the current value at the second moment is input as an error value to a proportional-integral controller, and the carrier counting period value is adjusted by the proportional-integral controller; Outputting a corresponding carrier signal based on the adjusted carrier count period value; The adjusting the carrier count period value by the proportional integral controller includes: When the error value is positive, increasing the carrier count period value based on a first adjustment strategy; When the error value is negative, reducing the carrier count period value based on a second adjustment strategy; When the error value is zero, the carrier counting period value is kept unchanged.

2. The method according to claim 1, characterized in that The waveform of the carrier signal is a triangular wave, the first moment is the moment when the carrier count value is zero, and the second moment is the moment when the carrier count value is the carrier count period value.

3. The method according to claim 2, characterized in that The sampling of the output current of the inverter device at the first moment and the second moment of each preset carrier adjustment period to obtain the current value at the first moment and the current value at the second moment includes: When the carrier count value of each preset carrier adjustment period is zero, a first sampling signal is triggered, and the output current of the inverter device is sampled based on the first sampling signal to obtain the current value at the first moment; When the carrier count value of each preset adjusted carrier period is the carrier count period value, a second sampling signal is triggered, and the output current of the inverter device is sampled based on the second sampling signal to obtain the current value at the second moment.

4. The method according to claim 1, wherein The adjusted carrier cycle is a carrier cycle selected from all carrier cycles included in a power frequency cycle according to a preset cycle interval.

5. A method for synchronizing parallel carrier waves, characterized in that: Applied to a multi-machine parallel inverter system, the multi-machine parallel inverter system includes a master machine and at least one slave machine, the method includes: Each of the at least one slave is controlled to execute the method according to any one of claims 1 to 4.

6. An inverter device, characterized in that: The inverter device includes at least one processor and a memory communicatively connected to the at least one processor, the memory storing instructions executable by the at least one processor, and the instructions being executed by the at least one processor so as to enable the at least one processor to perform the method according to any one of claims 1 to 5.

7. A multi-machine parallel inverter system, characterized in that: The multi-machine parallel inverter system includes a master machine and at least one slave machine, and controls each of the at least one slave machine to execute the method according to any one of claims 1 to 4.

8. A computer storage medium, characterized in that The computer storage medium stores instructions or programs, and when the instructions or programs are executed by at least one processor, the at least one processor is caused to perform the method according to any one of claims 1 to 5.

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