On-time control circuit, control circuit and DC-DC conversion circuit

Abstract

The invention provides a turn-on time control circuit, a control circuit and a DC-DC conversion circuit, which introduces a difference value between an input voltage and a voltage of an output node of a power switch circuit into the turn-on time control circuit on the basis of a traditional COT mode without increasing the area of the power switch circuit (namely a power switch tube). Therefore, the turn-on time control circuit automatically adjusts the turn-on time of the power switch circuit in each switching period according to the input voltage, the output voltage and the change of the difference value, so that the turn-on time of the power switch circuit and the duty ratio D influenced by the internal resistance of the power switch tube in the power switch circuit are synchronously increased. Therefore, the circuit frequency is kept relatively stable.

Description

Technical Field

[0001] The present invention relates to the technical field of power conversion, and particularly relates to a conduction time control circuit, a control circuit and a DC-DC conversion circuit. Background Art

[0002] As a high-efficiency switching power converter, a DC-DC (direct current to direct current) converter has the advantages of fast dynamic response, simple control, and direct control of output current, and is widely used in the power management systems of various products. Among them, the constant on-time (COT) mode is one of the commonly used control modes for DC-DC conversion circuits. By setting a fixed conduction time for the corresponding power switch tube in the power stage circuit, the output voltage of the DC-DC conversion circuit is adjusted.

[0003] In a traditional DC-DC conversion circuit controlled by the COT mode, the voltage consumed by the internal resistance of the power switch tube increases with the increase of the load current, which will cause the relative calculated value of the duty cycle of the power switch tube to be too large. Since the conduction time Ton of the power switch tube in the COT mode remains constant for the same set of input and output voltages, but the deviation of the duty cycle increases with the increase of the load, which will further bring a frequency deviation. Summary of the Invention

[0004] The purpose of the present invention is to provide a conduction time control circuit, a control circuit and a DC-DC conversion circuit, which can reduce the influence of the internal resistance of the power switch tube on the circuit frequency without increasing the area of the power switch tube.

[0005] To achieve the above purpose, the present invention provides a conduction time control circuit for controlling the on and off of a power switch circuit in a DC-DC conversion circuit, so that the DC-DC conversion circuit converts a corresponding input voltage into an output voltage. The conduction time control circuit is coupled to the output node of the power switch circuit and is used to control the conduction time of the power switch circuit in a corresponding switching period to be adjustable according to the input voltage, the output voltage, and the difference between the input voltage and the voltage of the output node, so as to maintain the relative stability of the frequency of the DC-DC conversion circuit.

[0006] Optionally, the conduction time of the power switch circuit increases synchronously with the duty cycle of the power switch circuit.

[0007] Optionally, the conduction time control circuit includes:

[0008] A first current conversion circuit for converting the input voltage into an input current;

[0009] A second current conversion circuit for converting the difference between the input voltage and the voltage of the output node into a first difference current;

[0010] A current superposition circuit coupled to the first current conversion circuit, the second current conversion circuit and the output node, and configured to subtract the input current from the first difference current under the control of the voltage of the output node to generate a second difference current;

[0011] A voltage conversion circuit coupled to the current superposition circuit and configured to convert the second difference current into a corresponding voltage;

[0012] A first comparator having a first input terminal coupled to the voltage conversion circuit and a second input terminal coupled to the output voltage, and configured to compare the magnitudes of the output voltage and the voltage converted by the voltage conversion circuit to generate and output a corresponding conduction time control signal for controlling the conduction time.

[0013] Optionally, the first current conversion circuit includes a first transconductance amplifier, a first switching switch, and a first resistor. The source of the first switching switch is coupled to one end of the first resistor and the second input terminal of the first transconductance amplifier. The other end of the first resistor is grounded. The first input terminal of the first transconductance amplifier receives the input voltage. The output terminal of the first transconductance amplifier is coupled to the gate of the first switching switch. The drain of the first switching switch is coupled to the current superposition circuit.

[0014] Optionally, the second current conversion circuit includes a second transconductance amplifier and a second switching switch. The source of the second switching switch is grounded. The first input terminal of the second transconductance amplifier is coupled to the input voltage. The second input terminal of the second transconductance amplifier is coupled to the voltage of the output node. The output terminal of the second transconductance amplifier is coupled to the gate of the second switching switch. The drain of the second switching switch is coupled to the current superposition circuit.

[0015] Optionally, the second transconductance amplifier includes:

[0016] A differential pair circuit having a first input terminal coupled to the input voltage and a second input terminal coupled to the voltage of the output node;

[0017] A bias circuit coupled to the input stage circuit and configured to provide a bias current to the input stage circuit;

[0018] An output stage circuit having an input terminal coupled to the differential input circuit and an output terminal coupled to the gate of the second switching switch.

[0019] Optionally, the current superposition circuit has a current mirror and a superposer; a control terminal of the superposer is coupled to a voltage of the output node, the current mirror is coupled to an output terminal of the first current conversion circuit and one end of the superposer, the other end of the superposer is coupled to an output terminal of the second current conversion circuit, a node of the superposer for generating the second difference current is coupled to the voltage conversion circuit, the current mirror is configured to mirror the input current into the superposer, and the superposer is configured to subtract the input current from the first difference current under the control of the voltage of the output node to generate a second difference current.

[0020] Optionally, the current mirror has a first mirror MOS transistor and a second mirror MOS transistor, and the superposer includes a superposition MOS transistor; a gate and a drain of the first mirror MOS transistor and a gate of the second mirror MOS transistor are all coupled to an output terminal of the first current conversion circuit; a drain of the second mirror MOS transistor is coupled to a drain of the superposition MOS transistor, the voltage conversion circuit, and a first input terminal of the first comparator; a gate of the superposition MOS transistor is coupled to the voltage of the output node, and a source of the superposition MOS transistor is coupled to an output terminal of the second current conversion circuit.

[0021] Optionally, the voltage conversion circuit includes a capacitor and a discharge switch, one end of the capacitor is coupled to one end of the discharge switch, a first input terminal of the first comparator, and the current superposition circuit, the other end of the capacitor and the other end of the discharge switch are both grounded, and a control terminal of the discharge switch receives a corresponding control signal.

[0022] Based on the same inventive concept, the present invention provides a control circuit for controlling on / off of a power switch circuit in the DC-DC conversion circuit, characterized in that the control circuit includes the on-time control circuit as described in the present invention.

[0023] Optionally, the control circuit further includes:

[0024] A feedback circuit, coupled to an output terminal of the DC-DC conversion circuit, and configured to sample the output voltage to generate a feedback voltage for feeding back changes and magnitude of the output voltage;

[0025] A PWM generator, configured to generate a pulse width modulation signal according to a voltage of an output node of the power switch circuit and the feedback voltage of the output voltage;

[0026] A zero-crossing detection circuit, configured to detect a zero-crossing point of a voltage of an output node of the power switch circuit to generate a zero-crossing signal;

[0027] A logic control circuit, coupled to the PWM generator, the on-time control circuit, the zero-crossing detection circuit, and the power switch circuit, is configured to drive the power switch circuit to turn on or off according to the pulse-width modulation signal, the on-time control signal, and the zero-crossing signal.

[0028] Optionally, the PWM generator includes:

[0029] An error amplifier, configured to compare a feedback voltage of the output voltage of the DC-DC conversion circuit with a first reference voltage to generate an error amplification signal;

[0030] A ramp generator, configured to compare a node voltage of the power switch circuit with a second reference voltage to generate a ramp signal;

[0031] A second comparator, with a first input terminal coupled to the output terminal of the error amplifier and a second input terminal coupled to the output terminal of the ramp generator, is configured to compare the error amplification signal and the ramp signal to generate the pulse-width modulation signal.

[0032] Based on the same inventive concept, the present invention further provides a DC-DC conversion circuit, which includes a power stage circuit and the control circuit as described in the present invention. The power switch circuit in the power stage circuit is coupled to the control circuit and is turned on and off under the control of the control circuit.

[0033] Compared with the prior art, the technical solution of the present invention, without the need to increase the area of the power switch circuit (i.e., the power switch transistor), on the basis of the traditional COT mode, introduces the difference between the input voltage and the voltage of the output node of the power switch circuit into the on-time control circuit, so that the on-time control circuit automatically adjusts the charging time of each switching cycle (i.e., the on-time of the power switch circuit in this switching cycle) according to the changes of the input voltage, the output voltage, and this difference, making the on-time of the power switch circuit increase synchronously with the duty cycle D affected by the internal resistance of the power switch transistor in the power switch circuit, thereby maintaining the relative stability of the circuit frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0035] Figure 1 is a schematic structural diagram of a DC-DC conversion circuit and a control circuit for the DC-DC conversion circuit according to an embodiment of the present invention.

[0036] Figure 2 is a schematic structural diagram of an example of an on-time control circuit according to an embodiment of the present invention.

[0037] Figure 3 It is a schematic circuit diagram of an error amplifier in a conduction time control circuit according to an embodiment of the present invention.

[0038] Figure 4 It is a schematic diagram for comparing signal timings under ideal COT control and actual COT control when a DC-DC conversion circuit according to an embodiment of the present invention is under heavy load.

[0039] Figure 5 It is a schematic diagram of a DC-DC conversion circuit according to another embodiment of the present invention and an architecture for the DC-DC conversion circuit. Detailed implementation manners

[0040] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other instances, in order to avoid confusion with the present invention, some well-known technical features are not described. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0041] The technical solutions proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0042] Please refer to Figure 1 , an embodiment of the present invention provides a conduction time control circuit 100, which is used to control the on / off of a power switch circuit of a DC-DC conversion circuit, so that the DC-DC conversion circuit converts a corresponding input voltage V IN into an output voltage V OUTThis DC-DC conversion circuit has a control circuit 10 and a power stage circuit 11. The power stage circuit 11 has an inductor L and an output capacitor C OUT and electronic components and circuit structures such as a power switch circuit including at least one power switch transistor. By controlling the control circuit 10 to turn on and off the power switch circuit in the power stage circuit 11, the power stage circuit 11 can convert the input voltage V IN into an output voltage V OUT . The power stage circuit 11 can be any suitable topology such as a Buck topology, a Boost topology, or a Buck-Boost topology

[0043] As an example, please refer to Figure 1 , the power stage circuit 11 is a buck Buck topology, which includes an inductor L and an output capacitor C OUT and a power switch circuit, which is formed by connecting a power switch transistor HS and a power switch transistor LS. Among them, the power switch transistor HS and the power switch transistor LS can be any controllable semiconductor switch device, such as a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a triode, etc. The control circuit 10 outputs a drive signal VGATEP to the gate of the power switch transistor HS to control the power switch transistor HS to alternately turn on and off, and outputs a drive signal VGATEN to the gate of the power switch transistor LS to control the power switch transistor LS to alternately turn on and off. The source of the power switch transistor HS is coupled to the input voltage V IN , the source of the power switch transistor LS is grounded, and the drain of the power switch transistor HS and the drain of the power switch transistor LS are coupled to form an output node of the power switch circuit to generate a voltage V SW . The output node of the power switch circuit is coupled to one end of the inductor L, and the other end of the inductor L is coupled to one end of the output capacitor C OUT to generate an output voltage V OUT . One end of the output capacitor C OUT is grounded at the other end

[0044] In this embodiment, the on-time control circuit (ON_TIMER) 100 belongs to the internal circuit of the control circuit 10, and is used to generate and output an on-time control signal TON for controlling the on-time of the power switch transistors HS and LS according to the input voltage V IN of the DC-DC conversion circuit, the output voltage V OUT and the difference between the input voltage V IN and the voltage V SW at the output node of the power switch circuit

[0045] It should be understood that the on-time control circuit 100 can adopt any suitable circuit design, and the present invention does not make specific limitations thereto. For example only, please refer to Figure 2 , the on-time control circuit 100 includes a first current conversion circuit 100a, a second current conversion circuit 100b, a current superposition circuit 100c, a voltage conversion circuit 100d, and a first comparator CMP0.

[0046] Among them, the first current conversion circuit 100a is coupled to the input voltage VIN and is used to convert the input voltage VIN into an input current I1 = V IN / Rton.

[0047] The second current conversion circuit 100b is coupled to the input voltage VIN and the output node of the power switch circuit, and converts the difference voltage V IN between the input voltage V SW and the voltage V IN -V SW at the output node of the power switch circuit into a first difference current Icomp.

[0048] The current superposition circuit 100c is coupled to the first current conversion circuit 100a, the second current conversion circuit 100b, and the output node of the power switch circuit, and is used to mirror the input current I1 in a 1:1 ratio to I2, that is, at this time I2 = I1 = V IN / Rton, and at the same time, under the control of the voltage V SW at the output node of the power switch circuit, the current I2 is subtracted from the first difference current Icomp to generate a second difference current I1 - Icomp.

[0049] The voltage conversion circuit 100d is coupled to the current mirror circuit 100b, and is used to convert the second difference current I1 - Icomp generated by the current superposition circuit 100c into a corresponding voltage (not shown).

[0050] The first input terminal (for example, the non-inverting input terminal “+”) of the first comparator CMP0 is coupled to the voltage conversion circuit 100d to receive the voltage output by the voltage conversion circuit 100d, and the second input terminal (for example, the inverting input terminal “-”) receives the output voltage V OUT , and the first comparator CMP0 is used to compare the magnitudes of the voltage V OUT and the voltage Vton converted by the voltage conversion circuit to generate and output an on-time control signal TON.

[0051] It should be understood that circuit modules such as the first current conversion circuit 100a, the second current conversion circuit 100b, the current superposition circuit 100c, the voltage conversion circuit 100d, and the first comparator CMP0 inside the conduction time control circuit 100 can adopt any suitable circuit design, and the internal circuit modules of the conduction time control circuit 100 can also be not limited to the first current conversion circuit 100a, the second current conversion circuit 100b, the current superposition circuit 100c, the voltage conversion circuit 100d, and the first comparator CMP0 according to functional requirements. The present invention does not make specific limitations on this.

[0052] As an example, the first current conversion circuit 100a includes a first transconductance amplifier OTA1, a first switching element M0, and a first resistor Rton. Among them, the first switching element M0 can be any controllable semiconductor switching device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a triode, etc. The source of the first switching element M0 is coupled to one end of the first resistor Rton and the second input terminal (such as the inverting input terminal “-”) of the first transconductance amplifier OTA1. The other end of the first resistor Rton is grounded. The first input terminal (such as the non-inverting input terminal “+”) of the first transconductance amplifier OTA1 serves as the input terminal of the first current conversion circuit 100a and is connected to the input voltage V IN , the output terminal of the first transconductance amplifier OTA1 is coupled to the gate of the first switching element M0, and the drain of the first switching element M0 serves as the node (which can be referred to as the output terminal of the first current conversion circuit 100a) for the first current conversion circuit 100a to provide an input current I1 to the current superposition circuit 100c. The input current I1 provided by the first current conversion circuit 100a to the current superposition circuit 100c is I1 = V IN / Rton.

[0053] As an example, the second current conversion circuit 100b includes a second transconductance amplifier OTA2 and a second switching element NM4. The source of the second switching element NM4 is grounded. The first input terminal (such as the non-inverting input terminal “+”) of the second transconductance amplifier OTA2 is coupled to the input voltage V IN , the second input terminal (such as the inverting input terminal “-”) of the second transconductance amplifier OTA2 is coupled to the voltage V SW at the output node of the power switching circuit. The output terminal of the second transconductance amplifier OTA2 is coupled to the gate of the second switching element NM4. The drain of the second switching element NM4 serves as the node (which can be referred to as the output terminal of the second current conversion circuit 100b) for the second current conversion circuit 100b to provide a first differential current Icomp to the current superposition circuit 100c. The first differential current Icomp provided by the second current conversion circuit 100b to the current superposition circuit 100c is related to the difference VIN -V SW has a linear relationship with its absolute value.

[0054] Among them, please refer to Figure 3 , the second transconductance amplifier OTA2 includes a differential pair circuit 200, a bias circuit 201, and an output stage circuit 202. Optionally, the differential pair circuit 200 includes a first input transistor NM1, a second input transistor NM2, a first load transistor PM1, and a second load transistor PM2. The bias circuit 201 includes a bias transistor NM0, and the output stage circuit 202 includes an output transistor NM3. The gate of the first input transistor NM1 serves as the first input terminal of the second transconductance amplifier OTA2 and is coupled to the input voltage V IN , the gate of the second input transistor NM2 serves as the second input terminal of the second transconductance amplifier OTA2 and is coupled to the voltage V SW . The sources of the first input transistor NM1 and the second input transistor NM2 are both coupled to the drain of the bias transistor NM0. The gate of the bias transistor NM0 is coupled to the bias voltage VNBIAS. The drain of the first input transistor NM1 is coupled to the drain and gate of the first load transistor PM1 and the gate of the second load transistor PM2. The drain of the second input transistor NM2 serves as the output terminal of the second transconductance amplifier OTA2 and is respectively coupled to the drain of the second load transistor PM2, the drain and gate of the output transistor NM3, and the gate of the second switching transistor NM4. The source of the first load transistor PM1 is coupled to the source of the second load transistor PM2 and may further be coupled to a corresponding power supply voltage (not shown). The source of the bias transistor NM0 is coupled to the source of the output transistor NM3 and the source of the second switching transistor NM4 and may further be grounded. The bias transistor NM0 provides a bias current for the first input transistor NM1 and the second input transistor NM2.

[0055] The second transconductance amplifier OTA2 can convert the difference between the input voltage V IN and the voltage V SW into a first difference current Icomp, and Icomp is specifically as follows:

[0056]

[0057] Wherein, g mn1,2 is the transconductance ratio of the first input transistor NM1 and the second input transistor NM2, g mn4 is the transconductance of the second switching transistor NM4, and g mn3 is the transconductance of the output transistor NM3. Obviously, the first difference current Icomp is proportional to V IN- V SW .

[0058] Optionally, the current superposition circuit 100c includes a current mirror and a summer. The control terminal of the summer is coupled to the voltage Vsw of the output node. The current mirror is coupled to the output terminal of the first current conversion circuit 100a and one end of the summer. The other end of the summer is coupled to the output terminal of the second current conversion circuit 100b. The node of the summer that generates the second difference current is coupled to the voltage conversion circuit 100d. The current mirror is configured to mirror the input current I1 into the summer. The summer is configured to subtract the input current I1 from the first difference current Icomp under the control of the voltage Vsw of the output node to generate a second difference current I1 - Icomp.

[0059] As an example, the current mirror of the current superposition circuit 100c includes a first mirror MOS transistor M1 and a second mirror MOS transistor M2. The summer includes a superposition switch MOS transistor M4. The gates of the first mirror MOS transistor M1 and the second mirror MOS transistor M2 are both coupled to the drain of the first mirror MOS transistor M1 and the drain of the first conversion switch M0 to access the input current I1. The drain of the second mirror MOS transistor M2 is respectively coupled to the drain of the superposition switch MOS transistor M4 as one end of the summer and the node of the summer that provides the second difference current, and to the voltage conversion circuit 100d and the first input terminal (e.g., the non-inverting input terminal “+”) of the first comparator CMP0, thereby forming an adjustable point n1. The voltage Vton provided at the adjustable point n1 is generated by the voltage conversion circuit 100d based on the second difference current and thus changes with the change of the second difference current. The source of the superposition switch MOS transistor M4 (as the other end of the summer) is coupled to the drain of the second conversion switch NM4. The gate of the superposition switch MOS transistor M4 serves as the control terminal of the summer (and also the control terminal of the current superposition circuit 100c) and receives the voltage VSW. The superposition switch MOS transistor M4 can also be replaced with any other suitable controllable semiconductor switch device, such as an insulated gate bipolar transistor (IGBT), a triode, etc. The ratio of the aspect ratios of the first to second mirror MOS transistors M1 to M2 is 1:1.

[0060] As an example, the voltage conversion circuit 100d includes a capacitor Cton and a discharge switch M3. One end (i.e., the upper plate) of the capacitor Cton serves as the node where the voltage conversion circuit 100d provides the voltage Vton, and is coupled to the adjustable point n1. That is, one end (i.e., the upper plate) of the capacitor Cton is respectively coupled to the drain of the discharge switch M3, the first input terminal of the first comparator CMP0, and the drains of M2 and M4. The other end (i.e., the lower plate) of the capacitor Cton is coupled to the source of the discharge switch M3 and can be further grounded. The gate of the discharge switch M3 receives a corresponding control signal (for example, a drive signal VGATEN). This control signal is usually in phase with the corresponding drive signal received in the power switch circuit (the drive signal is generated based on the on-time control signal TON), but the gate of the discharge switch M3 is usually not directly coupled to the gate of the power switch transistor in the power switch circuit. For example, when the discharge switch M3 is an NMOS transistor, the control signal received by its gate can be in phase with the drive signal received by the gate of the power switch transistor LS. In this article, in order to indicate that the signals received by the two gates are in phase, in Figure 2 the control signal of the gate of the discharge switch M3 is also marked as VGATEN. Thus, when the power switch transistor HS needs to be turned on and LS needs to be turned off, the discharge switch M3 is also turned off, and the second differential current I1 - Icomp charges the capacitor Cton. The charging time is the on-time of the power switch transistor HS. Furthermore, the second differential current I1 - Icomp output by the current superposition circuit 100c is converted into a corresponding voltage Vton = Q / Cton = (I1 - Icomp)*t / Cton = (VIN / Rton - Icomp)*t / Cton. Thus, the voltage Vton that can change with the second differential current I1 - Icomp can be provided at the adjustable point n1, and the second differential current I1 - Icomp changes with the difference V IN -V SW and thus the voltage Vton provided at the adjustable point n1 changes with the difference V IN -V SW .

[0061] To better illustrate the technical effects of the technical solution of the present invention, a comparison is made between the ideal COT control and the actual COT control of the DC-DC conversion circuit in the CCM (operating state under heavy load). Among them, Figure 4 shows the waveforms of the operation of the DC-DC conversion circuit under ideal COT control and actual COT control.

[0062] Please refer to Figures 1 to 4 as shown. According to the volt-second law, under CCM (operating state under heavy load) and ideal COT control, there are the following relationships:

[0063] (VIN -V OUT )*D = V OUT *(1 - D), D = V OUT / V IN 。

[0064] Under the CCM (operating state under overload) and actual COT control, the following relationship exists:

[0065] (V IN - IL*Rp - V OUT )*D’ = (V OUT + IL*Rn)*(1 - D’),

[0066] D’ = (V OUT + IL*Rn) / [V IN -(Rp - Rn)*IL]。

[0067] Where D is the duty cycle of the power switch circuit under ideal COT control, D’ is the duty cycle of the power switch circuit under actual COT control, Rp is the internal resistance of the power switch tube HS, and Rn is the internal resistance of the power switch tube LS.

[0068] From the above relational expressions, it can be seen that when the conduction time ton (for example, the conduction time of the power switch tube HS) remains unchanged, as the load current IL increases, the voltages consumed by the internal resistances Rp and Rn of the power switch tubes in the power switch circuit increase with the increase of the load current IL. This will cause the duty cycle D to be relatively larger than the calculated value, that is, D’ > D. According to T = ton / D, the cycle time T will decrease, that is Figure 4 the T’ in > T. Therefore, in order to keep the frequency of the DC - DC conversion circuit constant, it is necessary to synchronize ton to increase with D.

[0069] Assume that when V IN -V SW is not introduced into the conduction time control circuit 100, the conduction time ton of the power switch tube HS (also known as the upper tube) is ton = Cton*V OUT / I1 = Cton*V OUT *Rton / V IN 。When the input voltage V IN and the output voltage V OUT remain unchanged, ton is a constant fixed value.

[0070] And after introducing V IN -V SW into the conduction time control circuit 100, the calculation formula for the conduction time ton’ of the power switch tube HS (also known as the upper tube) is:

[0071]

[0072] Obviously, V is included in ton IN -V SW The information of, which is equivalent to including the information of the load current IL. And the duty cycle D is related to the load current IL. Therefore, when the load current IL rises (i.e., when V IN -V SW changes), the DC-DC conversion circuit can effectively compensate the conduction time ton according to the magnitude of the load current IL, so that it increases together with the duty cycle D affected by the internal resistance of the power transistor, thereby being able to reduce the fluctuation of the circuit frequency with the load and maintain the relative stability of the circuit frequency. That is to say, when the DC-DC conversion circuit modulated in the COT mode works, without the need to increase the area of the power switch circuit (i.e., the power switch transistor), by introducing V IN -V SW into the conduction time control circuit 100, it can automatically adjust the charging time of each switching cycle (i.e., the conduction time ton of the power switch transistor HS in this switching cycle) according to the change of this V IN -V SW so that the conduction time ton of the power switch transistor HS increases synchronously with the duty cycle D affected by the internal resistance of the power switch transistor HS, thereby maintaining the relative stability of the circuit frequency.

[0073] In addition, it should be understood that Figure 1 , Figure 2 and Figure 3 The various transistors and switches in (such as HS, LS, M0-M4, NM0-NM4, and PM1-PM2) are respectively shown by taking the corresponding NMOS transistors or PMOS transistors as examples. However, the technical solution of the present invention is not limited thereto. In other embodiments of the present invention Figures 1 to 3 The corresponding NMOS transistor in can be replaced by any controllable semiconductor switch device such as a PMOS transistor, a triode, an insulated gate bipolar transistor (IGBT), etc. Similarly Figures 1 to 3 The corresponding PMOS transistor in can be replaced by any controllable semiconductor switch device such as an NMOS transistor, a triode, an insulated gate bipolar transistor (IGBT), etc.

[0074] Based on the same inventive concept, please refer to Figure 1 , this embodiment also provides a control circuit 10, which is used to control the on and off of the power switch circuit in the DC-DC conversion circuit. The control circuit 10 includes the conduction time control circuit 100 as described in the present invention. For example, the control circuit 10 can respectively control the conduction time ton in each switching cycle of the power switch transistors HS and LS to be adjustable based on the conduction time control circuit 100. Optionally, the conduction time ton of the power switch transistors HS and LS increases synchronously with their duty cycle D.

[0075] Optionally, the control circuit 10 further includes a PWM generator 101 and a logic control circuit (LOGIC CONTROL) 102. The PWM generator 101 generates a pulse width modulation signal PWM according to the voltage V at the connection node of the power switching transistors HS and LS and the feedback voltage V of the output voltage V SW and the output voltage V OUT of the feedback voltage V FB . The logic control circuit 102 is coupled to the PWM generator 101, the on-time control circuit 100, and the gates of the power switching transistors HS and LS. The logic control circuit 102 performs a logic operation (such as an AND logic operation) on the pulse width modulation signal PWM and the on-time control signal TON to generate drive signals VGATEP and VGATEN to drive the power switching transistors HS and LS to alternately turn on and off. The pulse width modulation signal PWM is mainly used to determine the switching period (or switching frequency) of the power switching transistors HS and LS, and the on-time control signal TON is mainly used to determine the on-time ton of the power switching transistors HS and LS in each switching period.

[0076] It should be understood that the PWM generator 101 and the logic control circuit (LOGIC CONTROL) 102 can be implemented by any suitable circuit design, and the internal structure of the control circuit 10 is only an example, which does not indicate that the internal structure of the control circuit 10 of the present invention is limited thereto. In other embodiments of the present invention, the control circuit 10 may further have other functional circuits, and the DC-DC conversion circuit may further include other circuit structures.

[0077] For example, please refer to Figure 5 . In an embodiment of the present invention, the PWM generator 101 includes an error amplifier EA1, a ramp generator RAMP, and a second comparator CMP1. The error amplifier EA1 is used to compare the feedback voltage V of the output voltage V of the DC-DC conversion circuit with a first reference voltage V OUT to generate an error amplification signal V FB and a first reference voltage V REF1 . The ramp generator RAMP is used to compare the voltage V at the connection node of the power switching transistors HS and LS with a second reference voltage V EAO . The ramp generator RAMP is used to compare the voltage V at the connection node of the power switching transistors HS and LS with a second reference voltage V SW to generate a ramp signal V REF2 . The first input terminal (for example, the non-inverting input terminal “+”) of the second comparator CMP1 is coupled to the output terminal of the error amplifier EA1, and the second input terminal (for example, the inverting input terminal “-”) is coupled to the output terminal of the ramp generator RAMP. The second comparator CMP1 is used to compare the error amplification signal V RAMP and the ramp signal V EAO and the ramp signal V RAMPThe size therebetween is used to generate the pulse width modulation signal PWM required by the logic control circuit 102.

[0078] For example, in another embodiment of the present invention, please refer to Figure 5 , the control circuit 10 further includes a zero-crossing detection circuit (not labeled), and the output terminal of the zero-crossing detection circuit is coupled to the logic control circuit 102; the zero-crossing detection circuit is used to detect the voltage V SW at the output node of the power switch circuit to generate a zero-crossing signal ZCD; the logic control circuit 102 performs corresponding logical operations on the pulse width modulation signal PWM, the zero-crossing signal ZCD, and the conduction time control signal TON to control the on and off of the corresponding power switch tube (HS or LS) in the power switch circuit.

[0079] As an example, the zero-crossing detection circuit includes a third comparator CMP2. The first input terminal of the third comparator CMP2 receives the voltage V SW at the connection node of the power switch tubes HS and LS. The second input terminal of the third comparator CMP2 is connected to 0V or grounded or connected to a reference voltage. The output terminal of the third comparator CMP2 is coupled to the logic control circuit 102 to provide the zero-crossing signal ZCD.

[0080] Based on the same inventive concept, please refer to Figure 1 and Figure 5 , an embodiment of the present invention further provides a DC-DC conversion circuit, which includes a power stage circuit 11 and a control circuit 10 as described in any embodiment of the present invention. The power stage circuit 11 can adopt any suitable topology such as a Buck topology, a Buck-boost topology, or a Boost topology, and it has an inductor L, an output capacitor C OUT and a corresponding power switch circuit. The power switch circuit has at least one power switch tube, such as Figure 1 and Figure 5 HS and LS in IN . The control circuit 10 is coupled to the gate of the corresponding power switch tube in the power switch circuit of the power stage circuit 11 to turn on and off under the control of the control circuit 10, thereby enabling the DC-DC conversion circuit to operate in a corresponding mode (such as the COT mode), and converting the input voltage V OUT .

[0081] Optionally, please refer to Figure 5 , the DC-DC conversion circuit further includes a feedback circuit 12, which can sample the output voltage V OUT to generate a feedback voltage V OUT for feedback on the change and magnitude of the output voltage V FB。As an example, the feedback circuit 12 includes resistors R1 and R2. One end of resistor R1 is coupled to the upper plate of output capacitor C OUT and one end of inductor L. The other end of resistor R1 is connected to one end of resistor R2 and outputs a feedback voltage V FB , and the other end of resistor R2 is grounded.

[0082] In summary, the on-time control circuit, control circuit, and DC-DC conversion circuit provided by the present invention, without increasing the area of the power switch circuit (i.e., the power switch transistor), but on the basis of the traditional COT mode, introduce the difference between the input voltage and the voltage of the output node of the power switch circuit into the on-time control circuit. The on-time control circuit can control the on-time of the power switch circuit within the corresponding switching period to be adjustable according to the input voltage, output voltage, and the difference between the input voltage and the voltage of the output node of the power switch circuit, so that the on-time of the power switch circuit increases synchronously with the duty cycle D affected by the internal resistance of the power switch transistor in the power switch circuit, thereby maintaining the relative stability of the circuit frequency.

[0083] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A conduction time control circuit is used to control the on / off of a power switch circuit in a DC-DC conversion circuit, so that the DC-DC conversion circuit converts a corresponding input voltage into an output voltage, and is characterized in that, The on-time control circuit is coupled to the output node of the power switch circuit and is configured to control the on-time of the power switch circuit in a corresponding switching period to be adjustable according to the input voltage, the output voltage, and the difference between the input voltage and the voltage of the output node, so as to maintain the relative stability of the frequency of the DC-DC conversion circuit.

2. The turn-on time control circuit according to claim 1, wherein, The on-time of the power switch circuit increases synchronously with the duty cycle of the power switch circuit.

3. The turn-on time control circuit according to claim 1, wherein, The on-time control circuit includes: A first current conversion circuit configured to convert the input voltage into an input current; A second current conversion circuit configured to convert the difference between the input voltage and the voltage of the output node into a first difference current; A current superposition circuit coupled to the first current conversion circuit, the second current conversion circuit, and the output node, and configured to subtract the input current from the first difference current under the control of the voltage of the output node to generate a second difference current; A voltage conversion circuit coupled to the current superposition circuit and configured to convert the second difference current into a corresponding voltage; A first comparator having a first input terminal coupled to the voltage conversion circuit, a second input terminal coupled to the output voltage, and configured to compare the magnitudes of the output voltage and the voltage converted by the voltage conversion circuit to generate and output a corresponding on-time control signal for controlling the on-time.

4. The turn-on time control circuit according to claim 3, wherein The first current conversion circuit includes a first transconductance amplifier, a first switching switch, and a first resistor. The source of the first switching switch is coupled to one end of the first resistor and the second input terminal of the first transconductance amplifier. The other end of the first resistor is grounded. The first input terminal of the first transconductance amplifier receives the input voltage. The output terminal of the first transconductance amplifier is coupled to the gate of the first switching switch. The drain of the first switching switch is coupled to the current superposition circuit.

5. The turn-on time control circuit according to claim 3, wherein The second current conversion circuit includes a second transconductance amplifier and a second switching switch. The source of the second switching switch is grounded. The first input terminal of the second transconductance amplifier is coupled to the input voltage. The second input terminal of the second transconductance amplifier is coupled to the voltage of the output node. The output terminal of the second transconductance amplifier is coupled to the gate of the second switching switch. The drain of the second switching switch is coupled to the current superposition circuit.

6. The turn-on time control circuit according to claim 5, wherein, The second transconductance amplifier includes: A differential pair circuit having a first input terminal coupled to the input voltage and a second input terminal coupled to the voltage of the output node; A bias circuit coupled to the input stage circuit and configured to provide a bias current to the input stage circuit; An output stage circuit having an input terminal coupled to the differential input circuit and an output terminal coupled to the gate of the second switching switch.

7. The turn-on time control circuit according to claim 3, wherein The current superposition circuit has a current mirror and a summer; a control end of the summer is coupled to a voltage of the output node, the current mirror is coupled to an output end of the first current conversion circuit and one end of the summer, the other end of the summer is coupled to an output end of the second current conversion circuit, a node of the summer for generating the second differential current is coupled to the voltage conversion circuit, the current mirror is used for mirroring the input current into the summer, and the summer is used for subtracting the input current from the first differential current under the control of the voltage of the output node to generate a second differential current.

8. The turn-on time control circuit according to claim 7, characterized in that The current mirror has a first mirror MOS transistor and a second mirror MOS transistor, and the summer includes a summing MOS transistor; a gate and a drain of the first mirror MOS transistor and a gate of the second mirror MOS transistor are all coupled to the output end of the first current conversion circuit; a drain of the second mirror MOS transistor is coupled to a drain of the summing MOS transistor, the voltage conversion circuit and a first input end of the first comparator; a gate of the summing MOS transistor is coupled to the voltage of the output node, and a source of the summing MOS transistor is coupled to the output end of the second current conversion circuit.

9. The turn-on time control circuit according to claim 3, wherein The voltage conversion circuit includes a capacitor and a discharge switch, one end of the capacitor is coupled to one end of the discharge switch, the first input end of the first comparator and the current superposition circuit, the other end of the capacitor and the other end of the discharge switch are both grounded, and a control end of the discharge switch is connected to a corresponding control signal.

10. A control circuit for controlling the on / off of a power switch circuit in the DC-DC conversion circuit, characterized in that, The control circuit includes a turn-on time control circuit as described in any one of claims 1-9.

11. The control circuit according to claim 10, characterized in that, Further included are: a feedback circuit, coupled to an output end of the DC-DC conversion circuit, and used for sampling the output voltage to generate a feedback voltage for feeding back a change and a magnitude of the output voltage; a PWM generator, used for generating a pulse width modulation signal according to the voltage of an output node of the power switch circuit and the feedback voltage of the output voltage; a zero-crossing detection circuit, used for detecting a zero-crossing point of the voltage of the output node of the power switch circuit to generate a zero-crossing signal; a logic control circuit, coupled to the PWM generator, the turn-on time control circuit, the zero-crossing detection circuit and the power switch circuit, and used for driving the power switch circuit to turn on or off according to the pulse width modulation signal, the turn-on time control signal and the zero-crossing signal.

12. The control circuit according to claim 11, wherein The PWM generator includes: an error amplifier, used for comparing the feedback voltage of the output voltage of the DC-DC conversion circuit with a first reference voltage to generate an error amplification signal; a ramp generator, used for comparing the node voltage of the power switch circuit with a second reference voltage to generate a ramp signal; a second comparator, with a first input end coupled to an output end of the error amplifier and a second input end coupled to an output end of the ramp generator, and used for comparing the error amplification signal and the ramp signal to generate the pulse width modulation signal.

13. A DC-DC conversion circuit, characterized in that, Including a power stage circuit and a control circuit as described in any one of claims 10-12, wherein the power switch circuit in the power stage circuit is coupled to the control circuit and is turned on and off under the control of the control circuit.

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