Comparator threshold correction device of assembly line ADC (Analog to Digital Converter)
By designing a comparator threshold correction device for pipeline ADC, using the combination of error data calculation, comparison and adjustment modules, the problem of large area and long convergence time in the prior art correction method is solved, high-precision and fast threshold correction are achieved, and good resistance to process fluctuations is achieved.
Patent Information
- Application Number
- CN202510263668.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-06
- Publication Date
- 2025-07-01
AI Technical Summary
In the existing pipeline ADC, the comparator threshold correction method has defects such as large area, long convergence time, and inability to follow process changes, resulting in the ADC's problems such as loss of codes when facing process deviations and aging.
A comparator threshold correction device for pipeline ADC is designed, including an error data calculation module, a comparison module and an adjustment module. The error data calculation module calculates the periodic error accumulation data within the error accumulation period through the first signal and the second signal. The comparison module compares the periodic error accumulation data of two adjacent error accumulation periods. The adjustment module adjusts the reference current in the first stage comparator according to the comparison results to realize the correction of the comparator threshold.
The device can correct the comparator threshold with high accuracy and quickly, reduce power consumption and area occupation, have good adjustment freedom, and can effectively resist process fluctuations and avoid ADC code loss.
Smart Images
Figure CN120238124A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and particularly to a comparator threshold correction device for a pipelined ADC. Background Art
[0002] Wireless communication and instrumentation systems have driven the development of high-sampling-rate and high-performance analog-to-digital converters (ADCs). Low power consumption and small chip area are key concerns for ADCs. Among various ADC architectures, pipelined ADCs are suitable for high-speed and high-resolution application scenarios. To further save power and area, the pipelined ADC architecture without a front-end sample-and-hold amplifier (SHA) is widely adopted in the industry. Removing the SHA simplifies the signal chain because the SHA not only consumes a large amount of power but also introduces additional noise contributions. In some low-power pipelined ADCs, the comparator discards the preamplifier structure at the front end. This poses additional challenges to the sampling and comparison accuracy of signals. In addition, process variations and aging can cause deviations in the comparator threshold, which may lead to phenomena such as missing codes in the pipelined ADC. To meet the requirements of the entire system for signal conversion speed and accuracy, it is necessary to correct the comparator threshold of the first-stage sub-ADC. Traditional correction methods have defects such as large occupied area, long convergence time, and inability to follow process changes. Summary of the Invention
[0003] In view of the above-mentioned disadvantages of the prior art, this application provides a comparator threshold correction device for a pipelined ADC to solve at least one defect in the prior art.
[0004] To achieve the above object and other objects, this application provides a comparator threshold correction device for a pipelined ADC, and the correction device includes:
[0005] An error data calculation module, configured to determine periodic error cumulative data within an error accumulation period based on a first signal and a second signal; the first signal is the output signal of the first-stage comparator of the ADC, and the second signal is the error valid data in the digital domain determined based on the intercepted signal of the first signal;
[0006] A comparison module, configured to compare the periodic error cumulative data of two adjacent error accumulation periods to obtain a comparison result;
[0007] An adjustment module, configured to adjust the reference current in the first-stage comparator according to the comparison result to achieve correction of the comparator threshold.
[0008] In an embodiment of this application, the error data calculation module includes:
[0009] A control module, configured to receive the first signal,
[0010] A first register for receiving the second signal;
[0011] A first accumulator that outputs a third signal when the first signal is a first value and the second signal meets a first condition; and outputs a first accumulation result based on the second signal and the third signal;
[0012] A second accumulator that outputs a fourth signal when the second signal is a second value and the second signal meets a second condition; and outputs a second accumulation result based on the second signal and the fourth signal;
[0013] An adder that outputs the periodic error accumulation data based on the first accumulation result and the second accumulation result;
[0014] A second register for receiving the periodic error accumulation data.
[0015] In an embodiment of the present application, the second signal D[5:0] is:
[0016] D[5:0] = Data[N - n] - stage1[0] + Data[N - n - 1:N - n - 5] + WD[N - n:N - n - 5]
[0017] where Data[N - n] represents the N-bit data output by the N-bit pipelined ADC, stage1[0] represents the first signal, Data[N - n - 1:N - n - 5] represents the truncated signal of the first signal, and WD[N - n:N - n - 5] represents the perturbation injection amount; the perturbation injection amount is determined based on the perturbation injection weight, the perturbation injection capacitance, and the sampling capacitance.
[0018] In an embodiment of the present application, the perturbation injection weight is:
[0019] Wdither_n = WCs * (Cdither_n / Cs) n = 1, 2…
[0020] where Wdither_n represents the perturbation injection weight, WCs represents the sampling capacitance weight, Cdither_n represents the perturbation injection capacitance, and Cs represents the sampling capacitance.
[0021] In an embodiment of the present application, the first value is 2^(n - 1), 2^(n - 1) + 1, 2^(n - 1) + 2, …, 2^n - 1, the second value is 0, 1, 2, …, 2^(n - 1) - 1, and the first condition is that the absolute value |Q[5:0]| of Q[5:0] is less than or equal to 9;
[0022] When the first signal is 2^(n - 1), 2^(n - 1)+1, 2^(n - 1)+2, …, 2^n - 1, and the absolute value |Q[5:0]| of Q[5:0] is less than or equal to 9, the first accumulator accumulates (10 + |Q[5:0]|).
[0023] When the first signal is 0, 1, 2, …, 2^(n - 1)-1, and the absolute value |Q[5:0]| of Q[5:0] is less than or equal to 9, the second accumulator accumulates (-10 + |Q[5:0]|).
[0024] In an embodiment of the present application, the error data calculation module further includes a first counter and a second counter. When the first counter counts to 2^(N - 1) and the second counter counts to 2^(N - 1)-1, it is regarded as an error accumulation period.
[0025] In an embodiment of the present application, the first signal is obtained by injecting a pseudo-random sequence into a first comparator.
[0026] In an embodiment of the present application, the first-stage comparator includes:
[0027] A first perturbation DAC that converts the pseudo-random sequence generated by a pseudo-random generator into a first analog signal;
[0028] A first summing unit that adds the analog input signal and the first analog signal to obtain a second analog signal;
[0029] A first-stage ADC connected to the first summing unit that converts the second analog signal into a digital code;
[0030] A first-stage DAC connected to the first-stage ADC that converts the digital code into a third analog signal;
[0031] A second perturbation DAC that converts the pseudo-random sequence generated by a pseudo-random generator into a fourth analog signal;
[0032] A second summing unit that adds the first analog signal and the fourth analog signal, and then subtracts the third analog signal;
[0033] An amplification unit that amplifies the output signal of the second summing unit and outputs the first signal.
[0034] In an embodiment of the present application, the correction device further includes:
[0035] A state machine connected to the comparison module. The state machine performs jump output control codes according to the output result of the comparison module to control the magnitude of the reference current in the first-stage comparator through the control codes.
[0036] In an embodiment of the present application, when the periodic error cumulative data of the previous error accumulation period of two adjacent error accumulation periods is greater than the periodic error cumulative data of the latter error accumulation period of the two adjacent error accumulation periods, the adjustment module reduces the reference current; and when the periodic error cumulative data of the previous error accumulation period of two adjacent error accumulation periods is less than or equal to the periodic error cumulative data of the latter error accumulation period of the two adjacent error accumulation periods, the adjustment module increases the reference current.
[0037] Advantages of the present application:
[0038] A comparator threshold correction device for a pipelined ADC of the present application includes: an error data calculation module for determining periodic error cumulative data within an error accumulation period based on a first signal and a second signal; the first signal is the output signal of the first-stage comparator of the ADC, and the second signal is the error valid data in the digital domain determined based on the truncated signal of the first signal; a comparison module for comparing the periodic error cumulative data of two adjacent error accumulation periods to obtain a comparison result; an adjustment module for adjusting the reference current in the first-stage comparator according to the comparison result to achieve correction of the comparator value. The present application estimates the error valid data and feeds back the trimming code value to the first-stage comparator, thereby automatically adjusting the current flowing through the resistor string of the first-stage comparator to achieve the purpose of overall stretching or compressing the comparator threshold; it has the advantages of high calculation accuracy, fast convergence speed, small occupied layout area, low cost, and high trimming freedom, and can effectively resist process fluctuations.
[0039] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Brief Description of the Drawings
[0040] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In the drawings:
[0041] Figure 1 It is a schematic structural diagram of an ADC according to an embodiment of the present application;
[0042] Figure 2 It is a schematic diagram of generating the reference voltage of the reference first-stage comparator according to an embodiment of the present application;
[0043] Figure 3 It is an ideal transfer curve diagram of the first stage of a pipelined ADC according to an embodiment of the present application;
[0044] Figure 4 Schematic diagram of the comparator module in an embodiment of the present application;
[0045] Figure 5 Schematic diagram of a comparator threshold correction device for a pipelined ADC in an embodiment of the present application. Detailed implementation manners
[0046] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0047] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0048] Although terms such as "first", "second", "A", and "B" may be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, without departing from the scope of the following technology, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. The term "and / or" includes combinations of multiple related items or any item in multiple related items.
[0049] As used herein, unless the context indicates otherwise, the singular form is also intended to include the plural form. It will be understood that the term "comprising" means the presence of the described features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.
[0050] Before the detailed description, it is intended to clarify that the division of components in this specification is only based on the main functions of each component. That is, two or more of the following-described components can be combined into one component, or can be divided into two or more components according to more detailed functions. In addition to the main functions of the components, each of the following-described components can also perform some or all of the functions of other components, and some of the main functions of each component can be specifically performed by other components.
[0051] Please refer to Figure 1 , which is a schematic diagram of the structure of an ADC. As Figure 1 shown, this ADC is a pipelined ADC and includes multiple comparator modules. The analog input signal Vin enters the first-stage comparator module (stage1), and the first-stage comparator module (stage1) quantizes the analog input signal Vin, and the digital output code D1< n - 1 : 0 >, and the output signal Vout_1 is output. The signal Vout1 enters the second-stage comparator module (stage2), and the second comparator module (stage2) outputs the signal Vout_1 and generates the digital output code D2< n - 2 : 0 >. The digital output codes obtained by quantizing each stage comparator module are generated in sequence according to similar steps. In the last stage, that is, the Mth-stage comparator module (stageM), the signal Vout_M-1 generated by the M-1 comparator module is quantized to generate the digital output code Dk <n-m:0>。
[0052] For the first-stage comparator module, the threshold voltage of the first-stage comparator module is generated by adding a reference voltage to a resistor string, as Figure 2 shown.
[0053] The calculation formula for the first-stage comparator voltage is as follows.
[0054] +Vrefn = VNn - VMn = PIBI * 2n * R
[0055] -Vrefn = VMn - VNn = -PIBI * 2n * R
[0056] n = 0, 1, 2, 3...
[0057] Taking n = 7 as an example, the ideal transfer curve of the first stage of the pipelined ADC is as Figure 3 shown.
[0058] Among them, the comparator thresholds are ±13 / 16, ±11 / 16, ±9 / 16, ±7 / 16, ±5 / 16, ±3 / 16, ±1 / 16 respectively.
[0059] Assume that the process deviation or device aging causes a deviation of ΔI in the reference current PIBI, then the threshold deviation ΔVref is
[0060] ΔVref = (ΔI / PIBI) * 100%
[0061] If ΔVref exceeds the redundancy range, it will cause the ADC to have a missing code. Therefore, it is necessary to correct the comparator threshold.
[0062] Please refer to Figure 5 , Figure 5 which is a comparator threshold correction device for a pipelined ADC according to an embodiment of the present application, and is used to correct the reference current of the comparator in the first-stage comparator module. As Figure 5 shown, the correction device includes:
[0063] An error data calculation module, configured to determine the periodic error cumulative data within an error accumulation period based on a first signal and a second signal; the first signal is the output signal of the first-stage comparator of the ADC, and the second signal is the error valid data in the digital domain determined based on the intercepted signal of the first signal;
[0064] A comparison module, configured to compare the periodic error cumulative data of two adjacent error accumulation periods to obtain a comparison result;
[0065] An adjustment module, configured to adjust the reference current in the first-stage comparator according to the comparison result to achieve the correction of the comparator threshold.
[0066] For an N-bit pipelined ADC, its output is N-bit data Data[N-1:0]. The output code value of the first-stage comparator module (the first-stage n-bit sub-ADC) is stage1[n-1:0]. Then, six bits are intercepted to obtain Data[N-n:N-n-5], getting the effective data for estimating the error in the digital domain. That is, the second signal is:
[0067] D[5:0] = Data[N-n] - stage1[0] + Data[N-n-1:N-n-5] + WD[N-n:N-n-5].
[0068] Wherein, Data[N-n] represents the N-bit data output by the N-bit pipelined ADC, stage1[0] represents the first signal, Data[N-n-1:N-n-5] represents the intercepted signal of the first signal, and WD[N-n:N-n-5] represents the perturbation injection amount; the perturbation injection amount is determined based on the perturbation injection weight, the perturbation injection capacitance, and the sampling capacitance.
[0069] In one embodiment, the perturbation injection weight is:
[0070] Wdither_n = WCs * (Cdither_n / Cs) n = 1, 2…
[0071] Wherein, Wdither_n represents the perturbation injection weight, WCs represents the sampling capacitance weight, Cdither_n represents the perturbation injection capacitance, and Cs represents the sampling capacitance.
[0072] In one embodiment, the first signal is obtained by injecting a pseudo-random sequence into the first comparator.
[0073] Please refer to Figure 4 , Figure 4 which is the schematic diagram of the comparator module in an embodiment of the present application. In Figure 4 , the first-stage comparator includes:
[0074] A first perturbation DAC that converts the pseudo-random sequence generated by the pseudo-random generator PN into a first analog signal;
[0075] A first summing unit that adds the analog input signal and the first analog signal to obtain a second analog signal;
[0076] A first-stage ADC connected to the first summing unit that converts the second analog signal into a digital code;
[0077] A first-stage DAC connected to the first-stage ADC that converts the digital code into a third analog signal;
[0078] A second perturbation DAC that converts the pseudo-random sequence generated by the pseudo-random generator into a fourth analog signal;
[0079] A second summing unit that adds the first analog signal and the fourth analog signal and then subtracts the third analog signal;
[0080] An amplification unit G that amplifies the output signal of the second summing unit and outputs a first signal.
[0081] Perturbation is injected into the first-stage ADC, where the perturbation injection capacitance is Cdither_n and the sampling capacitance is Cs. In the digital domain, the weight of the first-stage sampling capacitance Cs is WCs, then the perturbation injection weight in the digital domain is
[0082] Wdither_n = WCs * (Cdither_n / Cs) n = 1, 2…
[0083] In an N-bit pipelined ADC, in the first-stage comparison module, WCs = (2^N) / (2^n). If the perturbation injection capacitances are: Cdither_1 = 1 / 2 * Cs, Cdither_2 = 1 / 4 * Cs
[0084] Then the perturbation injection amount WD in the digital domain is
[0085] WD1 = Wdither_1 + Wdither_2;
[0086] WD2 = -Wdither_1 - Wdither_2;
[0087] WD3 = Wdither_2;
[0088] WD4 = -Wdither_2.
[0089] Please refer to Figure 5 , the error data calculation module includes:
[0090] A control module for receiving the first signal;
[0091] A first register for receiving the second signal;
[0092] A first accumulator that outputs a third signal when the first signal is a first value and the second signal satisfies a first condition; outputs a first accumulation result based on the second signal and the third signal;
[0093] A second accumulator that outputs a fourth signal when the second signal is a second value and the second signal satisfies a second condition; outputs a second accumulation result based on the second signal and the fourth signal;
[0094] An adder that outputs the period error cumulative data based on the first cumulative result and the second cumulative result;
[0095] A second register for receiving the period error cumulative data.
[0096] In one embodiment, the first value is 2^(n - 1), 2^(n - 1)+1, 2^(n - 1)+2, …, 2^n - 1, the second value is 0, 1, 2, …, 2^(n - 1)-1, and the first condition is that the absolute value |Q[5:0]| of Q[5:0] is less than or equal to 9;
[0097] When the first signal is 2^(n - 1), 2^(n - 1)+1, 2^(n - 1)+2, …, 2^n - 1 and the absolute value |Q[5:0]| of Q[5:0] is less than or equal to 9, the first accumulator accumulates (10 + |Q[5:0]|);
[0098] When the first signal is 0, 1, 2, …, 2^(n - 1)-1 and the absolute value |Q[5:0]| of Q[5:0] is less than or equal to 9, the second accumulator accumulates (-10 + |Q[5:0]|).
[0099] In one embodiment, the error data calculation module further includes a first counter and a second counter. When the first counter counts to 2^(N - 1) and the second counter counts to 2^(N - 1)-1, it is regarded as an error accumulation period.
[0100] In one embodiment, when the period error cumulative data of the previous error accumulation period of two adjacent error accumulation periods is greater than that of the latter error accumulation period of the two adjacent error accumulation periods, the adjustment module reduces the reference current; and when the period error cumulative data of the previous error accumulation period of two adjacent error accumulation periods is less than or equal to that of the latter error accumulation period of the two adjacent error accumulation periods, the adjustment module increases the reference current.
[0101] In one embodiment, the correction device further includes:
[0102] A state machine connected to the comparison module. The state machine makes a jump output control code according to the output result of the comparison module to control the magnitude of the reference current in the first - stage comparator through the control code.
[0103] In one embodiment, for the error data calculation module, stage1[n - 1:0] is sent to the control module. After D[5:0] passes through the first register, Q[5:0] is obtained, and Q[5:0] enters the first accumulator and the second accumulator respectively.
[0104] When stage1[n - 1:0] = 2^(n - 1), 2^(n - 1)+1, 2^(n - 1)+2…2^n - 1, and the absolute value of Q[5:0], |Q[5:0]| <= 9, the first accumulator accumulates (10 + |Q[5:0]|), and the accumulation result is A[N + 4:0];
[0105] When stage1[n - 1:0] = 0, 1, 2…, 2^(n - 1)-1, and the absolute value of Q[5:0], |Q[5:0]| <= 9, the second accumulator accumulates (-10 + |Q[5:0]|), and the accumulation result is B[N + 4:0].
[0106] The calculation result in the adder is SUM1[N + 4:0] = A[N + 4:0] - B[N + 4:0].
[0107] When stage1[n - 1:0] = 2^(n - 1), 2^(n - 1)+1, 2^(n - 1)+2,…, 2^n - 1, the first counter makes one count.
[0108] When stage1[n - 1:0] = 0, 1, 2…, 2^(n - 1)-1, the second counter makes one count.
[0109] When the first counter counts to 2^(N - 1) and the second counter counts to 2^(N - 1)-1, it is regarded as an error accumulation period Tn. At this time, the second register loads the Tn period error accumulation data SUM1[N + 4:0] into A[N + 4:0] in the comparison module, and the algorithm continues to perform the error accumulation of SUM1[N + 4:0] in the next error accumulation period Tn+1. The output of the comparison module is the comparison result of the Tn period error accumulation data SUM1[N + 4:0] and the Tn+1 period error accumulation data SUM1[N + 4:0]. In the comparison module, when the Tn period error accumulation data SUM1 is greater than the Tn+1 period error accumulation data SUM1, the comparison module outputs EQ = 1, and the state machine jumps according to the output result of the comparison module, and outputs a 4-bit control code CTRL[3:0] to control the magnitude of the PIBI current in the analog circuit; in the comparison module, when the Tn period error accumulation data SUM1 is less than or equal to the Tn+1 period error accumulation data SUM1, the comparison module outputs EQ = 0, and the state machine jumps according to the output result of the comparison module, and outputs a 4-bit control code CTRL[3:0] to control the magnitude of the PIBI current in the analog circuit.
[0110] A comparator threshold correction device for a pipelined ADC of the present application includes: an error data calculation module, configured to determine periodic error cumulative data within an error accumulation period based on a first signal and a second signal; the first signal is an output signal of a first-stage comparator of the ADC, and the second signal is error valid data in the digital domain determined based on an intercepted signal of the first signal; a comparison module, configured to compare the periodic error cumulative data of two adjacent error accumulation periods to obtain a comparison result; an adjustment module, configured to adjust a reference current in the first-stage comparator according to the comparison result to achieve correction of the comparator value. The present application estimates error valid data and feeds back a trimming code value to the first-stage comparator, thereby automatically adjusting the magnitude of the current flowing through the resistor string of the first-stage comparator to achieve the purpose of adjusting the overall stretching or compression of the comparator threshold; it has the advantages of high calculation accuracy, fast convergence speed, small layout area occupation, cost saving, and high trimming freedom, and can effectively resist process fluctuations.
[0111] It should be noted that a large number of technical features are recorded in the specification of the present application, distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of the present application are listed, the specification will be too lengthy. To avoid this problem, each technical feature disclosed in the above-mentioned invention content of the present application, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, features A+B+C are disclosed, and in another example, features A+B+D+E are disclosed, and features C and D are equivalent technical means that play the same role. Only one of them can be used technically and it is impossible to use both at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be regarded as having been recorded.
[0112] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element. In the application documents of this patent, if it is mentioned that an act is performed according to a certain element, it means that the act is performed at least according to that element, including two cases: performing the act only according to that element and performing the act according to that element and other elements. Expressions such as multiple, many times, various, etc. include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.
[0113] The term "coupled to" and its derivatives may be used herein. "Coupling" may mean that two or more elements are in direct physical or electrical contact. However, "coupling" may also mean that two or more elements are in contact with each other indirectly, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.
[0114] This specification includes combinations of various embodiments described herein. Separate references to embodiments (such as "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated to be mutually exclusive or clearly mutually exclusive to those skilled in the art, these embodiments are not mutually exclusive. It should be noted that the word "or" is used in a non-exclusive sense in this specification unless the context clearly dictates otherwise or requires otherwise.
[0115] The above embodiments are only used to exemplarily illustrate the principles and effects of this application, rather than to limit this application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in this application should still be covered by the claims of this application.
Claims
1. A comparator threshold correction device for a pipeline ADC, characterized in that: The correction device comprises: An error data calculation module, used to determine periodic error accumulation data within an error accumulation period based on a first signal and a second signal; the first signal is an output signal of a first-stage comparator of the ADC, and the second signal is effective error data in a digital domain determined based on an intercepted signal of the first signal; A comparison module, used for comparing the period error accumulation data of two adjacent error accumulation periods to obtain a comparison result; The adjustment module is used to adjust the reference current in the first-stage comparator according to the comparison result to achieve correction of the comparator threshold.
2. The comparator threshold correction device of the pipeline ADC according to claim 1, characterized in that: The error data calculation module comprises: A control module, configured to receive the first signal, A first register, configured to receive the second signal; a first accumulator, which outputs a third signal when the first signal is a first value and the second signal satisfies a first condition; and outputs a first accumulation result based on the second signal and the third signal; a second accumulator, which outputs a fourth signal when the second signal is a second value and satisfies a second condition; and outputs a second accumulation result based on the second signal and the fourth signal; an adder, outputting the period error accumulation data based on the first accumulation result and the second accumulation result; The second register is used to receive the period error accumulation data.
3. The comparator threshold correction device of the pipeline ADC according to claim 2, characterized in that: The second signal D[5:0] is: D[5:0]=Data[Nn]-stage1[0]+Data[Nn-1:Nn-5]+WD[Nn:Nn-5] Among them, Data[Nn] represents the N-bit data output by the N-bit pipeline ADC, stage1[0] represents the first signal, Data[Nn-1:Nn-5] represents the intercepted signal of the first signal, and WD[Nn:Nn-5] represents the disturbance injection amount; the disturbance injection amount is determined based on the disturbance injection weight, the disturbance injection capacitor and the sampling capacitor.
4. The comparator threshold correction device for pipeline ADC according to claim 3, characterized in that: The disturbance injection weight is: Wdither_n=WCs*(Cdither_n / Cs)n=1,2…,N Among them, Wdither_n represents the disturbance injection weight, WCs represents the sampling capacitor weight, Cdither_n represents the disturbance injection capacitor, and Cs represents the sampling capacitor.
5. The comparator threshold correction device for pipeline ADC according to claim 3, characterized in that: The first value is 2^(n-1), 2^(n-1)+1, 2^(n-1)+2, ..., 2^n-1, the second value is 0, 1, 2, ..., 2^(n-1)-1, and the first condition is that the absolute value of Q[5:0] |Q[5:0]| is less than or equal to 9; When the first signal is 2^(n-1), 2^(n-1)+1, 2^(n-1)+2, …, 2^n-1, and the absolute value of Q[5:0] |Q[5:0]| is less than or equal to 9, the first accumulator accumulates (10+|Q[5:0]|); When the first signal is 0, 1, 2, ..., 2^(n-1)-1, and the absolute value of Q[5:0] |Q[5:0]| is less than or equal to 9, the second accumulator accumulates (-10+|Q[5:0]|).
6. The comparator threshold correction device for pipeline ADC according to claim 5, characterized in that: The error data calculation module further includes a first counter and a second counter. When the first counter counts to 2^(N-1) and the second counter counts to 2^(N-1)-1, it is regarded as an error accumulation cycle.
7. The comparator threshold correction device of the pipeline ADC according to claim 1, characterized in that: The first signal is obtained by injecting a pseudo-random sequence into the first comparator.
8. The comparator threshold correction device for pipeline ADC according to claim 1, characterized in that: The first stage comparator comprises: a first disturbance DAC, converting the pseudo-random sequence generated by the pseudo-random generator into a first analog signal; A first summing unit, adding the analog input signal to the first analog signal to obtain a second analog signal; A first-stage ADC, connected to the first summing unit, converting the second analog signal into a digital code; A first-stage DAC, connected to the first-stage ADC, converts the digital code into a third analog signal; a second disturbance DAC, converting the pseudo-random sequence generated by the pseudo-random generator into a fourth analog signal; a second summing unit, adding the first analog signal and the fourth analog signal, and then subtracting the sum from the third analog signal; The amplifying unit amplifies the output signal of the second summing unit and outputs a first signal.
9. The comparator threshold correction device of the pipeline ADC according to claim 1, characterized in that: The correction device also includes: A state machine is connected to the comparison module, and the state machine jumps and outputs a control code according to an output result of the comparison module, so as to control the size of the reference current in the first-stage comparator through the control code.
10. The comparator threshold correction device of the pipeline ADC according to claim 9, characterized in that: The adjustment module reduces the reference current when the period error accumulation data of the first error accumulation cycle of two adjacent error accumulation cycles is greater than the period error accumulation data of the second error accumulation cycle of two adjacent error accumulation cycles; And the reference current is increased when the period error accumulation data of the first error accumulation period between two adjacent error accumulation periods is less than or equal to the period error accumulation data of the second error accumulation period between two adjacent error accumulation periods.