Output negative voltage protection circuit applied to N-type power device linear voltage regulator

Abstract

The invention provides an output negative voltage protection circuit applied to an N-type power device linear voltage regulator. The output negative voltage protection circuit comprises a voltage comparator, a current comparator, an error amplifier, a buffer driver, a power device MP, a resistor R1, a resistor R2, a resistor Rload and a capacitor Cout. The method comprises the following steps: acquiring a voltage difference between an S-pole output voltage Vout of a power device MP and a reference voltage Vos through a voltage comparator, converting the voltage difference into a current signal Ieg, and comparing the current signal Ieg with a reference current Ios through a current comparator to generate a current signal Ilim; adjusting the output of an error amplifier according to the current signal Ilim, and dynamically adjusting the G pole voltage Vgate of the power device MP; when the output voltage Vout is lower than the reference voltage Vos, the G pole voltage Vgate is pulled down to turn off the power device MP through the current signal Ilim, and protection of the power device MP is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power management, more particularly, to an output negative voltage protection circuit applied to an N-type power device linear regulator. BACKGROUND

[0002] As an important component in power management integrated circuits, low dropout linear regulators (LDOs) have been widely used in mobile devices, Internet of Things terminals and portable electronic products due to their low noise, high power supply rejection ratio and fast transient response. The over-current protection circuit is an indispensable key module in LDO design, and its performance directly affects the reliability and safety of the LDO. In the following, the development history, technical characteristics and research status of LDO over-current protection technology will be systematically combed from three aspects of constant over-current protection, foldback over-current protection and adjustable protection circuit.

[0003] Constant over-current protection is the most basic protection mechanism in LDO, and its core principle is to limit the current to a fixed value to prevent the power tube from being damaged when the output current exceeds the preset threshold. Early constant over-current protection circuits mostly use the architecture of resistance sampling combined with voltage comparators, which realizes the protection function by comparing the voltage signal converted from the current signal with the reference voltage. Although this scheme is simple in structure, it has two main shortcomings: first, the sampling resistance leads to large discreteness of the protection point due to process fluctuations; second, the voltage comparator increases the circuit complexity and power consumption.

[0004] Foldback over-current protection technology is developed to solve the problem that the power tube is easily damaged by overheating when working in a large current state for a long time under constant protection mode. Its core feature is that when over-current is detected, not only is the current limited, but the current limit value is also further reduced as the output voltage drops, thereby significantly reducing power dissipation.

[0005] With the diversification of application scenarios, the flexibility and intelligence of LDO over-current protection are increasingly required. The latest research trend is to develop protection circuits that are parameter-adjustable and adaptive to the environment. Some schemes achieve flexible configuration of protection parameters through external resistance networks, allowing the same LDO to adapt to different load requirements. More advanced intelligent protection circuits begin to introduce digital control interfaces. These circuits configure protection parameters through registers, and can even dynamically adjust protection thresholds according to working states.

[0006] There are many patents on LDO over-current protection in the market, and the following lists several typical patents related to the present application.

[0007] In patent CN118585026A, by setting an automatic clamping module at the output end of the error amplifier of the traditional LDO circuit, when the LDO circuit works in a high temperature state, the automatic clamping module outputs a clamping voltage to suppress the trend of the error amplifier increasing the control signal of the power transistor at high temperature, thereby avoiding the problem of increased current of the LDO circuit power transistor due to temperature rise.

[0008] In patent CN119597101A, according to the input reference voltage of the first operational amplifier, an output voltage is generated and a detection current and a feedback voltage are provided; according to the proposed overcurrent protection loop, the detection current is introduced to raise the positive terminal voltage of the second operational amplifier, and when the positive terminal voltage is detected to be higher than the feedback voltage, the overcurrent protection opens the switch current mirror, which controls the output voltage of the first operational amplifier, so that the output current of the first operational amplifier is accurately copied to the output of the LDO loop.

[0009] In patent CN119376478A, an overcurrent protection circuit applicable to low-voltage input LDO is proposed. In this invention, the output tube and the sampling tube are at the same potential during sampling, which has the characteristics of accurate sampling and easy design, and has certain universality in circuit design.

[0010] For many overcurrent protection technologies, most of them only consider the case when the output voltage of LDO is positive. However, for NMOS LDO, when the output voltage decreases to negative due to changes in external load environment, most overcurrent protection circuits have failed at this time, the gate-source voltage of NMOS power tube further increases, resulting in high power dissipation of power tube, which may cause the chip to work abnormally, and even cause circuit damage.

[0011] Taking the widely used foldback current protection in the current market as an example, its output voltage and load current curve is as shown in Figure 1 It can be seen that when the load current reaches the current limiting threshold, it will not continue to increase, and the output voltage will start to decrease. But the lower the output voltage, the more power the internal output power device dissipates, which has the risk of overheating damage. Therefore, when VOUT further decreases, the threshold of current limiting will gradually decrease to limit the internal dissipation power. Until Vout decreases to 0V, the current limiting threshold also decreases to a level greater than 0 but less than the initial threshold. In this way, the current limiting value is folded back.

[0012] The current limiting protection in the known such voltage stabilizers only considers the case where the output is 0, but in practice there are cases where the output is negative. At this time, if the general current limiting protection strategy is represented by an equivalent foldback graph, the following situations may occur.

[0013] AsFigure 2 As shown, when VOUT is less than 0, the output current is reduced to 0, but this strategy can cause the abnormal state to disappear and cannot automatically restore VOUT.

[0014] As shown, when VOUT is less than 0, the output current is reduced to 0, but this strategy can cause the abnormal state to disappear and cannot automatically restore VOUT. Figure 3 As shown, when VOUT is less than 0, the output current is reduced to 0, but this strategy can cause the abnormal state to disappear and cannot automatically restore VOUT.

[0015] As shown, when VOUT is less than 0, the output current is reduced to 0, but this strategy can cause the abnormal state to disappear and cannot automatically restore VOUT. Figure 4 As shown, when VOUT is less than 0, the output current is reduced to 0, but this strategy can cause the abnormal state to disappear and cannot automatically restore VOUT.

[0016] Therefore, how to design a dynamic adjustment of the current limiting protection mechanism, real-time monitoring of output voltage and current, and according to the load change flexible adjustment protection strategy is an urgent problem to be solved. SUMMARY

[0017] The purpose of the present application is to solve the problem of output negative voltage protection of linear voltage regulator, and propose an output negative voltage protection circuit applied to N-type power device linear voltage regulator.

[0018] The technical scheme of the present application is: The present application provides an output negative voltage protection circuit applied to N-type power device linear voltage regulator, which comprises a voltage comparator, a current comparator, an error amplifier, a buffer driver, a power device MP, resistors R1, R2 and Rload, and a capacitor Cout. The S pole of the power device MP is connected to the ground through the series connection of resistors R1 and R2, the series connection of resistors R1 and R2 is connected to resistor Rload and capacitor Cout, the connection point of the series connection of resistors R1 and R2 is connected to the inverting input terminal of the error amplifier, the non-inverting input terminal of the error amplifier is connected to reference voltage Vref, the output of the error amplifier is connected to the G pole of the power device MP through the series connection of the buffer driver, the D pole of the power device MP is connected to input voltage Vin, the S pole of the power device MP is also connected to the inverting input terminal of the voltage comparator, the non-inverting input terminal of the voltage comparator is connected to reference voltage Vos, the output terminal of the voltage comparator is connected to the non-inverting input terminal of the current comparator, the inverting input terminal of the current comparator is connected to reference current Ios, and the output terminal of the current comparator is connected to the connection point of the error amplifier and the buffer driver. The voltage difference between the S pole output voltage Vout of the power device MP and the reference voltage Vos is obtained by the voltage comparator and converted into a current signal Ineg, and the current signal Ineg is compared with the reference current Ios by the current comparator to generate a current signal Ilim. The output of the error amplifier is adjusted according to the current signal Ilim, and the G-pole voltage Vgate of the power device MP is dynamically adjusted; when the output voltage Vout is lower than the reference voltage Vos, the G-pole voltage Vgate is pulled down to the off state of the power device MP by the current signal Ilim, so as to realize the protection of the power device MP.

[0019] Further, the voltage comparator adopts an operational transconductance amplifier OTA.

[0020] Further, the voltage comparator comprises transistors M1-M6, M8-M9 and resistors R3, R4, the gate of the transistor M2 is connected to the reference voltage Vos as the non-inverting input terminal of the voltage comparator, the gate of the transistor M1 is connected to the output voltage Vout as the inverting input terminal of the voltage comparator, the drain of the transistor M1 and the drain of the transistor M2 are connected to one end of the resistor R3 and one end of the resistor R4 respectively and then to the ground, the source of the transistor M1 and the source of the transistor M2 are connected in parallel and connected to the drain of the transistor M3, the drain of the transistor M1 is connected to the source of the transistor M5, the drain of the transistor M2 is connected to the source of the transistor M6, the gates of the transistors M5 and M6 are connected, the drain of the transistor M5 is connected to the drain of the transistor M4, the drain of the transistor M6 is connected to the drain of the transistor M8, the gate of the transistor M5 is connected to the drain of the transistor M5, the gate of the transistor M3 is connected to the gate of the transistor M4, the gate of the transistor M8 is connected to the gate of the transistor M9, the gate of the transistor M8 is connected to the drain of the transistor M8, the source of the transistors M3, M4, M8 and M9 are connected in parallel and connected to the power supply VDD, and the drain of the transistor M9 outputs the current signal Ineg as the input signal of the non-inverting terminal of the current comparator according to the result of the voltage comparison.

[0021] Further, the current comparator comprises transistors M9-M15, the gate of the transistor M15 is connected to the bias voltage Vbn, the current IOS generated at the drain of the transistor M15 is taken as the input signal of the inverting terminal of the current comparator, the drains of the transistors M9 and M15 are connected for current comparison, the difference between the two flows into the drain of the transistor M10, the drain of the transistor M10 is connected to the gate of the transistor M10, the gate of the transistor M10 is connected to the gate of the transistor M11, the sources of the transistors M15, M10 and M11 are connected to the ground, the drain of the transistor M11 is connected to the drain and the gate of the transistor M12, the gates of the transistors M12 and M13 are connected, the sources of the transistors M12 and M13 are connected and connected to the power supply VDD, and the drain of the transistor M13 generates the current signal Ilim as the output of the current comparator and connects the error amplifier and the buffer driver.

[0022] Further, the G-pole voltage Vgate of the power device MP is dynamically adjusted, comprising: The output voltage of the error amplifier is acquired, the adjustment direction and amplitude of the G electrode voltage Vgate of the power device MP are determined based on the change of the output voltage, and the G electrode voltage Vgate of the power device MP is dynamically reduced; the reduction of the G electrode voltage Vgate of the power device MP is inversely proportional to the increase of the current signal Ilim.

[0023] An output negative voltage protection circuit applied to an N-type power device linear voltage regulator includes a voltage comparator, a current comparator, an error amplifier, a current limiting module, a subtractor, a buffer driver, a power device MP, resistors R1, R2, Rload, and a capacitor Cout. The S electrode of the power device MP is connected to the ground through the series connection of resistors R1 and R2, the series connection of resistors R1 and R2 is connected to the resistor Rload and the capacitor Cout in parallel, the connection point of the series connection of resistors R1 and R2 is connected to the inverting input terminal of the error amplifier, the non-inverting input terminal of the error amplifier is connected to the reference voltage Vref, the output of the error amplifier is connected to the buffer driver in series and then to the G electrode of the power device MP, the D electrode of the power device MP is connected to the input voltage Vin, the S electrode of the power device MP is connected to the non-inverting input terminal of the voltage comparator and the non-inverting input terminal of the current limiting module, the non-inverting input terminal of the voltage comparator is connected to the reference voltage Vos, the output of the voltage comparator is connected to the non-inverting input terminal of the current comparator, the non-inverting input terminal of the current comparator is connected to the reference current Ios, the output of the current comparator is connected to the first input terminal of the subtractor, the second input terminal of the subtractor is configured to receive a current limiting threshold signal, the output of the subtractor is connected to the non-inverting input terminal of the current limiting module, and the output of the current limiting module is connected to the connection point of the error amplifier and the buffer driver. The voltage difference between the S electrode output voltage Vout of the power device MP and the reference voltage Vos is acquired by the voltage comparator and converted into a current signal Ineg, and the current signal Ineg is compared with the reference current IOS by the current comparator to generate a current signal Ilim. The current limiting threshold is reduced according to the current signal Ilim to adjust the output of the error amplifier and dynamically adjust the G electrode voltage Vgate of the power device MP; when the output voltage Vout is lower than the reference voltage Vos, the current signal Ilim generated by reducing the threshold of the current limiting module causes the current limiting module to pull down the G electrode voltage Vgate to turn off the power device MP, thereby protecting the power device MP.

[0024] Further, the voltage comparator uses an operational transconductance amplifier OTA.

[0025] Further, the voltage comparator comprises transistors M1-M6, M8-M9 and resistors R3, R4, the gate of the transistor M2 is connected with a reference voltage Vos as the non-inverting input terminal of the voltage comparator, the gate of the transistor M1 is connected with the output voltage Vout as the inverting input terminal of the voltage comparator, the drain of the transistors M1, M2 is connected with one end of the resistor R3 and R4 respectively and then grounded, the source of the transistors M1, M2 is connected in parallel and connected with the drain of the transistor M3, the drain of the transistors M1, M2 is connected with the source of the transistors M5, M6 respectively, the gates of the transistors M5, M6 are connected, the drain of the transistors M5, M6 is connected with the drain of the transistors M4, M8 respectively, the gate and the drain of the transistor M5 are connected, the gate of the transistors M3 and M4 are connected, the gate of the transistors M8 and M9 are connected, the gate and the drain of the transistor M8 are connected, the source of the transistors M3, M4, M8, M9 are connected in parallel and connected with the power supply VDD, the drain of the transistor M9 outputs the current signal Ineg as the input signal of the non-inverting terminal of the current comparator according to the result of the voltage comparison.

[0026] Further, the current comparator comprises transistors M9-M15, the gate of the transistor M15 is connected with a bias voltage Vbn, the current IOS generated at the drain of the transistor M15 is the input signal of the inverting terminal of the current comparator, the drain of the transistors M9 and M15 are connected for current comparison, the difference current of the two flows into the drain of the transistor M10, the drain and the gate of the transistor M10 are connected, the gate of the transistor M10 is connected with the gate of the transistor M11, the source of the transistors M15, M10, M11 are grounded, the drain of the transistor M11 is connected with the drain and the gate of the transistor M12, the gates of the transistors M12, M13 are connected, the sources of the transistors M12, M13 are connected in parallel and connected with the power supply VDD, the drain of the transistor M13 generates the current signal Ilim as the output of the current comparator and connected with the connection point of the error amplifier and the buffer driver.

[0027] Further, the G-pole voltage Vgate of the dynamic adjustment power device MP comprises: The output voltage of the error amplifier is acquired, the adjustment direction and the amplitude of the G-pole voltage Vgate of the power device MP are determined based on the change of the output voltage, the G-pole voltage Vgate of the power device MP is dynamically reduced, and the reduction of the G-pole voltage Vgate of the power device MP is inversely proportional to the increase of the current signal Ilim.

[0028] The present application has the following advantages: The application discloses a current-limiting protection method for a linear voltage regulator, which comprises the following steps: comparing an output voltage with a reference voltage to generate a difference current signal, comparing the difference current signal with a reference current to generate a current-limiting control current signal, gradually reducing an error amplifier output voltage according to the current-limiting control current signal Ilim when the difference current Ineg exceeds the reference current Ios, adjusting the on degree of a power device, dynamically limiting the output current capacity, and protecting the device safety. Meanwhile, the current-limiting control current Ilim is continuously updated to ensure that the output current gradually approaches zero and record the change trend for optimizing the protection strategy.

[0029] The current-limiting return curve generated by the method of the application reflects the dynamic protection relationship between the output voltage and the current, realizes the accurate current-limiting protection of the linear voltage regulator under overload and short circuit conditions, and effectively improves the reliability and safety of the voltage regulator. Figure 8

[0030] Other features and advantages of the application will be described in detail in the following specific embodiment part. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout the several views, and in which:

[0032] Figure 1 A voltage and load current curve graph is shown when the output voltage is less than 0 in the background art.

[0033] Figure 2 A voltage and load current curve graph is shown when the output current is reduced to 0 when VOUT is less than 0 in the background art.

[0034] Figure 3 A voltage and load current curve graph is shown when the output current is reduced to 0 when VOUT is less than 0 in the background art.

[0035] Figure 4 A voltage and load current curve graph is shown when the output current is continuously increased when the original current-limiting module cannot normally work when VOUT is less than 0 in the background art.

[0036] Figure 5 A voltage and load current curve graph is shown when the output current is continuously increased when the original current-limiting module cannot normally work when VOUT is less than 0 in the background art.

[0037] Figure 6 A voltage and load current curve graph is shown when the output current is continuously increased when the original current-limiting module cannot normally work when VOUT is less than 0 in the background art.

[0038] Figure 7 ​A circuit diagram of the voltage comparator and the current comparator in the negative voltage protection circuit of the present application is shown.

[0039] Figure 8 A current protection output voltage and load current curve diagram when the negative voltage protection circuit of the present application is applied is shown. DETAILED DESCRIPTION

[0040] The preferred embodiments of the present application will be described in more detail by referring to the attached drawings. Although the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein.

[0041] Figure 5 One of the output negative voltage protection circuit diagrams of the present application applied to an N-type power device linear voltage regulator is shown.

[0042] As shown in Figure 5 the present application provides an output negative voltage protection circuit applied to an N-type power device linear voltage regulator, which comprises a voltage comparator, a current comparator, an error amplifier, a buffer driver, a power device MP, resistors R1, R2, Rload, and a capacitor Cout; the S pole of the power device MP is connected to the ground through the series connection of resistors R1 and R2, the series connection of resistors R1 and R2 is connected to the resistor Rload and the capacitor Cout in parallel, the connection point of the series connection of resistors R1 and R2 is connected to the inverting input terminal of the error amplifier, the non-inverting input terminal of the error amplifier is connected to the reference voltage Vref, the output of the error amplifier is connected to the G pole of the power device MP through the buffer driver, and the D pole of the power device MP is connected to the input voltage Vin; the S pole of the power device MP is also connected to the inverting input terminal of the voltage comparator, the non-inverting input terminal of the voltage comparator is connected to the reference voltage Vos, the output of the voltage comparator is connected to the non-inverting input terminal of the current comparator, the inverting input terminal of the current comparator is connected to the reference current Ios, and the output of the current comparator is connected to the connection point of the error amplifier and the buffer driver; the voltage difference between the S pole output voltage Vout of the power device MP and the reference voltage Vos is obtained by the voltage comparator and converted into a current signal Ineg, and the current signal Ineg is compared with the reference current Ios by the current comparator to generate a current signal Ilim; the output of the error amplifier is adjusted according to the current signal Ilim, and the G pole voltage Vgate of the power device MP is dynamically adjusted; when the output voltage Vout is lower than the reference voltage Vos, the G pole voltage Vgate is pulled down to the off state of the power device MP by the current signal Ilim, thereby realizing the protection of the power device MP.

[0043] In the embodiment, the main principle of the negative voltage protection is to compare the output voltage Vout and a reference voltage Vos, and convert the voltage difference into current Ineg through an OTA, the reference voltage Vos can be adjusted to GND voltage or other voltage according to the requirement. Ineg is compared with a reference current Ios and outputs a current signal Ilim. When Ineg is less than Ios, the output current ILIM is 0; when Ineg is greater than Ios, Ilim outputs the difference between the two currents. When the output voltage is continuously lower than the set reference voltage Vos, Ilim continuously increases, the current gradually pulls down the output of the error amplifier, and then reduces the G pole voltage Vgate of the output power device MP, until it is pulled to Vout or lower, and the power device is completely turned off, and no conduction current is achieved, and the protection target is achieved.

[0044] The equivalent current limiting foldback graph of the current limiting strategy is shown in the figure. Figure 8 When the output voltage is less than 0, the current limiting threshold when the output voltage is equal to 0 is maintained or slightly changed. When the output voltage is further reduced to a certain set threshold, the output current capability of the voltage regulator is further reduced until 0.

[0045] Figure 6 The application of the output negative voltage protection circuit of the N-type power device linear voltage regulator is shown in the second circuit diagram.

[0046] The application of the output negative voltage protection circuit of the N-type power device linear voltage regulator is shown in the second circuit diagram. Figure 6 As shown in the figure, Ilim achieves the protection target by gradually reducing the current limiting threshold of the original LDO current limiting protection function, and the circuit includes a voltage comparator, a current comparator, an error amplifier, a current limiting module, a subtractor, a buffer driver, a power device MP, resistors R1, R2 and Rload, and a capacitor Cout. The S pole of the power device MP is connected in series with resistors R1 and R2, and the connection point of the resistors R1 and R2 is connected to the inverting input terminal of an error amplifier, the non-inverting input terminal of the error amplifier is connected to a reference voltage Vref, the output of the error amplifier is connected in series with a buffer driver, and the G pole of the power device MP is connected to the output of the buffer driver, and the D pole of the power device MP is connected to an input voltage Vin; the S pole of the power device MP is connected to the non-inverting input terminal of a voltage comparator and the non-inverting input terminal of a current limiting module, the non-inverting input terminal of the voltage comparator is connected to a reference voltage Vos, the output of the voltage comparator is connected to the non-inverting input terminal of a current comparator, the non-inverting input terminal of the current comparator is connected to a reference current Ios, the output of the current comparator is connected to the first input terminal of a subtractor, the second input terminal of the subtractor is configured to receive a current limiting threshold signal, the output of the subtractor is connected to the non-inverting input terminal of the current limiting module, and the output of the current limiting module is connected to the connection point of the error amplifier and the buffer driver. The voltage difference between the S pole output voltage Vout of the power device MP and the reference voltage Vos is obtained by the voltage comparator and converted into a current signal Ineg, and the current signal Ineg is compared with the reference current IOS by the current comparator to generate a current signal Ilim. The current limiting threshold is reduced according to the current signal Ilim to adjust the output of the error amplifier and dynamically adjust the G pole voltage Vgate of the power device MP; when the output voltage Vout is lower than the reference voltage Vos, the current signal Ilim generated by reducing the threshold of the current limiting module causes the current limiting module to pull down the G pole voltage Vgate to turn off the power device MP, thereby protecting the power device MP.

[0047] In the embodiment, the output negative voltage protection circuit applied to the N-type power device linear voltage regulator has the following main advantages Figure 8 As shown in the figure, which can be seen from the current limiting foldback diagram thereof. The output current capacity can be maintained within a certain negative voltage range, and the output current capacity can be gradually reduced to 0 after the output negative voltage exceeds the expected value, thereby ensuring the safety of related devices and avoiding damage.

[0048] Figure 7 A circuit diagram of the voltage comparator and the current comparator in the negative voltage protection circuit is shown.

[0049] The voltage comparator comprises transistors M1-M6, M8-M9 and resistors R3, R4, the gate of the transistor M2 is connected to a reference voltage Vos as the non-inverting input of the voltage comparator, the gate of the transistor M1 is connected to an output voltage Vout as the inverting input of the voltage comparator, the drains of the transistors M1, M2 are connected to one end of the resistors R3, R4 respectively and then to ground, the sources of the transistors M1, M2 are connected in parallel and to the drain of the transistor M3, the drains of the transistors M1, M2 are connected to the sources of the transistors M5, M6 respectively, the gates of the transistors M5, M6 are connected, and the drains of the transistors M5, M6 are connected to the drains of the transistors M4, M8 respectively, the gate and the drain of the transistor M5 are connected, the gates of the transistors M3 and M4 are connected, the gates of M8 and M9 are connected, the gate and the drain of the transistor M8 are connected, the sources of the transistors M3, M4, M8, M9 are connected in parallel and to a power supply VDD, and the drain of the transistor M9 outputs a current signal Ineg as the non-inverting input signal of the current comparator according to the result of the voltage comparison.

[0050] The current comparator comprises transistors M9-M15, the gate of the transistor M15 is connected to a bias voltage Vbn, the current IOS generated at the drain of the transistor M15 is the input signal of the inverting terminal of the current comparator, the drains of the transistors M9 and M15 are connected for current comparison, the difference between the two flows into the drain of the transistor M10, the drain and the gate of the transistor M10 are connected, and the gate of the transistor M10 is connected to the gate of the transistor M11, the sources of the transistors M15, M10, M11 are connected to ground, the drain of the transistor M11 is connected to the drain and the gate of the transistor M12, the gates of the transistors M12, M13 are connected, the sources of the transistors M12, M13 are connected in parallel and to a power supply VDD, and the drain of the transistor M13 generates a current signal Ilim as the output of the current comparator and connects to the connection point of the error amplifier and the buffer driver.

[0051] In the present embodiment, it is considered that when Ineg=Ios, the negative voltage protection circuit starts to intervene. The value of Vos is generally determined by the desired value of the specific application and is provided by other modules. For simplicity, Vos can be directly connected to ground.

[0052] The above has described the embodiments of the present application, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. An output negative voltage protection circuit for an N-type power device linear regulator, characterized in that: It includes a voltage comparator, a current comparator, an error amplifier, a buffer driver, a power device MP, resistors R1, R2, Rload and a capacitor Cout; The S-pole of the power device MP is connected to ground via series resistors R1 and R2, which are then connected in parallel to a resistor Rload and a capacitor Cout. The connection point of the series resistors R1 and R2 is connected to the inverting input of an error amplifier, the non-inverting input of the error amplifier is connected to a reference voltage Vref, the output of the error amplifier is connected in series to a buffer driver, and then to the G-pole of the power device MP, while the D-pole of the power device MP is connected to an input voltage Vin. The S-pole of the power device MP is also connected to the inverting input of a voltage comparator, the non-inverting input of the voltage comparator is connected to a reference voltage Vos, the output of the voltage comparator is connected to the non-inverting input of a current comparator, the inverting input of the current comparator is connected to a reference current Ios, and the output of the current comparator is connected to the connection point between the error amplifier and the buffer driver. The voltage difference between the S-pole output voltage Vout of the power device MP and the reference voltage Vos is obtained by a voltage comparator, and converted into a current signal Ineg. The current signal Ineg is compared with the reference current Ios by a current comparator to generate a current signal Ilim; The output of the error amplifier is adjusted according to the current signal Ilim, and the G-pole voltage Vgate of the power device MP is dynamically adjusted. When the output voltage Vout is lower than the reference voltage Vos, the G-pole voltage Vgate is pulled down to turn off the power device MP through the current signal Ilim, thereby protecting the power device MP.

2. The output negative voltage protection circuit for an N-type power device linear regulator according to claim 1, wherein: The voltage comparator adopts an operational transconductance amplifier OTA.

3. The output negative voltage protection circuit for an N-type power device linear regulator according to claim 1, wherein: The voltage comparator includes transistors M1-M6, M8-M9 and resistors R3 and R4. The gate of the transistor M2 is connected to the reference voltage Vos as the non-inverting input terminal of the voltage comparator. The gate of the transistor M1 is connected to the output voltage Vout as the inverting input terminal of the voltage comparator. The drains of the transistors M1 and M2 are connected in series with one end of the resistors R3 and R4 respectively and then grounded. The sources of the transistors M1 and M2 are connected in parallel and connected to the drain of the transistor M3. The drains of the transistors M1 and M2 are connected to the sources of the transistors M5 and M6 respectively. The gates of the transistors M5 and M6 are connected, and the drains of the transistors M5 and M6 are connected to the drains of the transistors M4 and M8 respectively. The gate and drain of the transistor M5 are connected, the gates of the transistors M3 and M4 are connected, the gates of M8 and M9 are connected, the gate and drain of the transistor M8 are connected, the sources of the transistors M3, M4, M8, and M9 are connected in parallel and connected to the power supply VDD, and the drain of the transistor M9 outputs a current signal Ineg as the non-inverting input signal of the current comparator according to the result of voltage comparison.

4. The output negative voltage protection circuit for an N-type power device linear regulator according to claim 1, wherein: The current comparator includes transistors M9-M15. The gate of transistor M15 is connected to a bias voltage Vbn. The current IOS generated at the drain of transistor M15 serves as an input signal to the inverting terminal of the current comparator. The drains of transistors M9 and M15 are connected for current comparison, and the difference between the two flows into the drain of transistor M10. The drain and gate of transistor M10 are connected, and the gate of transistor M10 is connected to the gate of transistor M11. The sources of transistors M15, M10, and M11 are grounded. The drain of transistor M11 is connected to the drain and gate of transistor M12. The gates of transistors M12 and M13 are connected. The sources of transistors M12 and M13 are connected and connected to a power supply VDD. The drain of transistor M13, as the output of the current comparator, generates a current signal Ilim, which is connected to the connection point of the error amplifier and the buffer driver.

5. The output negative voltage protection circuit for an N-type power device linear regulator according to claim 1, wherein: The dynamically adjusting the G-pole voltage Vgate of the power device MP includes: The output voltage of the error amplifier is obtained, and the adjustment direction and amplitude of the G-pole voltage Vgate of the power device MP are determined based on the change of the output voltage, so as to dynamically reduce the G-pole voltage Vgate of the power device MP; the reduction of the G-pole voltage Vgate of the power device MP is inversely proportional to the increase of the current signal Ilim.

6. An output negative voltage protection circuit for an N-type power device linear regulator, characterized in that: It includes a voltage comparator, a current comparator, an error amplifier, a current limiting module, a subtractor, a buffer driver, a power device MP, resistors R1, R2, Rload and a capacitor Cout; The S-pole of the power device MP is connected to ground via series resistors R1 and R2, which are then connected in parallel to a resistor Rload and a capacitor Cout. The connection point of the series resistors R1 and R2 is connected to the inverting input of an error amplifier, the non-inverting input of the error amplifier is connected to a reference voltage Vref, the output of the error amplifier is connected in series to a buffer driver, and then to the G-pole of the power device MP, while the D-pole of the power device MP is connected to an input voltage Vin. The S-pole of the power device MP is connected to the inverting input of a voltage comparator and the non-inverting input of a current limiting module, the non-inverting input of the voltage comparator is connected to a reference voltage Vos, the output of the voltage comparator is connected to the non-inverting input of a current comparator, the inverting input of the current comparator is connected to a reference current Ios, the output of the current comparator is connected to a first input of a subtractor, the second input of the subtractor is configured to receive a current limiting threshold signal, the output of the subtractor is connected to the inverting input of the current limiting module, and the output of the current limiting module is connected to the connection point of the error amplifier and the buffer driver. The voltage difference between the S-pole output voltage Vout of the power device MP and the reference voltage Vos is obtained by a voltage comparator, and converted into a current signal Ineg. The current signal Ineg is compared with the reference current IOS by a current comparator to generate a current signal Ilim; The current limiting threshold is lowered according to the current signal Ilim to adjust the output of the error amplifier and dynamically adjust the G-pole voltage Vgate of the power device MP. When the output voltage Vout is lower than the reference voltage Vos, the generated current signal Ilim reduces the threshold of the current limiting module, causing the current limiting module to pull the G-pole voltage Vgate down to the point where the power device MP is turned off, thereby protecting the power device MP.

7. The output negative voltage protection circuit for an N-type power device linear regulator according to claim 6, wherein: The voltage comparator adopts an operational transconductance amplifier OTA.

8. The output negative voltage protection circuit for an N-type power device linear regulator according to claim 6, wherein: The voltage comparator includes transistors M1-M6, M8-M9 and resistors R3 and R4. The gate of the transistor M2 is connected to the reference voltage Vos as the non-inverting input terminal of the voltage comparator. The gate of the transistor M1 is connected to the output voltage Vout as the inverting input terminal of the voltage comparator. The drains of the transistors M1 and M2 are connected in series with one end of the resistors R3 and R4 respectively and then grounded. The sources of the transistors M1 and M2 are connected in parallel and connected to the drain of the transistor M3. The drains of the transistors M1 and M2 are connected to the sources of the transistors M5 and M6 respectively. The gates of the transistors M5 and M6 are connected, and the drains of the transistors M5 and M6 are connected to the drains of the transistors M4 and M8 respectively. The gate and drain of the transistor M5 are connected, the gates of the transistors M3 and M4 are connected, the gates of M8 and M9 are connected, the gate and drain of the transistor M8 are connected, the sources of the transistors M3, M4, M8, and M9 are connected in parallel and connected to the power supply VDD, and the drain of the transistor M9 outputs a current signal Ineg as the non-inverting input signal of the current comparator according to the result of voltage comparison.

9. The output negative voltage protection circuit for an N-type power device linear regulator according to claim 6, wherein: The current comparator includes transistors M9-M15. The gate of transistor M15 is connected to a bias voltage Vbn. The current IOS generated at the drain of transistor M15 serves as an input signal to the inverting terminal of the current comparator. The drains of transistors M9 and M15 are connected for current comparison, and the difference between the two flows into the drain of transistor M10. The drain and gate of transistor M10 are connected, and the gate of transistor M10 is connected to the gate of transistor M11. The sources of transistors M15, M10, and M11 are grounded. The drain of transistor M11 is connected to the drain and gate of transistor M12. The gates of transistors M12 and M13 are connected. The sources of transistors M12 and M13 are connected and connected to a power supply VDD. The drain of transistor M13, as the output of the current comparator, generates a current signal Ilim, which is connected to the connection point of the error amplifier and the buffer driver.

10. The output negative voltage protection circuit for an N-type power device linear regulator according to claim 6, wherein: The dynamically adjusting the G-pole voltage Vgate of the power device MP includes: The output voltage of the error amplifier is obtained, and the adjustment direction and amplitude of the G-pole voltage Vgate of the power device MP are determined based on the change of the output voltage, so as to dynamically reduce the G-pole voltage Vgate of the power device MP; the reduction of the G-pole voltage Vgate of the power device MP is inversely proportional to the increase of the current signal Ilim.

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