Semiconductor element with vertical transistor and preparation method thereof

Abstract

The invention provides a semiconductor element and a preparation method of the semiconductor element. The semiconductor element may include a first vertical transistor. The first vertical transistor may include a first channel region. The first vertical transistor may also include a first word line surrounding the first channel region. The first vertical transistor may also include a first bit line dielectric layer between the first channel region and the first word line. The first vertical transistor may also include a first conductive pad between the first bit line dielectric layer and the first word line.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 18 / 399,798 (i.e., the priority date is "December 29, 2023"), the content of which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to a semiconductor device and a method of manufacturing the same. In particular, it relates to a semiconductor device including one or more vertical transistors and a method of manufacturing the same. Background Art

[0003] A dynamic random access memory (DRAM) device is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, DRAMs are arranged in a square array of one capacitor and one transistor per cell. A vertical transistor has been developed for 4F 2 DRAM cells, where F represents the lithographic minimum feature size or critical dimension (CD). However, recently, with the continuous reduction of the word line pitch and word line size, DRAM manufacturers are facing a huge challenge in reducing the memory cell area. For example, the resistance value of the word line can increase as the word line width decreases. Therefore, a novel structure is needed to reduce the word line resistance value.

[0004] The above "Prior Art" description only provides background art and does not admit that the above "Prior Art" description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above "Prior Art" should not be taken as any part of this case. Summary of the Invention

[0005] An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first vertical transistor. The first vertical transistor may include a first channel region. The first vertical transistor may further include a first word line surrounding the first channel region. The first vertical transistor may also include a first word line dielectric layer located between the first channel region and the first word line. The first vertical transistor may further include a first conductive pad located between the first word line dielectric layer and the first word line.

[0006] Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first vertical transistor and a first barrier layer. The first vertical transistor may include a first channel region. The first vertical transistor may further include a first word line surrounding the first channel region. The first vertical transistor may also include a first word line dielectric layer surrounding the first word line. The first vertical transistor may further include a first conductive pad surrounding the first word line. The first barrier layer is located on each sidewall of the first word line and directly contacts the first conductive pad.

[0007] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The manufacturing method may include providing a capacitor on a substrate. The manufacturing method may further include forming a vertical transistor above the capacitor, where the vertical transistor includes: a channel region; a word line surrounding the channel region; a word line dielectric layer located between the channel region and the word line; and a conductive pad located between the word line dielectric layer and the word line.

[0008] In the semiconductor device, through the design of the conductive pad, the width of the narrow region of the word line is directly connected and electrically connected to the conductive pad. That is, the distance between the barrier layer and the word line dielectric layer (e.g., the narrow region of the word line) is increased. Therefore, the conductive pad and the word line can be used together as a composite word line with an increased width, thus reducing the word line resistance value, which is beneficial to the electrical function of the semiconductor device.

[0009] The technical features and advantages of the present disclosure have been outlined quite extensively above so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those of ordinary skill in the art to which the present disclosure pertains should understand that the concepts disclosed below and the specific embodiments can be quite easily used as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains should also understand that such equivalent structures cannot depart from the spirit and scope of the present disclosure defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and the claims. The present disclosure should also be understood as being associated with the element numbers in the drawings, and the element numbers in the drawings represent similar elements throughout the description.

[0011] Figure 1A is a cross-sectional schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 1B is a top view schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0013] Figure 1C is a three-dimensional schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0014] Figure 2A is a top view schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0015] Figure 2B is a top view schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 3A is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0017] Figure 3B is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0018] Figure 4A is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0019] Figure 4B is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0020] Figure 5A is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0021] Figure 5B is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0022] Figure 6A is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0023] Figure 6B is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0024] Figure 7A is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0025] Figure 7B is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0026] Figure 8A is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0027] Figure 8B is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0028] Figure 9AIt is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0029] Figure 9B It is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0030] Figure 10A It is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0031] Figure 10B It is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0032] Figure 11A It is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0033] Figure 11B It is a schematic diagram illustrating one or more stages of a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0034] Figure 12 It is a process schematic diagram illustrating a method for manufacturing a semiconductor element of some embodiments of the present disclosure.

[0035] Among them, the reference numerals are explained as follows:

[0036] 1: Semiconductor element

[0037] 2A: Semiconductor element

[0038] 2B: Semiconductor element

[0039] 10: Substrate

[0040] 12: Dielectric layer

[0041] 20: Dielectric layer

[0042] 30: Dielectric layer

[0043] 100C: Capacitor

[0044] 100T: Vertical transistor

[0045] 110: Electrode

[0046] 112: Insulating layer

[0047] 114: Electrode

[0048] 120: Channel region

[0049] 120H: Through-hole

[0050] 122: Character line dielectric layer

[0051] 122A: Character line dielectric material

[0052] 126: Conductive pad

[0053] 126A: Conductive pad material

[0054] 128: Barrier layer

[0055] 128a: Portion

[0056] 128b: Portion

[0057] 128e: Edge

[0058] 200C: Capacitor

[0059] 200T: Vertical transistor

[0060] 210: Electrode

[0061] 212: Insulating layer

[0062] 214: Electrode

[0063] 220: Channel region

[0064] 220H: Through-hole

[0065] 222: Character line dielectric layer

[0066] 222A: Character line dielectric material

[0067] 226: Conductive pad

[0068] 226A: Conductive pad material

[0069] 228: Barrier layer

[0070] 300C: Capacitor

[0071] 300T: Vertical transistor

[0072] 310: Electrode

[0073] 312: Insulating layer

[0074] 314: Electrode

[0075] 320: Channel region

[0076] 320H: Through-hole

[0077] 322: Character line dielectric layer

[0078] 322A: Character line dielectric material

[0079] 326: Conductive gasket

[0080] 326A: Conductive gasket material

[0081] 328: Barrier layer

[0082] 1200: Preparation method

[0083] BL1: Bit line

[0084] BL2: Bit line

[0085] BL3: Bit line

[0086] D1: Distance

[0087] D2: Distance

[0088] D3: Distance

[0089] D4: Distance

[0090] DR1: Direction

[0091] DR2: Direction

[0092] H1: Through hole

[0093] H2: Through hole

[0094] H3: Through hole

[0095] OP1: Opening

[0096] OP2: Opening

[0097] OP3: Opening

[0098] P1: Cylinder

[0099] P2: Cylinder

[0100] P3: Cylinder

[0101] S1: Step

[0102] S2: Step

[0103] TR1: Groove

[0104] TR2: Groove

[0105] TR3: Groove

[0106] W1: Width

[0107] W2: Width

[0108] WL1: Character line

[0109] WL2: Word line

[0110] WL3: Word line

[0111] WL1A: Word line material

[0112] WL2A: Word line material

[0113] WL3A: Word line material

[0114] WL1e: Edge Detailed implementation manners

[0115] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, when it is described that the first component is formed on the second component, it may include an embodiment where the first and second components are in direct contact, or it may include an embodiment where additional components are formed between the first and second components so that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specifically stated in the text, they do not themselves represent a specific relationship between various embodiments and / or the configurations discussed.

[0116] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of progressiveness of the present invention, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0117] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0118] Figure 1A is a cross-sectional schematic diagram illustrating the semiconductor element 1 of some embodiments of the present disclosure. Figure 1Bis a top view schematic diagram illustrating the semiconductor element 1 of some embodiments of the present disclosure. Figure 1C is a perspective view schematic diagram illustrating the semiconductor element 1 of some embodiments of the present disclosure. In some embodiments, Figure 1A is along Figure 1B the sectional view taken along the section line 1A-1A’ in Figure 1A is along Figure 1C the sectional view taken along the section line 1A-1A’ in

[0119] The semiconductor element 1 may include a substrate 10, capacitors 100C, 200C, and 300C, dielectric layers 12, 20, and 30, vertical transistors 100T, 200T, and 300T, barrier layers 128, 228, and 328, pillars P1, P2, and P3, and bit lines BL1, BL2, and BL3.

[0120] In some embodiments, the substrate 10 may be a semiconductor substrate. In some embodiments, the substrate 10 may include a conductive structure disposed thereon, such as a contact plug (not shown in the figure).

[0121] In some embodiments, the capacitors 100C, 200C, and 300C are disposed on the substrate 10. In some embodiments, the capacitors 100C, 200C, and 300C are respectively disposed below the vertical transistors 100T, 200T, and 300T.

[0122] In some embodiments, the capacitor 100C includes a pillar as an electrode 110, an insulating layer 112, and an electrode 114. In some embodiments, the electrode 110 includes a conductive material, such as tungsten, copper, or the like. Although Figure 1A and Figure 1C the shown electrode 110 is columnar, the shape of the electrode 110 is not limited thereto. In some embodiments, the insulating layer 112 covers and surrounds the electrode 110. In some embodiments, the insulating layer 112 includes silicon oxide, tungsten oxide, copper oxide, aluminum oxide, hafnium oxide, or the like. In some embodiments, the electrode 114 covers and surrounds the insulating layer 112. In some embodiments, the electrode 114 includes a conductive material, such as tungsten, copper, or the like. In some examples, the material of the electrode 114 may be the same as that of the electrode 110.

[0123] In some embodiments, the capacitor 200C includes a pillar as an electrode 210, an insulating layer 212, and an electrode 214. In some embodiments, the electrode 210 includes a conductive material, such as tungsten, copper, or the like. Although Figure 1A and Figure 1CThe illustrated electrode 210 is columnar, but the shape of the electrode 210 is not limited thereto. In some embodiments, the insulating layer 212 covers and surrounds the electrode 210. In some embodiments, the insulating layer 212 includes silicon oxide, tungsten oxide, copper oxide, aluminum oxide, hafnium oxide, or the like. In some embodiments, the electrode 214 covers and surrounds the insulating layer 212. In some embodiments, the electrode 214 includes a conductive material such as tungsten, copper, or the like. In some examples, the material of the electrode 214 may be the same as that of the electrode 210.

[0124] In some embodiments, the capacitor 300C includes a column as an electrode 310, an insulating layer 312, and an electrode 314. In some embodiments, the electrode 310 includes a conductive material such as tungsten, copper, or the like. Although Figure 1A and Figure 1C the illustrated electrode 310 is columnar, but the shape of the electrode 310 is not limited thereto. In some embodiments, the insulating layer 312 covers and surrounds the electrode 310. In some embodiments, the insulating layer 312 includes silicon oxide, tungsten oxide, copper oxide, aluminum oxide, hafnium oxide, or the like. In some embodiments, the electrode 314 covers and surrounds the insulating layer 312. In some embodiments, the electrode 314 includes a conductive material such as tungsten, copper, or the like. In some examples, the material of the electrode 314 may be the same as that of the electrode 310.

[0125] In some embodiments, the dielectric layer 12 covers the capacitors 100C, 200C, and 300C. Specifically, the vertical transistors 100T, 200T, and 300T are disposed on the dielectric layer 12 and are respectively aligned with the capacitors 100C, 200C, and 300C.

[0126] In some embodiments, the vertical transistor 100T includes a channel region 120, a word line dielectric layer 122, a conductive pad 126, and a word line WL1. In some embodiments, the channel region 120 includes silicon or an oxide semiconductor. Specifically, the column P1 may be a silicon column or an oxide semiconductor column, and a part of the column P1 serves as a channel (i.e., the channel region 120) of the vertical transistor 100T. In some embodiments, the word line WL1 extends along a direction DR1 and surrounds the channel region 120. In some embodiments, the word line WL1 includes tungsten (W), copper (Cu), or molybdenum (Mo), but is not limited thereto. In some embodiments, the word line dielectric layer 122 is disposed between the channel region 120 and the word line WL1. In some embodiments, the channel region 120 is surrounded by the word line dielectric layer 122. In some embodiments, the word line dielectric layer 122 may include one or more dielectric materials such as silicon oxide.

[0127] In some embodiments, the conductive pad 126 is located between the character line dielectric layer 122 and the character line WL1. In some embodiments, the conductive pad 126 surrounds the character line dielectric layer 122. In some embodiments, the conductive pad 126 directly contacts the character line dielectric layer 122 and the character line WL1. In some embodiments, the character line WL1 surrounds the conductive pad 126. In some embodiments, a resistance value of the conductive pad 126 is lower than a resistance value of the character line WL1. In some embodiments, a width W1 of the conductive pad 126 is greater than a width W2 of the character line dielectric layer 122. In some embodiments, the conductive pad 126 partially protrudes from an edge WL1e of the character line WL1. In some embodiments, the conductive pad 126 includes titanium (Ti), titanium nitride (TiN), nickel (Ni), or cobalt (Co), but is not limited thereto.

[0128] In some embodiments, the vertical transistor 200T is adjacent to the vertical transistor 100T. In some embodiments, the vertical transistor 200T includes a channel region 220, a character line dielectric layer 222, a conductive pad 226, and a character line WL2. In some embodiments, the channel region 220 includes silicon or an oxide semiconductor. Specifically, the pillar P2 can be a silicon pillar or an oxide semiconductor pillar, and a part of the pillar P2 serves as the channel of the vertical transistor 200T (i.e., the channel region 220). In some embodiments, the character line WL2 extends along the direction DR1 and surrounds the channel region 220. In some embodiments, the character line WL2 includes tungsten (W), copper (Cu), or molybdenum (Mo), but is not limited thereto. In some embodiments, the character line dielectric layer 222 is disposed between the channel region 220 and the character line WL2. In some embodiments, the channel region 220 is surrounded by the character line dielectric layer 222. In some embodiments, the character line dielectric layer 222 may include one or more dielectric materials, such as silicon oxide.

[0129] In some embodiments, the conductive pad 226 is located between the character line dielectric layer 222 and the character line WL2. In some embodiments, the conductive pad 226 surrounds the character line dielectric layer 222. In some embodiments, the conductive pad 226 directly contacts the character line dielectric layer 222 and the character line WL2. In some embodiments, the character line WL2 surrounds the conductive pad 226. In some embodiments, a resistance value of the conductive pad 226 is lower than a resistance value of the character line WL2. In some embodiments, a width of the conductive pad 226 is greater than a width of the character line dielectric layer 222. In some embodiments, the conductive pad 226 partially protrudes from an edge of the character line WL2. In some embodiments, the conductive pad 226 includes titanium (Ti), titanium nitride (TiN), nickel (Ni), or cobalt (Co), but is not limited thereto. In some embodiments, a distance D2 between the conductive pad 126 and the conductive pad 226 is less than a distance D1 between the character line WL1 and the character line WL2.

[0130] In some embodiments, the vertical transistor 300T is adjacent to the vertical transistor 200T. In some embodiments, the vertical transistor 300T includes a channel region 320, a character line dielectric layer 322, a conductive pad 326, and a character line WL3. In some embodiments, the channel region 320 includes silicon or an oxide semiconductor. Specifically, the pillar P3 may be a silicon pillar or an oxide semiconductor pillar, and a part of the pillar P3 serves as the channel of the vertical transistor 300T (i.e., the channel region 320). In some embodiments, the character line WL3 extends along the direction DR1 and surrounds the channel region 320. In some embodiments, the character line WL3 includes tungsten (W), copper (Cu), or molybdenum (Mo), but is not limited thereto. In some embodiments, the character line dielectric layer 322 is disposed between the channel region 320 and the character line WL3. In some embodiments, the channel region 320 is surrounded by the character line dielectric layer 322. In some embodiments, the character line dielectric layer 322 may include one or more dielectric materials, such as silicon oxide.

[0131] In some embodiments, the conductive pad 326 is located between the character line dielectric layer 322 and the character line WL3. In some embodiments, the conductive pad 326 surrounds the character line dielectric layer 322. In some embodiments, the conductive pad 326 directly contacts the character line dielectric layer 322 and the character line WL3. In some embodiments, the character line WL3 surrounds the conductive pad 326. In some embodiments, a resistance value of the conductive pad 326 is lower than a resistance value of the character line WL3. In some embodiments, a width of the conductive pad 326 is greater than a width of the character line dielectric layer 322. In some embodiments, the conductive pad 326 partially protrudes from an edge of the character line WL3. In some embodiments, the conductive pad 326 includes titanium (Ti), titanium nitride (TiN), nickel (Ni), or cobalt (Co), but is not limited thereto.

[0132] In some embodiments, the dielectric layer 20 is disposed or formed over the dielectric layer 12. In some embodiments, the dielectric layer 20 encapsulates the vertical transistors 100T, 200T, and 300T. In some embodiments, the dielectric layer 20 directly contacts the conductive pad 126. In some embodiments, the dielectric layer 20 directly contacts the conductive pad 226. In some embodiments, the dielectric layer 20 directly contacts the conductive pad 326. In some embodiments, a distance D4 between the dielectric layer 20 and the conductive pad 126 is less than a distance D3 between the dielectric layer 20 and the word line WL1.

[0133] In some embodiments, the barrier layer 128 is located on each sidewall of the word line WL1. In some embodiments, the barrier layer 128 directly contacts the conductive pad 126. In some embodiments, the barrier layer 128 has a non-uniform width. In some embodiments, the barrier layer 128 includes a portion 128a and a portion 128b, where portion 128a contacts the conductive pad 126 and portion 128b contacts the word line WL1. In some embodiments, a width (distance D3) of the portion 128a of the barrier layer 128 is less than a width (distance D4) of the portion 128b of the first barrier layer 128. In some embodiments, the conductive pad 126 partially protrudes into the barrier layer 128. In some embodiments, the barrier layer 128 directly contacts the dielectric layer 20. In some embodiments, the barrier layer 128 includes titanium (Ti), titanium nitride (TiN), nickel (Ni), or cobalt (Co), but is not limited thereto.

[0134] In some embodiments, the barrier layer 228 is located on each sidewall of the word line WL2. In some embodiments, the barrier layer 228 directly contacts the conductive pad 226. In some embodiments, the barrier layer 228 has a non-uniform width. In some embodiments, the barrier layer 228 includes a portion that contacts the conductive pad 226 and a portion that contacts the word line WL2. In some embodiments, the two portions of the barrier layer 228 have different widths. In some embodiments, the conductive pad 226 partially protrudes into the barrier layer 228. In some embodiments, the barrier layer 228 directly contacts the dielectric layer 20. In some embodiments, the barrier layer 228 includes titanium (Ti), titanium nitride (TiN), nickel (Ni), or cobalt (Co), but is not limited thereto.

[0135] In some embodiments, the barrier layer 328 is located on each sidewall of the word line WL3. In some embodiments, the barrier layer 328 is in direct contact with the conductive pad 326. In some embodiments, the barrier layer 328 has a non-uniform width. In some embodiments, the barrier layer 328 includes a portion in contact with the conductive pad 326 and a portion in contact with the word line WL3. In some embodiments, the two portions of the barrier layer 328 have different widths. In some embodiments, the conductive pad 326 partially protrudes into the barrier layer 328. In some embodiments, the barrier layer 328 is in direct contact with the dielectric layer 20. In some embodiments, the barrier layer 328 includes titanium (Ti), titanium nitride (TiN), nickel (Ni), or cobalt (Co), but is not limited thereto.

[0136] In some embodiments, the dielectric layer 30 is disposed or formed above the dielectric layer 20. In some embodiments, the dielectric layer 30 includes the same materials as the dielectric layers 12 and 20. In some examples, the dielectric layer 30 includes an oxide, a nitride, or a low-k material.

[0137] In some embodiments, the bit lines BL1, BL2, and BL3 are located above the vertical transistors 100T, 200T, and 300T. In some embodiments, the bit lines BL1, BL2, and BL3 cross the word lines WL1, WL2, and WL3. In some embodiments, the bit lines BL1, BL2, and BL3 extend along a direction DR2 perpendicular to the direction DR1. In some embodiments, the bit lines BL1, BL2, and BL3 include tungsten (W), copper (Cu), or molybdenum (Mo), but are not limited thereto.

[0138] The semiconductor device 1 may be a dynamic random access memory (DRAM) configured as an array of one capacitor and one transistor per cell. Assuming a pitch of 2F for each of the word line and the bit line, a horizontal dimension of the memory cell may be 4F. 2 The semiconductor device 1 may have an area of approximately 4F 2 or less, where F is the minimum lithography feature size.

[0139] Figure 2A is a top view schematic diagram illustrating the semiconductor device 2A of some embodiments of the present disclosure. In some embodiments, Figure 1A may show a cross-sectional view along the Figure 2A section line 1A-1A' in

[0140] In some embodiments, the conductive pad 126 and the barrier layer 128 are partially integrally formed. In some embodiments, the conductive pad 126 and the barrier layer 128 may be formed of or include the same material, such as Ti or TiN.

[0141] In some embodiments, the conductive gasket 226 is partially integrally formed with the barrier layer 228. In some embodiments, the conductive gasket 226 and the barrier layer 228 may be formed of or include the same material, such as Ti or TiN.

[0142] In some embodiments, the conductive gasket 326 is partially integrally formed with the barrier layer 328. In some embodiments, the conductive gasket 326 and the barrier layer 328 may be formed of the same material or include the same material, such as Ti or TiN.

[0143] Figure 2B is a top view schematic diagram illustrating a semiconductor element 2B according to some embodiments of the present disclosure. In some embodiments, Figure 1A may show a cross-sectional view along Figure 2B the cutting line 1A-1A' in

[0144] In some embodiments, the conductive gasket 126 partially protrudes from an edge 128e of the barrier layer 128. In some embodiments, the conductive gasket 126 directly contacts the dielectric layer 20. In some embodiments, the conductive gasket 126 is partially integrally formed with the barrier layer 128. In some embodiments, the conductive gasket 126 and the barrier layer 128 may be formed of or include the same material, such as Ti or TiN.

[0145] In some embodiments, the conductive gasket 226 partially protrudes from an edge of the barrier layer 228. In some embodiments, the conductive gasket 226 directly contacts the dielectric layer 20. In some embodiments, the conductive gasket 226 is partially integrally formed with the barrier layer 228. In some embodiments, the conductive gasket 226 and the barrier layer 228 may be formed of or include the same material, such as Ti or TiN.

[0146] In some embodiments, the conductive gasket 326 partially protrudes from an edge of the barrier layer 328. In some embodiments, the conductive gasket 326 directly contacts the dielectric layer 20. In some embodiments, the conductive gasket 326 is partially integrally formed with the barrier layer 328. In some embodiments, the conductive gasket 326 and the barrier layer 328 may be formed of or include the same material, such as Ti or TiN.

[0147] According to some embodiments of the present disclosure, through the design of the conductive gasket, the width of the narrow region of the word line is directly connected and electrically connected to the conductive gasket. That is, the distance between the barrier layer and the word line dielectric layer (e.g., the narrow region of the word line) is increased. Therefore, the conductive gasket and the word line can be used together as a composite word line with an increased width, thus reducing the word line resistance value, which is beneficial to the electrical function of the semiconductor element.

[0148] Figures 3A to 11Bis a schematic diagram illustrating different stages of a method for fabricating a semiconductor element 1 of semiconductor elements according to some embodiments of the present disclosure.

[0149] Figure 3A is a schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element of semiconductor elements according to some embodiments of the present disclosure. Figure 3B is a schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element of semiconductor elements according to some embodiments of the present disclosure. Figure 3A is Figure 3B a cross-sectional view of the structure shown. In some embodiments, Figure 3A is along Figure 3B the cutting line 3A - 3A' in

[0150] Please refer to Figure 3A and Figure 3B , a substrate 10 can be provided, and capacitors 100C, 200C, and 300C can be provided above the substrate 10. In some configurations, a dielectric layer 12 can be formed to cover or encapsulate the capacitors 100C, 200C, and 300C.

[0151] In some embodiments, as Figure 3A and Figure 3B shown, trenches TR1, TR2, and TR3 can be formed above the capacitors 100C, 200C, and 300C respectively. In some embodiments, barrier layers 128, 228, and 328 are respectively formed on the sidewalls of the trenches TR1, TR2, and TR3. In some embodiments, a dielectric layer 20 can be formed above the capacitors 100C, 200C, and 300C, and the trenches TR1, TR2, and TR3 can be formed in the dielectric layer 20. In some embodiments, the dielectric layer 20 defines the trenches TR1, TR2, and TR3.

[0152] Figure 4A is a schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element of semiconductor elements according to some embodiments of the present disclosure. Figure 4B is a schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element of semiconductor elements according to some embodiments of the present disclosure. In some embodiments, Figure 4A is Figure 4B a cross-sectional view of the structure shown. In some embodiments, Figure 4A is along Figure 4B the cutting line 4A - 4A' in

[0153] Please refer to Figure 4A and Figure 4B , word line materials WL1A, WL2A, and WL3A can be respectively formed in the trenches TR1, TR2, and TR3.

[0154] Figure 5A is a schematic diagram illustrating one or more stages of a method of manufacturing a semiconductor device of some embodiments of the present disclosure. Figure 5B is a schematic diagram illustrating one or more stages of a method of manufacturing a semiconductor device of some embodiments of the present disclosure. In some embodiments, Figure 5A is Figure 5B a cross-sectional view of the structure shown. In some embodiments, Figure 5A is a cross-sectional view taken along Figure 5B section line 5A-5A' in

[0155] Please refer to Figure 5A and Figure 5B , the word line materials WL1A, WL2A, and WL3A can be etched to form word lines WL1, WL2, and WL3 and openings OP1, OP2, and OP3 respectively surrounded by the word lines WL1, WL2, and WL3. In some embodiments, the etch barrier layers 128, 228, and 328 are etched to form openings OP1, OP2, and OP3 respectively surrounded by the word lines WL1, WL2, and WL3. In some embodiments, the etching of the etch barrier layers 128, 228, and 328 and the etching of the word line materials WL1A, WL2A, and WL3A are performed in the same operation.

[0156] Figure 6A is a schematic diagram illustrating one or more stages of a method of manufacturing a semiconductor device of some embodiments of the present disclosure. Figure 6B is a schematic diagram illustrating one or more stages of a method of manufacturing a semiconductor device of some embodiments of the present disclosure. In some embodiments, Figure 6A is Figure 6B a cross-sectional view of the structure shown. In some embodiments, Figure 6A is a cross-sectional view taken along Figure 6B section line 6A-6A' in

[0157] Please refer to Figure 6A and Figure 6B , conductive pad materials 126A, 226A, and 326A can be formed in the openings OP1, OP2, and OP3 respectively.

[0158] Figure 7A is a schematic diagram illustrating one or more stages of a method of manufacturing a semiconductor device of some embodiments of the present disclosure. Figure 7B is a schematic diagram illustrating one or more stages of a method of manufacturing a semiconductor device of some embodiments of the present disclosure. In some embodiments, Figure 7A is Figure 7B a cross-sectional view of the structure shown. In some embodiments, Figure 7A is a cross-sectional view taken along Figure 7BCross-sectional view taken along cutting line 7A-7A'.

[0159] Please refer to Figure 7A and Figure 7B , the etchable conductive pad materials 126A, 226A, and 326A can be etched to form conductive pads 126, 226, and 326 and vias H1, H2, and H3 respectively surrounded by the conductive pads 126, 226, and 326.

[0160] Figure 8A is a schematic diagram illustrating one or more stages of a method of manufacturing a semiconductor element of some embodiments of the present disclosure. Figure 8B is a schematic diagram illustrating one or more stages of a method of manufacturing a semiconductor element of some embodiments of the present disclosure. In some embodiments, Figure 8A is Figure 8B a cross-sectional view of the structure shown. In some embodiments, Figure 8A is taken along Figure 8B cutting line 8A-8A' in

[0161] Please refer to Figure 8A and Figure 8B , the character line dielectric materials 122A, 222A, and 322A can be formed in the vias H1, H2, and H3 respectively surrounded by the conductive pads 126, 226, and 326. In some embodiments, the character line dielectric materials 122A, 222A, and 322A can be deposited in the vias H1, H2, and H3.

[0162] Figure 9A is a schematic diagram illustrating one or more stages of a method of manufacturing a semiconductor element of some embodiments of the present disclosure. Figure 9B is a schematic diagram illustrating one or more stages of a method of manufacturing a semiconductor element of some embodiments of the present disclosure. In some embodiments, Figure 9A is Figure 9B a cross-sectional view of the structure shown. In some embodiments, Figure 9A is taken along Figure 9B cutting line 9A-9A' in

[0163] Please refer to Figure 9A and Figure 9B, the character line dielectric materials 122A, 222A, and 322A can be etched to form the character line dielectric layers 122, 222, and 322 and the vias 120H, 220H, and 320H respectively surrounded by the character line dielectric layers 122, 222, and 322. In some embodiments, the character line dielectric layers 122, 222, and 322 are respectively formed on the conductive pads 126, 226, and 326. The fabrication techniques for the character line dielectric layers 122, 222, and 322 can include a combination of deposition methods such as chemical vapor deposition (CVD) and etching methods such as reactive ion etching (RIE).

[0164] Figure 10A is a schematic diagram illustrating one or more stages of a method of fabricating a semiconductor device of some embodiments of the present disclosure. Figure 10B is a schematic diagram illustrating one or more stages of a method of fabricating a semiconductor device of some embodiments of the present disclosure. In some embodiments, Figure 10A is Figure 10B a cross-sectional view of the structure shown. In some embodiments, Figure 10A is along Figure 10B the cutting line 10A-10A' in

[0165] Please refer to Figure 10A and Figure 10B , the channel regions 120, 220, and 320 can be respectively formed in the vias 120H, 220H, and 320H. In this way, the vertical transistors 100T, 200T, and 300T are respectively formed in the trenches TR1, TR2, and TR3. In some embodiments, the vias 120H, 220H, and 320H are completely filled with one or more semiconductor materials to form the channel regions 120, 220, and 320. A planarization process, such as chemical mechanical polishing (CMP), can also be performed so that the respective surfaces of the channel regions 120, 220, and 320 can be substantially flush with an upper surface of the dielectric layer 20, the respective upper surfaces of the character lines WL1, WL2, and WL3, and the respective upper surfaces of the character line dielectric layers 122, 222, and 322.

[0166] Figure 11A is a schematic diagram illustrating one or more stages of a method of fabricating a semiconductor device of some embodiments of the present disclosure. Figure 11B is a schematic diagram illustrating one or more stages of a method of fabricating a semiconductor device of some embodiments of the present disclosure. In some embodiments, Figure 11A is Figure 11B a cross-sectional view of the structure shown. In some embodiments, Figure 11A is along Figure 11B the cutting line 11A-11A' in

[0167] Please refer toFigure 11A and Figure 11B , bit lines BL1, BL2, and BL3 may be formed above vertical transistors 100T, 200T, and 300T. In some embodiments, a dielectric layer 30 is formed above dielectric layer 20 and vertical transistors 100T, 200T, and 300T. In some embodiments, bit lines BL1, BL2, and BL3 are also formed on dielectric layer 30 to be located above vertical transistors 100T, 200T, and 300T.

[0168] Figure 12 is a flow diagram illustrating a method 1200 for fabricating a semiconductor device according to some embodiments of the present disclosure.

[0169] Method 1200 begins at step S1, where a capacitor is provided above a substrate.

[0170] Method 1200 proceeds to step S2, where a vertical transistor is formed above the capacitor. In some embodiments, the vertical transistor includes a channel region, a word line, a word line dielectric layer, and a conductive pad. In some embodiments, the word line surrounds the channel region, the word line dielectric layer is located between the channel region and the word line, and the conductive pad is located between the word line dielectric layer and the word line.

[0171] Method 1200 is merely an example and is not intended to limit the present disclosure beyond what is expressly recited in the claims. Additional steps may be provided before, during, or after each step of method 1200, and some of the described steps may be replaced, eliminated, or moved for additional embodiments of the method. In some embodiments, method 1200 may include Figure 12 other steps not depicted in Figure 12 In some embodiments, method 1200 may include one or more steps depicted in

[0172] An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first vertical transistor. The first vertical transistor may include a first channel region. The first vertical transistor may also include a first word line surrounding the first channel region. The first vertical transistor may further include a first word line dielectric layer located between the first channel region and the first word line. The first vertical transistor may still further include a first conductive pad located between the first word line dielectric layer and the first word line.

[0173] Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first vertical transistor and a first barrier layer. The first vertical transistor may include a first channel region. The first vertical transistor may further include a first word line surrounding the first channel region. The first vertical transistor may further include a first word line dielectric layer surrounding the first word line. The first vertical transistor may further include a first conductive pad surrounding the first word line. The first barrier layer is located on each sidewall of the first word line and directly contacts the first conductive pad.

[0174] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The manufacturing method may include providing a capacitor on a substrate. The manufacturing method may further include forming a vertical transistor above the capacitor, where the vertical transistor includes: a channel region; a word line surrounding the channel region; a word line dielectric layer located between the channel region and the word line; and a conductive pad located between the word line dielectric layer and the word line.

[0175] In the semiconductor device, through the design of the conductive pad, the width of the narrow region of the word line is directly connected and electrically connected to the conductive pad. That is, the distance between the barrier layer and the word line dielectric layer (e.g., the narrow region of the word line) is increased. Therefore, the conductive pad and the word line can be jointly used as a composite word line with an increased width, thereby reducing the word line resistance value, which is beneficial to the electrical function of the semiconductor device.

[0176] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0177] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that can be used according to the present disclosure and have the same function or achieve substantially the same result as the corresponding embodiments described herein are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: A first vertical transistor, comprising: a first channel area; a first word line surrounding the first channel region; a first word line dielectric layer located between the first channel region and the first word line; and A first conductive pad is located between the first word line dielectric layer and the first word line. 2 . The semiconductor device as claimed in claim 1 , wherein the first conductive pad surrounds the first word line dielectric layer. 3 . The semiconductor device as claimed in claim 2 , wherein the first conductive pad directly contacts the first word line dielectric layer and the first word line. 4 . The semiconductor device as claimed in claim 1 , wherein the first word line surrounds the first conductive pad. 5 . The semiconductor device as claimed in claim 1 , wherein a resistance value of the first conductive pad is lower than a resistance value of the first word line. 6 . The semiconductor device as claimed in claim 1 , wherein a width of the first conductive pad is greater than a width of the first word line dielectric layer. 7 . The semiconductor device as claimed in claim 1 , wherein the first conductive pad partially protrudes from an edge of the first word line.

8. The semiconductor device according to claim 1, further comprising: A dielectric layer encapsulates the first vertical transistor, wherein a distance between the dielectric layer and the first conductive pad is smaller than a distance between the dielectric layer and the first word line.

9. The semiconductor device according to claim 1, further comprising: a second vertical transistor, adjacent to the first vertical transistor, the second vertical transistor comprising: a second channel area; a second word line surrounding the second channel region; a second word line dielectric layer located between the second channel region and the second word line; and A second conductive pad is located between the second word line dielectric layer and the second word line. 10 . The semiconductor device as claimed in claim 9 , wherein a distance between the first conductive pad and the second conductive pad is smaller than a distance between the first word line and the second word line.

11. A semiconductor element, comprising: A first vertical transistor, comprising: a first channel area; a first word line surrounding the first channel region; a first word line dielectric layer surrounding the first word line; and a first conductive pad surrounding the first word line; and A first barrier layer is located on each sidewall of the first word line and directly contacts the first conductive pad. 12 . The semiconductor device as claimed in claim 11 , wherein the first barrier layer has a non-uniform width. 13 . The semiconductor device as claimed in claim 12 , wherein the first barrier layer comprises a first portion and a second portion, the first portion contacts the first conductive pad, and the second portion contacts the first word line. 14 . The semiconductor device as claimed in claim 13 , wherein a width of the first portion of the first barrier layer is smaller than a width of the second portion of the first barrier layer. 15 . The semiconductor device as claimed in claim 11 , wherein the first conductive pad partially protrudes into the first barrier layer. 16 . The semiconductor device as claimed in claim 15 , wherein the first conductive pad and the first barrier layer are partially formed integrally. 17 . The semiconductor device as claimed in claim 15 , wherein the first conductive pad partially protrudes from an edge of the first barrier layer. 18 . The semiconductor device as claimed in claim 17 , wherein the first conductive pad and the first barrier layer are partially formed integrally.

19. The semiconductor device according to claim 17, further comprising: A dielectric layer encapsulates the first vertical transistor, wherein the dielectric layer directly contacts the first conductive pad and the first barrier layer.

20. The semiconductor device according to claim 11, further comprising: a second vertical transistor, adjacent to the first vertical transistor, the second vertical transistor comprising: a second channel area; a second word line surrounding the first channel region; a second word line dielectric layer surrounding the first word line; and a second conductive pad surrounding the first word line; and A second barrier layer is located on each sidewall of the second word line and directly contacts the second conductive pad.

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