Semiconductor device

Abstract

A semiconductor device includes: a first active pattern and a second active pattern adjacent to each other in a first direction, and each including a first edge portion and a second edge portion spaced apart from each other; a word line crossing between the first edge portion and the second edge portion of each of the first active pattern and the second active pattern and extending in a waveform in the first direction; a bit line on the first edge portion of the first active pattern; and a storage node contact located on the second edge portion of the first active pattern, in which the first active pattern extends in a second direction intersecting the first direction, and the second active pattern extends in a third direction, the third direction is symmetrical with respect to the first direction and the second direction.

Description

Technical Field

[0001] The inventive concept relates to semiconductors, and more particularly, to semiconductor devices and methods of manufacturing the same. Background Art

[0002] Semiconductor devices may have relatively small sizes, multifunctional characteristics, and / or relatively low manufacturing costs. Semiconductor devices may be classified into any one of semiconductor memory devices that store logic data, semiconductor logic devices that process logic data, and hybrid semiconductor devices that combine the functions of semiconductor memory devices and semiconductor logic devices.

[0003] Due to the increasing demand for high-speed and low-power electronic devices, semiconductor devices require fast operating speeds or low operating voltages. To meet this demand, semiconductor devices require high integration densities. Accordingly, many studies are being conducted to increase the integration degree of semiconductor devices. Summary of the Invention

[0004] An object of the inventive concept is to provide a semiconductor device and a method of manufacturing the same that are easy to manufacture and have an increased integration degree.

[0005] An object of the inventive concept is to provide a semiconductor device and a method of manufacturing the same in which electrical characteristics are improved.

[0006] Problems to be solved by the inventive concept are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] According to one aspect of the present disclosure, a semiconductor device includes: a substrate provided with a first active pattern and a second active pattern, wherein the first active pattern and the second active pattern are adjacent to each other in a first direction, and each of the first active pattern and the second active pattern includes a first edge portion, a second edge portion, and a central portion located between the first edge portion and the second edge portion, and the first direction is parallel to the upper surface of the substrate; a word line having a waveform extending in the first direction and including a first portion overlapping with the central portion of the first active pattern and a second portion overlapping with the central portion of the second active pattern; a first bit line provided on the first edge portion of the first active pattern; and a first storage node contact provided on the second edge portion of the first active pattern. The first active pattern extends longitudinally in a second direction intersecting the first direction, and the second direction is parallel to the upper surface of the substrate. The second active pattern extends longitudinally in a third direction intersecting the first direction and the second direction, and the third direction is parallel to the upper surface of the substrate. The first active pattern and the second active pattern are symmetric in shape.

[0008] According to one aspect of the present disclosure, a semiconductor device includes: a first active pattern and a second active pattern, the first active pattern and the second active pattern being adjacent to each other in a first direction and each including a first edge portion and a second edge portion spaced apart from each other; a word line crossing between the first edge portion and the second edge portion of each of the first active pattern and the second active pattern and extending in the first direction; a bit line located on the first edge portion of the first active pattern; and a storage node contact located on the second edge portion of the first active pattern. The first active pattern extends longitudinally in a second direction intersecting the first direction. The second active pattern extends longitudinally in a third direction intersecting the first direction and the second direction. The second direction and the third direction are symmetric with respect to the first direction. The first direction, the second direction, and the third direction are in the same plane. Each side of the opposite sides of the word line has convex surfaces and concave surfaces alternately arranged along the first direction.

[0009] According to one aspect of the present disclosure, a semiconductor device includes: a first active pattern and a second active pattern, the first active pattern and the second active pattern being adjacent to each other in a first direction and each including a first edge portion and a second edge portion spaced apart from each other; a word line crossing between the first edge portion and the second edge portion of each of the first active pattern and the second active pattern and having a waveform extending in the first direction; a bit line disposed on the first edge portion of the first active pattern; a storage node contact disposed on the second edge portion of the first active pattern; a landing pad disposed on the storage node contact; and a data storage pattern disposed on the landing pad. The first active pattern extends longitudinally in a second direction intersecting the first direction. The second active pattern extends longitudinally in a third direction intersecting the first direction and the second direction. The second direction and the third direction are symmetric with respect to the first direction. The first direction, the second direction, and the third direction are in the same plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings depict non-limiting example embodiments as described herein.

[0011] Figure 1A is a top view showing a semiconductor device according to some embodiments of the inventive concept.

[0012] Figure 1B is Figure 1A an enlarged view of a part of the structure of

[0013] Figure 1C is Figure 1A an enlarged view of a part of the structure of

[0014] Figures 2A to 2D are, respectively, cross-sectional views corresponding to lines A-A', B-B', C-C', and D-D' of Figure 1A

[0015] Figure 3 is a top view showing a semiconductor device according to some embodiments of the inventive concept.

[0016] Figure 4A and Figure 4B are, respectively, cross-sectional views corresponding to lines A-A' and D-D' of Figure 1A

[0017] Figure 5 is a cross-sectional view corresponding to line C-C' of Figure 1A ​​​

[0018] Figure 6 is a top view of a semiconductor device showing some embodiments according to the inventive concept.

[0019] Figures 7A to 7C are respectively Figure 6 cross-sectional views corresponding to lines A-A', C-C', and D-D' of

[0020] Figure 8 is a top view of a semiconductor device showing some embodiments according to the inventive concept.

[0021] Figure 9A and Figure 9B are respectively Figure 8 cross-sectional views corresponding to lines B-B' and D-D' of

[0022] Figure 10 is a top view of a semiconductor device showing some embodiments according to the inventive concept.

[0023] Figure 11A and Figure 11B are respectively Figure 10 cross-sectional views corresponding to lines A-A' and D-D' of

[0024] Figure 12A and Figure 12B are respectively Figure 10 cross-sectional views corresponding to lines A-A' and D-D' of

[0025] Figure 13 is a top view of a semiconductor device showing some embodiments according to the inventive concept.

[0026] Figures 14A to 14D are respectively Figure 13 cross-sectional views corresponding to lines A-A', B-B', C-C', and D-D' of

[0027] Figure 15 , Figure 16A , Figure 16B , Figure 17 , Figures 18A to 18D , Figure 19 and Figures 20A to 20D are views showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0028] Figure 21 , Figures 22A to 22C , Figure 23 and Figures 24A to 24C are views showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0029] Figure 25 , Figure 26A and Figure 26B are views showing methods of manufacturing semiconductor devices according to some embodiments of the inventive concept.

[0030] Figure 27 , Figure 28A and Figure 28B are views showing methods of manufacturing semiconductor devices according to some embodiments of the inventive concept.

[0031] Figure 29 , Figure 30A and Figure 30B are views showing methods of manufacturing semiconductor devices according to some embodiments of the inventive concept.

[0032] Figure 31A and Figure 31B are views showing methods of manufacturing semiconductor devices according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0033] Hereinafter, to describe the inventive concept in more detail, embodiments according to the inventive concept will be described in more detail with reference to the accompanying drawings.

[0034] Figure 1A is a top view of a semiconductor device according to some embodiments of the inventive concept. Figure 1B is Figure 1A an enlarged view of a part of the structure of Figure 1C is Figure 1A an enlarged view of a part of the structure of Figures 2A to 2D are respectively cross-sectional views corresponding to lines A-A', B-B', C-C', and D-D' of Figure 1A .

[0035] Referring to Figures 1A to 1C and Figures 2A to 2D , a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0036] A device isolation pattern STI may be provided in the substrate 100 and an active pattern ACT may be defined. A plurality of active patterns ACT may be provided. As an example, the active pattern ACT may include a portion of the substrate 100 surrounded by the device isolation pattern STI. For ease of explanation, unless otherwise specified, in this specification, the substrate 100 is defined to refer to the portion of the substrate 100 other than the above-described portion. The device isolation pattern STI may include or may be formed of the following insulating materials: for example, at least one of silicon oxide (SiO2) and silicon nitride (SiN). The device isolation pattern STI may be a single layer formed of a single material or a composite layer including two or more materials. As used herein, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include all possible combinations of the items enumerated together in the corresponding phrases in these phrases.

[0037] The active pattern ACT may include a first active pattern ACT1 and a second active pattern ACT2 adjacent to each other in a first direction D1 parallel to the lower surface of the substrate 100. The first active pattern ACT1 may have an elongated shape extending in a second direction D2 parallel to the lower surface of the substrate 100. For example, the first active pattern ACT1 may extend longitudinally in the second direction. The second active pattern ACT2 may have an elongated shape extending in a third direction D3 parallel to the lower surface of the substrate 100. For example, the second active pattern ACT2 may extend longitudinally in the third direction D3. The first direction D1, the second direction D2, and the third direction D3 may intersect each other. For example, the second direction D2 may intersect the first direction D1 at an angle greater than 0° and less than 60° in the clockwise direction. For example, the third direction D3 may intersect the first direction D1 at an angle greater than 0° and less than 60° in the counterclockwise direction. For example, the third direction D3 is symmetric with respect to the first direction D1 and the second direction D2. A fourth direction D4 may be parallel to the lower surface of the substrate 100 and intersect the first direction D1, the second direction D2, and the third direction D3. For example, when viewed in a top view, the first active pattern ACT1 and the second active pattern ACT2 have a symmetric profile (symmetric in shape). For example, when viewed in a top view, the first active pattern ACT1 and the second active pattern ACT2 may be spaced farther and farther apart in the first direction D1 along an imaginary line therebetween. The imaginary line may extend in a fourth direction D4 parallel to the upper surface of the substrate 100 and perpendicular to the first direction D1. In some embodiments, the distance between the imaginary line and the first active pattern ACT1 in the first direction may be equal to the distance between the imaginary line and the second active pattern ACT2 in the first direction.

[0038] Each of the first active pattern ACT1 and the second active pattern ACT2 may protrude in a direction perpendicular to the lower surface of the substrate 100 (e.g., the seventh direction D7 to be described later). As an example, the first active pattern ACT1 and the second active pattern ACT2 may include silicon (e.g., single crystal silicon). In some embodiments, the first active pattern ACT1 and the second active pattern ACT2 may be provided together with the substrate 100. The first active pattern ACT1 and the second active pattern ACT2 may be formed epitaxially from the substrate 100, or may be formed by patterning the substrate 100 through etching.

[0039] The first active pattern ACT1 may include a plurality of first active patterns ACT1 arranged along a first direction D1 and a fourth direction D4 parallel to the lower surface of the substrate 100. For example, the first active pattern ACT1 may be repeatedly positioned along the first direction D1 and the fourth direction D4 to form a plurality of first active patterns ACT1. The fourth direction D4 may be parallel to the lower surface of the substrate 100 and intersect the first direction D1, the second direction D2, and the third direction D3. The fourth direction D4 may be perpendicular to the first direction D1. The second active pattern ACT2 may include a plurality of second active patterns ACT2 arranged along the first direction D1 and the fourth direction D4. The first active pattern ACT1 and the second active pattern ACT2 may be alternately arranged along the first direction D1.

[0040] The first active pattern ACT1 may include a first edge portion E1 and a second edge portion E2 spaced apart from each other in the second direction D2 and a central portion CA therebetween. The first edge portion E1 and the second edge portion E2 may be opposite ends of the first active pattern ACT1 in the second direction D2. The first edge portion E1 and the second edge portion E2 of the first active pattern ACT1 may be arranged in order along the second direction D2.

[0041] The second active pattern ACT2 may include a first edge portion E1 and a second edge portion E2 spaced apart from each other in the third direction D3 and a central portion CA therebetween. The first edge portion E1 and the second edge portion E2 may be opposite ends of the second active pattern ACT2 in the third direction D3. The first edge portion E1 and the second edge portion E2 of the second active pattern ACT2 may be arranged in order in the third direction D3.

[0042] The first edge portion E1 of the first active pattern ACT1 may be adjacent to the second edge portion E2 of the second active pattern ACT2 in the first direction D1. For example, the first edge portion E1 of the first active pattern ACT1 and the second edge portion E2 of the second active pattern ACT2 may be spaced apart from each other in the first direction D1 by a first distance. The second edge portion E2 of the first active pattern ACT1 may be adjacent to the first edge portion E1 of the second active pattern ACT2 in the first direction D1. For example, the second edge portion E2 of the first active pattern ACT1 and the first edge portion E1 of the second active pattern ACT2 may be spaced apart from each other in the first direction D1 by a second distance. The second distance may be different from the first distance. In some embodiments, the first distance may be greater than the second distance. The central portion of the first active pattern ACT1 may be adjacent to the central portion of the second active pattern ACT2 in the first direction. For example, the central portion of the first active pattern ACT1 and the central portion of the second active pattern ACT2 may be spaced apart from each other in the first direction by a third distance. In some embodiments, the third distance may be different from the first distance and the second distance. For example, the third distance may be a value between the second distance and the first distance.

[0043] The central portion CA of each of the first active pattern ACT1 and the second active pattern ACT2 may be disposed below a word line WL to be described later. The word line WL may overlap perpendicularly with the central portion CA of each of the first active pattern ACT1 and the second active pattern ACT2. The central portions CA of the first active pattern ACT1 and the second active pattern ACT2 may be arranged to be spaced apart in the first direction D1.

[0044] Each of the first edge portion E1, the second edge portion E2, and the central portion CA of the first active pattern ACT1 and the second active pattern ACT2 may include a doped impurity region having an impurity (e.g., an n-type or p-type impurity) therein. The impurity region may form a source-drain region and / or a channel region of a transistor.

[0045] The adjacent first active patterns ACT1 may be arranged side by side in the first direction D1 (or its opposite direction) or the fourth direction D4 (or its opposite direction). In this specification, arranging the adjacent first active patterns ACT1 side by side in a specific direction means that the first edge portions E1 of the adjacent first active patterns ACT1 are arranged in the specific direction.

[0046] The adjacent second active patterns ACT2 may be arranged side by side in the first direction D1 (or its opposite direction) or the fourth direction D4 (or its opposite direction). In this specification, arranging the adjacent second active patterns ACT2 side by side in a specific direction means that the first edge portions E1 of the adjacent second active patterns ACT2 are arranged in the specific direction.

[0047] The first active pattern ACT1 and the second active pattern ACT2 adjacent to each other may be arranged side by side in the first direction D1 (or its opposite direction). In this specification, the adjacent first active pattern ACT1 and second active pattern ACT2 being arranged side by side in a specific direction means that the first edge portion E1 of the first active pattern ACT1 and the second edge portion E2 of the second active pattern ACT2 are arranged in the specific direction.

[0048] Referring Figure 1B , the first pattern PT1, the second pattern PT2, the fourth pattern PT4, and the third pattern PT3 of the first active pattern ACT1 may be arranged in the counterclockwise direction. The first pattern PT1 of the second active pattern ACT2 may be between the first pattern PT1 and the second pattern PT2 of the first active pattern ACT1. The second pattern PT2 of the second active pattern ACT2 may be between the third pattern PT3 and the fourth pattern PT4 of the first active pattern ACT1.

[0049] The first pattern PT1 of the first active pattern ACT1 and the first pattern PT1 of the second active pattern ACT2 adjacent to the first active pattern ACT1 may be arranged side by side in the first direction D1. The first pattern PT1 of the second active pattern ACT2 and the second pattern PT2 of the first active pattern ACT1 adjacent thereto may be arranged side by side in the first direction D1. The third pattern PT3 of the first active pattern ACT1 and the second pattern PT2 of the second active pattern ACT2 adjacent to the first active pattern ACT1 may be arranged parallel to each other in the first direction D1. The second pattern PT2 of the second active pattern ACT2 and the fourth pattern PT4 of the first active pattern ACT1 adjacent to the second active pattern ACT2 may be arranged parallel to each other in the first direction D1.

[0050] The first pattern PT1 of the first active pattern ACT1 and the third pattern PT3 of the first active pattern ACT1 adjacent thereto may be arranged side by side in the fourth direction D4. The second pattern PT2 of the first active pattern ACT1 and the fourth pattern PT4 of the first active pattern ACT1 adjacent thereto may be arranged parallel to each other in the fourth direction D4. The first pattern PT1 of the second active pattern ACT2 and the second pattern PT2 of the second active pattern ACT2 adjacent thereto may be arranged parallel to each other in the fourth direction D4.

[0051] The first edge portion E1 of the first pattern PT1 of the first active pattern ACT1, the second edge portion E2 of the first pattern PT1 of the second active pattern ACT2, and the first edge portion E1 of the second pattern PT2 of the first active pattern ACT1 may be arranged in order along the first direction D1. The first edge portion E1 of the third pattern PT3 of the first active pattern ACT1, the second edge portion E2 of the second pattern PT2 of the second active pattern ACT2, and the first edge portion E1 of the fourth pattern PT4 of the first active pattern ACT1 may be arranged in order along the first direction D1.

[0052] The first edge portion E1 of the first pattern PT1 of the first active pattern ACT1 and the first edge portion E1 of the third pattern PT3 of the first active pattern ACT1 may be arranged in order along the fourth direction D4. The first edge portion E1 of the second pattern PT2 of the first active pattern ACT1 and the first edge portion E1 of the fourth pattern PT4 of the first active pattern ACT1 may be arranged in order along the fourth direction D4. The first edge portion E1 of the first pattern PT1 of the second active pattern ACT2 and the first edge portion E1 of the second pattern PT2 of the second active pattern ACT2 may be arranged in order along the fourth direction D4.

[0053] According to the inventive concept, the first active pattern ACT1 and the second active pattern ACT2 may be arranged side by side along the first direction D1 (or its opposite direction) or the fourth direction D4 (or its opposite direction), thereby simplifying the arrangement of components in the semiconductor device. Accordingly, the difficulty of patterning for forming the semiconductor device may be reduced, and as a result, the manufacturing of the semiconductor device may be facilitated. Additionally, by arranging the components relatively simply, the integration degree of the semiconductor device may be increased.

[0054] Reference Figures 1A to 1C and Figures 2A to 2D , the word line WL may cross the active pattern ACT and the device isolation pattern STI. The word line WL may be disposed on the central portion CA of the first active pattern ACT1 and the second active pattern ACT2, and may be interposed between the first edge portion E1 and the second edge portion E2 of the first active pattern ACT1 and the second active pattern ACT2. The word line WL may be repeatedly positioned along the fourth direction D4 to form a plurality of word lines WL. Each word line WL may extend in the first direction D1 and be spaced apart from each other in the fourth direction D4. As an example, one word line WL is formed on the central portion CA of each of the first active pattern ACT1 and the second active pattern ACT2 arranged side by side along the first direction D1 and may extend in the first direction D1. For example, each active pattern of the first active pattern ACT1 and the second active pattern ACT2 may overlap with a single word line.

[0055] Each word line WL may include a gate electrode GE, a gate dielectric pattern GI, and a gate capping pattern GC. The gate electrode GE may penetrate a first active pattern ACT1, a second active pattern ACT2, and a device isolation pattern STI in a first direction D1. The gate dielectric pattern GI may be interposed between the gate electrode GE and each of the first active pattern ACT1 and the second active pattern ACT2, and between the gate electrode GE and the device isolation pattern STI. The gate capping pattern GC may cover an upper surface of the gate electrode GE. As an example, the gate electrode GE may include or may be formed of a conductive material. For example, the gate electrode GE may be a single layer formed of a single material or a composite layer including two or more materials. As an example, the gate dielectric pattern GI may include at least one of silicon oxide (SiO2) and a high-k dielectric material, or may be formed of at least one of silicon oxide (SiO2) and a high-k dielectric material. In the present specification, the high-k dielectric material is defined as an insulating material having a higher dielectric constant than silicon oxide. As an example, the gate capping pattern GC may include silicon nitride (SiN) or may be formed of silicon nitride (SiN).

[0056] The word line WL may have a first upper surface W1a and a second upper surface W2a. The first upper surface W1a of the word line WL may be a portion of the upper surface of the word line WL located below a bit line BL to be described later, and the second upper surface W2a may be another portion of the upper surface of the word line WL. For example, the second upper surface W2a of the word line WL may be disposed below a fence pattern FN to be described later. For example, the first upper surface W1a of the word line WL may be positioned at a lower height than the second upper surface W2a.

[0057] Reference Figure 1C , the word line WL may extend in a fifth direction D5 parallel to a lower surface of the substrate 100 between a first edge portion E1 and a second edge portion E2 of a first pattern PT1 of the first active pattern ACT1. The fifth direction D5 may be a direction between the first direction D1 and a fourth direction D4. The fifth direction D5 may form a first angle A with the first direction D1 in a counterclockwise direction. The first angle A may be greater than 0° and less than 90°. As an example, the first angle A may be greater than 0° and less than or equal to 60°.

[0058] The word line WL may extend in a sixth direction D6 parallel to a lower surface of the substrate 100 between a first edge portion E1 and a second edge portion E2 of a first pattern PT1 of the second active pattern ACT2. The sixth direction D6 may be a direction between the first direction D1 and a second direction D2. The sixth direction D6 may form a second angle B with the first direction D1 in a clockwise direction. The second angle B may be greater than 0° and less than 90°. As an example, the second angle B may be greater than 0° and less than or equal to 60°.

[0059] Again, the word line WL may extend in a fifth direction D5 between a first edge portion E1 and a second edge portion E2 of the second pattern PT2 of the first active pattern ACT1.

[0060] In summary, the word line WL may extend in a fifth direction D5 on the central portion CA of each first active pattern ACT1 arranged in a first direction D1. Additionally, the word line WL may extend in a sixth direction D6 on the central portion CA of each second active pattern ACT2 arranged in the first direction D1.

[0061] Since the first active pattern ACT1 and the second active pattern ACT2 are alternately arranged in the first direction D1, the regions where the word line WL extends in the fifth direction D5 and the regions where the word line WL extends in the sixth direction D6 may be alternately arranged in the first direction D1. Accordingly, the word line WL has a waveform overlapping portion (e.g., the central portion CA) between the first edge portion E1 and the second edge portion E2 of the first active pattern ACT1 and the second active pattern ACT2. In some embodiments, the waveform of the word line WL may have a substantially constant width in a fourth direction. In some embodiments, the word line WL may include a first portion overlapping the central portion of the first active pattern and a second portion overlapping the central portion of the second active pattern.

[0062] The word line WL may have opposite sides of a waveform extending in the first direction D1. Among the two sides of the word line WL, the side facing the fourth direction D4 is defined as the first side S1, and the side facing the first side S1 is defined as the second side S2. For example, the first side S1 may be adjacent to the first edge portion E1 of the first active pattern ACT1 and the second edge portion E2 of the second active pattern ACT2, and the second side S2 may be adjacent to the second edge portion E2 of the first active pattern ACT1 and the first edge portion E1 of the second active pattern ACT2.

[0063] Since each of the first side S1 and the second side S2 extends in a waveform, each of the first side S1 and the second side S2 may have convex surfaces PS and concave surfaces CS alternately arranged in the first direction D1.

[0064] The convex surface PS of the first side S1 and the convex surface PS of the second side S2 may protrude in different directions. That is, the convex surface PS of the first side S1 may protrude toward the fourth direction D4, and the convex surface PS of the second side S2 may protrude in the direction opposite to the fourth direction D4. The first portion of the word line WL having the convex surface PS of the first side S1 may refer to the rising portion in the fourth direction D4, and the second portion of the word line WL having the concave surface CS of the first side S1 may refer to the falling portion in the direction opposite to the fourth direction D4.

[0065] The concave surface CS of the first side S1 and the concave surface CS of the second side S2 may be recessed in different directions. That is, the concave surface CS of the first side S1 may be recessed in a direction opposite to the fourth direction D4, and the concave surface CS of the second side S2 may be recessed in the fourth direction D4.

[0066] Each convex surface PS of the first side S1 may be adjacent to a corresponding concave surface CS of the second side S2 in the fourth direction D4. Each concave surface CS of the first side S1 may be adjacent to a corresponding convex surface PS of the second side S2 in the fourth direction D4. Each convex surface PS of the first side S1 may be adjacent to a corresponding convex surface PS of the adjacent second side S2 in the second direction D2 or the third direction D3. The convex surfaces PS of the first side S1 and the convex surfaces PS of the second side S2 may be alternately arranged in a zigzag manner along the first direction D1. Each concave surface CS of the first side S1 may be adjacent to the concave surface CS of the adjacent second side S2 in the second direction D2 or the third direction D3. The concave surfaces CS of the first side S1 and the concave surfaces CS of the second side S2 may be alternately arranged in a zigzag manner along the first direction D1.

[0067] The first edge portion E1 of the first active pattern ACT1 and the second edge portion E2 of the second active pattern ACT2 may be respectively disposed on two adjacent concave surfaces CS of the first side S1 of the word line WL. The second edge portion E2 of the first active pattern ACT1 and the first edge portion E1 of the second active pattern ACT2 may be respectively disposed on two adjacent concave surfaces CS of the second side S2 of the word line WL.

[0068] According to the inventive concept, the word line WL may have a waveform extending in a first direction D1 between a first edge portion E1 and a second edge portion E2 of each of the first active pattern ACT1 and the second active pattern ACT2. Portions of the word line WL adjacent to each of the first edge portion E1 of the first active pattern ACT1 and the second edge portion E2 of the second active pattern ACT2 may be recessed in a direction opposite to a fourth direction D4. In addition, other portions of the word line WL adjacent to each of the second edge portion E2 of the first active pattern ACT1 and the first edge portion E1 of the second active pattern ACT2 may be recessed in a direction opposite to the fourth direction D4. Accordingly, a region PO1 that will be described later and that is in contact with the first edge portion E1 of the first active pattern ACT1 and the bit line BL, and a region PO2 that will be described later and that is in contact with the second edge portion E2 of the first active pattern ACT1 and the lower storage node contact BCx may be increased. In addition, a region PO3 that will be described later and that is in contact with the first edge portion E1 of the second active pattern ACT2 and the bit line BL, and a region PO4 that will be described later and that is in contact with the second edge portion E2 of the second active pattern ACT2 and the lower storage node contact BCx may be increased. As a result, contact components may be easily electrically connected, thereby improving electrical characteristics of the semiconductor device.

[0069] Reference Figures 1A to 1C and Figures 2A to 2D , the lower storage node contact BCx may be disposed on the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2. The lower storage node contact BCx may be in contact with the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2. As an example, the lower storage node contact BCx may include at least one of silicon (e.g., polysilicon containing impurities) and a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0070] The lower storage node contacts BCx may be spaced apart from each other in the first direction D1 and the fourth direction D4. The lower storage node contacts BCx adjacent to each other in the first direction D1 may be spaced apart from each other, and the bit line BL, which will be described later and is located therebetween, may be interposed therebetween. The lower storage node contacts BCx adjacent to each other in the fourth direction D4 may be spaced apart from each other, and the fence pattern FN, which will be described later and is located therebetween, may be interposed therebetween.

[0071] Reference Figure 1B, the first lower storage node contact BCx1 can be disposed on the second edge portion E2 of the first pattern PT1 of the first active pattern ACT1. The second lower storage node contact BCx2 can be disposed on the second edge portion E2 of the first pattern PT1 of the second active pattern ACT2. The third lower storage node contact BCx3 can be disposed on the second edge portion E2 of the second pattern PT2 of the first active pattern ACT1. The fourth lower storage node contact BCx4 can be disposed on the second edge portion E2 of the third pattern PT3 of the first active pattern ACT1. The fifth lower storage node contact BCx5 can be disposed on the second edge portion E2 of the second pattern PT2 of the second active pattern ACT2. The sixth lower storage node contact BCx6 can be disposed on the second edge portion E2 of the fourth pattern PT4 of the first active pattern ACT1.

[0072] Again, referring to Figures 1A to 1C and Figures 2A to 2D , the fence pattern FN can be disposed on the word line WL. Specifically, the fence pattern FN can be interposed between bit lines BL that will be described later and are adjacent to each other in the first direction D1, and can be interposed between lower storage node contacts BCx that are adjacent to each other in the fourth direction D4. The lower surface of the fence pattern FN can be positioned at a higher height than the lower surface of the bit line BL.

[0073] A plurality of fence patterns FN can be provided. The plurality of fence patterns FN can be spaced apart from each other in the first direction D1 and the fourth direction D4. As an example, the fence pattern FN can include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbide (SiOC), and silicon oxynitride (SiOCN), or can be formed of at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbide (SiOC), and silicon oxynitride (SiOCN).

[0074] The buffer pattern BP can cover the upper surface of the lower storage node contact BCx and the upper surface of the fence pattern FN. The buffer pattern BP can be interposed between bit lines BL that will be described later and are adjacent to each other in the first direction D1. As an example, the buffer pattern BP can include at least one of silicon oxide, silicon nitride, and silicon oxynitride, or can be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The buffer pattern BP can be a single layer formed of a single material or a composite layer including two or more materials.

[0075] The bit line trench region BTR can be defined between adjacent lower storage node contacts BCx in the first direction D1 and between the fence patterns FN. The bit line trench region BTR can extend in the fourth direction D4 on the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2. The upper portion of the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2 can be recessed to a specific depth through the bit line trench region BTR. The bit line trench region BTR may not overlap perpendicularly with the second edge portion E2 of the first active pattern ACT1 and the second active pattern ACT2.

[0076] A plurality of bit line trench regions BTR can be provided. The plurality of bit line trench regions BTR can be spaced apart from each other in the first direction D1. The bit line trench regions BTR adjacent to each other in the first direction D1 can be spaced apart from the lower storage node contact BCx or the fence pattern FN therebetween.

[0077] The bit line BL can be disposed on the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2 in the bit line trench region BTR and can extend in the fourth direction D4. The lower surface of the bit line BL can be positioned at a lower height than the upper surface of the second edge portion E2 of each of the first active pattern ACT1 and the second active pattern ACT2. The bit line BL can be repeatedly positioned in the first direction D1 to form a plurality of bit lines BL. The bit lines BL can be spaced apart from each other in the first direction D1 and can each extend in the fourth direction D4.

[0078] The bit line BL can be a composite layer including two or more materials. As an example, the bit line BL can include a lower bit line BLx and an upper bit line BLy. The upper bit line BLy can extend in the fourth direction D4. The lower bit line BLx can be interposed between the upper bit line BLy and the first edge portion E1 of each of the first active pattern ACT1 and the second active pattern ACT2.

[0079] As an example, the lower bit line BLx may include at least one of a first barrier pattern (not shown) that prevents the diffusion of the material of the upper bit line BLy and a first silicide pattern (not shown) that improves the contact resistance between the upper bit line BLy and the first edge portion E1 of each of the first active pattern ACT1 and the second active pattern ACT2. As an example, the lower bit line BLx may include metal silicides (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and metal nitrides (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or may be formed of metal silicides (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and metal nitrides (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). As an example, the upper bit line BLy may include a metal (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0080] The bit line BL may be in contact with the first edge portion E1 of each of the first active pattern ACT1 and the second active pattern ACT2. Accordingly, the resistance between the bit line BL and the first edge portion E1 of each of the first active pattern ACT1 and the second active pattern ACT2 may be reduced, thereby improving the electrical characteristics of the semiconductor device.

[0081] Reference Figure 1B , the first bit line BL1 may extend in a fourth direction D4 on the first edge portion E1 of each of the first pattern PT1 and the third pattern PT3 of the first active pattern ACT1. The second bit line BL2 may extend in a fourth direction D4 on the first edge portion E1 of each of the first pattern PT1 and the second pattern PT2 of the second active pattern ACT2. The third bit line BL3 may extend in a fourth direction D4 on the first edge portion E1 of each of the second pattern PT2 and the fourth pattern PT4 of the first active pattern ACT1.

[0082] Again, reference Figures 1A to 1C and Figures 2A to 2D, the bit line capping pattern BCP can be disposed on the upper surface of the bit line BL in the bit line trench region BTR. The bit line capping pattern BCP can extend in the fourth direction D4 together with the bit line BL. The bit line capping pattern BCP can be repeatedly positioned in the first direction D1 to form a plurality of bit line capping patterns BCP. The plurality of bit line capping patterns BCP can be spaced apart from each other in the first direction D1. The bit line capping pattern BCP can be composed of a single layer or multiple layers. As an example, the bit line capping pattern BCP can include a first capping pattern, a second capping pattern, and a third capping pattern that are sequentially stacked on each other. As an example, each of the first capping pattern to the third capping pattern can include silicon nitride (SiN). As another example, the bit line capping pattern BCP can include capping patterns stacked in four or more layers.

[0083] The bit line spacer BSP can be disposed in the bit line trench region BTR. For example, the bit line spacer BSP can be disposed on the side surface of the bit line BL and the side surface of the bit line capping pattern BCP. The bit line spacer BSP can cover the side surface of the bit line BL, the side surface of the bit line capping pattern BCP, and the inner surface of the bit line trench region BTR. The bit line spacer BSP can also cover the side surface of the lower storage node contact BCx. The bit line spacer BSP can extend in the fourth direction D4 on the side surface of the bit line BL. For example, the upper surface of the bit line spacer BSP can be positioned at substantially the same height as the upper surface of the buffer pattern BP. The bit line spacer BSP can be repeatedly placed in the first direction D1 to form a plurality of bit line spacers BSP. The plurality of bit line spacers BSP can be spaced apart from each other in the first direction D1. In one bit line trench region BTR, two adjacent bit line spacers BSP in the first direction D1 can be spaced apart, and a bit line BL is interposed therebetween. As an example, the bit line spacer BSP can include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbide (SiOC), and silicon oxynitride (SiOCN), or can be formed of at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbide (SiOC), and silicon oxynitride (SiOCN). The bit line spacer BSP can be a single layer formed of a single material or a composite layer containing two or more materials.

[0084] The molded pattern MP may be disposed on the buffer pattern BP, the bit line capping pattern BCP, and the bit line spacer BSP. The molded pattern MP may surround the landing pad LP which will be described later. The molded pattern MP may be interposed between adjacent landing pads LP. When observed in a two-dimensional view, the molded pattern MP may have a grid shape including the contact hole CH which will be described later. As an example, the molded pattern MP may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbide (SiOC), and silicon oxynitride (SiOCN), or may be formed of at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbide (SiOC), and silicon oxynitride (SiOCN).

[0085] The contact hole CH may be disposed on the second edge portion E2 of each of the first active pattern ACT1 and the second active pattern ACT2. The contact hole CH may penetrate the molded pattern MP and the buffer pattern BP. The upper portions of the lower storage node contact BCx, the bit line capping pattern BCP, and the bit line spacer BSP may be recessed to a specific depth through the contact hole CH. The contact hole CH may be further displaced from the lower storage node contact BCx in the first direction D1 (or in the direction opposite to the first direction D1). A part of the contact hole CH may overlap perpendicularly with the bit line BL. A part of the contact hole CH may overlap perpendicularly with the lower storage node contact BCx. The contact hole CH may be repeatedly positioned to form a plurality of contact holes CH arranged in rows in the first direction D1 and in a zigzag shape in the fourth direction D4.

[0086] The upper storage node contact BCy may be disposed in the contact hole CH. The upper storage node contact BCy may be disposed on and in contact with the lower storage node contact BCx. As an example, the upper storage node contact BCy may include at least one of silicon (e.g., polysilicon containing impurities) and metals (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or may be formed of at least one of silicon (e.g., polysilicon containing impurities) and metals (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). Thus, in the case where two upper storage node contacts BCy and two lower storage node contacts BCx are shown Figure 2AIn this case, the upper storage node contact BCy on the left side can be electrically connected to the second edge portion E2 of the corresponding first active pattern ACT1 through the lower storage node contact BCx on the left side, and the upper storage node contact BCy on the right side can be electrically connected to the second edge portion E2 of the corresponding second active pattern ACT2 through the lower storage node contact BCx on the right side. The upper storage node contact BCy can be further shifted from the lower storage node contact BCx in the first direction D1 (or in the direction opposite to the first direction D1). A part of the upper storage node contact BCy can overlap perpendicularly with the bit line BL. The upper storage node contact BCy can contact the bit line covering pattern BCP and the bit line spacer BSP. The upper storage node contact BCy and the lower storage node contact BCx can together constitute the storage node contact BC.

[0087] The upper storage node contact BCy can be repeatedly positioned to form a plurality of upper storage node contacts BCy. Each of the plurality of upper storage node contacts BCy can be disposed in a corresponding contact hole CH. The upper storage node contacts BCy can be spaced apart from each other in the first direction D1 and the fourth direction D4. The upper storage node contacts BCy can be arranged in a line in the first direction D1 together with the contact holes CH, and can be arranged in a zigzag shape in the fourth direction D4.

[0088] The landing pad LP can be provided in the contact hole CH and on the upper storage node contact BCy. The landing pad LP can overlap perpendicularly with the upper storage node contact BCy. As an example, the landing pad LP can include at least one metal (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or can be formed of at least one metal (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). Therefore, the landing pad LP can be electrically connected to the second edge portions E2 of the corresponding active patterns ACT1 and ACT2 through the corresponding upper storage node contact BCy and the corresponding lower storage node contact BCx. The landing pad LP can be repeatedly placed to form a plurality of landing pads LP. The plurality of landing pads LP can be spaced apart from each other in the first direction D1 and the fourth direction D4.

[0089] As an example, a second silicide pattern SC may be further provided between the landing pad LP and the upper storage node contact BCy. As an example, the second silicide pattern SC may include a metal silicide (e.g., a silicide such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or may be formed of a metal silicide (e.g., a silicide such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). As an example, a second barrier pattern (not shown) may be interposed between the landing pad LP and other components and may prevent the diffusion of the landing pad LP material. As an example, the second barrier pattern may include a metal nitride (e.g., a nitride such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or may be formed of a metal nitride (e.g., a nitride such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0090] A data storage pattern DSP may be disposed on the landing pad LP. The data storage pattern DSP may be repeatedly placed to form a plurality of data storage patterns DSP. The plurality of data storage patterns DSP may be spaced apart from each other in a first direction D1 and a fourth direction D4. Each data storage pattern DSP may be electrically connected to a second edge portion E2 of a corresponding active pattern ACT1 and ACT2 through a corresponding landing pad LP and a corresponding storage node contact BC.

[0091] The data storage pattern DSP may be, for example, a capacitor including a lower electrode, a dielectric layer, and an upper electrode. In this case, the semiconductor device according to the inventive concept may be a dynamic random access memory (DRAM). As an example, the data storage pattern DSP may include a magnetic tunnel junction pattern. In this case, the semiconductor device according to the inventive concept may be a magnetic random access memory (MRAM). As an example, the data storage pattern DSP may include a phase change material or a variable resistance material. In this case, the semiconductor device according to the inventive concept may be a phase change random access memory (PRAM) or a resistive random access memory (ReRAM). However, this is merely an example and the inventive concept is not limited thereto, and the data storage pattern DSP may include various structures and / or materials capable of storing data.

[0092] Hereinafter, Figures 3 to 14D various embodiments of the inventive concept will be described. To simplify the description, descriptions of content overlapping with the above will be omitted, and the description will focus on the differences from the above.

[0093] Figure 3 is a top view of a semiconductor device according to some embodiments of the inventive concept.

[0094] Reference Figure 3, when observed in a top view, the contours of the first active pattern ACT1 and the second active pattern ACT2 can be different from those described by the reference Figures 1A to 1C and Figures 2A to 2D described.

[0095] Each first active pattern ACT1 can extend in a waveform in the second direction D2. Each second active pattern ACT2 can extend in a waveform in the third direction D3.

[0096] Opposite sides of each first active pattern ACT1 can have a curved contour. Opposite sides of each second active pattern ACT2 can have a curved contour. Opposite sides of each first active pattern ACT1 can extend in a waveform in the second direction D2. Opposite sides of each second active pattern ACT2 can extend in a waveform in the third direction D3.

[0097] Figure 4A and Figure 4B are cross-sectional views corresponding to the lines A-A' and D-D' of Figure 1A respectively.

[0098] Reference Figure 4A and Figure 4B , the lower surface BCxb of the lower storage node contact BCx can be positioned at a lower height compared to the upper surface E2a of the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2. The lower storage node contact BCx can cover the upper portions of the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2. For example, the lower storage node contact BCx can contact the upper surface and the side surfaces of the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2. Thus, compared with the semiconductor device of Figures 2A to 2D , the contact area between the lower storage node contact BCx and the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2 can be increased. As a result, the lower storage node contact BCx can be electrically connected to the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2 with an increased contact area, and the electrical characteristics of the semiconductor device can be improved.

[0099] Figure 5 is a cross-sectional view corresponding to the line C-C' in Figure 1A .

[0100] Reference Figure 5, the word line WL can further extend into the bit line BL. As an example, the gate capping pattern GC can further extend into the bit line BL. The gate capping pattern GC can be interposed between the lower bit lines BLx in the fourth direction D4. The upper surface W1a of the word line WL (e.g., the upper surface of the gate capping pattern GC) can be positioned at a higher height than the upper surface of the lower bit line BLx. Accordingly, the separation distance between the upper bit line Bly and the gate electrode GE can be increased, thereby reducing the electrical interference between the upper bit line Bly and the gate electrode GE. As a result, the electrical characteristics of the semiconductor device can be improved.

[0101] Figure 6 is a top view of a semiconductor device showing some embodiments according to the inventive concept. Figures 7A to 7C are respectively related to Figure 6 cross-sectional views corresponding to lines A-A', C-C', and D-D' of.

[0102] Reference Figures 6 to 7C , the upper surface of each of the first edge portion E1 and the second edge portion E2 of the first active pattern ACT1 and the second active pattern ACT2 can be positioned at a higher height than the upper surface of the device isolation pattern STI.

[0103] The active pad XO can be disposed on the upper surface of the device isolation pattern STI and surround and cover the side surfaces of the first edge portion E1 and the second edge portion E2 of the first active pattern ACT1 and the second active pattern ACT2. The active pad XO can include a first active pad XO1 and a second active pad XO2. The first active pad XO1 surrounds and covers the side surface of the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2, and the second active pad XO2 surrounds and covers the side surface of the second edge portion E2 of the first active pattern ACT1 and the second active pattern ACT2. The active pad XO can include an impurity region doped with an impurity (e.g., an n-type or p-type impurity). The impurity region of the active pad XO and the impurity regions of the first active pattern ACT1 and the second active pattern ACT2 can constitute the source-drain region and / or the channel region of the transistor. Accordingly, when observed in a two-dimensional view, the area of the source-drain region of the transistor can be increased. For example, the active pad XO can include the same material as the first active pattern ACT1 and the second active pattern ACT2. As an example, the active pad XO can include at least one of silicon (e.g., single-crystalline silicon), germanium, and silicon germanium doped with an impurity (e.g., an n-type or p-type impurity), or can be formed of at least one of silicon (e.g., single-crystalline silicon), germanium, and silicon germanium doped with an impurity (e.g., an n-type or p-type impurity).

[0104] A pad insulating pattern XI may be disposed on the upper surface of the device isolation pattern STI. The pad insulating pattern XI may be interposed between the first active pad XO1 and the second active pad XO2. The pad insulating pattern XI may include an insulating material or may be formed of an insulating material. As an example, the pad insulating pattern XI may include at least one of silicon oxide (SiO2) and silicon nitride (SiN), or may be formed of at least one of silicon oxide (SiO2) and silicon nitride (SiN).

[0105] The bit line BL may be in contact with the first active pad XO1. The bit line BL may be electrically connected to the first active pad XO1 and the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2. The first active pad may be configured to increase the contact area between the bit line BL and the source-drain region, thereby reducing the contact resistance.

[0106] The lower storage node contact BCx may be in contact with the second active pad XO2. The storage node contact BC may be electrically connected to the second active pad XO2 and the second edge portion E2 of the first active pattern ACT1 and the second active pattern ACT2. The second active pad XO2 may be configured to increase the contact area between the storage node contact BC and the source-drain region, thereby reducing the contact resistance between the storage node contact BC and the source-drain region.

[0107] Figure 8 is a top view of a semiconductor device showing some embodiments according to the inventive concept. Figure 9A and Figure 9B are cross-sectional views corresponding to lines B-B' and D-D' of Figure 8 respectively.

[0108] Referring to Figures 8 to 9B , the fence pattern FN may not be provided. The word line WL may extend in the first direction D1 and the seventh direction D7 perpendicular to the lower surface of the substrate 100 between the lower storage node contacts BCx adjacent to each other in the fourth direction D4. The second upper surface W2a of the word line WL may be positioned at substantially the same height as the upper surface of the lower storage node contact BCx. The word line WL may be in contact with the buffer pattern BP. The word lines WL may be spaced apart in the fourth direction D4, and the lower storage node contacts BCx are interposed between the word lines WL.

[0109] The bit line trench region BTR may be provided in the word line WL (e.g., in the gate capping pattern GC). The bit line trench region BTR may cross the word line WL in the fourth direction D4. In one word line WL, the bit line trench regions BTR may be spaced apart in the first direction D1.

[0110] Figure 10 and Figure 13is a top view of a semiconductor device showing some embodiments according to the inventive concept. Figure 11A and Figure 11B are cross-sectional views corresponding to lines A-A' and D-D' of Figure 10 respectively. Figure 12A and Figure 12B are cross-sectional views corresponding to lines A-A' and D-D' of Figure 10 respectively. Figures 14A to 14D are cross-sectional views corresponding to lines A-A', B-B', C-C' and D-D' of Figure 13 respectively.

[0111] Referring to Figures 10 to 14D , a lower landing pad LPx may be disposed on the lower storage node contact BCx. As an example, the lower landing pad LPx may be in contact with the upper surface of the lower storage node contact BCx. Referring to Figures 10 to 11B and Figures 13 to 14D , the lower landing pad LPx may be interposed between the buffer pattern BP and the lower storage node contact BCx. The lower landing pad LPx may be interposed between adjacent bit line covering patterns BCP in the first direction D1. The lower landing pad LPx may be interposed between adjacent fence patterns FN in the fourth direction D4.

[0112] The lower landing pads LPx may be repeatedly positioned to form a plurality of lower landing pads LPx. The plurality of lower landing pads LPx may be spaced apart from each other in the first direction D1 and the fourth direction D4. The lower landing pads LPx adjacent to each other in the first direction D1 may be spaced apart from each other, and the bit line covering pattern BCP is interposed between the lower landing pads LPx adjacent to each other in the first direction D1. The lower landing pads LPx adjacent to each other in the fourth direction D4 may be spaced apart, and the fence pattern FN is interposed between the lower landing pads LPx adjacent to each other in the fourth direction D4.

[0113] Referring to Figures 10 to 11B , the upper landing pad LPy may fill the interior of the contact hole CH. The upper storage node contact BCy and the second silicide pattern SC may not be disposed in the contact hole CH. The upper landing pad LPy may be in contact with the bit line covering pattern BCP and the bit line spacer BSP. The upper landing pad LPy may contact the lower landing pad LPx at a height lower than the lower surface of the molding pattern MP.

[0114] Referring to Figure 10 , Figure 12A and Figure 12B, the molding pattern MP and the contact hole CH may not be provided. The upper landing pad LPy may be provided on the lower landing pad LPx. The upper landing pad LPy may be shifted in the first direction D1 (or the opposite direction) compared to the lower landing pad LPx. A part of the upper landing pad LPy may overlap perpendicularly with the bit line BL. The upper landing pad LPy may be repeatedly positioned to form a plurality of upper landing pads LPy. The upper landing pads LPy may be arranged in a line in the first direction D1 and in a zigzag shape in the fourth direction D4.

[0115] The upper landing pad LPy and the lower landing pad LPx may constitute the landing pad LP. The landing pad LP may include a conductive material or may be formed of a conductive material.

[0116] The filling pattern FL may surround the upper landing pad LPy. The filling pattern FL may be interposed between adjacent upper landing pads LPy. When observed in a top view, the filling pattern FL may have a grid shape including holes penetrated by the upper landing pads LPy. As an example, the filling pattern FL may include at least one of silicon nitride, silicon oxide, and silicon oxynitride, or may be formed of at least one of silicon nitride, silicon oxide, and silicon oxynitride. As an example, the filling pattern FL may include an empty space containing an air layer (i.e., an air gap). The term "air" as discussed herein may refer to the atmosphere or other gases that may be present during the manufacturing process.

[0117] Reference Figure 13 and Figures 14A to 14D , the molding pattern MP may not be provided. The interlayer insulating layer ILD may be provided on the entire surface of the substrate 100. Specifically, the interlayer insulating layer ILD may be provided on the bit line covering pattern BCP and the buffer pattern BP. The interlayer dielectric layer ILD may include at least one of silicon nitride, silicon oxide, or silicon oxynitride, or may be formed of at least one of silicon nitride, silicon oxide, or silicon oxynitride. As an example, the interlayer insulating layer ILD may include an empty area. When observed in a top view, the contact hole CH may penetrate the interlayer insulating layer ILD, and the interlayer insulating layer ILD may have a grid shape including the contact hole CH.

[0118] The lower electrode BE may be provided on the lower landing pad LPx. The lower electrode BE may include a lower part BEx below the contact height CLV and an upper part BEy above the contact height CLV. The contact height CLV is defined as the height at which the upper surface of the interlayer dielectric layer ILD is located. For example, the lower part BEx and the upper part BEy of the lower electrode BE may be divided from each other at the contact height CLV, and there is no interface at the contact height CLV, but it is not limited thereto.

[0119] The lower portion BEx of the lower electrode BE may be disposed in the contact hole CH. The lower portion BEx of the lower electrode BE may fill the interior of the contact hole CH. The lower portion BEx of the lower electrode BE may contact the bit line capping pattern BCP, the bit line spacer BSP, and the lower landing pad LPx. The lowermost surface of the lower portion BEx of the lower electrode BE may be positioned at a lower height than the upper surface of the lower landing pad LPx.

[0120] The upper portion BEy of the lower electrode BE may be disposed on the lower portion BEx of the lower electrode BE. For example, the upper portion BEy of the lower electrode BE may be columnar in shape. As an example, although not shown, the upper portion BEy of the lower electrode BE may be in the shape of a hollow cylinder with one end closed. According to some embodiments, although not shown, the upper portion BEy of the lower electrode BE may have a columnar lower portion and a hollow cylinder-shaped upper portion.

[0121] The lower electrode BE may be repeatedly positioned to form a plurality of lower electrodes BE. The lower electrodes BE may be spaced apart from each other in a first direction D1 and a fourth direction D4. For example, when viewed in a top view, the lower electrodes BE may be arranged in a honeycomb shape. Specifically, in the case where one lower electrode BE is at the center, six lower electrodes BE may be arranged in a hexagonal arrangement around the one lower electrode BE. However, the inventive concept is not limited thereto.

[0122] An upper electrode TE may be disposed on the lower electrode BE. Specifically, the upper electrode TE may cover the upper surface of the upper portion BEy of the lower electrode BE, and may surround and cover the side surface of the upper portion BEy of the lower electrode BE. The upper electrode TE may fill the space between the upper portions BEy of the lower electrode BE.

[0123] Each of the lower electrode BE and the upper electrode TE may include a conductive material or may be formed of a conductive material. As an example, each of the lower electrode BE and the upper electrode TE may include at least one of the following or may be formed of at least one of the following: silicon (Si) doped with impurities, silicon germanium (SiGe) doped with impurities, a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), titanium silicon nitride (e.g., TiSiN), titanium aluminum nitride (e.g., TiAlN), tantalum aluminum nitride (e.g., TaAlN), a conductive oxide (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), LSCo), and a metal silicide. Each of the lower electrode BE and the upper electrode TE may be a single layer formed of a single material or a composite layer including two or more materials.

[0124] The dielectric layer DL may be interposed between each upper BEy of the lower electrode BE and the upper electrode TE, and between the upper electrode TE and the interlayer insulating layer ILD. The dielectric layer DL may conformally cover the upper BEy of the lower electrode BE. As an example, the dielectric layer DL may include at least one of metal oxides such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2 and perovskite-structured dielectric materials such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT, or may be formed of at least one of metal oxides such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2 and perovskite-structured dielectric materials such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT.

[0125] Hereinafter, a method of manufacturing a semiconductor device according to some embodiments of the inventive concept will be described. To simplify the description, descriptions of overlapping content with the above will be omitted, and the description will focus on the differences from the above. Figures 15 to 31B

[0126] Figures 15 to 20D Figures 15 to 20D is a diagram showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Specifically, Figure 15 , Figure 17 and Figure 19 is a top view showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Figure 16A , Figure 18A and Figure 20A are cross-sectional views corresponding to line A-A' of Figure 15 , Figure 17 and Figure 19 respectively. Figure 16B , Figure 18B and Figure 20B are cross-sectional views corresponding to line B-B' of Figure 15 , Figure 17 and Figure 19 respectively. Figure 18C and Figure 20C are cross-sectional views corresponding to line C-C' of Figure 17 and Figure 19 respectively. Figure 18D and Figure 20D are cross-sectional views corresponding to line D-D' of Figure 17 and Figure 19 respectively.

[0127] Refer to Figures 15 to 16B, the substrate 100 can be fabricated. A first active mask pattern MK1 can be formed on the substrate 100. Each first active mask pattern MK1 can be formed to extend longitudinally in the second direction D2. When observed in a two-dimensional view, each first active mask pattern MK1 can be formed to have the same / similar shape as the first active pattern ACT1 described in reference Figures 1A to 2D . The arrangement of the first active mask patterns MK1 can be the same / similar to the arrangement of the first active pattern ACT1 described in reference Figures 1A to 2D .

[0128] Reference Figures 17 to 18D can be used to perform a removal process on the substrate 100 using the first active mask pattern MK1 as an etching mask. Thus, the first active pattern ACT1 can be formed on the substrate 100.

[0129] A second active mask pattern (not shown) can be formed on the substrate 100. Each second active mask pattern can be formed to extend longitudinally in the third direction D3. When observed in a top view, the second active mask pattern can be formed to be adjacent to the first active pattern ACT1 in the first direction D1. When observed in a top view, each second active mask pattern can have the same / similar shape as the second active pattern ACT2 described in reference Figures 1A to 2D . The arrangement of the second active mask pattern can be the same / similar to the arrangement of the second active pattern ACT2 described in reference Figures 1A to 2D .

[0130] The second active mask pattern can be used as an etching mask to perform a removal process on the substrate 100. Thus, the second active pattern ACT2 can be formed on the substrate 100.

[0131] Depending on the profiles and arrangements of the first active mask pattern MK1 and the second active mask pattern, the profiles of the first active pattern ACT1 and the second active pattern ACT2 can be formed in various ways. For example, depending on the profiles and arrangements of the first active mask pattern MK1 and the second active mask pattern, the first active pattern ACT1 and the second active pattern ACT2 can have the profiles as shown in Figure 3 .

[0132] A device isolation pattern STI can be formed on the substrate 100 to surround each of the first active pattern ACT1 and the second active pattern ACT2.

[0133] The word line WL can be formed to cross the first active pattern ACT1, the second active pattern ACT2, and the device isolation pattern STI. Forming the word line WL can include: forming a mask pattern on the first active pattern ACT1, the second active pattern ACT2, and the device isolation pattern STI; using the mask pattern to perform an anisotropic etching process to form a word line trench region WTR that crosses the first active pattern ACT1, the second active pattern ACT2, and the device isolation pattern STI; and filling the word line trench region WTR with the word line WL. The word line WL can be formed on the central portion CA of the first active pattern ACT1 and the second active pattern ACT2, and can be formed between the first edge portion E1 and the second edge portion E2.

[0134] The word line trench region WTR can be formed to extend in a waveform in the first direction D1. Accordingly, the word line WL filling the word line trench region WTR can be formed to have a waveform extending in the first direction D1.

[0135] The formation of the word line WL can include, for example: conformally depositing a gate dielectric pattern GI on the inner surface of the word line trench region WTR; filling the inner space of the word line trench region WTR with a conductive layer; forming a gate electrode GE on the conductive layer by a planarization process such as an etch-back process and / or a polishing process; and filling the remaining portion of the word line trench region WTR on the gate electrode GE to form a gate capping pattern GC.

[0136] The lower storage node contact BCx and the fence pattern FN can be formed to be alternately arranged on the substrate 100 in the fourth direction D4. The lower storage node contact BCx can be formed to extend in the first direction D1, and can be disposed on the second edge portion E2 of the first active pattern ACT1 and the second active pattern ACT2. The fence pattern FN can be formed to extend in the first direction D1, and can be disposed on the central portion CA of the first active pattern ACT1 and the second active pattern ACT2. For example, the formation of the lower storage node contact BCx and the fence pattern FN can include: forming a lower storage node contact layer (not shown) to cover the entire surface of the substrate 100; and forming the fence pattern FN such that the lower storage node contact layer is divided into a plurality of lower storage node contacts BCx spaced apart from each other in the fourth direction D4. Thereafter, a buffer pattern BP can be formed to cover the entire surface of the substrate 100.

[0137] As an example, although not shown in the drawings, after forming the word line WL and before forming the lower storage node contact layer, a removal process may be performed on the upper portions of each of the device isolation pattern STI and the gate dielectric pattern GI. Each of the device isolation pattern STI and the gate dielectric pattern GI may have an etching selectivity with respect to surrounding components (e.g., the active patterns ACT1 and ACT2 and the gate capping pattern GC, etc.). Thus, when the removal process continues, the surrounding components may not be removed or may be removed to a small extent. Accordingly, the upper side surfaces of the first edge portions E1 and the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2 may be exposed to the outside. Thereafter, as described above, the lower surface of the lower storage node contact BCx may be formed to be positioned at a lower height than the upper surface of each of the first edge portions E1 and the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2. Thus, the semiconductor device may be formed to have the characteristics described with reference to Figure 4A and Figure 4B description.

[0138] A bit line mask pattern BMP may be formed on the buffer pattern BP. The bit line mask pattern BMP may include a plurality of mask patterns spaced apart from each other in a first direction D1 and each extending in a fourth direction D4. The bit line mask pattern BMP may be formed on the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2.

[0139] Reference Figures 19 to 20D , a bit line trench region BTR may be formed by an etching process using the bit line mask pattern BMP as an etching mask. By the etching process, the buffer pattern BP, the lower storage node contact BCx, the fence pattern FN, the upper portion of the word line WL, and the upper portion of the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2 may be removed, and the bit line trench region BTR may be defined in these removed regions. The bit line trench region BTR may be formed on the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2. The upper surface of the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2 may be exposed to the outside from the inner surface of the bit line trench region BTR.

[0140] A lower storage node contact BCx can be divided into a plurality of lower storage node contacts BCx spaced apart from each other in a first direction D1 through a bit line trench region BTR. A fence pattern FN can be divided into a plurality of fence patterns FN spaced apart from each other in the first direction D1 through the bit line trench region BTR. During the formation of the bit line trench region BTR, a part of the upper surface of the word line WL can be recessed. Accordingly, the upper surface of the word line WL can be divided into a first upper surface W1a and a second upper surface W2a.

[0141] For example, although not shown in the drawings, when forming the bit line trench region BTR, the gate capping pattern GC can be formed to protrude more in a seventh direction D7 than the gate dielectric pattern GI. This can be adjusted using the etching selectivity of the gate capping pattern GC with respect to surrounding components (e.g., active patterns ACT1 and ACT2 and the gate dielectric pattern GI, etc.). When the bit line trench region BTR is formed, the gate capping pattern GC can be removed to a lesser extent than the surrounding components, and thus, the gate capping pattern GC can protrude more than the surrounding components, and the semiconductor device can be formed to have the characteristics Figure 5 described in the reference.

[0142] A bit line spacer BSP can be formed inside the bit line trench region BTR. The bit line spacer BSP can be formed to cover the inner surface of the bit line trench region BTR. As an example, a pair of bit line spacers BSP can cover opposite inner sides of the bit line trench region BTR, respectively. The bit line spacer BSP may not cover at least a part of a first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2. For example, between the pair of bit line spacers BSP, the upper surface of the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2 can be exposed to the outside.

[0143] A lower bit line BLx may be formed on an exposed upper surface of a first edge portion E1 of a first active pattern ACT1 and a second active pattern ACT2. An upper bit line BLy may be formed on the lower bit line BLx. The lower bit line BLx and the upper bit line BLy may constitute a bit line BL. As an example, the lower bit line BLx may be formed by selective epitaxial growth (SEG) using the upper surface of the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2 as a seed layer. Through the SEG process, the lower bit line BLx may be selectively grown on the upper surface of the first edge portion E1 of the first active pattern ACT1 and the second active pattern ACT2. For example, the lower bit line BLx and the upper bit line BLy may be formed in sequence. As an example, after forming the bit line BL, a separate process may be performed to distinguish the lower bit line BLx from the upper bit line BLy. Thereafter, a bit line capping pattern BCP may be formed on the bit line BL to fill a remaining portion of each bit line trench region BTR. A molding pattern MP may be formed to cover an entire surface of the substrate 100.

[0144] Reference Figures 1A to 2D , a contact hole CH may be formed to penetrate the molding pattern MP. For example, the formation of the contact hole CH may include: forming a mask pattern (not shown) including a hole (not shown) to cover the upper surface of the molding pattern MP; and performing a removal process on the molding pattern MP using the mask pattern as an etch mask. The contact hole CH may be formed to be arranged in a line in a first direction D1 or to be arranged in a zigzag shape in a fourth direction D4.

[0145] An upper storage node contact BCy may be formed inside each contact hole CH. A second silicide pattern SC may be formed in the contact hole CH and may be disposed on the upper storage node contact BCy. As an example, a second barrier pattern (not shown) may be further formed together with the second silicide pattern SC. Thereafter, a landing pad LP may be formed to fill a remaining portion of each contact hole CH. An upper surface of the landing pad LP may be positioned at substantially the same height as an upper surface of the molding pattern MP and may be coplanar. Thereafter, a data storage pattern DSP may be formed on each landing pad LP.

[0146] Figures 21 to 24C is a diagram showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Specifically, Figure 21 and Figure 23 are top views showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Figure 22A and Figure 24A are cross-sectional views corresponding to a line A-A' of Figure 21 and Figure 23 respectively. Figure 22B and Figure 24Bare cross-sectional views corresponding to lines C-C' of Figure 21 and Figure 23 respectively. Figure 22C and Figure 24C are cross-sectional views corresponding to lines D-D' of Figure 21 and Figure 23 respectively.

[0147] Referring to Figures 21 to 22C after forming the device isolation pattern STI described in reference Figures 17 to 18D a removal process for the device isolation pattern STI can be performed. When the removal process is performed, upper side surfaces of first edge portions E1 and second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2 can be exposed to the outside.

[0148] The active pad XO can be formed to surround the upper side surfaces of the first edge portions E1 and the second edge portions E2 of the first active pattern ACT1 and the second active pattern ACT2. Thereafter, a pad insulating pattern XI can be formed on the device isolation pattern STI.

[0149] Referring to Figures 23 to 24C the word line WL can be formed to cross the first active pattern ACT1, the second active pattern ACT2, the device isolation pattern STI, and the active pad XO. The formation of the word line WL can be the same / similar to the formation of the word line WL described in reference Figures 17 to 18D During the formation of the word line WL, the active pad XO can be divided into a first active pad XO1 and a second active pad XO2.

[0150] Thereafter, a semiconductor device described in reference Figures 6 to 7C can be formed using the above-described semiconductor device manufacturing method.

[0151] Figures 25 to 26B is a diagram showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Specifically, Figure 25 is a top view showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Figure 26A is a cross-sectional view corresponding to line B-B' of Figure 25 respectively. Figure 26B is a cross-sectional view corresponding to line D-D' of Figure 25 respectively.

[0152] Referring to Figures 25 to 26B after forming the device isolation pattern STI described in reference Figures 17 to 18D before forming the word line WL, a lower storage node contact layer (not shown) can be formed on the entire surface of the substrate 100.

[0153] Thereafter, a word line WL may be formed to cross the first active pattern ACT1, the second active pattern ACT2, and the device isolation pattern STI. The word line WL may be formed to penetrate the lower storage node contact layer. Accordingly, a plurality of lower storage node contacts BCx spaced apart from each other in a fourth direction D4 and all extending in a first direction D1 may be formed. Formation of a fence pattern FN for spacing the lower storage node contacts BCx apart in the fourth direction D4 may be omitted.

[0154] Thereafter, the semiconductor device described with reference to Figures 8 to 9B may be formed using the above-described semiconductor device manufacturing method.

[0155] Figures 27 to 28B is a diagram illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Specifically, Figure 27 is a top view illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Figure 28A is corresponding to Figure 27 section view taken along line A-A' of Figure 28B is corresponding to Figure 27 section view taken along line D-D' of

[0156] Referring to Figures 27 to 28B after forming the word line WL described with reference to Figures 17 to 18D a lower storage node contact layer (not shown) and a lower landing layer (not shown) may be formed to be sequentially stacked on the substrate 100.

[0157] A fence pattern FN may be formed to extend in the first direction D1 and may be disposed on the word line WL. The fence pattern FN may be formed to penetrate the lower storage node contact layer (not shown) and the lower landing layer (not shown). Accordingly, lower storage node contacts BCx spaced apart from each other in the fourth direction D4 and all extending in the first direction D1 and lower landing pads LPx spaced apart from each other in the fourth direction D4 and all extending in the first direction D1 may be formed. Thereafter, a buffer pattern BP may be formed on the upper landing pads LPx.

[0158] A bit line trench region BTR, a bit line spacer BSP, a bit line BL, and a bit line capping pattern BCP may be formed in sequence, and forming the bit line trench region BTR, the bit line spacer BSP, the bit line BL, and the bit line capping pattern BCP may be similar to that described with reference to Figures 19 to 20D When forming the bit line trench region BTR, one lower storage node contact BCx and one lower landing pad LPx may be divided into lower storage node contacts BCx spaced apart from each other in the first direction D1 and lower landing pads LPx spaced apart from each other in the first direction D1. Thereafter, a molding pattern MP may be formed on the entire surface of the substrate 100.

[0159] Referring again to Figures 10 to 11B , the contact hole CH may be formed to penetrate the molded pattern MP. Forming the contact hole CH may be similar to the formation described in reference Figures 1A to 1C and Figures 2A to 2D .

[0160] Thereafter, the processes of forming the upper storage node contact BCy and the second silicide pattern SC described in reference Figures 1A to 1C and Figures 2A to 2D may be omitted.

[0161] Each upper landing pad LPy may be formed to fill the remaining portion of the corresponding contact hole CH in the contact hole CH. A data storage pattern DSP may be formed on each upper landing pad LPy.

[0162] Figures 29 to 30B is a diagram illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Specifically, Figure 29 is a top view illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Figure 30A is Figure 29 a cross-sectional view corresponding to line A-A' of Figure 30B is Figure 29 a cross-sectional view corresponding to line D-D' of

[0163] Referring to Figures 29 to 30B , after forming the bit line capping pattern BCP described in reference Figures 27 to 28B , an upper landing pad layer LPL may be formed to cover the entire surface of the substrate 100. Forming the buffer pattern BP described in reference Figures 27 to 28B and forming the upper storage node contact BCy and the second silicide pattern SC described in reference Figures 1A to 1C and Figures 2A to 2D may be omitted.

[0164] A landing pad mask pattern LMP may be formed on the upper landing pad layer LPL. When observed in a top view, the position of the landing pad mask pattern LMP may be similar to the position of the contact hole CH described in reference Figures 1A to 1C and Figures 2A to 2D . The landing pad mask pattern LMP may be arranged in a line in the first direction D1 and in a zigzag shape in the fourth direction D4.

[0165] Referring again to Figure 10 , Figure 12A and Figure 12B , the landing pad mask pattern LMP may be used as an etching mask to remove the upper landing pad layer LPL to form a plurality of upper landing pads LPy.

[0166] Thereafter, a fill pattern FIL may be formed in a region where the upper landing pad LPy has been removed. The fill pattern FIL may be formed to surround each upper landing pad LPy. A data storage pattern DSP may be formed on each upper landing pad LPy.

[0167] Figure 31A and Figure 31B are diagrams illustrating methods of manufacturing semiconductor devices according to some embodiments of the inventive concept. Specifically, Figure 31A is Figure 27 a cross-sectional view corresponding to line A-A' of Figure 31B is Figure 27 a cross-sectional view corresponding to line D-D' of

[0168] Referring to Figure 31A and Figure 31B after forming the bit line capping pattern BCP described with reference to Figures 27 to 28B an interlayer insulating layer ILD may be formed on the entire surface of the substrate 100.

[0169] Referring again to Figures 13 to 14D contact holes CH may be formed to penetrate the interlayer insulating layer ILD. Forming the contact holes CH may be similar to the formation described with reference to Figures 1A to 1C and Figures 2A to 2D The formation of each of the upper storage node contact BCy, the second silicide pattern SC, and the landing pad LP described with reference to

[0170] forming the Figures 1A to 1C and Figures 2A to 2D may be omitted.

[0171] A lower electrode BE may be formed on the contact holes CH. Forming the lower electrode BE may include: forming a lower electrode layer (not shown) that fills the contact holes CH and covers the upper surface of the interlayer insulating layer ILD; and removing a portion of the lower electrode layer to form the lower electrode BE. The lower electrode BE may include a lower portion BEx and an upper portion BEy.

[0172] A dielectric layer DL may be formed to conformally cover the upper surface of the interlayer insulating layer ILD and the upper portion BEy of the lower electrode BE. Thereafter, an upper electrode TE may be formed between and on the upper portions BEy of the lower electrode BE.

[0173] According to some embodiments, the first active pattern and the second active pattern may be arranged side by side in the first direction (or the opposite direction) or the fourth direction (or the opposite direction), thereby simplifying the arrangement of components in the semiconductor device. Accordingly, the difficulty of patterning for forming the semiconductor device may be reduced, thereby facilitating the manufacture of the semiconductor device. Additionally, such an arrangement of the first active pattern and the second active pattern may be desirable for the integration of the semiconductor device.

[0174] According to some embodiments, a word line may extend in a waveform along a first direction between a first edge portion and a second edge portion of each of a first active pattern and a second active pattern. Accordingly, a contact area between the first edge portion of the first active pattern and a bit line contact and a contact area between the second edge portion of the first active pattern and a lower storage node contact may be increased. In addition, a contact area between the first edge portion of the second active pattern and the bit line and a contact area between the second edge portion of the second active pattern and the lower storage node contact may be increased. As a result, a resistance between each contact component may be reduced, and electrical characteristics of a semiconductor device may be improved.

[0175] Although the embodiments have been described above, those skilled in the art will understand that many modifications and variations have been made without departing from the spirit and scope of the inventive concept defined in the appended claims. Accordingly, the exemplary embodiments of the inventive concept should be considered illustrative rather than restrictive in all respects, and the spirit and scope of the inventive concept are indicated by the appended claims.

Claims

1. A semiconductor device, comprising: a substrate provided with a first active pattern and a second active pattern, wherein the first active pattern and the second active pattern are adjacent to each other in a first direction, each of the first active pattern and the second active pattern includes a first edge portion, a second edge portion, and a central portion located between the first edge portion and the second edge portion, and the first direction is parallel to an upper surface of the substrate; a word line having a waveform extending in the first direction and including a first portion overlapping a central portion of the first active pattern and a second portion overlapping a central portion of the second active pattern; a first bit line disposed on the first edge portion of the first active pattern; and a first storage node contact disposed on the second edge portion of the first active pattern, wherein the first active pattern extends longitudinally in a second direction intersecting the first direction, and the second direction is parallel to the upper surface of the substrate, wherein the second active pattern extends longitudinally in a third direction intersecting the first direction and the second direction, and the third direction is parallel to the upper surface of the substrate, and Wherein, the first active pattern and the second active pattern are symmetrical in shape.

2. The semiconductor device according to claim 1, in, The first edge portion of the first active pattern, the first portion of the word line, and the second edge portion of the first active pattern are sequentially disposed along the second direction.

3. The semiconductor device according to claim 2, further comprising: a second bit line disposed on the first edge portion of the second active pattern, The first edge portion of the first active pattern and the second edge portion of the second active pattern are spaced apart from each other by a first distance in the first direction.

4. The semiconductor device according to claim 3, further comprising: a second storage node contact disposed on the second edge portion of the second active pattern, wherein the second edge portion of the first active pattern is spaced apart from the first edge portion of the second active pattern by a second distance in the first direction, and The second distance is different from the first distance.

5. The semiconductor device according to claim 2, in, The second edge portion of the second active pattern, the second portion of the word line, and the first edge portion of the second active pattern are sequentially disposed along the third direction.

6. The semiconductor device according to claim 1, in, When viewed in a plan view, the first active pattern and the second active pattern are spaced farther and farther apart in the first direction along an imaginary line therebetween, and The imaginary line extends in a fourth direction that is parallel to the upper surface of the substrate and perpendicular to the first direction.

7. The semiconductor device according to claim 1, in, The first active patterns are repeatedly positioned along the first direction to form a plurality of first active patterns, wherein the second active pattern is repeatedly positioned along the first direction to form a plurality of second active patterns, and Wherein, each of the plurality of first active patterns and each of the plurality of second active patterns are alternately arranged along the first direction.

8. The semiconductor device according to claim 1, in, The word line has a first side on the first edge portion of the first active pattern and a second side opposite to the first side, and Wherein, when viewed in a top view, each of the first side and the second side of the word line has a concave surface.

9. The semiconductor device according to claim 8, in, The concave surface of the first side of the word line and the concave surface of the second side of the word line are concave toward opposite directions when viewed in a plan view.

10. The semiconductor device according to claim 8, in, The first edge portion of the first active pattern and the second edge portion of the second active pattern are disposed on the concave surface of the first side of the word line when viewed in a plan view.

11. The semiconductor device according to claim 8, in, The second edge portion of the first active pattern and the first edge portion of the second active pattern are disposed on the concave surface of the second side of the word line when viewed in a plan view.

12. The semiconductor device according to claim 1, in, The waveform of the word line has a substantially constant width in a fourth direction parallel to the upper surface of the substrate and perpendicular to the first direction.

13. A semiconductor device, comprising: a first active pattern and a second active pattern, the first active pattern and the second active pattern being adjacent to each other in a first direction and each including a first edge portion and a second edge portion spaced apart from each other; a word line crossing between the first edge portion and the second edge portion of each of the first active pattern and the second active pattern and extending in the first direction; a bit line located on the first edge portion of the first active pattern; as well as a storage node contact located on the second edge portion of the first active pattern, wherein the first active pattern extends longitudinally in a second direction intersecting the first direction, wherein the second active pattern extends longitudinally in a third direction intersecting the first direction and the second direction, wherein the second direction and the third direction are symmetrical with respect to the first direction, wherein the first direction, the second direction and the third direction are on the same plane, and Each of the opposite sides of the word line has convex surfaces and concave surfaces alternately arranged along the first direction.

14. The semiconductor device according to claim 13, in, When viewed in a plan view, each of the opposite sides of the word line has a wave shape extending in the first direction.

15. The semiconductor device according to claim 13, in, The concave surface on one of the opposite sides of the word line and the concave surface on the other side are concave toward opposite directions when viewed in a plan view.

16. The semiconductor device according to claim 13, in, The convex surface on one of the opposite sides of the word line and the convex surface on the other side protrude toward opposite directions.

17. The semiconductor device according to claim 13, in, The convex surface of one of the opposite sides of the word line is adjacent to the concave surface of the other of the opposite sides of the word line in the second direction or the third direction.

18. The semiconductor device according to claim 13, in, The first active patterns are repeatedly positioned in the first direction to form a plurality of first active patterns, wherein the second active pattern is repeatedly positioned in the first direction to form a plurality of second active patterns, and Wherein, each of the plurality of first active patterns and each of the plurality of second active patterns are alternately arranged along the first direction.

19. A semiconductor device, comprising: a first active pattern and a second active pattern, the first active pattern and the second active pattern being adjacent to each other in a first direction and each including a first edge portion and a second edge portion spaced apart from each other; a word line crossing between the first edge portion and the second edge portion of each of the first active pattern and the second active pattern and having a waveform extending in the first direction; a bit line disposed on the first edge portion of the first active pattern; a storage node contact disposed on the second edge portion of the first active pattern; a landing pad disposed on the storage node contact; as well as a data storage pattern, the data storage pattern being disposed on the landing pad, wherein the first active pattern extends longitudinally in a second direction intersecting the first direction, wherein the second active pattern extends longitudinally in a third direction intersecting the first direction and the second direction, wherein the second direction and the third direction are symmetrical with respect to the first direction, and Wherein, the first direction, the second direction and the third direction are on the same plane.

20. The semiconductor device according to claim 19, in, Each of the opposite sides of the word line has convex surfaces and concave surfaces alternately arranged along the first direction.

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