Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method of the semiconductor structure comprises the steps that a substrate is provided, the substrate comprises a plurality of active regions, gate structures arranged on the active regions and isolation layers, isolation structures are arranged between the adjacent gate structures, the isolation layers cover the gate structures and the isolation structures, and the spaces between the gate structures and the isolation structures are filled with the isolation layers; a plurality of openings are formed in the isolation layer, the bottom of each opening exposes part of the active region, and the side face, close to the isolation structure, of the opening exposes at least part of the surface of the isolation structure; forming a protection layer, wherein the protection layer at least covers the surface of the isolation structure exposed through the side surface of the opening; performing an ion implantation process on each active region through the bottom surface of the opening to form a source region or a drain region; and forming a conductive plug in each opening, wherein the conductive plug is connected with the corresponding source region or drain region. By arranging the protection layer, the isolation structure is prevented from being damaged, and the manufacturing reliability of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the development of dynamic random access memories, the integration degree of memories has gradually increased, and the power consumption has gradually decreased. However, due to the reduction in the size of semiconductor structures in memories, there are problems of low reliability in the process of manufacturing semiconductor structures. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the claims.

[0004] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor structure, the method for manufacturing the semiconductor structure including: Providing a substrate, the substrate including a plurality of active regions, a gate structure disposed on the active regions, and an isolation layer, an isolation structure being disposed between adjacent gate structures, the isolation layer covering the gate structure and the isolation structure and filling the space between the gate structure and the isolation structure; Forming a plurality of openings in the isolation layer, the bottom of each opening exposing a part of the active region, and the side of the opening close to the isolation structure exposing at least a part of the surface of the isolation structure; Forming a protective layer, the protective layer covering at least the surface of the isolation structure exposed through the side of the opening; Performing an ion implantation process on each active region through the bottom of the opening to form a source region or a drain region; Forming a conductive plug in each opening, the conductive plug being connected to the corresponding source region or drain region.

[0006] According to some embodiments of the present disclosure, the forming of the protective layer includes: Forming the protective layer by a deposition process, the protective layer covering the top surface of the isolation layer and the side and bottom surfaces of the opening; Removing the protective layer located on the bottom surface of the opening.

[0007] According to some embodiments of the present disclosure, the temperature of the deposition process is less than or equal to 600 °C.

[0008] According to some embodiments of the present disclosure, the substrate is a silicon substrate; before forming conductive plugs in each of the openings, the manufacturing method of the semiconductor structure further includes: Form a first metal layer on the bottom surface of the opening and perform heat treatment to obtain a metal silicide layer.

[0009] According to some embodiments of the present disclosure, forming the conductive plugs in each of the openings includes: Form a diffusion barrier layer in the opening, the diffusion barrier layer covering the sidewalls of the opening and the top surface of the metal silicide layer, and the diffusion barrier layer enclosing to form a receiving space; Fill a second metal layer in the receiving space to obtain the conductive plug.

[0010] According to some embodiments of the present disclosure, the ion implantation process includes an ion implantation step, an ashing step, and a cleaning step.

[0011] A second aspect of the present disclosure provides a semiconductor structure, which includes: A substrate, the substrate includes a plurality of active regions, a gate structure disposed on the active regions, and an isolation layer, an isolation structure is disposed between adjacent gate structures, the isolation layer covers the gate structure and the isolation structure and fills the space between the gate structure and the isolation structure, a plurality of openings are provided on the isolation layer, the bottom of each opening exposes a source region or a drain region in a part of the active region, and the side surface of the opening close to the isolation structure exposes at least a part of the surface of the isolation structure; A conductive plug, the conductive plug is disposed in the opening; A protective layer, the protective layer is disposed between the conductive plug and the isolation structure.

[0012] According to some embodiments of the present disclosure, the material of the isolation structure includes an oxide.

[0013] According to some embodiments of the present disclosure, the material of the protective layer includes silicon nitride; and / or, the thickness of the protective layer is 1 mm to 10 mm.

[0014] According to some embodiments of the present disclosure, the substrate is a silicon substrate, and a metal silicide layer is disposed in the source region or the drain region; the conductive plug includes: A diffusion barrier layer and a second metal layer, the diffusion barrier layer is disposed between the second metal layer and the sidewalls of the opening and the metal silicide layer.

[0015] According to some embodiments of the present disclosure, the top surface of the isolation structure is higher than the top surface of the gate structure.

[0016] In the method for manufacturing a semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure, a substrate including a plurality of active regions, a gate structure disposed on the active regions, and an isolation layer is provided, so as to form an expected semiconductor structure through processing of the substrate. A plurality of openings are formed in the isolation layer, so as to perform ion implantation on the active regions through the openings and form conductive plugs. A protective layer covering the surface of the exposed isolation structure is formed to protect the isolation structure during the ion implantation process. Ion implantation processes are performed on each active region through the bottom surface of the opening to form source regions or drain regions, and conductive plugs connected to the corresponding source regions or drain regions are formed in each opening, so that the source regions or drain regions are externally connected through the corresponding conductive plugs. By forming a protective layer on the surface of the exposed isolation structure, damage to the isolation structure during the ion implantation process is avoided, and short circuits between adjacent conductive plugs are prevented, thereby improving the reliability of manufacturing the semiconductor structure. At the same time, since the protective layer is not easily damaged, the size of the opening remains basically unchanged, and no voids occur during the formation of the conductive plugs, thereby further improving the reliability of manufacturing the semiconductor structure. Moreover, since the size of the opening is basically not affected by the ion implantation process, the size of the conductive plugs is small to retain a sufficient safety margin, thereby further improving the reliability of manufacturing the semiconductor structure.

[0017] Other aspects will be apparent after reading and understanding the drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, like reference numerals are used to represent like elements. The drawings in the following description are some embodiments of the present disclosure, but not all embodiments. Those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0019] Figure 1 is a cross-sectional view of a semiconductor structure; Figure 2 is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment; Figure 3 is a cross-sectional view of a semiconductor structure during manufacturing according to a first exemplary embodiment; Figure 4 is a cross-sectional view of a semiconductor structure during manufacturing according to a second exemplary embodiment; Figure 5 is a flowchart of a method for manufacturing a semiconductor structure according to a first exemplary embodiment; Figure 6is a cross-sectional view of a semiconductor structure during fabrication according to a third exemplary embodiment; Figure 7 is a cross-sectional view of a semiconductor structure during fabrication according to a fourth exemplary embodiment; Figure 8 is a flowchart of a method for fabricating a semiconductor structure according to a second exemplary embodiment; Figure 9 is a cross-sectional view of a semiconductor structure according to an exemplary embodiment; Figure 10 is a flowchart of a method for fabricating a semiconductor structure according to a third exemplary embodiment.

[0020] In the figure: 10, substrate; 11, active region; 12, gate structure; 13, isolation layer; 14, isolation structure; 20, conductive plug; 21, anti-diffusion layer; 22, second metal layer; 30, protective layer; 111, metal silicide layer; 131, opening. Detailed implementation manners

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure. It should be noted that, without conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other arbitrarily. It should also be understood that the term "and / or" as used herein refers to any and all possible combinations including one or more of the associated listed items.

[0022] With the development of dynamic random access memories, the integration degree of memories gradually increases, and the power consumption gradually decreases. Due to the increased integration degree of memories, the size of semiconductor structures in the memories decreases, and the distance between some structures in the semiconductor structures shortens. As Figure 1As shown, in the process of fabricating a semiconductor structure, it is necessary to process a substrate provided with a plurality of active regions 11, a gate structure 12 disposed on the active regions 11, and an isolation layer 13. An isolation structure 14 is provided between adjacent gate structures 12. A plurality of openings are formed in the isolation layer 13, and after performing an ion implantation process on the active regions 11 through the openings, conductive plugs 20 are formed in each opening. Since one or more ion implantation steps, ashing steps, and cleaning steps are required during the ion implantation process, the isolation structure 14 may be damaged and its size may be reduced due to the cleaning step. Since the isolation structure 14 is damaged, the distance between adjacent conductive plugs 20 is reduced, posing a risk of short circuit, resulting in low reliability in fabricating the semiconductor structure. At the same time, since the isolation structure 14 is damaged and the openings become larger, the conductive plugs 20 may have voids during formation, affecting the performance of the semiconductor structure, further leading to low reliability in fabricating the semiconductor structure. Moreover, since the openings become larger, the size of the conductive plugs 20 formed in the openings is relatively large without sufficient safety margin, further leading to low reliability in fabricating the semiconductor structure.

[0023] Based on this, the present disclosure provides a method for fabricating a semiconductor structure. By forming a protective layer on the surface of the exposed isolation structure before the ion implantation process, damage to the isolation structure during the ion implantation process is avoided, which affects the distance between adjacent conductive plugs, thereby improving the reliability of fabricating the semiconductor structure. At the same time, since the isolation structure is protected by the protective layer and the size of the openings does not change, there are no voids in the formation of the conductive plugs, further improving the reliability of fabricating the semiconductor structure. Moreover, since the size of the openings does not change, the size of the formed conductive plugs is relatively small with a certain safety margin, further improving the reliability of fabricating the semiconductor structure.

[0024] In an exemplary embodiment of the present disclosure, a method for fabricating a semiconductor structure is provided, as Figure 2 shown, Figure 2 FIG. shows a flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure. The method for fabricating a semiconductor structure includes: S100. Provide a substrate, the substrate including a plurality of active regions, a gate structure disposed on the active regions, and an isolation layer. An isolation structure is provided between adjacent gate structures. The isolation layer covers the gate structure and the isolation structure and fills the space between the gate structure and the isolation structure.

[0025] S200. Form a plurality of openings in the isolation layer. The bottom of each opening exposes a part of the active region, and the side surface of the opening adjacent to the isolation structure exposes at least a part of the surface of the isolation structure.

[0026] S300. Form a protective layer that covers at least the surface of the isolation structure exposed on the side surfaces through the openings.

[0027] S400. Perform an ion implantation process on each active region through the bottom surface of the opening to form a source region or a drain region.

[0028] S500. Form conductive plugs in each opening, and connect the conductive plugs to the corresponding source region or drain region.

[0029] In this embodiment, a substrate including a plurality of active regions, a gate structure disposed on the active regions, and an isolation layer is provided, so as to form an expected semiconductor structure through the processing of the substrate. A plurality of openings are formed on the isolation layer to perform ion implantation on the active regions through the openings and to form conductive plugs. A protective layer covering the surface of the exposed isolation structure is formed to protect the isolation structure under the ion implantation process. An ion implantation process is performed on each active region through the bottom surface of the opening to form a source region or a drain region, and conductive plugs connected to the corresponding source region or drain region are formed in each opening, so that the source region or the drain region is externally connected through the corresponding conductive plugs. By forming a protective layer on the surface of the exposed isolation structure, the isolation structure is prevented from being damaged under the ion implantation process and causing a short circuit between adjacent conductive plugs, thereby improving the reliability of manufacturing the semiconductor structure. At the same time, since the protective layer is not easily damaged and the size of the opening remains basically unchanged, the conductive plugs will not have voids during the formation process, thereby further improving the reliability of manufacturing the semiconductor structure. Moreover, since the size of the opening is basically not affected by the ion implantation process and the size of the conductive plugs is small to reserve sufficient safety margins, the reliability of manufacturing the semiconductor structure is further improved.

[0030] Exemplarily, as Figure 3 shown, providing the substrate in step S100 may be to provide a substrate 10 including a plurality of active regions 11, a gate structure 12 disposed on the active regions 11, and an isolation layer 13. An isolation structure 14 is disposed between adjacent gate structures 12 in the substrate 10, and the isolation layer 13 covers the gate structure 12 and the isolation structure 14 and fills the space between the gate structure 12 and the isolation structure 14. As Figure 4 shown, forming a plurality of openings on the isolation layer in step S200 may be to remove a part of the isolation layer 13 between the gate structure 12 and the isolation structure 14 through an etching process to form a plurality of openings 131. The cross-sectional shape of the opening 131 may be, for example, a rectangle.

[0031] In some exemplary embodiments provided by the present disclosure, as Figure 5 shown, Figure 5 shows a flowchart of forming the protective layer in step S300, including: S310. Form a protective layer through a deposition process, where the protective layer covers the top surface of the isolation layer and the side and bottom surfaces of the opening.

[0032] S320. Remove the protective layer located on the bottom surface of the opening.

[0033] In this embodiment, since the protective layer needs to cover the surface of the isolation structure exposed through the side surface of the opening, the protective layer is formed by a deposition process of a deposition material. Since the deposition process has no directionality, the formed protective layer covers not only the surface of the isolation structure exposed through the side surface of the opening, but also the top surface of the isolation layer and the side and bottom surfaces of the opening. Since the protective layer on the bottom surface of the opening affects ion implantation and the formation of conductive plugs, the protective layer located on the bottom surface of the opening is removed. By forming the protective layer through a deposition process, the protective layer is formed uniformly to avoid damage to the isolation structure, thereby improving the reliability of semiconductor structure fabrication. By removing the protective layer located on the bottom surface of the opening before forming the conductive plug, it is avoided that the protective layer affects the ion implantation and the formation of the conductive plug, resulting in a decrease in the performance of the semiconductor structure, thereby further improving the reliability of semiconductor structure fabrication.

[0034] In some exemplary embodiments provided by the present disclosure, the deposition process is an atomic layer deposition process (ALD).

[0035] Exemplarily, forming the protective layer through the deposition process in the above steps may be to deposit a protective layer of an insulating material having a certain mechanical strength. The insulating material may include, for example, silicon nitride. As Figure 6 shown, after forming the protective layer 30, the protective layer 30 covers the top surface of the isolation layer 13 and the side and bottom surfaces of the opening 131. That is, the protective layer 30 covers the top surface of the isolation layer 13, the surface of the isolation structure 14 exposed through the side surface of the opening 131, a part of the isolation layer 13 exposed through the side surface of the opening 131, and a part of the active region 11 exposed through the bottom surface of the opening 131. Among them, the protective layer 30 may not cover the top surface of the isolation layer 13 either.

[0036] Exemplarily, removing the protective layer located on the bottom surface of the opening in the above steps can be achieved through an etching process. As Figure 7 shown, after removing the protective layer 30 located on the bottom surface of the opening 131, a part of the active region 11 located on the bottom surface of the opening 131 is exposed.

[0037] In some exemplary embodiments provided by the present disclosure, the temperature of the deposition process is less than or equal to 600 °C.

[0038] In this embodiment, since after the gate structure in the substrate is formed, if a high-temperature process is used for processing, it will affect the performance of the semiconductor structure. By making the temperature of the deposition process less than or equal to 600 °C, it is avoided to affect the gate structure, thereby improving the reliability of semiconductor structure fabrication.

[0039] In some exemplary embodiments provided by the present disclosure, the ion implantation process includes an ion implantation step, an ashing step, and a cleaning step.

[0040] In this embodiment, ion implantation is performed through the ion implantation step to form a source region or a drain region in the active region. Since photoresist remains after the ion implantation step, affecting subsequent processes, the photoresist is removed through the ashing step. Since contaminants remain after the ashing step, affecting the performance of the semiconductor structure, the contaminants are removed through the cleaning step. By performing the ion implantation step, the ashing step, and the cleaning step, impurities that affect subsequent processes and the performance of the semiconductor structure are avoided while forming the source region or the drain region, thereby improving the reliability of fabricating the semiconductor structure.

[0041] Exemplarily, the ion implantation process may include one or more ion implantation steps, ashing steps, and cleaning steps. The ions implanted in multiple ion implantation steps may be the same or different.

[0042] In one embodiment, the ions implanted in the ion implantation process include arsenic ions, germanium ions, and carbon ions.

[0043] In this embodiment, by implanting arsenic ions in the ion implantation process, a source region or a drain region can be formed in the active region. By implanting germanium ions in the ion implantation process, the mobility of carriers in the active region can be improved, and the doping uniformity can be optimized. By implanting carbon ions in the ion implantation process, the lifetime of carriers in the active region can be increased, and the characteristics of the semiconductor structure can be adjusted. By implanting arsenic ions, germanium ions, and carbon ions in the ion implantation process, the performance of the semiconductor structure can be optimized, thereby improving the reliability of fabricating the semiconductor structure.

[0044] It can be understood that the ions implanted in the ion implantation process may include, in addition to arsenic ions, germanium ions, and carbon ions, phosphorus ions, antimony ions, boron ions, indium ions, gallium ions, etc., which are not limited herein.

[0045] Exemplarily, the ion implantation process may include the following steps: a first photolithography step, an arsenic ion implantation step, a first ashing step, a first cleaning step, a second photolithography step, a first germanium ion implantation step, a carbon ion implantation step, a second germanium ion implantation step, a second ashing step, a second cleaning step, a measurement step, a rapid thermal annealing step, and a dry etching step.

[0046] In some exemplary embodiments provided by the present disclosure, the substrate is a silicon substrate. Before forming the conductive plugs in each opening in step S500, the method for fabricating the semiconductor structure further includes: Forming a first metal layer on the bottom surface of the opening and performing heat treatment to obtain a metal silicide layer.

[0047] In this embodiment, a first metal layer is formed on the bottom surface of the opening and heat-treated to obtain a metal silicide layer, so as to reduce the contact resistance of the semiconductor structure. By reducing the contact resistance of the semiconductor structure, the performance of the semiconductor structure is improved, thereby enhancing the reliability of manufacturing the semiconductor structure.

[0048] In some exemplary embodiments provided by the present disclosure, as Figure 8 shown, Figure 8 An exemplary method flow diagram of forming conductive plugs in each opening in step S500 is shown, including: S510. A diffusion barrier layer is formed in the opening. The diffusion barrier layer covers the sidewalls of the opening and the top surface of the metal silicide layer, and the diffusion barrier layer encloses a receiving space.

[0049] S520. The receiving space is filled with a second metal layer to obtain a conductive plug.

[0050] In this embodiment, by forming a diffusion barrier layer in the opening, the second metal layer is prevented from diffusing when the second metal layer is filled. By filling the receiving space with the second metal layer, a conductive plug including the diffusion barrier layer and the second metal layer is formed. By sequentially forming the diffusion barrier layer and the second metal layer, the conductive plug can preferably contact the source region or the drain region to enhance the performance of the semiconductor structure, thereby enhancing the reliability of manufacturing the semiconductor structure.

[0051] Exemplarily, forming the first metal layer on the bottom surface of the opening in the above steps, forming the diffusion barrier layer in the opening in step S510, and filling the receiving space with the second metal layer in step S520 can be achieved by a deposition process. As Figure 9 shown, the metal silicide layer 111 obtained by processing on the bottom surface of the opening 131 is located in the active region 11. The material of the metal silicide layer 111 may include, for example, cobalt silicide. The diffusion barrier layer 21 formed in the opening 131 can cover the sidewalls of the opening 131, the top surface of the metal silicide layer 111, and the top surface of the isolation layer 13. At least part of the diffusion barrier layer 21 on the top surface of the isolation layer 13 is removed during subsequent patterning. The material of the diffusion barrier layer 21 may include, for example, titanium nitride. The material of the second metal layer 22 filled in the receiving space may include, for example, tungsten. Compared with Figure 1 this, since the isolation structure 14 is not damaged and the shape of the receiving space is not expanded, no voids will be generated when filling the second metal layer 22 to obtain the conductive plug 20.

[0052] In some exemplary embodiments provided by the present disclosure, as Figure 10 shown, the manufacturing method of the semiconductor structure includes: S600. Provide a substrate including a plurality of active regions, a gate structure disposed on the active regions, and an isolation layer.

[0053] S610. Form a plurality of openings on the isolation layer.

[0054] S620. Form a protective layer covering the surface of the isolation structure exposed on the side surfaces of the openings through a deposition process.

[0055] S630. Remove the protective layer located on the bottom surface of the opening.

[0056] S640. Perform an ion implantation process on each active region through the bottom surface of the opening to form a source region or a drain region.

[0057] S650. Form a first metal layer on the bottom surface of the opening and perform a heat treatment to obtain a metal silicide layer.

[0058] S660. Form an anti-diffusion layer in the opening.

[0059] S670. Fill a second metal layer in the accommodation space to obtain a conductive plug.

[0060] In this embodiment, a substrate including a plurality of active regions, a gate structure disposed on the active regions, and an isolation layer is provided to form an expected semiconductor structure through processing of the substrate. A plurality of openings are formed on the isolation layer to perform ion implantation of the active regions and form a conductive plug through the openings. A protective layer covering the surface of the isolation structure exposed on the side surfaces of the openings is formed through a deposition process to protect the isolation structure through the protective layer. Since the protective layer covers the active regions on the bottom surface of the opening and affects the formation of the conductive plug and ion implantation, the protective layer located on the bottom surface of the opening is removed. An ion implantation process is performed on each active region through the bottom surface of the opening to form a source region or a drain region to obtain a source region or a drain region. A first metal layer is formed on the bottom surface of the opening and a heat treatment is performed to obtain a metal silicide layer to reduce the contact resistance of the semiconductor structure. An anti-diffusion layer is formed in the opening to prevent the second metal layer from diffusing when the second metal layer is filled. A second metal layer is filled in the accommodation space to form a conductive plug including the anti-diffusion layer and the second metal layer. By forming a protective layer on the surface of the exposed isolation structure, the isolation structure is prevented from being damaged under the ion implantation process and causing a short circuit between adjacent conductive plugs, thereby improving the reliability of manufacturing the semiconductor structure. At the same time, since the protective layer is not easily damaged and the size of the opening remains basically unchanged, the conductive plug will not have an air pocket during the formation process, thereby further improving the reliability of manufacturing the semiconductor structure. And, since the size of the opening is basically not affected by the ion implantation process, the size of the conductive plug is small to reserve a sufficient safety margin, thereby further improving the reliability of manufacturing the semiconductor structure.

[0061] In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, such as Figure 3 and Figure 9 shown, the semiconductor structure includes a substrate 10, a conductive plug 20, and a protective layer 30. The substrate 10 includes a plurality of active regions 11, a gate structure 12 disposed on the active regions 11, and an isolation layer 13. An isolation structure 14 is disposed between adjacent gate structures 12. The isolation layer 13 covers the gate structure 12 and the isolation structure 14 and fills the space between the gate structure 12 and the isolation structure 14. A plurality of openings 131 are provided on the isolation layer 13. The bottom of each opening 131 exposes a source region or a drain region in a part of the active region 11, and the side surface of the opening 131 close to the isolation structure 14 exposes at least a part of the surface of the isolation structure 14. The conductive plug 20 is disposed in the opening 131. The protective layer 30 is disposed between the conductive plug 20 and the isolation structure 14.

[0062] In this embodiment, the semiconductor structure includes a substrate, a conductive plug, and a protective layer. An isolation structure is disposed between adjacent gate structures on the substrate, and the surface of the isolation structure exposed through the side surface of the opening is covered with a protective layer. By covering the surface of the exposed isolation structure with a protective layer, the protective layer can prevent the short - circuit risk caused by the reduction of the distance between the conductive plugs on both sides of the isolation structure, thereby improving the reliability of the semiconductor structure. At the same time, since the protective layer protects the isolation structure from being damaged, there is no air pocket in the conductive plug, thereby further improving the reliability of the semiconductor structure. And, since the size of the isolation structure does not change and the protective layer reduces the size of the opening, the size of the conductive plug is small to retain a sufficient safety margin, thereby further improving the reliability of the semiconductor structure.

[0063] Exemplarily, the gate structure 12 may include a plurality of materials stacked in sequence. For example, it may include silicon nitride, tungsten, titanium nitride, polysilicon, titanium nitride, lanthanum oxide, and hafnium silicate. The thicknesses of the materials of different layers may be the same or different.

[0064] In some exemplary embodiments provided by the present disclosure, the material of the isolation structure 14 includes an oxide.

[0065] In this embodiment, by using an oxide as at least one material of the isolation structure, effective isolation between the conductive plugs can be achieved, thereby improving the reliability of the semiconductor structure.

[0066] In some exemplary embodiments provided by the present disclosure, the material of the protective layer 30 includes silicon nitride.

[0067] In this embodiment, due to the high mechanical strength of silicon nitride, it can effectively prevent the isolation structure from being damaged, thereby improving the reliability of the semiconductor structure.

[0068] Exemplarily, the material of the isolation layer 13 may be the same as or different from the material of the protection layer 30.

[0069] It can be understood that the material of the protection layer 30 may include, in addition to silicon nitride, other insulating materials with a certain mechanical strength, which are not limited herein.

[0070] In some exemplary embodiments provided by the present disclosure, the thickness of the protection layer 30 is 1 mm to 10 mm.

[0071] In this embodiment, by setting the thickness of the protection layer to 1 mm to 10 mm, it is avoided that the thickness of the protection layer is too thin to protect the isolation structure and too thick to affect the formation of the conductive plug, thereby improving the reliability of the semiconductor structure.

[0072] In some exemplary embodiments provided by the present disclosure, the protection layer 30 covers the top surface of the isolation layer 13 and the side surface of the opening 131, and the protection layer 30 does not cover the bottom surface of the opening 131.

[0073] In this embodiment, by making the protection layer cover the top surface of the isolation layer and the side surface of the opening, it is avoided that the isolation layer is damaged and air pockets are formed in the conductive plug, thereby improving the reliability of the semiconductor structure. By making the protection layer not cover the bottom surface of the opening, it is avoided that the metal silicide layer formed on the bottom surface of the opening is affected and the performance of the semiconductor structure is reduced, thereby further improving the reliability of the semiconductor structure.

[0074] In some exemplary embodiments provided by the present disclosure, the top surface of the isolation structure 14 is higher than the top surface of the gate structure 12.

[0075] In this embodiment, by making the top surface of the isolation structure higher than the top surface of the gate structure, it is avoided that short circuits occur between adjacent gate structures, thereby improving the reliability of the semiconductor structure. At the same time, since the top surface of the isolation structure is relatively high, adjacent conductive plugs can be effectively isolated, thereby further improving the reliability of the semiconductor structure.

[0076] In some exemplary embodiments provided by the present disclosure, the substrate 10 is a silicon substrate, and a metal silicide layer 111 is provided in the source region or the drain region. The conductive plug 30 includes a diffusion prevention layer 21 and a second metal layer 22. The diffusion prevention layer 21 is disposed between the second metal layer 22 and the sidewall of the opening 131 and the metal silicide layer 111.

[0077] In this embodiment, by providing a metal silicide layer on the bottom surface of the opening, the contact resistance of the semiconductor structure can be reduced. By providing a diffusion prevention layer in the conductive plug, the diffusion of the second metal layer is prevented. By using the diffusion prevention layer and the second metal layer as the conductive plug, the conductive plug can effectively connect the active region and the external structure, thereby improving the reliability of the semiconductor structure.

[0078] Exemplarily, the metal silicide layer 111 is located in the active region 11. The material of the metal silicide layer 111 may include, for example, cobalt silicide. The anti-diffusion layer 21 may cover the sidewalls of the opening 131, the top surface of the metal silicide layer 111, and the top surface of the isolation layer 13. The material of the anti-diffusion layer 21 may include, for example, titanium nitride. The material of the second metal layer 22 may include, for example, tungsten.

[0079] In some exemplary embodiments provided by the present disclosure, as Figure 9 shown, the semiconductor structure includes a substrate 10, a conductive plug 20, and a protective layer 30. The substrate 10 includes a plurality of active regions 11, gate structures 12 disposed on the active regions 11, and an isolation layer 13. An isolation structure 14 is disposed between adjacent gate structures 12. The gate structure 12 includes a plurality of materials stacked in sequence. The isolation layer 13 covers the gate structure 12 and the isolation structure 14, and fills the space between the gate structure 12 and the isolation structure 14. A plurality of openings 131 are provided on the isolation layer 13. The bottom of each opening 131 exposes a source region or a drain region in a part of the active region 11. The side surface of the opening 131 disposed close to the isolation structure 14 exposes at least a part of the surface of the isolation structure 14. The top surface of the isolation structure 14 is higher than the top surface of the gate structure 12. A metal silicide layer 111 is provided on the bottom surface of the opening 131, and the metal silicide layer 111 is located in the active region 11. The conductive plug 20 includes an anti-diffusion layer 21 and a second metal layer 22. The anti-diffusion layer 21 is disposed between the second metal layer 22 and the sidewalls of the opening 131 and the metal silicide layer 111. The protective layer 30 is disposed between the conductive plug 20 and the isolation structure 14.

[0080] In some exemplary embodiments provided by the present disclosure, the semiconductor structure is a dynamic random access memory, as Figure 3 and Figure 9As shown, it includes a substrate 10. The substrate 10 is divided into an array region and a peripheral region. The array region is used for storing data, and the peripheral region is used for operating the array region. The peripheral region includes a plurality of active regions 11, a gate structure 12 disposed on the active regions 11, and an isolation layer 13. An isolation structure 14 is disposed between adjacent gate structures 12. The gate structure 12 includes multiple materials stacked in sequence. The isolation layer 13 covers the gate structure 12 and the isolation structure 14, and fills the space between the gate structure 12 and the isolation structure 14. A plurality of openings 131 are provided on the isolation layer 13. The bottom of each opening 131 exposes the source region or the drain region in a part of the active region 11. The side surface of the opening 131 disposed close to the isolation structure 14 exposes at least a part of the surface of the isolation structure 14. The top surface of the isolation structure 14 is higher than the top surface of the gate structure 12. A metal silicide layer 111 is provided on the bottom surface of the opening 131, and the metal silicide layer 111 is located in the active region 11. The conductive plug 20 includes a diffusion prevention layer 21 and a second metal layer 22. The diffusion prevention layer 21 is disposed between the second metal layer 22 and the side wall of the opening 131 and the metal silicide layer 111. A protective layer 30 is disposed between the conductive plug 20 and the isolation structure 14.

[0081] In the present disclosure, the terms "comprise", "include" or any other variation thereof are intended to cover non-exclusive inclusion, such that an article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or also includes elements inherent to such article or device. Without further limitation, the elements defined by the statement "comprising..." do not preclude the existence of additional identical elements in the article or device including the said elements.

[0082] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0083] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the intention of the present disclosure also includes these changes and modifications.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The manufacturing method of the semiconductor structure includes: Providing a substrate, the substrate includes a plurality of active regions, gate structures disposed on the active regions, and an isolation layer. An isolation structure is disposed between adjacent gate structures. The isolation layer covers the gate structures and the isolation structure, and fills the space between the gate structures and the isolation structure; Forming a plurality of openings in the isolation layer, the bottom of each opening exposes a part of the active region, and the side of the opening disposed close to the isolation structure exposes at least a part of the surface of the isolation structure; Forming a protective layer, the protective layer covers at least the surface of the isolation structure exposed through the side of the opening; Performing an ion implantation process on each active region through the bottom of the opening to form a source region or a drain region; Forming a conductive plug in each opening, and the conductive plug is connected to the corresponding source region or drain region.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The forming of the protective layer includes: Forming the protective layer through a deposition process, the protective layer covers the top surface of the isolation layer, and the side and bottom surfaces of the opening; Removing the protective layer located on the bottom surface of the opening.

3. The manufacturing method of the semiconductor structure according to claim 2, wherein, The temperature of the deposition process is less than or equal to 600 °C.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein, The substrate is a silicon substrate; Before forming the conductive plug in each opening, the manufacturing method of the semiconductor structure further includes: Forming a first metal layer on the bottom surface of the opening, and performing a heat treatment to obtain a metal silicide layer.

5. The manufacturing method of the semiconductor structure according to claim 4, wherein The forming of the conductive plug in each opening includes: Forming a diffusion barrier layer in the opening, the diffusion barrier layer covers the sidewall of the opening and the top surface of the metal silicide layer, and the diffusion barrier layer encloses to form a receiving space; Filling a second metal layer in the receiving space to obtain the conductive plug.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, characterized in that, The ion implantation process includes an ion implantation step, an ashing step, and a cleaning step.

7. A semiconductor structure, characterized in that, The semiconductor structure includes: A substrate, the substrate includes a plurality of active regions, gate structures disposed on the active regions, and an isolation layer. An isolation structure is disposed between adjacent gate structures. The isolation layer covers the gate structures and the isolation structure, and fills the space between the gate structures and the isolation structure. A plurality of openings are disposed on the isolation layer, the bottom of each opening exposes a source region or a drain region in a part of the active region, and the side of the opening disposed close to the isolation structure exposes at least a part of the surface of the isolation structure; A conductive plug, the conductive plug is disposed in the opening; A protective layer, the protective layer is disposed between the conductive plug and the isolation structure.

8. The semiconductor structure according to claim 7, wherein The material of the isolation structure includes an oxide.

9. The semiconductor structure according to claim 7, wherein The material of the protective layer includes silicon nitride; and / or, the thickness of the protective layer is 1 mm to 10 mm.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that, The substrate is a silicon substrate, and a metal silicide layer is disposed in the source region or the drain region; the conductive plug includes: A diffusion barrier layer and a second metal layer, the diffusion barrier layer is disposed between the second metal layer and the sidewall of the opening and the metal silicide layer.

11. The semiconductor structure according to any one of claims 7 to 9, characterized in that, The top surface of the isolation structure is higher than the top surface of the gate structure.

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