Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing a semiconductor structure includes: providing a substrate, the substrate including multiple active regions, a gate structure arranged on the active regions, and an isolation layer, an isolation structure arranged between adjacent gate structures, the isolation layer covering the gate structure and the isolation structure, and filling the space between the gate structure and the isolation structure; forming multiple openings on the isolation layer, the bottom of each opening exposing a portion of the active region, and the side of the opening arranged near the isolation structure exposing at least a portion of the surface of the isolation structure; forming a protective layer, the protective layer at least covering the surface of the isolation structure exposed through the side of the opening; performing an ion implantation process on each active region through the bottom of the opening to form a source region or a drain region; forming a conductive plug in each opening, the conductive plug being connected to the corresponding source region or drain region. By providing a protective layer, damage to the isolation structure is avoided, thereby improving the reliability of the semiconductor structure manufacturing.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the development of dynamic random access memory, the integration of memory has gradually increased and the power consumption has gradually decreased. However, due to the reduction in the size of the semiconductor structure in the memory, the semiconductor structure has a low reliability problem during the manufacturing process. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] According to a first aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0006] Providing a substrate, the substrate comprising a plurality of active regions, a gate structure disposed on the active regions, and an isolation layer, wherein an isolation structure is disposed between adjacent gate structures, the isolation layer covers the gate structure and the isolation structure, and fills the space between the gate structure and the isolation structure;

[0007] forming a plurality of openings on the isolation layer, wherein a bottom of each of the openings exposes a portion of the active area, and a side surface of the opening disposed near the isolation structure exposes at least a portion of a surface of the isolation structure;

[0008] forming a protective layer, wherein the protective layer at least covers the surface of the isolation structure exposed through the side of the opening;

[0009] Performing an ion implantation process on each of the active regions through the bottom surface of the opening to form a source region or a drain region;

[0010] A conductive plug is formed in each of the openings, and the conductive plug is connected to the corresponding source region or drain region.

[0011] According to some embodiments of the present disclosure, forming the protective layer includes:

[0012] forming the protective layer by a deposition process, wherein the protective layer covers the top surface of the isolation layer and the side and bottom surfaces of the opening;

[0013] The protective layer on the bottom surface of the opening is removed.

[0014] According to some embodiments of the present disclosure, the temperature of the deposition process is less than or equal to 600°C.

[0015] According to some embodiments of the present disclosure, the substrate is a silicon substrate; before forming a conductive plug in each of the openings, the method for manufacturing the semiconductor structure further includes:

[0016] A first metal layer is formed on the bottom surface of the opening and is subjected to heat treatment to obtain a metal silicide layer.

[0017] According to some embodiments of the present disclosure, forming a conductive plug in each of the openings includes:

[0018] forming an anti-diffusion layer in the opening, wherein the anti-diffusion layer covers the sidewalls of the opening and the top surface of the metal silicide layer, and the anti-diffusion layer encloses an accommodating space;

[0019] A second metal layer is filled in the accommodation space to obtain the conductive plug.

[0020] According to some embodiments of the present disclosure, the ion implantation process includes an ion implantation step, an ashing step, and a cleaning step.

[0021] A second aspect of the present disclosure provides a semiconductor structure, comprising:

[0022] a substrate comprising a plurality of active regions, gate structures disposed on the active regions, and an isolation layer, wherein an isolation structure is disposed between adjacent gate structures, the isolation layer covers the gate structures and the isolation structures and fills the space between the gate structures and the isolation structure, and the isolation layer is provided with a plurality of openings, the bottom of each of the openings exposing a portion of a source region or a drain region in the active region, and a side surface of the opening disposed near the isolation structure exposes at least a portion of a surface of the isolation structure;

[0023] a conductive plug disposed in the opening;

[0024] A protection layer is disposed between the conductive plug and the isolation structure.

[0025] According to some embodiments of the present disclosure, the material of the isolation structure includes oxide.

[0026] According to some embodiments of the present disclosure, the material of the protective layer includes silicon nitride; and / or the thickness of the protective layer is 1 mm to 10 mm.

[0027] According to some embodiments of the present disclosure, the substrate is a silicon substrate, a metal silicide layer is provided in the source region or the drain region; and the conductive plug includes:

[0028] An anti-diffusion layer and a second metal layer, wherein the anti-diffusion layer is disposed between the second metal layer and the sidewall of the opening and the metal silicide layer.

[0029] According to some embodiments of the present disclosure, a top surface of the isolation structure is higher than a top surface of the gate structure.

[0030] In the semiconductor structure manufacturing method and semiconductor structure provided by the embodiments of the present disclosure, a substrate including multiple active regions, a gate structure disposed on the active regions, and an isolation layer is provided, so that the desired semiconductor structure is formed by processing the substrate. Multiple openings are formed in the isolation layer to allow ion implantation of the active regions and the formation of conductive plugs through the openings. A protective layer is formed to cover the surface of the exposed isolation structure to protect the isolation structure during the ion implantation process. Ion implantation is performed on each active region through the bottom surface of the opening to form a source region or a drain region, and a conductive plug connected to the corresponding source region or drain region is formed in each opening to connect the source region or drain region to the outside through the corresponding conductive plug. By forming the protective layer on the surface of the exposed isolation structure, damage to the isolation structure during the ion implantation process is avoided, thereby improving the reliability of the semiconductor structure manufacturing. At the same time, because the protective layer is not easily damaged, the size of the opening remains essentially unchanged, and hollowing of the conductive plug will not occur during the formation process, further improving the reliability of the semiconductor structure manufacturing. Furthermore, since the size of the opening is substantially unaffected by the ion implantation process, the size of the conductive plug is relatively small to retain a sufficient safety margin, thereby further improving the reliability of semiconductor structure fabrication.

[0031] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0033] Figure 1 It is a cross-sectional view of a semiconductor structure;

[0034] Figure 2 is a flow chart showing a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0035] Figure 3is a cross-sectional view of a semiconductor structure during fabrication according to a first exemplary embodiment;

[0036] Figure 4 is a cross-sectional view of a semiconductor structure during fabrication according to a second exemplary embodiment;

[0037] Figure 5 is a flow chart of a method for manufacturing a semiconductor structure according to a first exemplary embodiment;

[0038] Figure 6 is a cross-sectional view of a semiconductor structure during fabrication according to a third exemplary embodiment;

[0039] Figure 7 is a cross-sectional view of a semiconductor structure during fabrication according to a fourth exemplary embodiment;

[0040] Figure 8 is a flow chart of a method for manufacturing a semiconductor structure according to a second exemplary embodiment;

[0041] Figure 9 is a cross-sectional view of a semiconductor structure according to an exemplary embodiment;

[0042] Figure 10 is a flow chart of a method for manufacturing a semiconductor structure according to a third exemplary embodiment.

[0043] In the figure: 10, substrate; 11, active area; 12, gate structure; 13, isolation layer; 14, isolation structure; 20, conductive plug; 21, anti-diffusion layer; 22, second metal layer; 30, protective layer; 111, metal silicide layer; 131, opening. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. It should also be understood that the term "and / or" used herein refers to any or all possible combinations of one or more associated listed items.

[0045] With the development of dynamic random access memory, the integration of memory has gradually increased, and the power consumption has gradually decreased. As the integration of memory increases, the size of the semiconductor structure in the memory decreases, and the distance between some structures in the semiconductor structure shortens. Figure 1 As shown, during the fabrication of a semiconductor structure, a substrate comprising multiple active regions 11, gate structures 12 disposed on the active regions 11, and an isolation layer 13 is processed. Isolation structures 14 are disposed between adjacent gate structures 12. Multiple openings are formed in the isolation layer 13. After ion implantation is performed through the openings into the active regions 11, conductive plugs 20 are formed in each opening. The ion implantation process requires one or more ion implantation steps, ashing steps, and cleaning steps. The cleaning steps may damage the isolation structures 14, causing them to be reduced in size. Damage to the isolation structures 14 reduces the distance between adjacent conductive plugs 20, creating the risk of short circuits and reducing the reliability of the semiconductor structure. Furthermore, damage to the isolation structures 14 enlarges the openings, leading to hollowing of the conductive plugs 20 during fabrication, impacting the performance of the semiconductor structure and further reducing the reliability of the semiconductor structure. Furthermore, due to the enlarged openings, the conductive plugs 20 formed in the openings are larger in size, lacking sufficient safety margins, further reducing the reliability of the semiconductor structure.

[0046] Based on this, the present disclosure provides a method for fabricating a semiconductor structure. By forming a protective layer on the surface of the exposed isolation structure before the ion implantation process, this method prevents damage to the isolation structure during the ion implantation process, which could affect the distance between adjacent conductive plugs. This improves the reliability of the semiconductor structure. Furthermore, because the isolation structure is protected by the protective layer and the dimensions of the opening are not altered, the conductive plugs are free of hollowing during the fabrication process, further improving the reliability of the semiconductor structure. Furthermore, because the dimensions of the opening remain unchanged, the conductive plugs are smaller in size, leaving a safety margin, further enhancing the reliability of the semiconductor structure.

[0047] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 2 As shown, Figure 2 A flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. The method for manufacturing a semiconductor structure includes:

[0048] S100. Provide a substrate, the substrate including multiple active areas, gate structures arranged on the active areas, and an isolation layer, an isolation structure is arranged between adjacent gate structures, the isolation layer covers the gate structure and the isolation structure, and fills the space between the gate structure and the isolation structure.

[0049] S200 , forming a plurality of openings on the isolation layer, wherein the bottom of each opening exposes a portion of the active area, and the side surfaces of the openings disposed near the isolation structure expose at least a portion of the surface of the isolation structure.

[0050] S300 , forming a protective layer, wherein the protective layer at least covers the surface of the isolation structure exposed through the side surface of the opening.

[0051] S400 , performing an ion implantation process on each active region through the bottom surface of the opening to form a source region or a drain region.

[0052] S500 , forming a conductive plug in each opening, wherein the conductive plug is connected to the corresponding source region or drain region.

[0053] In this embodiment, a substrate comprising multiple active regions, gate structures disposed on the active regions, and an isolation layer is provided. The substrate is processed to form a desired semiconductor structure. Multiple openings are formed in the isolation layer to allow ion implantation of the active regions and the formation of conductive plugs. A protective layer is formed covering the exposed surfaces of the isolation structures to protect them during the ion implantation process. Ion implantation is performed on each active region through the bottom surface of the openings to form a source region or a drain region. Conductive plugs connected to the corresponding source region or drain region are formed in each opening, allowing the source region or drain region to be externally connected through the corresponding conductive plug. Forming the protective layer on the exposed surfaces of the isolation structures prevents damage to the isolation structures during the ion implantation process, which could cause short circuits between adjacent conductive plugs. This improves the reliability of the semiconductor structure. Furthermore, because the protective layer is not easily damaged, the size of the openings remains substantially unchanged, preventing hollowing of the conductive plugs during the formation process, further improving the reliability of the semiconductor structure. Furthermore, because the size of the openings is largely unaffected by the ion implantation process, the conductive plugs can be kept small, retaining a sufficient safety margin, further improving the reliability of the semiconductor structure.

[0054] For example, Figure 3 As shown, the substrate provided in step S100 may be a substrate 10 including a plurality of active regions 11, a gate structure 12 disposed on the active regions 11, and an isolation layer 13. An isolation structure 14 is disposed between adjacent gate structures 12 in the substrate 10, and the isolation layer 13 covers the gate structure 12 and the isolation structure 14 and fills the space between the gate structure 12 and the isolation structure 14. Figure 4 As shown, in step S200, a plurality of openings are formed on the isolation layer. Part of the isolation layer 13 between the gate structure 12 and the isolation structure 14 can be removed by etching to form a plurality of openings 131. The cross-section of the opening 131 can be, for example, rectangular.

[0055] In some exemplary embodiments provided in the present disclosure, Figure 5 As shown, Figure 5 The flowchart of forming the protective layer in step S300 is shown, including:

[0056] S310 , forming a protection layer through a deposition process, where the protection layer covers the top surface of the isolation layer and the side and bottom surfaces of the opening.

[0057] S320: removing the protective layer on the bottom surface of the opening.

[0058] In this embodiment, since the protective layer needs to cover the surface of the isolation structure exposed through the side of the opening, the protective layer is formed by a process of depositing materials. Since the deposition process has no directionality, the protective layer formed not only covers the surface of the isolation structure exposed through the side of the opening, but also covers the top surface of the isolation layer and the side and bottom surfaces of the opening. Since the protective layer on the bottom surface of the opening affects ion implantation and the formation of the conductive plug, the protective layer located on the bottom surface of the opening is removed. By forming the protective layer by a deposition process, the protective layer is formed uniformly to avoid damage to the isolation structure, thereby improving the reliability of the semiconductor structure manufacturing. By removing the protective layer located on the bottom surface of the opening before forming the conductive plug, the protective layer is prevented from affecting the ion implantation and the formation of the conductive plug, thereby preventing the performance of the semiconductor structure from being reduced, thereby further improving the reliability of the semiconductor structure manufacturing.

[0059] In some exemplary embodiments provided in the present disclosure, the deposition process is an atomic layer deposition process (ALD).

[0060] For example, the protective layer formed by the deposition process in the above step may be a protective layer of an insulating material having a certain mechanical strength, and the insulating material may include silicon nitride. Figure 6 As shown, after forming the protective layer 30, the protective layer 30 covers the top surface of the isolation layer 13 and the side and bottom surfaces of the opening 131. That is, the protective layer 30 covers the top surface of the isolation layer 13, the surface of the isolation structure 14 exposed through the side surfaces of the opening 131, the portion of the isolation layer 13 exposed through the side surfaces of the opening 131, and the portion of the active area 11 exposed through the bottom surface of the opening 131. The protective layer 30 may not cover the top surface of the isolation layer 13.

[0061] For example, the removal of the protective layer on the bottom surface of the opening in the above step can be achieved by an etching process. Figure 7 As shown, after the protection layer 30 located on the bottom surface of the opening 131 is removed, a portion of the active area 11 located on the bottom surface of the opening 131 is exposed.

[0062] In some exemplary embodiments provided by the present disclosure, the temperature of the deposition process is less than or equal to 600°C.

[0063] In this embodiment, since the gate structure in the substrate may affect the performance of the semiconductor structure if processed using a high-temperature process after formation, the gate structure is prevented from being affected by the deposition process temperature being less than or equal to 600° C., thereby improving the reliability of the semiconductor structure fabrication.

[0064] In some exemplary embodiments provided by the present disclosure, the ion implantation process includes an ion implantation step, an ashing step, and a cleaning step.

[0065] In the present embodiment, ion implantation is performed by an ion implantation step to form a source region or a drain region in the active region. Since photoresist may remain after the ion implantation step, affecting subsequent processes, the photoresist is removed by an ashing step. Since contaminants may remain after the ashing step, affecting the performance of the semiconductor structure, the contaminants are removed by a cleaning step. By performing the ion implantation step, the ashing step, and the cleaning step, impurities that may affect subsequent processes and the performance of the semiconductor structure are avoided from remaining while forming the source region or the drain region, thereby improving the reliability of the semiconductor structure manufacturing.

[0066] For example, the ion implantation process may include one or more ion implantation steps, an ashing step, and a cleaning step. The ions implanted in the multiple ion implantation steps may be the same or different.

[0067] In one embodiment, the ions implanted in the ion implantation process include arsenic ions, germanium ions, and carbon ions.

[0068] In this embodiment, by injecting arsenic ions in an ion implantation process, a source region or a drain region can be formed in the active region. By injecting germanium ions in an ion implantation process, the mobility of carriers in the active region can be improved and the uniformity of doping can be optimized. By injecting carbon ions in an ion implantation process, the lifetime of carriers in the active region can be increased and the characteristics of the semiconductor structure can be adjusted. By injecting arsenic ions, germanium ions, and carbon ions in an ion implantation process, the performance of the semiconductor structure can be optimized, thereby improving the reliability of the semiconductor structure manufacturing.

[0069] It is understandable that the ions implanted in the ion implantation process may include not only arsenic ions, germanium ions and carbon ions, but also phosphorus ions, antimony ions, boron ions, indium ions, gallium ions, etc., which are not limited here.

[0070] Exemplarily, the ion implantation process may include the following steps: a first photolithography step, an arsenic ion implantation step, a first ashing step, a first cleaning step, a second photolithography step, a first germanium ion implantation step, a carbon ion implantation step, a second germanium ion implantation step, a second ashing step, a second cleaning step, a measurement step, a rapid thermal processing step, and a dry etching step.

[0071] In some exemplary embodiments provided by the present disclosure, the substrate is a silicon substrate. Before forming conductive plugs in each opening in step S500, the method for manufacturing the semiconductor structure further includes:

[0072] A first metal layer is formed on the bottom surface of the opening and is subjected to heat treatment to obtain a metal silicide layer.

[0073] In this embodiment, a first metal layer is formed on the bottom surface of the opening and then heat-treated to form a metal silicide layer, thereby reducing the contact resistance of the semiconductor structure. By reducing the contact resistance of the semiconductor structure, the performance of the semiconductor structure is improved, thereby improving the reliability of the semiconductor structure manufacturing.

[0074] In some exemplary embodiments provided in the present disclosure, Figure 8 As shown, Figure 8 The flowchart of the method for forming a conductive plug in each opening in step S500 is shown as an example, including:

[0075] S510 , forming an anti-diffusion layer in the opening, wherein the anti-diffusion layer covers the sidewalls of the opening and the top surface of the metal silicide layer, and the anti-diffusion layer encloses an accommodating space.

[0076] S520 , filling the accommodation space with a second metal layer to obtain a conductive plug.

[0077] In this embodiment, an anti-diffusion layer is formed in the opening to prevent diffusion of the second metal layer when the second metal layer is filled. By filling the accommodation space with the second metal layer, a conductive plug comprising the anti-diffusion layer and the second metal layer is formed. By sequentially forming the anti-diffusion layer and the second metal layer, the conductive plug can achieve better contact with the source or drain region, enhancing the performance of the semiconductor structure and thus improving the reliability of the semiconductor structure.

[0078] For example, the steps of forming the first metal layer on the bottom surface of the opening, forming the anti-diffusion layer in the opening in step S510, and filling the second metal layer in the accommodation space in step S520 can be achieved by a deposition process. Figure 9 As shown, the metal silicide layer 111 processed on the bottom surface of the opening 131 is located in the active area 11. The material of the metal silicide layer 111 may include cobalt silicide, for example. The anti-diffusion layer 21 formed in the opening 131 may cover the sidewalls of the opening 131, the top surface of the metal silicide layer 111, and the top surface of the isolation layer 13. In the subsequent patterning process, at least a portion of the anti-diffusion layer 21 on the top surface of the isolation layer 13 is removed. The material of the anti-diffusion layer 21 may include titanium nitride, for example. The material of the second metal layer 22 filled in the accommodating space may include tungsten, for example. Figure 1In contrast, since the isolation structure 14 is not damaged and the shape of the accommodating space is not expanded, no hollowing will occur when the conductive plug 20 is filled with the second metal layer 22 .

[0079] In some exemplary embodiments provided in the present disclosure, Figure 10 As shown, the method for manufacturing a semiconductor structure includes:

[0080] S600 , providing a substrate including a plurality of active regions, a gate structure disposed on the active regions, and an isolation layer.

[0081] S610 , forming a plurality of openings on the isolation layer.

[0082] S620 , forming a protection layer covering the surface of the isolation structure exposed through the side surface of the opening through a deposition process.

[0083] S630: Remove the protective layer on the bottom surface of the opening.

[0084] S640 , performing an ion implantation process on each active region through the bottom surface of the opening to form a source region or a drain region.

[0085] S650 , forming a first metal layer on the bottom surface of the opening, and performing heat treatment to obtain a metal silicide layer.

[0086] S660 , forming an anti-diffusion layer in the opening.

[0087] S670 , filling the accommodation space with a second metal layer to obtain a conductive plug.

[0088] In this embodiment, a substrate including multiple active regions, a gate structure disposed on the active regions, and an isolation layer is provided, so that the desired semiconductor structure can be formed by processing the substrate. Multiple openings are formed in the isolation layer so that ion implantation of the active regions and the formation of conductive plugs can be performed through the openings. A protective layer is formed by a deposition process to cover the surface of the isolation structure exposed through the side of the opening, so that the isolation structure is protected by the protective layer. Since the protective layer covers the active regions on the bottom surface of the opening, thereby affecting the formation and ion implantation of the conductive plug, the protective layer located on the bottom surface of the opening is removed. An ion implantation process is performed on each active region through the bottom surface of the opening to form a source region or a drain region, thereby obtaining a source region or a drain region. A first metal layer is formed on the bottom surface of the opening and heat-treated to obtain a metal silicide layer to reduce the contact resistance of the semiconductor structure. An anti-diffusion layer is formed in the opening to prevent the second metal layer from diffusing when the second metal layer is filled. The second metal layer is filled in the accommodation space to form a conductive plug comprising the anti-diffusion layer and the second metal layer. By forming a protective layer on the surface of the exposed isolation structure, damage to the isolation structure during the ion implantation process, which could cause short circuits between adjacent conductive plugs, improves the reliability of semiconductor structure fabrication. Furthermore, because the protective layer is not easily damaged, the size of the opening remains essentially unchanged, preventing hollowing of the conductive plug during the fabrication process, further improving the reliability of semiconductor structure fabrication. Furthermore, because the size of the opening is largely unaffected by the ion implantation process, the conductive plug can be kept small, retaining a sufficient safety margin, further enhancing the reliability of semiconductor structure fabrication.

[0089] In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, such as Figure 3 and Figure 9 As shown, the semiconductor structure includes a substrate 10, a conductive plug 20, and a protective layer 30. The substrate 10 includes multiple active regions 11, gate structures 12 disposed on the active regions 11, and an isolation layer 13. Isolation structures 14 are disposed between adjacent gate structures 12. The isolation layer 13 covers the gate structures 12 and the isolation structures 14 and fills the space between the gate structures 12 and the isolation structures 14. The isolation layer 13 is provided with multiple openings 131. The bottom of each opening 131 exposes a portion of the source region or drain region in the active region 11. The side surfaces of the openings 131 disposed near the isolation structures 14 expose at least a portion of the surface of the isolation structures 14. The conductive plugs 20 are disposed in the openings 131. The protective layer 30 is disposed between the conductive plugs 20 and the isolation structures 14.

[0090] In this embodiment, the semiconductor structure includes a substrate, a conductive plug, and a protective layer. An isolation structure is provided between adjacent gate structures on the substrate, and the surface of the isolation structure exposed through the side of the opening is covered with a protective layer. By covering the exposed surface of the isolation structure with the protective layer, the protective layer can prevent the risk of short circuits caused by a reduction in the distance between the conductive plugs located on both sides of the isolation structure, thereby improving the reliability of the semiconductor structure. At the same time, because the protective layer protects the isolation structure from damage, there is no hollowing in the conductive plug, further improving the reliability of the semiconductor structure. Furthermore, because the size of the isolation structure does not change and the protective layer reduces the size of the opening, the size of the conductive plug is smaller, retaining a sufficient safety margin, thereby further improving the reliability of the semiconductor structure.

[0091] For example, the gate structure 12 may include a plurality of materials stacked in sequence, such as silicon nitride, tungsten, titanium nitride, polysilicon, titanium nitride, lanthanum oxide, and hafnium silicate. The thicknesses of the materials in different layers may be the same or different.

[0092] In some exemplary embodiments provided in the present disclosure, the material of the isolation structure 14 includes oxide.

[0093] In this embodiment, by using oxide as at least one material of the isolation structure, isolation between conductive plugs can be effectively performed, thereby improving the reliability of the semiconductor structure.

[0094] In some exemplary embodiments provided by the present disclosure, the material of the protection layer 30 includes silicon nitride.

[0095] In this embodiment, due to the high mechanical strength of silicon nitride, the isolation structure can be effectively prevented from being damaged, thereby improving the reliability of the semiconductor structure.

[0096] Illustratively, the material of the isolation layer 13 and the material of the protection layer 30 may be the same or different.

[0097] It is understandable that the material of the protection layer 30 may include not only silicon nitride but also other insulating materials with certain mechanical strength, which is not limited here.

[0098] In some exemplary embodiments provided by the present disclosure, the thickness of the protective layer 30 is 1 mm to 10 mm.

[0099] In this embodiment, by setting the thickness of the protective layer to 1 mm to 10 mm, the protective layer is prevented from being too thin to protect the isolation structure or too thick to affect the formation of the conductive plug, thereby improving the reliability of the semiconductor structure.

[0100] In some exemplary embodiments provided by the present disclosure, the protection layer 30 covers the top surface of the isolation layer 13 and the side surfaces of the opening 131 , but does not cover the bottom surface of the opening 131 .

[0101] In this embodiment, by covering the top surface of the isolation layer and the side surfaces of the opening with a protective layer, damage to the isolation layer and the formation of hollows in the conductive plug are prevented, thereby improving the reliability of the semiconductor structure. By not covering the bottom surface of the opening with a protective layer, the metal silicide layer formed on the bottom surface of the opening is prevented from being affected and degrading the performance of the semiconductor structure, thereby further improving the reliability of the semiconductor structure.

[0102] In some exemplary embodiments provided in the present disclosure, a top surface of the isolation structure 14 is higher than a top surface of the gate structure 12 .

[0103] In this embodiment, by making the top surface of the isolation structure higher than the top surface of the gate structure, short circuits between adjacent gate structures are avoided, thereby improving the reliability of the semiconductor structure. Furthermore, because the top surface of the isolation structure is higher, adjacent conductive plugs can be effectively isolated, further improving the reliability of the semiconductor structure.

[0104] In some exemplary embodiments provided herein, substrate 10 is a silicon substrate, and a metal silicide layer 111 is disposed in the source region or drain region. Conductive plug 20 includes an anti-diffusion layer 21 and a second metal layer 22. Anti-diffusion layer 21 is disposed between the second metal layer 22 and the sidewalls of opening 131 and metal silicide layer 111.

[0105] In this embodiment, a metal silicide layer is provided on the bottom surface of the opening to reduce the contact resistance of the semiconductor structure. An anti-diffusion layer is provided on the conductive plug to prevent diffusion of the second metal layer. By using the anti-diffusion layer and the second metal layer as a conductive plug, the conductive plug can effectively connect the active area and external structures, thereby improving the reliability of the semiconductor structure.

[0106] Exemplarily, the metal silicide layer 111 is located in the active region 11. The material of the metal silicide layer 111 may include, for example, cobalt silicide. The anti-diffusion layer 21 may cover the sidewalls of the opening 131, the top surface of the metal silicide layer 111, and the top surface of the isolation layer 13. The material of the anti-diffusion layer 21 may include, for example, titanium nitride. The material of the second metal layer 22 may include, for example, tungsten.

[0107] In some exemplary embodiments provided in the present disclosure, Figure 9As shown, the semiconductor structure includes a substrate 10, a conductive plug 20, and a protective layer 30. The substrate 10 includes multiple active regions 11, gate structures 12 disposed on the active regions 11, and an isolation layer 13. An isolation structure 14 is disposed between adjacent gate structures 12. The gate structures 12 include multiple materials stacked in sequence. The isolation layer 13 covers the gate structures 12 and the isolation structures 14 and fills the space between the gate structures 12 and the isolation structures 14. The isolation layer 13 is provided with multiple openings 131. The bottom of each opening 131 exposes a portion of the source region or drain region in the active region 11. The side surfaces of the openings 131 disposed near the isolation structures 14 expose at least a portion of the surface of the isolation structures 14. The top surface of the isolation structures 14 is higher than the top surface of the gate structures 12. The bottom surface of the openings 131 is provided with a metal silicide layer 111. The metal silicide layer 111 is located in the active region 11. The conductive plug 20 includes an anti-diffusion layer 21 and a second metal layer 22. The anti-diffusion layer 21 is disposed between the second metal layer 22 and the sidewalls of the opening 131 and the metal silicide layer 111. The protection layer 30 is disposed between the conductive plug 20 and the isolation structure 14.

[0108] In some exemplary embodiments provided in the present disclosure, the semiconductor structure is a dynamic random access memory, such as Figure 3 and Figure 9 As shown, the substrate 10 includes a substrate 10. The substrate 10 is divided into an array region and a peripheral region. The array region is used for data storage, and the peripheral region is used for array region operations. The peripheral region includes multiple active regions 11, gate structures 12 disposed on the active regions 11, and an isolation layer 13. Isolation structures 14 are disposed between adjacent gate structures 12. The gate structures 12 include multiple materials stacked in sequence. The isolation layer 13 covers the gate structures 12 and the isolation structures 14 and fills the space between the gate structures 12 and the isolation structures 14. The isolation layer 13 is provided with multiple openings 131. The bottom of each opening 131 exposes a portion of the source region or drain region in the active region 11. The side surfaces of the openings 131 disposed near the isolation structures 14 expose at least a portion of the surface of the isolation structures 14. The top surface of the isolation structures 14 is higher than the top surface of the gate structures 12. The bottom surface of the openings 131 is provided with a metal silicide layer 111. The metal silicide layer 111 is located in the active region 11. The conductive plug 20 includes an anti-diffusion layer 21 and a second metal layer 22. The anti-diffusion layer 21 is disposed between the second metal layer 22 and the sidewalls of the opening 131 and the metal silicide layer 111. The protection layer 30 is disposed between the conductive plug 20 and the isolation structure 14.

[0109] In this disclosure, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the article or device comprising the element.

[0110] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0111] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: Providing a substrate, the substrate comprising a plurality of active regions, a gate structure disposed on the active regions, and an isolation layer, wherein an isolation structure is disposed between adjacent gate structures, the isolation layer covers the gate structure and the isolation structure, and fills the space between the gate structure and the isolation structure; forming a plurality of openings on the isolation layer, wherein a bottom of each of the openings exposes a portion of the active area, and a side surface of the opening disposed near the isolation structure exposes at least a portion of a surface of the isolation structure; forming a protective layer, wherein the protective layer at least covers the surface of the isolation structure exposed through the side of the opening; Performing an ion implantation process on each of the active regions through the bottom surface of the opening to form a source region or a drain region; forming a conductive plug in each of the openings, wherein the conductive plug is connected to the corresponding source region or drain region; Wherein, forming a protective layer comprises: forming the protective layer by a deposition process, wherein the protective layer covers the top surface of the isolation layer and the side and bottom surfaces of the opening; The protective layer on the bottom surface of the opening is removed to avoid affecting the ion implantation process.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The temperature of the deposition process is less than or equal to 600°C.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The substrate is a silicon substrate; Before forming a conductive plug in each of the openings, the method for manufacturing the semiconductor structure further includes: A first metal layer is formed on the bottom surface of the opening and is subjected to heat treatment to obtain a metal silicide layer.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The step of forming a conductive plug in each of the openings includes: forming an anti-diffusion layer in the opening, wherein the anti-diffusion layer covers the sidewalls of the opening and the top surface of the metal silicide layer, and the anti-diffusion layer encloses an accommodating space; A second metal layer is filled in the accommodation space to obtain the conductive plug.

5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The ion implantation process includes an ion implantation step, an ashing step, and a cleaning step.

6. A semiconductor structure manufactured by the manufacturing method according to any one of claims 1 to 5, characterized in that: The semiconductor structure comprises: a substrate comprising a plurality of active regions, gate structures disposed on the active regions, and an isolation layer, wherein an isolation structure is disposed between adjacent gate structures, the isolation layer covers the gate structures and the isolation structures and fills the space between the gate structures and the isolation structure, and the isolation layer is provided with a plurality of openings, the bottom of each of the openings exposing a portion of a source region or a drain region in the active region, and a side surface of the opening disposed near the isolation structure exposes at least a portion of a surface of the isolation structure; a conductive plug disposed in the opening; A protection layer is disposed between the conductive plug and the isolation structure.

7. The semiconductor structure according to claim 6, wherein: The material of the isolation structure includes oxide.

8. The semiconductor structure according to claim 6, wherein: The material of the protective layer includes silicon nitride; and / or the thickness of the protective layer is 1 mm to 10 mm.

9. The semiconductor structure according to any one of claims 6 to 8, characterized in that: The substrate is a silicon substrate, and a metal silicide layer is provided in the source region or the drain region; the conductive plug includes: An anti-diffusion layer and a second metal layer, wherein the anti-diffusion layer is disposed between the second metal layer and the sidewall of the opening and the metal silicide layer.

10. The semiconductor structure according to any one of claims 6 to 8, characterized in that: A top surface of the isolation structure is higher than a top surface of the gate structure.

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