Integrated circuit device and electronic system including same

Abstract

An integrated circuit device and an electronic system are disclosed. The integrated circuit device includes: a substrate; a channel region disposed in the substrate; a gate structure disposed on the channel region and including a gate dielectric layer, a gate electrode, and a gate capping layer sequentially stacked, and first and second gate spacers on first and second respective opposing sidewalls of the gate dielectric layer, the gate electrode, and the gate capping layer; a source region and a drain region disposed on opposite sides of the channel region; a source contact contacting the source region; a resistive structure contacting the drain region and including doped polysilicon; and a drain contact contacting the resistive structure and including a metal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2023 - 0197701, filed with the Korean Intellectual Property Office on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Aspects of the present inventive concept relate to an integrated circuit device and an electronic system including the integrated circuit device. More particularly, the present inventive concept relates to an integrated circuit device including a peripheral circuit transistor and an electronic system including the integrated circuit device. Background art

[0004] To meet the demands for excellent performance and economic feasibility, an integrated circuit device needs to have an increased integration degree. Specifically, the integration degree of a memory device is a key factor determining the economic feasibility of a product including the memory device. The integration degree of a two - dimensional memory device is mainly determined by the area occupied by a unit memory cell, and thus is greatly affected by the level of technology for forming a micro - pattern. However, to form a micro - pattern, expensive equipment is generally required, and the area of a chip die is limited. Therefore, although the integration degree of a two - dimensional memory device is increased, such an increase is still limited. Accordingly, technologies for increasing the integration degree of a two - dimensional memory device and technologies for a vertical memory device having a three - dimensional structure are being developed. Summary of the invention

[0005] Aspects of the present inventive concept provide an integrated circuit device and an electronic system including the integrated circuit device, which have a high integration degree since a resistance structure is formed in a drain region in a vertical direction and thereby replaces a field relaxation transistor (FRT) arranged in a horizontal direction.

[0006] The objects of the present inventive concept are not limited to those mentioned above, and one of ordinary skill in the art will clearly understand other unmentioned objects from the following description.

[0007] According to an aspect of the present inventive concept, an integrated circuit device includes: a substrate; a channel region disposed in the substrate; a gate structure disposed on the channel region and including a gate dielectric layer, a gate electrode, and a gate capping layer sequentially stacked, and first and second gate spacers on first and second corresponding opposite sidewalls of the gate dielectric layer, the gate electrode, and the gate capping layer; a source region and a drain region disposed on opposite sides of the channel region; a source contact contacting the source region; a resistance structure contacting the drain region and including doped polysilicon; and a drain contact contacting the resistance structure and including metal.

[0008] According to another aspect of the inventive concept, an integrated circuit device includes: a peripheral circuit structure and a cell array structure over the peripheral circuit structure, wherein the peripheral circuit structure includes a circuit substrate, peripheral circuit transistors on the circuit substrate, lower lines connected to the peripheral circuit transistors, and a first insulating layer covering the peripheral circuit transistors and the lower lines, and the cell array structure includes gate stacks, a plurality of channel structures extending through the gate stacks, and a second insulating layer covering the gate stacks, the gate stacks including a plurality of gate electrodes and a plurality of insulating layers stacked alternately, wherein the peripheral circuit transistors include: a channel region disposed in the circuit substrate; a gate structure disposed over the channel region and including a gate dielectric layer, a gate electrode, and a gate capping layer stacked in sequence, and first and second gate spacers on first respective opposite sidewalls and second respective opposite sidewalls of the gate dielectric layer, the gate electrode, and the gate capping layer; a source region and a drain region disposed on opposite sides of the channel region; a source contact contacting the source region; and a resistance structure contacting the drain region and a drain contact contacting the resistance structure.

[0009] According to another aspect of the inventive concept, an electronic system includes a main substrate, an integrated circuit device on the main substrate, and a controller electrically connected to the integrated circuit device on the main substrate. The integrated circuit device includes a peripheral circuit structure and a cell array structure disposed over the peripheral circuit structure, wherein the peripheral circuit structure includes a circuit substrate, peripheral circuit transistors on the circuit substrate, lower lines connected to the peripheral circuit transistors, and a first insulating layer covering the peripheral circuit transistors and the lower lines, and the cell array structure includes gate stacks, a plurality of channel structures extending through the gate stacks, and a second insulating layer covering the gate stacks, the gate stacks including a plurality of gate electrodes and a plurality of insulating layers stacked alternately. The peripheral circuit transistors include: a channel region disposed in the circuit substrate; a gate structure disposed over the channel region and including a gate dielectric layer, a gate electrode, and a gate capping layer stacked in sequence and gate spacers on opposite sidewalls of the gate dielectric layer, the gate electrode, and the gate capping layer; a source region and a drain region disposed on opposite sides of the channel region; a source contact contacting the source region; and a resistance structure contacting the drain region and a drain contact contacting the resistance structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic plan view of structural elements of an integrated circuit device according to an embodiment;

[0012] Figure 2 is a cross-sectional view of an integrated circuit device taken along line A-A' of Figure 1 ;

[0013] Figures 3 to 5 is a cross-sectional view of an integrated circuit device according to some embodiments;

[0014] Figure 6 is a flowchart of a method for manufacturing an integrated circuit device according to an embodiment;

[0015] Figures 7 to 17 is a cross-sectional view showing a method for manufacturing an integrated circuit device according to an embodiment in a process sequence;

[0016] Figure 18 is a block diagram of a three-dimensional integrated circuit device according to an embodiment;

[0017] Figure 19 is an equivalent circuit diagram of a memory cell array of a three-dimensional integrated circuit device according to an embodiment;

[0018] Figure 20 is a schematic plan view of a structural element of a three-dimensional integrated circuit device according to an embodiment;

[0019] Figure 21 is along Figure 20 a cross-sectional view of a three-dimensional integrated circuit device taken along line B-B';

[0020] Figure 22 is Figure 21 an enlarged view of region CC of

[0021] Figure 23 is Figure 21 an enlarged view of region DD of

[0022] Figure 24 is Figure 21 an enlarged view of region EE of

[0023] Figure 25 and Figure 26 are cross-sectional views of a three-dimensional integrated circuit device according to some embodiments;

[0024] Figure 27 is a diagram of an electronic system including an integrated circuit device according to an embodiment;

[0025] Figure 28 is a perspective view of an electronic system including an integrated circuit device according to an embodiment;

[0026] Figure 29 and Figure 30 are cross-sectional views of a semiconductor package including an integrated circuit device according to an embodiment. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0028] Throughout this specification, when a component is described as "including" a particular element or a set of elements, it will be understood that, unless the context clearly and / or explicitly dictates otherwise, the component consists only of that element or that set of elements, or that element or that set of elements may be combined with additional elements to form the component. On the other hand, the term "consisting of" indicates that the component consists only of the listed element(s).

[0029] It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on" another element, the element may be directly connected or directly coupled to the other element or directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element or "contacting" another element or "in contact with" another element (or using any form of the word "contact"), there are no intervening elements at the point of contact.

[0030] Terms such as "same", "equal", "flat", "coplanar", "parallel", and "perpendicular" as used herein encompass the same or approximately the same including variations that may be caused by conventional manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0031] Figure 1 is a schematic plan view of structural elements of an integrated circuit device 10 according to an embodiment. Figure 2 is along Figure 1 a cross-sectional view of the integrated circuit device 10 taken along line A-A' of.

[0032] Referring to Figure 1 and Figure 2 , the integrated circuit device 10 may include a channel region 62C, a source region 62S, and a drain region 62D disposed in a substrate 101, and a gate structure 60G, a source contact 72S, a drain contact 72D, and a resistor structure RS disposed on the substrate 101.

[0033] According to some embodiments, the substrate 101 may include silicon, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon. According to some embodiments, the substrate 101 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. According to some embodiments, the substrate 101 may include a conductive region, such as a well doped with impurities or a structure doped with impurities.

[0034] In the substrate 101, a channel region 62C, a source region 62S, and a drain region 62D may be disposed, where the source region 62S and the drain region 62D may be disposed on opposite sides of the channel region 62C in a first direction (X direction). According to some embodiments, the source region 62S and the drain region 62D may be formed by an ion implantation process using the gate structure 60G as a mask. Accordingly, the source region 62S and the drain region 62D may be formed on opposite sides of the gate structure 60G in the substrate 101, and the channel region 62C may be defined under the gate structure 60G.

[0035] According to some embodiments, the source region 62S and the drain region 62D may use the gate spacer 60S as an ion mask. For example, the source region 62S and the drain region 62D may also be formed by a first ion implantation process and a second ion implantation process performed before and after forming the gate spacer 60S.

[0036] The integrated circuit device 10 may include an nMOS region and a pMOS region. The source region 62S and the drain region 62D formed in the nMOS region of the integrated circuit device 10 and the source region 62S and the drain region 62D formed in the pMOS region of the integrated circuit device 10 may have different conduction types from each other. Specifically, each of the source region 62S and the drain region 62D in the pMOS region may have p-type conductivity. Additionally, each of the source region 62S and the drain region 62D in the nMOS region may have n-type conductivity.

[0037] According to some embodiments, the channel region 62C disposed under the gate structure 60G may have the same type of conductivity as the substrate 101 disposed under the gate structure 60G, and may have a different type of conductivity from the source region 62S and the drain region 62D formed around the gate structure 60G.

[0038] On the substrate 101, a gate structure 60G longitudinally extending in a second direction (Y direction) may be disposed above the channel region 62C. An item, layer, or part of an item or layer described as extending "longitudinally" in a specific direction has a length in that specific direction and a width perpendicular to that direction, where the length is greater than the width. The gate structure 60G may include a gate dielectric layer 60D, a gate electrode 60E, a gate capping layer 60C, and gate spacers 60S (e.g., two gate spacers).

[0039] The gate dielectric layer 60D may be disposed over the channel region 62C. The gate dielectric layer 60D may include silicon oxide, silicon oxynitride, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high-k dielectric material may include a metal oxide or a metal oxynitride. For example, the high-k dielectric material that may be included in the gate dielectric layer 60D may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0040] The gate electrode 60E may be disposed over the gate dielectric layer 60D. The gate electrode 60E may include doped polysilicon, a metal, or a combination thereof.

[0041] The gate capping layer 60C may be disposed over the gate electrode 60E. The gate capping layer 60C may cover the upper surface of the gate electrode 60E and may extend in a second direction (Y direction). For example, the gate capping layer 60C may include silicon nitride.

[0042] The gate spacers 60S may be disposed at two (e.g., opposite) sidewalls of the gate dielectric layer 60D, the gate electrode 60E, and the gate capping layer 60C and may extend in the second direction (Y direction). There may be two gate spacers 60S for each gate structure 60G, the two gate spacers 60S including a first gate spacer 60S on a first combined sidewall of the gate dielectric layer 60D, the gate electrode 60E, and the gate capping layer 60C and a second gate spacer 60S on a second combined sidewall of the gate dielectric layer 60D, the gate electrode 60E, and the gate capping layer 60C opposite the first combined sidewall. According to some embodiments, the gate spacers 60S may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or a combination thereof.

[0043] According to some embodiments, the gate spacers 60S may include a plurality of layers including materials different from each other. In Figure 2 FIG., the gate spacer 60S is shown including a single layer. However, in contrast thereto, the gate spacer 60S may include a first spacer layer (not shown), a second spacer layer (not shown), and a third spacer layer (not shown) sequentially stacked on the sidewalls of the gate dielectric layer 60D, the gate electrode 60E, and the gate capping layer 60C. According to some embodiments, the first spacer layer and the third spacer layer may include silicon nitride, silicon oxide, or silicon oxynitride. The second spacer layer may include an insulating material having a dielectric constant lower than that of the first spacer layer. For example, the second spacer layer may include an air space (i.e., a gas gap).

[0044] The interlayer insulating layer 80 covering the gate structure 60G may be disposed on the substrate 101. The interlayer insulating layer 80 may include silicon nitride, silicon oxide, silicon oxynitride, a TEOS layer, or an ultra-low-k (ULK) layer having an ultra-low dielectric constant of about 2.2 to about 2.4.

[0045] The integrated circuit device 10 may include different contact structures. For example, in one embodiment, the source contact 72S passes through the interlayer insulating layer 80 and is electrically connected to the source region 62S. Additionally, in one embodiment, the drain contact 72D passes through the interlayer insulating layer 80 and is electrically connected to the drain region 62D. Additionally, in one embodiment, the gate contact 72G passes through the interlayer insulating layer 80 and the gate capping layer 60C and is electrically connected to the gate electrode 60E.

[0046] Each contact structure (i.e., the source contact 72S, the drain contact 72D, and the gate contact 72G) may include a metal, a metal nitride, a metal silicide, or a combination thereof. For example, the source contact 72S, the drain contact 72D, and the gate contact 72G may be formed as a bilayer structure including a metal buried layer (not shown) and a conductive barrier layer (not shown) surrounding the side and bottom surfaces of the metal buried layer. For example, the metal buried layer may include at least one of Co, W, Ni, Ru, Gu, Al, its silicide, and its alloy, and the conductive barrier layer may include Ti, Ta, Ru, TiN, TaN, or a combination thereof, but the metal buried layer and the conductive barrier layer are not limited thereto.

[0047] In Figure 1 it is shown that one gate contact 72G may be disposed at the center of the gate structure 60G, and two source contacts 72S and two drain contacts 72D may be respectively disposed on both sides of the gate structure 60G. However, differently, two or more gate contacts 72G may be disposed at the center of the gate structure 60G, and three or more source contacts 72S and three or more drain contacts 72D may be respectively disposed on both sides of the gate structure 60G.

[0048] The integrated circuit device 10 according to the inventive concept may include a resistor structure RS that contacts the drain region 62D and includes doped polysilicon. The resistor structure RS may be formed by including doped polysilicon having a relatively higher resistance than a metal, such that the resistance on the drain region 62D may be increased. Accordingly, a first resistance of the source contact 72S not disposed with the resistor structure RS on the source region 62S may be less than a second resistance of the combined drain contact 72D and the resistor structure RS disposed with the resistor structure RS on the drain region 62D. The combined drain contact 72D and the resistor structure RS may form a contact described as a via electrode having a resistance different from that of a contact (e.g., a via electrode) including the source contact 72S. A component connecting the source region 62S to another wiring layer may generally be described as a source via electrode, and a component connecting the drain region 62D to another wiring layer may generally be described as a drain via electrode. In Figure 1 and Figure 2In the example of , the source via electrode may be the source contact 72S, and the drain via electrode may be a combination of the drain contact 72D and the resistor structure RS.

[0049] Here, the resistance of the resistor structure RS may vary according to the integrated circuit device 10 and may be determined by at least one of the doping concentration of the doped polysilicon included in the resistor structure RS, the grain size of the doped polysilicon, and the thickness of the doped polysilicon.

[0050] The resistor structure RS may contact each of the drain region 62D and the drain contact 72D. The first interface between the resistor structure RS and the drain region 62D and the second interface between the resistor structure RS and the drain contact 72D may not include materials that are substantially different from each other. Specifically, a silicide layer may not be formed on the second interface between the resistor structure RS and the drain contact 72D.

[0051] According to some embodiments, the source contact 72S, the drain contact 72D, and the gate contact 72G may be formed in the same process including materials that are substantially the same as each other. Therefore, the source contact 72S and the gate contact 72G may also include the metal, metal nitride, metal silicide, or a combination thereof included in the drain contact 72D. However, the source contact 72S and the gate contact 72G may not include the doped polysilicon included in the resistor structure RS.

[0052] In the integrated circuit device 10 according to an embodiment, the resistor structure RS may have a U shape with a trench in its center in a cross-sectional view, and the drain contact 72D may be arranged to fill the trench of the resistor structure RS. Additionally, the vertical level of the uppermost surface of the resistor structure RS and the vertical level of the uppermost surface of the drain contact 72D may be substantially the same as each other. In a three-dimensional aspect, the resistor structure RS may have a cup shape including an internal hole filled with the drain contact 72D. The cup shape may have square or rectangular sidewalls or circular sidewalls.

[0053] According to some embodiments, the maximum width of the resistor structure RS in the first direction (X direction) may be greater than the maximum width of the drain contact 72D in the first direction (X direction). For example, the drain contact 72D may be arranged only in the trench of the resistor structure RS. The resistor structure RS may be described as a drain contact cover or a drain contact shell surrounding the drain contact 72D. Additionally, more generally, as described in various embodiments, the resistor structure may be described as, for example, a resistor via that serves as a resistor or a higher resistance region between the drain contact 72D and the drain region 62D.

[0054] According to some embodiments, the resistive structure RS may include a bottom and sidewalls disposed on the bottom, and the thickness of the bottom in the vertical direction (Z direction) may have a value greater than the width of any one of the sidewalls in the first direction (X direction). As Figure 1 indicated, the sidewalls may be on each of the four sides of the drain contact 72D, and thus may be formed on the opposite sidewalls of the drain contact 72D in each of two horizontal directions (e.g., the X direction and the Y direction). Although a rectangular resistive structure RS is depicted, this is merely an example, and the shapes of the drain contact 72D and the resistive structure RS may be circular, elliptical, or other shapes when viewed from a plan view. Thus, in some examples, the resistive structure RS may have a single continuous sidewall with different cross-sections. When viewed from a cross-sectional view in the horizontal direction, these sidewalls may be described as separate sidewalls (even though they are part of a single continuously curved sidewall). The above width may be a characteristic of the manufacturing process for filling the drain contact hole 80HD having a high aspect ratio (see Figure 9 ).

[0055] To meet the criteria of excellent performance and economic feasibility, it is generally necessary to increase the integration degree of an integrated circuit device. Specifically, the integration degree of a memory device is an important factor for determining the economic feasibility of a product. The integration degree of a two-dimensional integrated circuit is mainly determined by the area occupied by a unit memory cell.

[0056] Generally, as an operating transistor of a two-dimensional integrated circuit device, a field relaxation transistor (FRT) disposed in the horizontal direction may be used as a resistor, such that the voltage applied to the drain region of the operating transistor becomes less than the drain voltage Vd. Thus, the degradation of the reliability of the operating transistor caused by the lateral field effect due to the drain voltage Vd can be reduced. However, in this case, although the degradation of reliability is reduced, the integration degree may be hindered according to the area occupied by the FRT.

[0057] Thus, in the integrated circuit device 10 according to an embodiment of the inventive concept, the resistive structure RS may be formed on the drain region 62D in the vertical direction (Z direction) to replace the FRT in the first direction (X direction), and thus, the area occupied by the FRT according to the prior art may be reduced.

[0058] Thus, the integrated circuit device 10 according to the inventive concept may improve the electrical characteristics (e.g., reliability degradation) of the operating transistor and may also achieve a high integration degree of the two-dimensional operating transistor.

[0059] Figures 3 to 5 are cross-sectional views of integrated circuit devices 20, 30, and 40 according to some embodiments.

[0060] Most of the elements included in the integrated circuit devices 20, 30, and 40 described below, and the materials included in the elements, may be substantially the same as or similar to those described above with reference to Figure 1 and Figure 2 . Therefore, for ease of explanation, the description will be given based on the differences from the above-described integrated circuit device 10.

[0061] Referring to Figure 3 , the integrated circuit device 20 may include a channel region 62C, a source region 62S, and a drain region 62D disposed in a substrate 101, and a gate structure 60G, a source contact 72S, a drain contact 72D2, and a resistance structure RS2 disposed on the substrate 101.

[0062] In the integrated circuit device 20 according to an embodiment, the source contact 72S may be in contact with the upper surface of the source region 62S on the same plane, and the resistance structure RS2 may extend downward in the vertical direction (Z direction) beyond the upper surface of the drain region 62D. Therefore, the vertical level of the lowermost surface of the source contact 72S may be higher than the vertical level of the lowermost surface of the resistance structure RS2. This may be a characteristic of the manufacturing process in which the drain contact hole 80HD (see Figure 9 ) and the source contact hole 80HS (see Figure 15 ) are formed in different processes.

[0063] According to some embodiments, in a cross-sectional view, the resistance structure RS2 may have a U-shape with a groove in its center, and the drain contact 72D2 may be arranged to fill the groove of the resistance structure RS2. Additionally, the vertical level of the uppermost surface of the resistance structure RS2 and the vertical level of the uppermost surface of the drain contact 72D2 may be substantially the same as each other. In a three-dimensional aspect, the resistance structure RS2 may have a cup shape including an internal hole filled with the drain contact 72D2.

[0064] According to some embodiments, the maximum width of the resistance structure RS2 in the first direction (X direction) may be greater than the maximum width of the drain contact 72D2 in the first direction (X direction). That is, the drain contact 72D2 may be arranged only in the groove of the resistance structure RS2.

[0065] According to some embodiments, the resistance structure RS2 may include a bottom and sidewalls disposed on the bottom, and the thickness of the bottom in the vertical direction (Z direction) may have a value greater than the width of any one of the sidewalls in the first direction (X direction). This may be a characteristic of the manufacturing process of filling the drain contact hole 80HD (see Figure 10 ) having a high aspect ratio.

[0066] Referring to Figure 4, the integrated circuit device 30 may include a channel region 62C, a source region 62S, and a drain region 62D disposed in a substrate 101, and a gate structure 60G, a source contact 72S, a drain contact 72D3, and a resistor structure RS3 disposed on the substrate 101.

[0067] In the integrated circuit device 30 according to an embodiment, the resistor structure RS3 may have a U-shape (e.g., cup-shaped from a three-dimensional perspective) having a trench in its center, and the drain contact 72D3 may be disposed to fill the trench (e.g., the hole in the resistor structure RS3) of the resistor structure RS3. Additionally, the vertical level of the uppermost surface of the resistor structure RS3 may be lower than the vertical level of the uppermost surface of the drain contact 72D3.

[0068] According to some embodiments, the maximum width of the resistor structure RS3 in a first direction (X direction) may be substantially the same as the maximum width of the drain contact 72D3 in the first direction (X direction). That is, the drain contact 72D3 may be disposed above the trench of the resistor structure RS3.

[0069] According to some embodiments, the resistor structure RS3 may include a bottom and sidewalls disposed on the bottom, and the thickness of the bottom in a vertical direction (Z direction) may have a value greater than the width of any one of the sidewalls in the first direction (X direction). This may be a characteristic of a manufacturing process for filling a drain contact hole 80HD having a high aspect ratio (see Figure 10 ).

[0070] Referring to Figure 5 , the integrated circuit device 40 may include a channel region 62C, a source region 62S, and a drain region 62D disposed in a substrate 101, and a gate structure 60G, a source contact 72S, a drain contact 72D4, and a resistor structure RS4 disposed on the substrate 101.

[0071] In the integrated circuit device 40 according to an embodiment, the resistor structure RS4 may have a rectangular shape, and the drain contact 72D4 may have another rectangular shape that completely covers the upper surface of the resistor structure RS4. For example, the two rectangular shapes may be solid rectangular shapes.

[0072] According to some embodiments, the maximum width of the resistor structure RS4 in a first direction (X direction) may be substantially the same as the maximum width of the drain contact 72D4 in the first direction (X direction). That is, the drain contact 72D4 and the resistor structure RS4 may have rectangular shapes having different lengths in a vertical direction (Z direction).

[0073] Figure 6 is a flowchart of a method of manufacturing an integrated circuit device according to an embodiment.

[0074] Referring toFigure 6 The method S10 of manufacturing an integrated circuit device may include a process sequence of a first operation S110 to a sixth operation S160.

[0075] When a specific embodiment is implemented differently, the specific operation sequence may be different from the described sequence. For example, two operations described sequentially may be performed substantially simultaneously, or may be performed in an order opposite to the described order.

[0076] The method S10 of manufacturing an integrated circuit device according to an embodiment of the inventive concept may include: a first operation S110 of forming a channel region, a source region, and a drain region in a substrate and forming a gate structure and an interlayer insulating layer on the substrate; a second operation S120 of forming a drain contact hole that penetrates the interlayer insulating layer and exposes the drain region; a third operation S130 of forming a resistance structure that fills a part of the drain contact hole; a fourth operation S140 of forming a source contact hole that penetrates the interlayer insulating layer and exposes the source region; a fifth operation S150 of forming an initial contact layer that fills the remaining portions of the entire source contact hole and the drain contact hole; and a sixth operation S160 of forming a source contact and a drain contact by removing an upper portion of the initial contact layer.

[0077] will be described below with reference to Figures 7 to 17 the technical characteristics of each of the first operation S110 to the sixth operation S160 will be described in detail.

[0078] Figures 7 to 17 is a cross-sectional view showing a method of manufacturing an integrated circuit device according to an embodiment in accordance with a process sequence.

[0079] Referring to Figure 7 , an initial gate dielectric layer (not shown), an initial gate electrode layer (not shown), and a gate capping layer 60C may be sequentially formed on the substrate 101.

[0080] The initial gate electrode layer and the initial gate dielectric layer may be patterned by using the gate capping layer 60C as an etch mask to form a gate electrode 60E and a gate dielectric layer 60D.

[0081] Next, a spacer insulating layer (not shown) covering the gate capping layer 60C, the gate electrode 60E, and the gate dielectric layer 60D may be formed by using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process, and an anisotropic etching process may be performed on the spacer insulating layer to form gate spacers 60S on sidewalls of the gate capping layer 60C, the gate electrode 60E, and the gate dielectric layer 60D. Accordingly, a gate structure 60G may be formed on the substrate 101.

[0082] Here, the channel region 62C, source region 62S, and drain region 62D disposed in the substrate 101 can be formed by an ion implantation process performed before, during, and / or after forming the gate structure 60G.

[0083] Next, an interlayer insulating layer 80 covering the gate structure 60G can be formed on the substrate 101. Next, a first mask pattern MP1 can be formed on the interlayer insulating layer 80. The first mask pattern MP1 can be formed into a desired pattern by using an exposure process and a development process.

[0084] Referring to Figure 8 , a drain contact hole 80HD passing through the interlayer insulating layer 80 and exposing the upper surface of the drain region 62D can be formed by using the first mask pattern MP1 as an etching mask.

[0085] Referring to Figure 9 , the first mask pattern MP1 (see Figure 8 ) can be removed by an ashing process and a stripping process. The first mask pattern MP1 (see Figure 8 ) can generally be a photoresist pattern and can be completely removed by the above processes.

[0086] Referring to Figure 10 , an initial resistance structure layer RSL filling the drain contact hole 80HD can be formed on the interlayer insulating layer 80. The initial resistance structure layer RSL can include doped polysilicon. According to some embodiments, based on the high aspect ratio of the drain contact hole 80HD, the thickness of the sidewall of the initial resistance structure layer RSL can be less than the thickness of its bottom.

[0087] Referring to Figure 11 , before the upper surface of the interlayer insulating layer 80 is exposed, the upper portion of the initial resistance structure layer RSL (see Figure 10 ) can be removed to form a resistance structure RS filling a part of the drain contact hole 80HD. Therefore, the resistance structure RS can be formed into a U-shape having a trench in its center (viewed from a cross-sectional view), or a cup-shape having a hole formed therein (as viewed from a three-dimensional perspective).

[0088] Referring to Figure 12 , a hard mask HM filling the remaining portion of the drain contact hole 80HD can be formed on the interlayer insulating layer 80. For example, the hard mask HM can include a carbon-based material. Specifically, the hard mask HM can include a spin-on hard mask (SOH) or the like, which is a layer including an amorphous carbon layer (ACL) or a hydrocarbon compound or a derivative thereof, and the hydrocarbon compound has a relatively increased carbon content of about 85 wt% to about 99 wt% with respect to the total weight %.

[0089] Referring to Figure 13, a second mask pattern MP2 can be formed on the hard mask HM. The second mask pattern MP2 can be formed into a desired pattern by using an exposure process and a development process.

[0090] Referring to Figure 14 , by using the second mask pattern MP2 as an etching mask, a source contact hole 80HS that penetrates the hard mask HM and the interlayer insulating layer 80 and exposes the upper surface of the source region 62S can be formed. Although not shown, in the process of forming the source contact hole 80HS, a gate contact hole (not shown) that exposes the upper surface of the gate electrode 60E can also be formed.

[0091] Referring to Figure 15 , the second mask pattern MP2 (see Figure 14 ) and the hard mask HM (see Figure 14 ) can be removed by an ashing process and a stripping process. The second mask pattern MP2 (see Figure 14 ) can generally be a photoresist pattern and can be completely removed by the above processes.

[0092] Referring to Figure 16 , an initial contact layer 72L that fills the source contact hole 80HS and the drain contact hole 80HD can be formed on the interlayer insulating layer 80. The initial contact layer 72L can include a metal, a metal nitride, a metal silicide, or a combination thereof. Here, a silicide layer is not formed at the interface between the initial contact layer 72L and the resistance structure RS.

[0093] Referring to Figure 17 , before the upper surface of the interlayer insulating layer 80 is exposed, the upper portion of the initial contact layer 72L (see Figure 16 ) can be removed to form a source contact 72S that completely fills the source contact hole 80HS and a drain contact 72D that fills the remaining portion of the drain contact hole 80HD. Although not shown, in the process of forming the source contact 72S and the drain contact 72D, a gate contact 72G (see Figure 1 ) (for example, as part of the first mask pattern MP1 or the second mask pattern MP2) can also be formed.

[0094] According to the above method of manufacturing an integrated circuit device, an integrated circuit device 10 according to an embodiment can be manufactured.

[0095] Figure 18 is a block diagram of a three-dimensional integrated circuit device 100 according to an embodiment.

[0096] Referring to Figure 18 , the integrated circuit device 100 can include a memory cell array MCA and a peripheral circuit 50 and can be part of a semiconductor device such as a semiconductor memory chip or a semiconductor memory package.

[0097] The memory cell array MCA may include a plurality of memory cell blocks BLK1, BLK2, ……, and BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, ……, and BLKn may include a plurality of memory cells. The plurality of memory cell blocks BLK1, BLK2, ……, and BLKn may be connected to the peripheral circuit 50 via bit lines BL, word lines WL, string selection lines SSL, and ground selection lines GSL.

[0098] The memory cell array MCA may be connected to the page buffer 54 via the bit lines BL, and may be connected to the row decoder 52 via the word lines WL, string selection lines SSL, and ground selection lines GSL. In the memory cell array MCA, the plurality of memory cells included in the plurality of memory cell blocks BLK1, BLK2, ……, and BLKn may be flash memory cells. The memory cell array MCA may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and each NAND string may include a plurality of memory cells connected to a plurality of vertically stacked word lines WL.

[0099] The peripheral circuit 50 may include a row decoder 52, a page buffer 54, a data input and output circuit 56, and a control logic 58. Although not shown, the peripheral circuit 50 may further include a voltage generation circuit configured to generate various voltages required for the operation of the integrated circuit device 100, an error correction circuit configured to correct errors in the data read from the memory cell array MCA, and various circuits such as input and output interfaces.

[0100] The peripheral circuit 50 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the integrated circuit device 100, and may send data DATA to a device outside the integrated circuit device 100 and receive data DATA from a device outside the integrated circuit device 100. The configuration of the peripheral circuit 50 is described in detail below.

[0101] The row decoder 52 may select at least one of the plurality of memory cell blocks BLK1, BLK2, ……, and BLKn in response to an address ADDR from the outside, and may select the word lines WL, string selection lines SSL, and ground selection lines GSL of the selected memory cell block. The row decoder 52 may send a voltage for performing a memory operation to the word lines WL of the selected memory cell block.

[0102] The page buffer 54 may be connected to the memory cell array MCA through the bit lines BL. The page buffer 54 may operate as a write driver during a programming operation and apply a voltage to the bit lines BL according to the data DATA to be stored in the memory cell array MCA, and may operate as a sense amplifier during a read operation and read the data DATA stored in the memory cell array MCA. The page buffer 54 may operate according to a control signal PCTL provided from the control logic 58. One or more transistors included in the row decoder 52, the control logic 58, the page buffer 54, the data input and output circuit 56, or the memory cell array MCA may include planar transistors having a structure of any one of Figures 1 to 6 in it.

[0103] The data input and output circuit 56 may be connected to the page buffer 54 through data lines DLs. During a programming operation, the data input and output circuit 56 may receive the data DATA from a memory controller (not shown) and provide the programming data DATA to the page buffer 54 based on a column address C_ADDR provided from the control logic 58. During a read operation, the data input and output circuit 56 may provide the read data DATA stored in the page buffer 54 to the memory controller based on the column address C_ADDR provided from the control logic 58. The data input and output circuit 56 may send an input address or an instruction to the control logic 58 or the row decoder 52.

[0104] The control logic 58 may receive a command CMD and a control signal CTRL from the memory controller. The control logic 58 may provide a row address R_ADDR to the row decoder 52 and a column address C_ADDR to the data input and output circuit 56. The control logic 58 may generate various internal control signals used in the integrated circuit device 100 in response to the control signal CTRL. For example, the control logic 58 may adjust voltage levels provided to the word lines WL and the bit lines BL during a memory operation such as a programming operation or an erase operation.

[0105] Figure 19 is an equivalent circuit diagram of a memory cell array of a three-dimensional integrated circuit device according to an embodiment.

[0106] Figure 19 shows an equivalent circuit diagram of a vertical NAND flash device having a vertical channel structure.

[0107] In the integrated circuit device 100 according to an embodiment of the inventive concept, a memory cell array MCA may include a plurality of memory cell strings MCS. The memory cell array MCA may include a plurality of bit lines BL (BL1, BL2, ……, BLm), a plurality of word lines WL (WL1, WL2, ……, WLn-1 and WLn), at least one string select line SSL, at least one ground select line GSL, and a common source line CSL.

[0108] The plurality of memory cell strings MCS may be formed between the plurality of bit lines BL and the common source line CSL. Figure 19 An example is shown in which each of the plurality of memory cell strings MCS includes two string select lines SSL. However, the inventive concept is not limited thereto. For example, each of the plurality of memory cell strings MCS may include one string select line SSL.

[0109] Each of the plurality of memory cell strings MCS may include a string select transistor SST, a ground select transistor GST, and a plurality of memory cell transistors MC1, MC2, ……, MCn-1 and MCn. The drain region of the string select transistor SST may be connected to the bit line BL, and the source region of the ground select transistor GST may be connected to the common source line CSL. The common source line CSL may be a region to which the source regions of the plurality of ground select transistors GST are commonly connected.

[0110] The string select transistor SST may be connected to the string select line SSL, and the ground select transistor GST may be connected to the ground select line GSL. The plurality of memory cell transistors MC1, MC2, ……, MCn-1 and MCn may be respectively connected to the plurality of word lines WL. The vertical NAND flash memory device may be connected to a peripheral circuit including one or more planar transistors having a structure of any one of Figures 1 to 6 .

[0111] Figure 20 is a schematic plan view of a structural element of a three-dimensional integrated circuit device according to an embodiment. Figure 21 is a cross-sectional view of the three-dimensional integrated circuit device taken along line B-B'. Figure 20 . Figure 22 is Figure 21 an enlarged view of region CC of Figure 23 is Figure 21 an enlarged view of region DD of Figure 24 is Figure 21 an enlarged view of region EE of. In one embodiment, Figure 20 depicts a schematic plan view of the structural elements of the integrated circuit device 100 constituting Figure 19 when implementing the vertical NAND flash memory device of Figure 18 .

[0112] Refer to together Figures 20 to 24 Integrated circuit device 100 may include a peripheral circuit structure PS and a cell array structure CS disposed at a vertical level higher than the peripheral circuit structure PS.

[0113] According to an embodiment, integrated circuit device 100 may have a peripheral-on-cell (COP) structure in which cell array structure CS is disposed on the periphery of peripheral circuit structure PS. A substrate structure 110 may be disposed between peripheral circuit structure PS and cell array structure CS.

[0114] Peripheral circuit structure PS may include peripheral circuit transistors 60TR and peripheral circuit lines 70 disposed on substrate 101. Active regions AC may be defined on substrate 101 by device isolation layers 102, and a plurality of peripheral circuit transistors 60TR may be formed in the active regions AC. The plurality of peripheral circuit transistors 60TR may include gate structures 60G and source / drain regions 62 disposed on both sides of the gate structures 60G on a part of substrate 101.

[0115] In integrated circuit device 100 according to an embodiment, some of the plurality of peripheral circuit transistors 60TR disposed in peripheral circuit structure PS (e.g., as Figure 24 shown) may include at least one of the above-described integrated circuit devices 10, 20, 30, and 40.

[0116] Peripheral circuit lines 70 may include a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit metal layers 74. An interlayer insulating layer 80 covering the peripheral circuit transistors 60TR and the peripheral circuit lines 70 may be disposed on substrate 101. The plurality of peripheral circuit metal layers 74 may have a multilayer structure including a plurality of metal layers disposed at different vertical levels. In Figure 21 it is shown that all of the plurality of peripheral circuit metal layers 74 are formed to have the same height (e.g., the same vertical thickness) with respect to each other. However, in contrast thereto, the peripheral circuit metal layers 74 disposed at some levels (e.g., the uppermost level) may be formed to have a thickness greater than that of the peripheral circuit metal layers 74 disposed at other levels.

[0117] Gate stack GS may extend on substrate structure 110 in a first direction (X direction) and a second direction (Y direction) parallel to the plane of substrate 101. Gate stack GS may include a plurality of gate electrodes 130 and a plurality of insulating layers 140, and the plurality of gate electrodes 130 and the plurality of insulating layers 140 may be alternately disposed on the upper surface of substrate structure 110 in a vertical direction (Z direction). In addition, an upper insulating layer 150 may be disposed on the uppermost part of gate stack GS.

[0118] Each gate electrode 130 may include a buried conductive layer 132 and an insulating liner 134 surrounding the upper, bottom, and side surfaces of the buried conductive layer 132. For example, the buried conductive layer 132 may include a metal such as tungsten, a metal silicide such as tungsten silicide, doped polysilicon, or a combination thereof. According to some embodiments, the insulating liner 134 may include a high-k dielectric material such as alumina.

[0119] The plurality of gate electrodes 130 may correspond to the ground selection lines GSL, word lines WL, and at least one string selection line SSL included in the memory cell string MCS described above with reference to Figure 19 For example, the lowermost gate electrode 130 may be used as the ground selection line GSL, the uppermost gate electrode 130 may be used as the string selection line SSL, and the other gate electrodes 130 may be used as the word lines WL. Thus, a memory cell string MCS may be provided in which a ground selection transistor GST, a string selection transistor SST, and memory cell transistors MC1, MC2, ……, MCn-1 and MCn between the ground selection transistor GST and the string selection transistor SST are connected in series with each other.

[0120] The plurality of word line cuts 170 may extend in a first direction (X direction) on the substrate structure 110. A gate stack GS disposed between a pair of word line cuts 170 may form a block, and the pair of word line cuts 170 may define the width of the gate stack GS in a second direction (Y direction). The word line cuts 170 may include insulating spacers 172 and insulating isolation layers 174. Thus, the word line cuts 170 may include an insulating structure.

[0121] In the memory cell region MCR, a plurality of channel structures 160 may extend in a vertical direction (Z direction) from the upper surface of the substrate structure 110 through the gate stack GS. The plurality of channel structures 160 may be arranged to be spaced apart from each other by a specific distance in the first direction (X direction) and the second direction (Y direction). The plurality of channel structures 160 may be arranged in a zigzag or staggered pattern.

[0122] A plurality of channel structures 160 may extend in channel holes 160H passing through the gate stack GS. Each of the plurality of channel structures 160 may include a gate insulating layer 162, a channel layer 164, a buried insulating layer 166, and a conductive plug 168. The gate insulating layer 162 and the channel layer 164 may be sequentially disposed on the sidewalls of the channel hole 160H. For example, the gate insulating layer 162 may be conformally disposed on the sidewalls of the channel hole 160H, and the channel layer 164 may be conformally disposed on the sidewalls and the bottom of the channel hole 160H. The buried insulating layer 166 may fill the remaining space of the channel hole 160H above the channel layer 164. The conductive plug 168 (the conductive plug 168 that blocks the entrance (e.g., the uppermost end) of the channel hole 160H) in contact with the channel layer 164 may be disposed in the upper portion of the channel hole 160H. According to other embodiments, the buried insulating layer 166 may be omitted, and the channel layer 164 may fill the remaining portion of the channel hole 160H in a columnar shape.

[0123] The gate insulating layer 162 may have a structure in which a tunneling dielectric layer 162A, a charge storage layer 162B, and a blocking dielectric layer 162C are sequentially provided on the outer sidewalls of the channel layer 164. The relative thicknesses of the tunneling dielectric layer 162A, the charge storage layer 162B, and the blocking dielectric layer 162C included in the gate insulating layer 162 are not limited to this illustration and may be variably changed.

[0124] The tunneling dielectric layer 162A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer 162B may be a place where electrons passing through the tunneling dielectric layer 162A from the channel layer 164 can be stored, and may include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric layer 162C may include silicon oxide, silicon nitride, or a metal oxide having a dielectric constant greater than that of silicon oxide.

[0125] In a plan view, the uppermost gate electrode 130 in a block may be isolated into two parts by a string isolation insulating layer (not shown). These two parts of the gate electrode 130 may form the string selection line SSL described above with reference to Figure 2 description.

[0126] In the connection region CON, the gate electrode 130 may extend to form a pad portion PAD at the end of the gate electrode 130, and a covering insulating layer 120 covering the pad portion PAD may be disposed. In the connection region CON, a plurality of gate electrodes 130 may extend away from the upper surface of the substrate structure 110 in the vertical direction (Z direction) to have a reduced length in the first direction (X direction). The plurality of gate electrodes 130 may have a stepped structure in the connection region CON.

[0127] In the connection region CON, the contact plug CNT can pass through the overlying insulating layer 120 and be connected to the pad portion PAD of the gate electrode 130. The contact plug CNT can have a tapered cylindrical shape with a width that decreases from its upper portion to its lower portion in the vertical direction (Z direction).

[0128] The bit line contact BLC can pass through the upper insulating layer 150 and can contact the conductive plug 168 of the channel structure 160, and the bit line BL in contact with the bit line contact BLC can extend on the upper insulating layer 150 in the second direction (Y direction). Additionally, the wire ML can be formed on the upper insulating layer 150 in the connection region CON. Although not shown, an upper support layer can also be formed between the upper insulating layer 150 and the bit line BL and between the upper insulating layer 150 and the wire ML.

[0129] Figure 25 and Figure 26 is a cross-sectional view of a three-dimensional integrated circuit device according to another embodiment.

[0130] Referring Figure 25 , the integrated circuit device 200 can include a first gate stack GS1 at its lower portion and a second gate stack GS2 at its upper portion.

[0131] In the integrated circuit device 200 according to an embodiment, the first gate stack GS1 can include a plurality of first gate electrodes 130 and a plurality of first insulating layers 140, and the plurality of first gate electrodes 130 and the plurality of first insulating layers 140 can be alternately arranged on the upper surface of the substrate structure 110 in the vertical direction (Z direction). Additionally, the first upper insulating layer 150 can be arranged on the uppermost portion of the first gate stack GS1.

[0132] The second gate stack GS2 can include a plurality of second gate electrodes 230 and a plurality of second insulating layers 240, and the plurality of second gate electrodes 230 and the plurality of second insulating layers 240 can be alternately arranged above the first gate stack GS1 in the vertical direction (Z direction). Additionally, the second upper insulating layer 250 can be arranged on the uppermost portion of the second gate stack GS2.

[0133] A plurality of channel structures 160 can extend in a first channel hole 160H1 passing through the first gate stack GS1 and a second channel hole 160H2 passing through the second gate stack GS2. The plurality of channel structures 160 can have a shape that protrudes outward from a boundary portion between the first channel hole 160H1 and the second channel hole 160H2.

[0134] The base structure 110 may include an upper base layer 110U, a lower base layer 110L, and a lamina 110P. A plurality of channel structures 160 may pass through the upper base layer 110U and the lower base layer 110L of the base structure 110 and may contact the lamina 110P of the base structure 110. Accordingly, the channel layer 164 may be electrically connected to the lower base layer 110L instead of contacting the lamina 110P.

[0135] In an integrated circuit device 200 according to an embodiment, the peripheral circuit structure PS may include peripheral circuit transistors 60TR and peripheral circuit lines 70 disposed on a substrate 101. An active region AC may be defined on the substrate 101 by a device isolation layer 102, and a plurality of peripheral circuit transistors 60TR may be formed in the active region AC. The plurality of peripheral circuit transistors 60TR may include a gate structure 60G as a peripheral circuit gate and source / drain regions 62 (e.g., 62S and 62D) disposed on opposite sides of the gate structure 60G on a portion of the substrate 101.

[0136] In an integrated circuit device 200 according to an embodiment, some of the plurality of peripheral circuit transistors 60TR disposed in the peripheral circuit structure PS may include at least one of the above-described integrated circuit devices 10, 20, 30, and 40.

[0137] Referring Figure 26 to, an integrated circuit device 300 may include a chip-to-chip bonding structure.

[0138] An integrated circuit device 300 according to an embodiment may include a chip-to-chip bonding structure in which, after manufacturing an upper chip including a cell array structure CS and manufacturing a lower chip including a peripheral circuit structure PS, the upper chip and the lower chip are connected to each other by a bonding method.

[0139] According to some embodiments, the bonding method may denote a method of bonding a bonding pad formed on the uppermost part of the upper chip to a bonding pad formed on the uppermost part of the lower chip. The bonding method may include a metal-metal bonding structure, a through-silicon via (TSV), a back via stack (BVS), a eutectic bonding structure, a ball grid array (BGA) bonding structure, a plurality of lines, or a combination thereof.

[0140] The peripheral circuit structure PS may include a circuit substrate 301, an interlayer insulating layer 310, a plurality of circuit devices 360, a first metal layer 330 connected to each of the plurality of circuit devices 360, and a second metal layer 340 formed on the first metal layer. The interlayer insulating layer 310 may be disposed on the circuit substrate 301 to cover the plurality of circuit devices 360, the first metal layer 330, and the second metal layer 340 and may include an insulating material.

[0141] In the integrated circuit device 300 according to an embodiment, some of the plurality of circuit devices 360 arranged in the peripheral circuit structure PS may include at least one of the integrated circuit devices 10, 20, 30, and 40 described above.

[0142] The lower bonding pad 370 may be formed on the second metal layer 340 of the word line bonding region BA1. In the word line bonding region BA1, the lower bonding pad 370 of the peripheral circuit structure PS may be electrically connected to the upper bonding pad 470 of the cell array structure CS by a bonding method.

[0143] The cell array structure CS may include at least one memory block. The cell array structure CS may include a cell substrate 401 and a common source line CSL. A plurality of word lines 430 and a plurality of insulating layers 440 may be stacked on the cell substrate 401 in a vertical direction (Z direction).

[0144] In the bit line bonding region BA2, the channel structure 460 may pass through the word line 430, the insulating layer 440, the string selection line, and the ground selection line in a vertical direction (Z direction).

[0145] In the word line bonding region BA1, the word line 430 may extend parallel to the upper surface of the cell substrate 401 and may be connected to a plurality of contact plugs CNT. The word line 430 and the contact plug CNT may be connected to each other in a pad portion PAD provided by some of the word lines 430 that extend to have different lengths from each other.

[0146] The common source line contact 480 may be arranged in the external pad bonding region PA. The common source line contact 480 may include a conductive material such as metal, metal compound, polysilicon, etc., and may be electrically connected to the common source line CSL.

[0147] The input and output pads 350 and 450 may be arranged in the external pad bonding region PA. The lower layer 320 covering the lower surface of the circuit substrate 301 may be formed below the circuit substrate 301, and the first input and output pad 350 may be formed on the lower layer 320. The upper layer 420 covering the upper surface of the cell substrate 401 may be formed above the cell substrate 401, and the second input and output pad 450 may be arranged on the upper layer 420.

[0148] Figure 27 It is a diagram of an electronic system 1000 including an integrated circuit device 1100 according to an embodiment.

[0149] Refer to Figure 27 , the electronic system 1000 according to an embodiment of the inventive concept may include an integrated circuit device 1100 and a controller 1200 electrically connected to the integrated circuit device 1100.

[0150] The electronic system 1000 may include a storage device including one or more integrated circuit devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may include a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including at least one integrated circuit device 1100.

[0151] The integrated circuit device 1100 may include a non-volatile vertical memory device. For example, the integrated circuit device 1100 may include a NAND flash memory device including at least one of the integrated circuit devices 100, 200, and 300 described above with reference to Figures 18 to 26 The integrated circuit device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. According to some embodiments, the first structure 1100F may be arranged beside the second structure 1100S.

[0152] The first structure 1100F may include a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may include a memory cell structure including bit lines BL, a common source line CSL, multiple word lines WL between the bit lines BL and the common source line CSL, an upper gate line UL1 and an upper gate line UL2 on the first gate, a lower gate line LL1 and a lower gate line LL2, and multiple memory cell strings CSTR.

[0153] Each of the multiple memory cell strings CSTR in the second structure 1100S may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit lines BL, and multiple memory cell transistors MCT arranged between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variably changed according to exemplary embodiments.

[0154] According to some embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The multiple lower gate lines LL1 and LL2 may be the gate layers of the lower transistors LT1 and LT2 respectively. The word line WL may be the gate layer of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be the gate layers of the upper transistors UT1 and UT2 respectively.

[0155] The common source line CSL, the multiple lower gate lines LL1 and LL2, the multiple word lines WL, and the multiple upper gate lines UL1 and UL2 can be electrically connected to the decoder circuit 1110 through the multiple first connection lines 1115 that extend from the first structure 1100F to the second structure 1100S. The multiple bit lines BL can be electrically connected to the page buffer 1120 through the multiple second connection lines 1125 that extend from the first structure 1100F to the second structure 1100S.

[0156] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the multiple memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130.

[0157] The integrated circuit device 1100 can communicate with the controller 1200 through the input and output pads 1101 electrically connected to the logic circuit 1130. The input and output pads 1101 can be electrically connected to the logic circuit 1130 through the input and output connection lines 1135 that extend from the first structure 1100F to the second structure 1100S.

[0158] The controller 1200 can include a processor 1210, a NAND controller 1220, and a host interface 1230. According to some embodiments, the electronic system 1000 can include multiple integrated circuit devices 1100, in which case the controller 1200 can control the multiple integrated circuit devices 1100.

[0159] The processor 1210 can control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 can operate according to specific firmware, and can control the NAND controller 1220 and can access the integrated circuit device 1100. The NAND controller 1220 can include a NAND interface 1221 configured to handle communication with the integrated circuit device 1100. Through the NAND interface 1221, control commands for controlling the integrated circuit device 1100, data to be written to the multiple memory cell transistors MCT of the integrated circuit device 1100, data to be read from the multiple memory cell transistors MCT of the integrated circuit device 1100, etc. can be sent. The host interface 1230 can provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 can control the integrated circuit device 1100 in response to the control command.

[0160] Figure 28 is a perspective view of an electronic system 2000 including an integrated circuit device according to an embodiment.

[0161] Refer to Figure 28, the electronic system 2000 according to an embodiment may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004.

[0162] The main substrate 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins of the connector 2006 may vary according to the communication interface between the electronic system 2000 and the external host. According to some embodiments, the electronic system 2000 may communicate with the external host according to any one of interfaces such as USB, Peripheral Component Interconnect Express (PCI-express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. According to some embodiments, the electronic system 2000 may operate based on the power supplied from the external host through the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) configured to distribute the power supplied from the external host to the controller 2002 and the semiconductor package 2003. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a plurality of wire patterns 2005 formed on the main substrate 2001.

[0163] The controller 2002 may write data to or read data from the semiconductor package 2003, and may improve the operation speed of the electronic system 2000.

[0164] The DRAM 2004 may include a buffer memory configured to reduce the speed difference between the external host and the semiconductor package 2003 serving as a data storage space. The DRAM 2004 included in the electronic system 2000 may also operate as a cache memory, and may provide a space for temporarily storing data in the control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, in addition to the NAND controller configured to control the semiconductor package 2003, the controller 2002 may further include a DRAM controller configured to control the DRAM 2004.

[0165] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, a bonding layer 2300 disposed on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the plurality of semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0166] The package substrate 2100 may include a printed circuit board including a plurality of upper pads 2130. Each of the plurality of semiconductor chips 2200 may include input and output pads 2201. The input and output pads 2201 may correspond to Figure 27 the input and output pads 1101. Each of the plurality of semiconductor chips 2200 may include a plurality of gate stacks 3210 and a plurality of channel structures 3220. The plurality of semiconductor chips 2200 may include at least one of the integrated circuit devices 100, 200, and 300 described above with reference to Figures 18 to 26 FIG.

[0167] According to some embodiments, the connection structure 2400 may include bonding leads that electrically connect the input and output pads 2201 to the upper pads 2130. Thus, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other by a wire bonding method and may be electrically connected to the upper pads 2130 of the package substrate 2100. According to some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other by a connection structure including TSVs instead of the connection structure 2400 using the wire bonding method.

[0168] According to some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. According to some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be mounted on an insertion substrate different from the main substrate 2001, and the controller 2002 and the plurality of semiconductor chips 2200 may be connected to each other by lines formed on the insertion substrate.

[0169] Figure 29 and Figure 30 are cross-sectional views of a semiconductor package 3003 including an integrated circuit device according to an embodiment.

[0170] Specifically, Figure 29 and Figure 30 is a cross-sectional view showing in detail the structure of the electronic system taken along line F-F'. Figure 28

[0171] Referring to Figure 29 , in the semiconductor package 3003, the package substrate 2100 may include a printed circuit board.

[0172] The package substrate 2100 may include a main body portion 2120, a plurality of upper pads 2130 disposed on the upper surface of the main body portion 2120 (see Figure 28 ), a plurality of lower pads 2125 disposed on the lower surface of the main body portion 2120 or exposed through the lower surface of the main body portion 2120, and a plurality of internal lines 2135 in the main body portion 2120 that electrically connect the plurality of upper pads 2130 to the plurality of lower pads 2125. The plurality of upper pads 2130 may be electrically connected to a plurality of connection structures 2400 (see Figure 28 ). The plurality of lower pads 2125 may be connected to a plurality of line patterns 2005 on the main substrate 2001 of the electronic system 2000 shown in Figure 28 through a plurality of conductive connection portions 2800.

[0173] Each of the plurality of semiconductor chips 2200 may include a substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the substrate 3010. The first structure 3100 may include a peripheral circuit region including a plurality of peripheral lines 3110. The second structure 3200 may include a common source line 3205, a gate stack 3210 on the common source line 3205, a channel structure 3220 passing through the gate stack 3210, and bit lines 3240 electrically connected to the channel structure 3220.

[0174] Each of the plurality of semiconductor chips 2200 may include a through line 3245 electrically connected to the plurality of peripheral lines 3110 of the first structure 3100 and extending into the second structure 3200. The through line 3245 may be disposed outside the gate stack 3210. According to some embodiments, the semiconductor package 3003 may further include a through line passing through the gate stack 3210. Each of the plurality of semiconductor chips 2200 may further include input and output pads 2201 electrically connected to the plurality of peripheral lines 3110 of the first structure 3100 (see Figure 28 ).

[0175] Referring to Figure 30 , the semiconductor package 4003 may have a structure substantially the same as that of the semiconductor package 3003 described with reference to Figure 29 . However, the semiconductor package 4003 may include a plurality of semiconductor chips 2200a.

[0176] Each of the plurality of semiconductor chips 2200a may include a substrate 4010, a first structure 4100 on the substrate 4010, and a second structure 4200 on the first structure 4100 and bonded to the first structure 4100 by a wafer bonding method. The first structure 4100 may include a peripheral circuit region including peripheral lines 4110 and a plurality of first bonding structures 4150. The second structure 4200 may include a common source line 4205, a gate stack 4210 between the common source line 4205 and the first structure 4100, and a channel structure 4220 passing through the gate stack 4210.

[0177] In addition, each of the plurality of semiconductor chips 2200a may include a plurality of second bonding structures 4250 respectively electrically connected to a plurality of gate layers of the gate stack 4210. For example, some of the plurality of second bonding structures 4250 may be connected to bit lines 4240 electrically connected to the channel structure 4220. Other second bonding structures 4250 of the plurality of second bonding structures 4250 may be electrically connected to the gate layers through a plurality of contact plugs CNT.

[0178] The plurality of first bonding structures 4150 of the first structure 4100 and the plurality of second bonding structures 4250 of the second structure 4200 may contact and bond to each other. The bonding portion of the plurality of first bonding structures 4150 and the plurality of second bonding structures 4250 may include a metal (e.g., Cu), but is not limited thereto.

[0179] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: substrate; a channel region disposed in the substrate; a gate structure disposed on the channel region and comprising a gate dielectric layer, a gate electrode and a gate capping layer stacked sequentially, and first and second gate spacers on first and second corresponding opposite sidewalls of the gate dielectric layer, the gate electrode and the gate capping layer; a source region and a drain region, the source region and the drain region being arranged on opposite sides of the channel region; a source contact contacting the source region; a resistive structure contacting the drain region and comprising doped polysilicon; as well as A drain contact contacts the resistive structure and includes a metal.

2. The integrated circuit device according to claim 1, wherein: The resistive structure is a resistor via having a resistance higher than that of the drain contact; and A silicide layer is not disposed at an interface between the resistance structure and the drain contact.

3. The integrated circuit device according to claim 2, wherein: The source contact includes the same metal included in the drain contact and excludes the doped polysilicon included in the resistance structure.

4. The integrated circuit device according to claim 3, wherein: When viewed in a horizontal cross-sectional view, the resistor structure has a U-shape having a groove at its center. The drain contact fills the trench of the resistor structure, A vertical level of an uppermost surface of the resistance structure and a vertical level of an uppermost surface of the drain contact are the same as each other, and A first maximum width of the resistance structure in the horizontal direction is greater than a second maximum width of the drain contact in the horizontal direction.

5. The integrated circuit device according to claim 4, wherein: The resistive structure includes a bottom and opposing side walls disposed on the bottom, and A thickness of the bottom of the resistance structure in the vertical direction is greater than a width of any one of the opposite side walls of the resistance structure in the horizontal direction.

6. The integrated circuit device according to claim 4, wherein: The source contact contacts the source region at an uppermost surface of the source region, The resistive structure extends vertically downward beyond the uppermost surface of the drain region, and A vertical level of a lowermost surface of the source contact is higher than a vertical level of a lowermost surface of the resistance structure.

7. The integrated circuit device according to claim 3, wherein: The resistor structure has a rectangular shape when viewed in a horizontal cross-sectional view, and The drain contact completely covers the uppermost surface of the resistor structure.

8. The integrated circuit device according to claim 3, wherein: When viewed in a horizontal cross-sectional view, the resistor structure has a U-shape having a groove at its center. The drain contact fills the trench of the resistor structure and is arranged above the resistor structure, and A vertical level of an uppermost surface of the resistance structure is lower than a vertical level of an uppermost surface of the drain contact.

9. The integrated circuit device according to claim 1, wherein: The source contact comprises a source through electrode; The drain contact combined with the resistance structure includes a drain through electrode, and A first resistance of the source through-electrode is smaller than a second resistance of the drain through-electrode.

10. The integrated circuit device according to claim 9, wherein: The resistance of the resistance structure is determined by at least one of a doping concentration of the doped polysilicon, a grain size of the doped polysilicon, and a thickness of the doped polysilicon.

11. The integrated circuit device according to claim 9, further comprising: Peripheral circuit structure; as well as a cell array structure above the peripheral circuit structure, The peripheral circuit structure includes a circuit substrate, a peripheral circuit transistor on the circuit substrate, a lower line connected to the peripheral circuit transistor, and a first insulating layer covering the peripheral circuit transistor and the lower line, and The cell array structure includes a gate stack, a plurality of channel structures extending through the gate stack, and a second insulating layer covering the gate stack, wherein the gate stack includes a plurality of gate electrodes and a plurality of insulating layers, and the plurality of gate electrodes and the plurality of insulating layers are alternately stacked. The peripheral circuit transistor includes the channel region, the gate structure, the source region, the drain region, the source contact, the drain contact and the resistance structure.

12. An integrated circuit device comprising: Peripheral circuit structure; as well as a cell array structure above the peripheral circuit structure, The peripheral circuit structure includes a circuit substrate, a peripheral circuit transistor on the circuit substrate, a lower line connected to the peripheral circuit transistor, and a first insulating layer covering the peripheral circuit transistor and the lower line, and The cell array structure includes a gate stack, a plurality of channel structures extending through the gate stack, and a second insulating layer covering the gate stack, wherein the gate stack includes a plurality of gate electrodes and a plurality of insulating layers, and the plurality of gate electrodes and the plurality of insulating layers are alternately stacked. Wherein, the peripheral circuit transistor comprises: a channel region disposed in the circuit substrate; a gate structure disposed on the channel region and comprising a gate dielectric layer, a gate electrode and a gate capping layer stacked sequentially, and first and second gate spacers on first and second corresponding opposite sidewalls of the gate dielectric layer, the gate electrode and the gate capping layer; a source region and a drain region, the source region and the drain region being arranged on opposite sides of the channel region; a source contact contacting the source region; and A resistor structure and a drain contact, the resistor structure contacts the drain region, and the drain contact contacts the resistor structure.

13. The integrated circuit device according to claim 12, wherein: The resistor structure includes doped polysilicon, and The source contact and the drain contact include the same metal as each other.

14. The integrated circuit device according to claim 13, wherein: The source contact comprises a source through electrode; The drain contact combined with the resistance structure includes a drain through electrode, and The first resistance of the source through-electrode is smaller than the second resistance of the drain through-electrode, and A silicide layer is not disposed at an interface between the resistance structure and the drain contact.

15. The integrated circuit device according to claim 12, wherein: The resistor structure has a cup shape, The drain contact fills the hole in the resistive structure, The vertical level of the lowermost surface of the source contact is lower than the vertical level of the lowermost surface of the drain contact, and An uppermost surface of the source contact is at the same vertical level as an uppermost surface of the drain contact.

16. The integrated circuit device according to claim 15, wherein: The source contact contacts the source region at an upper surface of the source region, The resistive structure extends vertically downward beyond the uppermost surface of the drain region, and A vertical level of a lowermost surface of the source contact is higher than a vertical level of a lowermost surface of the resistance structure.

17. The integrated circuit device according to claim 11, wherein: When viewed in a horizontal cross-sectional view, the resistor structure has a rectangular shape. The vertical level of the lowermost surface of the source contact is lower than the vertical level of the lowermost surface of the drain contact, and A vertical level of an uppermost surface of the source contact is the same as a vertical level of an uppermost surface of the drain contact.

18. The integrated circuit device according to claim 11, wherein: The peripheral circuit structure also includes a first bonding pad electrically connected to the peripheral circuit transistor, and The cell array structure further includes a second bonding pad electrically connected to the plurality of gate electrodes and the plurality of channel structures, Wherein, the first bonding pad and the second bonding pad are bonded to each other.

19. An electronic system comprising: main base plate; an integrated circuit device on the main substrate; as well as a controller electrically connected to the integrated circuit device on the main substrate, The integrated circuit device comprises a peripheral circuit structure and a cell array structure arranged on the peripheral circuit structure. The peripheral circuit structure includes a circuit substrate, a peripheral circuit transistor on the circuit substrate, a lower line connected to the peripheral circuit transistor, and a first insulating layer covering the peripheral circuit transistor and the lower line, and The cell array structure includes a gate stack, a plurality of channel structures extending through the gate stack, and a second insulating layer covering the gate stack, wherein the gate stack includes a plurality of gate electrodes and a plurality of insulating layers, and the plurality of gate electrodes and the plurality of insulating layers are alternately stacked. Wherein, the peripheral circuit transistor comprises: a channel region disposed in the circuit substrate; a gate structure disposed on the channel region and comprising a gate dielectric layer, a gate electrode and a gate capping layer stacked sequentially, and a gate spacer on opposite sidewalls of the gate dielectric layer, the gate electrode and the gate capping layer; a source region and a drain region, the source region and the drain region being arranged on opposite sides of the channel region; a source contact contacting the source region; and A resistor via and a drain contact, the resistor via contacts the drain region, the drain contact contacts the resistor via.

20. The electronic system according to claim 19, wherein: The main substrate further includes a line pattern electrically connecting the integrated circuit device to the controller, The resistor via comprises doped polysilicon, and the source contact and the drain contact comprise the same metal as each other, The source contact comprises a source through electrode, The drain contact combined with the resistor via comprises a drain through electrode, The first resistance of the source through-electrode is smaller than the second resistance of the drain through-electrode, and A silicide layer is not disposed at an interface between the resistor via and the drain contact.

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