Ferroelectric field effect transistor and preparation method thereof

Abstract

The embodiment of the invention provides a preparation method of a ferroelectric field effect transistor. The preparation method comprises the following steps: depositing a plurality of layers of OMO structures on a source electrode metal layer; photoetching and punching on the multi-layer OMO structure to form a cylindrical hole; a ferroelectric HZO layer and a channel IGZO layer are deposited in the cylindrical hole; and opening a hole at the bottom of the cylindrical hole, and performing oxide deposition between the channel IGZO layers to form an oxide filling layer. According to the preparation method of the ferroelectric field effect transistor provided by the embodiment of the invention, through the macaroni structure, the contact area between the grid electrode and the storage unit is increased, the leakage current is effectively reduced, and the electrical performance of the ferroelectric field effect transistor can be improved. The embodiment of the invention further provides the ferroelectric field effect transistor.

Description

Technical Field

[0001] This application belongs to the technical field of transistors, and particularly relates to a ferroelectric field-effect transistor and a preparation method thereof. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, the demand for hardware devices has increased day by day, especially in the aspects of memory and processors. However, the traditional von Neumann architecture has speed bottlenecks and power consumption problems when processing a large amount of data. In addition, as Moore's law approaches the physical limit, there are huge challenges in improving circuit integration. Therefore, it has become particularly important to develop new memory structures to solve these problems.

[0003] Ferroelectric random access memory (FeRAM) is considered a potential solution to solve these problems due to its advantages such as non-volatility, high read / write speed, and low power consumption. However, there are still many problems in existing three-dimensional ferroelectric memory devices in terms of gate control ability, device switching current ratio, storage capacity, and process complexity. Summary of the Invention

[0004] Aiming at the problems existing in the above-mentioned related technologies, the present invention provides a preparation method of a ferroelectric field-effect transistor and a ferroelectric field-effect transistor. Through the macaroni structure, the contact area between the gate and the storage unit is increased, the leakage current is effectively reduced, and the electrical performance of the ferroelectric field-effect transistor can be improved.

[0005] In a first aspect, an embodiment of the present application provides a preparation method of a ferroelectric field-effect transistor, including the following steps:

[0006] Deposit a multi-layer OMO structure on the source metal layer;

[0007] Lithographically punch holes in the multi-layer OMO structure to form cylindrical holes;

[0008] Deposit a ferroelectric HZO layer and a channel IGZO layer in the cylindrical holes; and

[0009] Open a hole at the bottom of the cylindrical hole, and deposit an oxide between the channel IGZO layers to form an oxide filling layer.

[0010] Further, after depositing the ferroelectric HZO layer and the channel IGZO layer in the cylindrical holes, it further includes:

[0011] Perform rapid thermal annealing treatment to improve the performance of the ferroelectric HZO layer and the channel IGZO layer.

[0012] Further, after depositing the ferroelectric HZO layer and the channel IGZO layer in the cylindrical holes, it further includes:

[0013] Deposit a silicon protection layer on the channel IGZO layer;

[0014] Before opening a hole at the bottom of the cylindrical hole, it further includes:

[0015] Remove the silicon protection layer.

[0016] Further, after opening a hole at the bottom of the cylindrical hole and depositing an oxide between the channel IGZO layers to form an oxide filling layer, it further includes:

[0017] Perform a planarization process to remove the excess oxide on the surface.

[0018] Further, after performing the planarization process to remove the excess oxide on the surface, it further includes:

[0019] Deposit a metal layer by a thin film deposition method to form a drain metal layer.

[0020] Further, after depositing a metal layer by a thin film deposition method to form a drain metal layer, it further includes:

[0021] Perform a thermal annealing process to improve the activity of the drain metal layer.

[0022] Further, after performing the thermal annealing process to improve the activity of the drain metal layer, it further includes:

[0023] Perform a step and metal contact process for integration and packaging.

[0024] Further, before depositing a multi-layer OMO structure on the source metal layer, it further includes:

[0025] Deposit the source metal layer on the substrate by a thin film deposition method.

[0026] Further, before depositing the source metal layer on the substrate by a thin film deposition method, it further includes:

[0027] Clean the substrate.

[0028] In a second aspect, an embodiment of the present application provides a ferroelectric field effect transistor, which is made by the method described in any one of the above.

[0029] In the method for fabricating a ferroelectric field-effect transistor provided by an embodiment of the present application, first, a multi-layer oxide-metal-oxide structure is constructed on the source metal layer to lay a foundation for subsequent steps. Subsequently, photolithography technology is used to precisely punch holes in the OMO structure to form cylindrical holes, providing space for the deposition of ferroelectric material and channel material. Then, a ferroelectric HZO layer and a channel IGZO layer are sequentially deposited in the holes. The ferroelectric HZO layer, as a key part, can regulate the conductivity of the channel IGZO layer under the action of an electric field to achieve the function of the transistor. Finally, holes are opened at the bottom of the holes, and an oxide is deposited to form a filling layer to protect the internal structure and provide stability and insulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the structures shown in these drawings.

[0031] Figure 1 It is a schematic flow chart of the method for fabricating a ferroelectric field-effect transistor provided by an embodiment of the present application;

[0032] Figure 2 It is a schematic diagram of the actual operation steps of the method for fabricating a ferroelectric field-effect transistor provided by an embodiment of the present application;

[0033] Figure 3 It is a schematic diagram of the structure of a ferroelectric field-effect transistor provided by an embodiment of the present application.

[0034] The realization of the objectives, functional features, and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0036] It should be understood that when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0037] It should also be understood that the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. As used in the specification of this application and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific circumstances.

[0038] Refer to Figure 1 and Figure 2 , an embodiment of this application provides a method for manufacturing a ferroelectric field-effect transistor, including the following steps:

[0039] S101: Deposit a multi-layer OMO (Oxide-Metal-Oxide) structure on the source metal layer;

[0040] S102: Lithographically punch holes in the multi-layer OMO structure to form cylindrical holes;

[0041] S103: Deposit a ferroelectric HZO (Hafnium Zirconium Oxide) layer and a channel IGZO (Indium Gallium Zinc Oxide) layer in the cylindrical holes; and

[0042] S104: Open holes at the bottom of the cylindrical holes, and deposit oxides between the channel IGZO layers to form an oxide filling layer.

[0043] In the method for manufacturing a ferroelectric field-effect transistor provided by the embodiment of this application, first, a multi-layer oxide-metal-oxide structure is constructed on the source metal layer, laying the foundation for subsequent steps. Subsequently, lithography technology is used to precisely punch holes in the OMO structure to form cylindrical holes, providing space for the deposition of ferroelectric materials and channel materials. Then, a ferroelectric HZO layer and a channel IGZO layer are sequentially deposited in the holes. The ferroelectric HZO layer, as a key part, can regulate the conductivity of the channel IGZO layer under the action of an electric field to realize the function of the transistor. Finally, holes are opened at the bottom of the holes, and oxides are deposited to form a filling layer to protect the internal structure and provide stability and insulation.

[0044] The method for manufacturing a ferroelectric field-effect transistor provided by the embodiment of this application has the following advantages:

[0045] 1. Improve the gate control ability: Through the macaroni structure, the contact area between the gate and the storage unit is increased, effectively reducing the leakage current, especially showing excellent performance in high-density integration.

[0046] 2. Reducing Crosstalk: Increasing the designed oxide layer in the vertical direction can effectively isolate the interlayer electric field interference, reduce the cross-layer leakage current, and enhance the independence of storage cells. In the multi-layer OMO structure, the metal part serves as the gate, and the oxide part acts as a barrier (passivation layer). In the vertical direction, one unit contains three serially connected FeFETs, namely a top selector gate and a bottom selector gate at the upper and lower parts respectively, and a control gate in the middle.

[0047] 3. Improving Electrical Performance: Using IGZO as the channel material, its high electron mobility (about 10 cm 2 / V·s) can significantly improve the device switching speed and drive current. At the same time, it reduces carrier scattering, lowers the leakage current, and enhances the device stability and durability.

[0048] 4. Simplifying the Process and Increasing the Integration Density: Compatible with the CMOS process, it reduces the process complexity. Meanwhile, the macaroni structure is filled with an oxide layer in the middle, reducing the harsh control conditions. In addition, one layer structure contains two transistors connected through an extended area, achieving a higher storage density.

[0049] 5. Promoting Research and Development: It provides a new method for the research of special structures in circuit integration, which is conducive to obtaining three-dimensional ferroelectric memory devices with high-quality performance, and promotes the research and development of next-generation multifunctional devices and memory integrated circuits.

[0050] Further, in some embodiments of the present application, after depositing the ferroelectric HZO layer and the channel IGZO layer in the cylindrical hole, it further includes:

[0051] Performing a rapid thermal annealing treatment to improve the performance of the ferroelectric HZO layer and the channel IGZO layer.

[0052] Specifically, after depositing the ferroelectric HZO layer and the channel IGZO layer in the cylindrical hole, the key subsequent step further includes performing a rapid thermal annealing treatment. The purpose of this step is to significantly improve the performance of the ferroelectric HZO layer and the channel IGZO layer.

[0053] The rapid thermal annealing treatment is an efficient heat treatment technology that can heat the material to a high temperature and rapidly cool it in a short time. For the ferroelectric HZO layer, this treatment can optimize its crystal structure, enhance the ferroelectric performance, such as increasing the polarization intensity and reducing the leakage current. At the same time, it also helps to reduce the defects and stress inside the material, improving the stability and reliability of the material.

[0054] For the channel IGZO layer, rapid thermal annealing treatment also has significant effects. It can improve the crystallization quality of IGZO, increase the electron mobility, and thus further enhance the electrical performance of the device. In addition, the annealing treatment helps to reduce the interface defects between the IGZO layer and the ferroelectric HZO layer, enhance the gate's control ability over the ferroelectric material, and further improve the stability and reliability of the device.

[0055] It should be noted that the thermal annealing temperature here should be 350°C - 400°C, and the time should be 10 to 30 seconds. The specific temperature and time depend on the actual situation.

[0056] Furthermore, in some embodiments of the present application, after depositing the ferroelectric HZO layer and the channel IGZO layer in the cylindrical hole, it further includes:

[0057] Depositing a silicon protection layer on the channel IGZO layer;

[0058] Before opening a hole at the bottom of the cylindrical hole, it further includes:

[0059] Removing the silicon protection layer.

[0060] Specifically, first, deposit a layer of silicon protection layer on the channel IGZO layer. The purpose of this step is to protect the channel IGZO layer from possible physical and chemical damages in subsequent process steps. The silicon protection layer has good chemical stability and mechanical strength, and can effectively isolate the channel layer from the external environment, reducing the risk of impurity contamination and mechanical scratches.

[0061] However, before opening a hole at the bottom of the cylindrical hole to form an oxide filling layer, this layer of silicon protection layer needs to be removed. This is because the presence of the silicon protection layer will hinder the direct contact between the oxide filling layer and the channel IGZO layer, thus affecting the electrical performance and stability of the device. Therefore, before opening the hole, an appropriate process method (such as wet etching or dry etching) must be used to completely remove the silicon protection layer to ensure that the oxide filling layer can be evenly deposited on the channel IGZO layer to form good electrical contact.

[0062] As an alternative, Si3N4 (silicon nitride) can be used instead of amorphous silicon as the protection layer material, which can be chemically treated with diluted hydrofluoric acid, and the cost in the process is lower than that of the silicon protection layer.

[0063] Furthermore, in some embodiments of the present application, after opening a hole at the bottom of the cylindrical hole and depositing an oxide between the channel IGZO layers to form an oxide filling layer, it further includes:

[0064] Performing a planarization treatment to remove the excess oxide on the surface.

[0065] Specifically, in the preparation process of the ferroelectric field-effect transistor, after opening the bottom of the cylindrical hole and depositing the oxide between the channel IGZO layers to form an oxide filling layer, the next key step is planarization.

[0066] The main purpose of planarization is to remove the excess oxide formed on the device surface during the deposition process and ensure the flatness of the entire device surface. An uneven surface may cause problems such as lithography alignment issues, difficult metal interconnection, and inconsistent device performance in subsequent process steps.

[0067] Planarization is usually carried out by methods such as chemical mechanical polishing (CMP) or dry etching. The CMP method can effectively remove the excess oxide on the surface through the combination of grinding and chemical reactions while maintaining the integrity of the device structure. Dry etching uses physical means such as plasma or ion beam to precisely etch the surface to achieve the purpose of planarization.

[0068] Through planarization, it can be ensured that the surface of the ferroelectric field-effect transistor is flat and the structure is clear, providing a good foundation for subsequent process steps such as metal interconnection and packaging. At the same time, the planar surface also helps to improve the electrical performance and reliability of the device because a flat surface can reduce carrier scattering and trap effects, thereby increasing the electron mobility and reducing the leakage current.

[0069] Furthermore, in some embodiments of the present application, after performing planarization to remove the excess oxide on the surface, it further includes:

[0070] Depositing a metal layer by a thin film deposition method to form a drain metal layer.

[0071] Specifically, in the preparation method of the ferroelectric field-effect transistor provided in the embodiments of the present application, after completing planarization and removing the excess oxide on the surface, the next step is to deposit a metal layer by a thin film deposition method to form a drain metal layer.

[0072] Thin film deposition methods usually include various techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). The selection of these methods depends on factors such as the required metal layer material, deposition rate, uniformity, and cost.

[0073] For the drain metal layer, the material selection is crucial. Commonly used metal materials include copper (Cu), aluminum (Al), gold (Au), and nickel (Ni), etc. These materials have good electrical conductivity and chemical stability and can meet the requirements of the drain performance of the ferroelectric field-effect transistor.

[0074] During the deposition process, it is necessary to precisely control the thickness and uniformity of the metal layer to ensure the electrical performance and reliability of the device. An overly thick metal layer may lead to an oversized device, increasing the manufacturing cost; while an overly thin metal layer may not provide sufficient conductivity, affecting the device's performance.

[0075] By adopting a suitable thin-film deposition method and precisely controlling the deposition parameters, a uniform and dense drain metal layer can be successfully formed on the surface of the ferroelectric field-effect transistor.

[0076] Furthermore, in some embodiments of the present application, after depositing the metal layer using the thin-film deposition method to form the drain metal layer, it further includes:

[0077] Performing a thermal annealing treatment to improve the activity of the drain metal layer.

[0078] Specifically, in the preparation process of the ferroelectric field-effect transistor, when the metal layer is successfully deposited using the thin-film deposition method to form the drain metal layer, in order to further improve the activity of the drain metal layer and enhance its bonding force and electrical properties with surrounding materials, a thermal annealing treatment is usually performed.

[0079] The thermal annealing treatment is a process of heating the material to a certain temperature and maintaining it for a period of time, and then slowly cooling it to room temperature. This process can promote the rearrangement of atoms in the metal layer, reduce defects, and improve the crystallinity and density of the material. At the same time, thermal annealing also helps to improve the interface quality between the metal layer and the surrounding oxide layer or semiconductor layer, reduce traps and scattering effects at the interface, thereby improving the electrical performance of the device.

[0080] For the drain metal layer, the thermal annealing treatment can significantly improve its activity, that is, enhance its reaction ability and bonding force with other materials. This helps to achieve better connection and stability in subsequent process steps, such as metal interconnection and packaging.

[0081] In addition, the thermal annealing treatment can also promote the diffusion and precipitation of impurities in the metal layer, further purify the material, and improve the reliability and lifespan of the device. The annealing temperature here should be 900°C - 1100°C, and the specific temperature depends on the actual situation.

[0082] Furthermore, in some embodiments of the present application, after performing the thermal annealing treatment to improve the activity of the drain metal layer, it further includes:

[0083] Performing stepped and metal contact treatment for integration and packaging.

[0084] Specifically, in the method for manufacturing a ferroelectric field-effect transistor provided by the embodiments of the present application, after completing the thermal annealing treatment and improving the activity of the drain metal layer, the next step is to perform stepwise and metal contact treatments to facilitate subsequent integration and packaging.

[0085] The stepwise treatment mainly involves microfabricating the device surface through physical or chemical methods to form step structures of different heights. The purpose of this step is to optimize the layout of metal interconnections and ensure unobstructed signal transmission paths within the device. At the same time, the stepwise treatment can also provide the necessary space for subsequent packaging steps, ensuring that the packaging material can evenly cover the device surface to form a firm packaging structure.

[0086] The metal contact treatment is to form specific contact holes or contact areas on the drain metal layer through processes such as photolithography and etching to achieve good electrical connection with external circuits or packaging materials. The accuracy and reliability of this step are crucial for the overall performance of the device because any poor contact or short circuit may cause the device to fail.

[0087] After completing the stepwise and metal contact treatments, the ferroelectric field-effect transistor is ready for integration and packaging. The integration step typically involves assembling multiple devices together to form a complex circuit system; while the packaging step is to encapsulate the circuit system in a protective housing to prevent interference and damage from the external environment.

[0088] Furthermore, in some embodiments of the present application, before depositing the multi-layer OMO structure on the source metal layer, it further includes:

[0089] Depositing the source metal layer on the substrate by a thin film deposition method.

[0090] Specifically, in the method for manufacturing a ferroelectric field-effect transistor provided by the embodiments of the present application, especially when constructing the source structure, some embodiments of the present application propose a key step: depositing the source metal layer on the substrate by a thin film deposition method. This step occurs before depositing the multi-layer OMO (oxide / metal / oxide) structure and is the basis for constructing a complete source structure.

[0091] Thin film deposition methods, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), etc., are widely used in the manufacturing of semiconductor devices. These methods can precisely control the thickness, composition, and uniformity of the deposited material, thus meeting the specific requirements of the device for the source metal layer.

[0092] The selection of the source metal layer is crucial for the performance of the device. Commonly used metal materials include copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), etc. These materials have good electrical conductivity and compatibility with surrounding materials. Through thin-film deposition methods, one or more layers of metal can be uniformly deposited on the substrate to form the source metal layer.

[0093] After depositing the source metal layer, a series of post-treatment steps are usually carried out, such as annealing treatment, to improve the crystallization quality of the metal layer and the bonding force with surrounding materials. These steps help to improve the electrical conductivity and stability of the source metal layer, providing guarantee for the subsequent device performance.

[0094] Furthermore, in some embodiments of the present application, before depositing the source metal layer on the substrate by thin-film deposition method, it further includes:

[0095] Cleaning the substrate.

[0096] Specifically, in the preparation process of the ferroelectric field-effect transistor, especially before depositing the source metal layer, cleaning the substrate is a crucial step. The purpose of this step is to remove impurities, contaminants and oxide layers on the substrate surface to ensure that the subsequently deposited metal layer can form good contact and bonding with the substrate.

[0097] Substrate cleaning usually includes multiple steps, such as wet cleaning, dry cleaning and ultrasonic cleaning, etc. Wet cleaning usually uses chemical solutions, such as deionized water, acidic or alkaline solutions, to remove impurities such as organic substances, inorganic substances and metal ions on the surface. Dry cleaning uses physical methods, such as plasma or ion beam, to bombard and etch the surface to remove more stubborn contaminants. Ultrasonic cleaning uses the cavitation effect of ultrasonic waves in the liquid to generate strong microjets and shock waves to wash and peel off contaminants on the surface.

[0098] The selection of the cleaning process and parameter settings depends on the material of the substrate, the type and degree of contaminants, and the requirements of subsequent processes. For different substrates and contaminants, different cleaning methods and conditions need to be adopted to achieve the best cleaning effect.

[0099] After cleaning is completed, the substrate needs to be dried to remove surface moisture and residual cleaning solution. The drying process needs to avoid causing additional damage or contamination to the substrate, and usually methods such as nitrogen blowing, vacuum drying or heating drying are adopted.

[0100] Only when it is ensured that the substrate surface is clean and contamination-free can the subsequent source metal layer deposition step be carried out.

[0101] For example, in an embodiment of the present application, the substrate wafer is cleaned. The process is alcohol + deionized water, and it is processed under ultrasonic conditions to remove as much as possible the organic matter, metal impurities, particles and other contaminants on the wafer surface to ensure the cleanliness of the substrate. The ultrasonic treatment time is 15 minutes.

[0102] In addition, with reference to Figure 3 , the embodiment of the present application also provides a ferroelectric field effect transistor, which is made by the method described in any one of the above. The specific preparation method of this ferroelectric field effect transistor refers to the above embodiment. Since the specific preparation method of the ferroelectric field effect transistor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, and will not be elaborated here one by one.

[0103] As mentioned above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for preparing a ferroelectric field effect transistor, characterized in that: The following steps are involved: Depositing a multi-layer OMO structure on the source metal layer; Photolithographically punching holes on the multilayer OMO structure to form cylindrical holes; Depositing a ferroelectric HZO layer and a channel IGZO layer in the cylindrical hole; and A hole is opened at the bottom of the cylindrical hole, and oxide is deposited between the channel IGZO layers to form an oxide filling layer.

2. The method according to claim 1, characterized in that After depositing the ferroelectric HZO layer and the channel IGZO layer in the cylindrical hole, the method further comprises: A rapid thermal annealing process is performed to improve the performance of the ferroelectric HZO layer and the channel IGZO layer.

3. The method according to claim 2, characterized in that After depositing the ferroelectric HZO layer and the channel IGZO layer in the cylindrical hole, the method further comprises: Depositing a silicon protection layer on the channel IGZO layer; Before the hole is opened at the bottom of the cylindrical hole, the method further comprises: The silicon protective layer is removed.

4. The method according to claim 3, characterized in that After opening a hole at the bottom of the cylindrical hole and depositing oxide between the channel IGZO layers to form an oxide filling layer, the method further includes: Planarization is performed to remove excess surface oxide.

5. The method according to claim 4, characterized in that After the planarization process is performed to remove excess oxide on the surface, the method further includes: A metal layer is deposited by a thin film deposition method to form a drain metal layer.

6. The method according to claim 5, characterized in that After the metal layer is deposited by the thin film deposition method to form the drain metal layer, the method further includes: A thermal annealing process is performed to improve the activity of the drain metal layer.

7. The method according to claim 6, characterized in that After the thermal annealing is performed to improve the activity of the drain metal layer, the method further includes: Perform stepping and metal contact processing for integration and packaging.

8. The method according to claim 1, characterized in that Before depositing the multi-layer OMO structure on the source metal layer, the method further includes: The source metal layer is deposited on the substrate by a thin film deposition method.

9. The method according to claim 8, characterized in that Before depositing the source metal layer on the substrate by a thin film deposition method, the method further includes: The substrate is cleaned.

10. A ferroelectric field effect transistor, characterized in that: The ferroelectric field effect transistor is manufactured by the method according to any one of claims 1 to 9.

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