III-N semiconductor device with substrate contacts

Abstract

The invention relates to a III-N semiconductor device with a substrate contact. A semiconductor device (100) is provided with: a semiconductor substrate (102); the III-N semiconductor layer (106) is positioned above the semiconductor substrate; the contact pad (114) is positioned on the III-N semiconductor layer; a first dielectric layer (202) over the III-N semiconductor layer (202); a first metal contact (502) passing through the first dielectric layer and contacting the contact pad; and a second metal contact (402MSP) including a first side contacting the first dielectric layer and a second side contacting a second dielectric layer (506), and contacting the semiconductor substrate.

Description

[0001] Cross - Reference to Related Applications

[0002] None applicable. Technical Field

[0003] The described examples relate to semiconductor devices and manufacturing, and more specifically but not exclusively, to III-N devices having a substrate contact structure, such as gallium nitride (GaN) or others (e.g., aluminum nitride, aluminum gallium nitride) and / or methods. Background Art

[0004] Semiconductor devices using III-N semiconductors such as GaN, such as integrated circuit (IC) devices, now provide a practical and viable alternative to silicon metal oxide semiconductor field effect transistors (MOSFETs) for designers and IC users. GaN devices operate faster in the MHz range with high-speed switching capabilities, are smaller allowing for higher power density systems, and are more efficient allowing for lower switching energy and reverse recovery losses.

[0005] In some examples, GaN devices are formed with one or more GaN layers on top of a silicon substrate. In this method and for proper operation, one or more electrical contacts from the higher layers in the device to the silicon substrate are required. For example, this contact allows maintaining a constant bias voltage in the silicon substrate and enables the GaN device to handle higher currents. Integrating substrate contacts into the silicon substrate while achieving the desired circuit density has been challenging. Summary of the Invention

[0006] In one example, there is a semiconductor device that includes: a semiconductor substrate; a III-N semiconductor layer located above the semiconductor substrate; a contact pad located on the III-N semiconductor layer; a first dielectric layer located above the III-N semiconductor layer; a first metal contact that passes through the first dielectric layer and contacts the contact pad; and a second metal contact that includes contacting a first side of the first dielectric layer and a second side of a second dielectric layer and contacts the semiconductor substrate.

[0007] Other aspects are also described and claimed. Brief Description of the Drawings

[0008] Figures 1 to 4 Are cross-sectional views showing successive manufacturing stages of a semiconductor device and the resulting structure.

[0009] Figure 5A And 5B Are for showing Figure 4 A cross-sectional view of a first alternative process sequence after

[0010] Figure 5C Are for showing Figure 5B A cross-sectional view of an alternative process sequence of

[0011] Figure 6A and 6B is a cross-sectional view showing the second alternative process sequence after Figure 4 .

[0012] Figure 6C is a cross-sectional view showing the alternative process sequence of Figure 6B .

[0013] Figure 7 is a flowchart outlining an example method for manufacturing a semiconductor device, showing various steps DETAILED DESCRIPTION

[0014] Examples are described with reference to the accompanying drawings, which may not be drawn to scale. For illustrative purposes, several aspects are described with reference to example applications, where like features correspond to like reference numerals. In Figure 1 and the various subsequent figures, cross-sectional views are shown in the x-y (horizontal-vertical) plane, but it should be understood that they also have features in the z dimension and are understood to extend in directions both in and out of the illustrated image plane. Directional references are for purposes of relative placement, but these terms are not intended to be restrictive, as the device can be rotated in space and thus change the absolute references rather than the relative references. Many specific details, relationships, and methods are set forth to provide an understanding, but the scope is not necessarily limited by the illustrated ordering of acts or events, as some acts may occur in a different order and / or concurrently with other acts or events. Additionally, not all of the illustrated acts or events may be required to implement the method according to one or more examples.

[0015] The examples relate to semiconductor device fabrication, and more specifically but not exclusively, to a semiconductor device 100 that can be implemented as a III-N (e.g., GaN) field effect transistor (FET). The GaN FETs can be formed simultaneously and share certain process steps with other devices. This document provides examples that can be conceptually improved as detailed below. While these examples are expected to provide various advantages, no specific result is required unless explicitly recited in the specific claims.

[0016] Figure 1 is a cross-sectional and partial view of a semiconductor device 100 (e.g., part of an IC). The semiconductor device 100 includes a semiconductor substrate 102, such as part of a silicon wafer. Such wafers typically contain multiple locations, each corresponding to the same or different ICs on the wafer, and thus Figure 1 (and subsequent figures) can be repeated at each wafer IC location. Wafers typically provide P-type or N-type semiconductors, and the semiconductor substrate 102 can represent part of a bulk wafer or a region formed in combination with the wafer (e.g., wells and / or buried layers and / or epitaxial layers).

[0017] As now Figure 1 Introduced and detailed in the remaining figures, a GaN device (which is a GaN FET in the illustrated example) is formed in conjunction with a substrate 102 and typically in conjunction with a lateral layout. Relatedly, a layer stack 104 is formed along an upper surface 102US of the substrate 102 and is shown by example to include three layers. The first layer in the layer stack 104 is a III-N layer 106, such as a GaN layer 106 (sometimes referred to as a GaN buffer), which is formed at least partially aligned along a plane (e.g., along the upper surface 102US of the substrate 102). The GaN layer 106 can be formed by a series of vapor phase epitaxy processes and can have a thickness in the range of 1.2 μm to 3.5 μm, which depends in part on the maximum operating potential of the GaN FET. The second layer in the layer stack 104 is an aluminum gallium nitride (AlGaN) barrier layer 108, which is formed along the upper surface 106US of the GaN layer 106. The AlGaN barrier layer 108 can have a thickness in the range of 5 nm to 30 nm. The third layer in the layer stack 104 is a passivation layer 110, such as a dielectric layer (e.g., silicon nitride (SiN)), which is formed along the upper surface 108US of the AlGaN barrier layer 108. The passivation layer 110 can be formed by a low pressure chemical vapor deposition (LPCVD) process and has a thickness in the range of 20nm to 100nm. The passivation layer 110 can also be referred to as a first pre-metal dielectric (PMD) layer.

[0018] Figure 1Also described are three conductive terminals of the GaN FET, each conductive terminal being formed of, for example, one or more metals (e.g., titanium, aluminum, nickel, or gold). The first conductive terminal is the gate terminal 112, which is formed along the AlGaN barrier layer 108 and is thus separated from the GaN layer 106 by the AlGaN barrier layer 108. The second conductive terminal is the source terminal 114, which is formed in a first direction, laterally away from the gate terminal 112 and has a portion that extends through both the passivation layer 110 and the AlGaN barrier layer 108 and contacts the GaN layer 106. The source terminal 114 also includes a source field plate 114FP, which extends laterally from the source terminal 114 and above the gate terminal 112 and is separated from the gate terminal 112 by a portion of the passivation layer 110. The third conductive terminal is the drain terminal 116, which is formed in a second direction opposite to the first direction, laterally away from the gate terminal 112 and has a portion that extends through both the passivation layer 110 and the AlGaN barrier layer 108 and contacts the GaN layer 106. In operation, the GaN FET does not have P / N junction operation as in the case of MOSFETs, but rather a heterojunction between the AlGaN barrier layer 108 and the GaN layer 106 forms a two-dimensional electron gas (2DEG) in a portion of the GaN layer 106 adjacent to the AlGaN barrier layer 108 (at least in the region 118 between the source terminal 114 and the drain terminal 116). The 2DEG has an extremely high charge carrier density and mobility, and current flows between the source terminal 114 and the drain terminal 116 under appropriate electrical conditions.

[0019] In Figure 2 , a second PMD layer 202 is formed over Figure 1 the structure and is thus at least partially aligned along a plane (e.g., along the upper surface 104US of the layer stack 104). In one example, the second PMD layer 202 is conformal and may comprise silicon nitride (SiN) or silicon dioxide (SiO2). Alternatively, the second PMD layer 202 may comprise multiple layers, such as a first layer of SiN, followed by a second layer of SiO2. The second PMD layer 202 (or its layers) may be formed by plasma enhanced chemical vapor deposition (PECVD) or high density plasma (HDP) deposition, for example, to use a relatively low temperature (e.g., at or below 300 °C) to avoid degradation of the conductive terminals (which may also be referred to as contact terminals). The second PMD layer 202 may have a thickness in the range of 1 μm to 5 μm and may provide dielectric isolation between the source potential and the drain potential and reduce capacitive coupling during GaN FET operation.

[0020] In Figure 3 , a mask 302 (e.g., photoresist) is formed over Figure 2Above the structure, and the mask 302 is patterned and etched at the desired location to form a first hole 304 that passes through the second PMD layer 202 and reaches the source terminal 114, a second hole 306 that passes through the second PMD layer 202 and reaches the drain terminal 116, and a third hole 308 that passes through the second PMD layer 202 and the layer stack 104 to reach the substrate 102. The third hole 308 may have the same or a greater lateral width (e.g., diameter) compared to either the first hole 304 or the second hole 306. For reasons shown below, in the illustrated example, the lateral width of the third hole 308 is at least twice as large as the lateral width of either the first hole 304 or the second hole 306, but its lateral width can be up to or greater than five times the lateral width of either the first hole 304 or the second hole 306. For example, the lateral width of the third hole 308 may be in the range of 2.0 μm to 10 μm, while the lateral width of each of the first hole 304 and the second hole 306 may be in the range of 0.2 μm to 0.8 μm.

[0021] The first hole 304, the second hole 306, and the third hole 308 may be formed in one or more steps. In one example, all of the first hole 304, the second hole 306, and the third hole 308 are formed simultaneously in the same etching step, e.g., using a patterned mask 302 as shown in Figure 3 . In another example, the first hole 304 and the second hole 306 having the same lateral width (i.e., in the y - direction of the cross - sectional view) are formed in one etching step, while the third hole 308 having a different lateral width from the first hole 304 and the second hole 306 is formed in a separate step. In this additional example, the mask 302 may be formed and patterned as a first mask having openings only for forming the first hole 304 and the second hole 306, and thereafter, a second mask is formed and patterned to have openings for forming only the third hole 308. Although not shown, at an x - y plane different from that illustrated in Figure 4 (i.e., at a different z - dimension), the mask 302 may also be patterned and etched to provide additional holes that pass through the second PMD 202 and are aligned with the gate terminal 112 to allow for the formation of contacts to the gate terminal 112.

[0022] In Figure 4 , the mask 302 has been removed, and a conformal interconnect or contact metal layer 402 is formed over the remaining Figure 3Above the structure. In some examples, the metal layer 402 includes an adhesion layer (e.g., titanium), a barrier layer on the adhesion layer (e.g., titanium nitride), and tungsten on the barrier layer. The thickness of the metal layer 402 is sufficient to fill the first hole 304 and the second hole 306. In contrast, and because the relatively large diameter of the third hole 308 is at least twice as wide as the smaller diameter of the first hole 304 and the second hole 306, the metal layer 402 aligns along the inner sidewall 308SW and the bottom of the third hole 308, but leaves a void region 404 between the metallized portions along the inner sidewall 308SW. Specifically, the metal layer 402 forms metal sidewall portions 402MSP along the respective inner sidewalls 308SW such that each of the metal sidewall portions 402MSP has a first outward side contacting the second PMD layer 202 and a second inward side facing the remaining void region 404. The metal layer 402 also forms a horizontal portion 402HP along the bottom of the third hole 308 (i.e., along a portion of the upper surface 102US) and extending between the metal sidewall portions 402MSP.

[0023] Figure 5A and 5B description Figure 4 The first alternative process sequence after. In Figure 5A , a etch-back (e.g., dry etch) is performed on the Figure 4 structure to remove a substantially lateral portion of the conformal interconnect metal layer 402. The dry etch may involve reactive ion etching (RIE) or plasma etching. After the etch, the non-lateral portions of the conformal interconnect metal layer 402 are retained as metal contacts, including a first metal contact 502 that passes through the second PMD layer 202 (and the first hole 304) and contacts the source terminal 114 and a second metal contact 504 that passes through the second PMD layer 202 (and the second hole 306) and contacts the drain terminal 116. Although not shown, additional metal contacts to the gate terminal 112 may also be formed at an x-y plane different from that illustrated at a different z dimension, provided that holes are pre-formed through the second PMD layer 202 and subsequently filled with the conformal interconnect metal layer 402. Additionally, due to the directional nature of the etch, the horizontal portion 402HP of the metal layer 402 is removed from below the void region 404, while the metal sidewall portions 402MSP are retained. Thus, the tops of the first contact 502, the second contact 504, and each of the metal sidewall portions 402MSP are aligned along the conformal upper surface 202USC of the PMD layer 202.

[0024] In Figure 5B , a third PMD layer 506 is formed in the void region 404, between the metal sidewall portions 402MSP and also contacting a portion of the upper surface 102US. For example, it can be formed by depositing across the entire Figure 5AA dielectric layer is formed over the structure and then etched such that only the portion of the dielectric layer filling the third void region 404 is retained to form the third PMD layer 506. Thus, although in Figure 4 each of the metal sidewall portions 402MSP has a second inward direction facing the void region 404, after the dielectric is formed in Figure 5B each of these second inward directions faces and contacts the third PMD layer 506 (while the other side of each contact point (e.g., the metal sidewall portion 402MSP) contacts the second PMD layer 202).

[0025] Next, a metal layer (sometimes referred to as metal-1) is formed over the structure and patterned and etched to leave the remaining metal portions, including the first metal portion 508 and the second metal portion 510. The first metal portion 508 contacts the first metal contact 502 and is in electrical communication with the first metal contact, thereby providing a conductive path to the source terminal 114. The second metal portion 510 contacts the second metal contact 504 and is in electrical communication with the second metal contact, thereby providing a conductive path to the drain terminal 116. The metal-1 layer etch also leaves a third metal portion 512. The third metal portion 512 contacts the metal sidewall portion 402MSP, thereby providing a conductive path to the substrate 102.

[0026] Once the Figure 5B structure is completed, additional processing steps may follow. For example, the next step may include forming an inter-metal dielectric layer (IMD) over the remaining portion of the metal-1 layer, and thereafter, forming other metal layers in combination with the formation or connection of other devices, etc. However, by completing the Figure 5B , note that the substrate contact is in place, for example, using in part the same process steps that have been in place for the formation of the contacts (e.g., forming the first metal contact 502 and the second metal contact 504). Additionally, based on the selected geometry, Figure 3 the widths of the holes 304, 306, and 308 of Figure 4 can be selected together with the thickness of the metal layer 402 of

[0027] Figure 5C such that the resulting metal sidewall portion 402MSP provides a contact to the substrate 102 with a greater lateral thickness compared to the first metal contact 502 and the second metal contact 504 that provide the respective contacts to the source terminal 114 and the drain terminal 116. Thus, the described process can be used and the resulting structure can be utilized to achieve favorable conductive properties (e.g., resistance). Additionally, in the illustrated example, IMD planarization is not required with respect to the substrate contact, and the substrate contact can be completed without interacting with the backend and packaging process steps. Figure 5B For a cross-sectional view representing an alternative process sequence of Figure 5CIn [the structure], a metal layer (e.g., Metal-1) is formed over the structure (e.g., Figure 5A the structure shown in [the figure]), and is patterned and etched to leave remaining metal portions, including a first metal portion 520 and a second metal portion 522. The first metal portion 520 contacts a first metal contact 502 and is in electrical communication with the first metal contact, thereby providing an electrical conduction path to the source terminal 114. The second metal portion 522 contacts a second metal contact 504 and is in electrical communication with the second metal contact, thereby providing an electrical conduction path to the drain terminal 116. The Metal-1 layer etch also leaves a third metal portion 524. In one example, the third metal portion 524 is conformal with the metal sidewall portion 402MSP, thereby forming a U-shaped structure that extends horizontally partially along the conformal upper surface 202USC and the upper surface of the metal sidewall portion 402MSP, vertically partially along one side of the metal sidewall portion 402MSP, and horizontally partially along the bottom of the void region 404 (i.e., along a portion of the upper surface 102US) and between the metal sidewall portions 402MSP.

[0028] Next, in Figure 5C [the structure], a dielectric layer 526, such as an intermetal dielectric (IMD), is formed over the structure, further filling the remaining portion of the void 404 that exists between the vertical portions of the U-shaped third metal portion 524. Thus, after the dielectric is formed in Figure 5C [the structure], each inward-facing (facing the void 404) side of the third metal portion 524 contacts the dielectric layer 526, while each outward-facing side of the third metal portion 524 contacts the sidewall portion 402MSP.

[0029] Figure 6A And 6B illustrate Figure 4 a second alternative process sequence after Figure 6A In Figure 4 [the structure], a planarization process (e.g., chemical mechanical planarization (CMP)) is performed on the Figure 6A structure. The planarization process continues downward to remove the material on the horizontal plane of the structure in a top-down manner and stops at the point shown in Figure 6AThe planarized top-down nature applied therein, then, Figure 4 The horizontal portion 402HP of Figure 4 remains in the bottom of the void region 404 and along the upper surface 102US, thereby disposing a generally U-shaped conductor in the previous third hole 308 and having a conduction path provided by the horizontal portion 402HP between the remaining metal sidewall portions 402MSP. In addition, due to the larger contact area with the substrate 102, adding the horizontal portion 402HP as part of the entire conductive region provides a lower contact resistance.

[0030] In addition, also due to planarization, the tops of each of the first contact 602, the second contact 604, and the metal sidewall portion 402MSP are aligned along a common plane, that is, along the flat upper surface 202USP of the PMD layer 202.

[0031] In Figure 6B therein, a third PMD layer 606 is formed inside the U-shaped conductor, which includes the horizontal portion 402HP and the remaining metal sidewall portions 402MSP. For example, the third PMD layer 606 can be formed by forming a dielectric layer over the entire Figure 6A structure and then etching it such that only the portion of the dielectric layer filling the inside of the U-shaped conductor is retained. In some instances, after forming a dielectric layer over the entire Figure 6A structure, CMP can be performed such that only the portion of the dielectric layer filling the inside of the U-shaped conductor is retained.

[0032] Next, a metal layer (e.g., metal-1) is formed over the structure and patterned and etched to leave remaining metal portions, including a first metal portion 608 and a second metal portion 610. The first metal portion 608 contacts the first metal contact 602 and is electrically connected to the first metal contact, thereby providing a conduction path to the source terminal 114. The second metal portion 610 contacts the second metal contact 604 and is electrically connected to the second metal contact, thereby providing a conduction path to the drain terminal 116. The metal-1 layer etching also leaves a third metal portion 612. The third metal portion 612 contacts the metal sidewall portion 402MSP, thereby providing a conduction path to the substrate 102.

[0033] Similar to the previous description regarding Figure 5B after forming the Figure 6B structure, additional processing steps may also follow. Also as described above, by completing Figure 6B the substrate contacts are in place, for example, using in part the same process steps that have been in place for contact formation (e.g., the first metal contact 602 and the second metal contact 604). In addition, Figure 6BIt is noted that the selected geometry may result in sidewall portions 402MSP and horizontal portions 402HP having a cross-sectional thickness greater than that of the first metal contact 602 and the second metal contact 604, where those cross-sectional thicknesses are in the x-dimension for the sidewall portions 402MSP and in the y-dimension for the horizontal portions 402HP.

[0034] Figure 6C Cross-sectional views representing Figure 6B alternative process sequences. In Figure 6C , a metal layer (e.g., metal-1) is formed over the structure (e.g., the structure shown in Figure 6A ) and patterned and etched to leave remaining metal portions, including a first metal portion 620 and a second metal portion 622. The first metal portion 620 contacts the first metal contact 602 and is in electrical communication with the first metal contact, thereby providing a conductive path to the source terminal 114. The second metal portion 622 contacts the second metal contact 604 and is in electrical communication with the second metal contact, thereby providing a conductive path to the drain terminal 116. The metal-1 layer etch also leaves a third metal portion 624. In one example, the third metal portion 624 is conformal with the metal sidewall portions 402MSP and the horizontal portions 402HP, thereby forming a U-shaped structure that extends horizontally partially along the flat upper surface 202USP and the upper surface of the metal sidewall portions 402MSP, extends vertically partially along one side of the metal sidewall portions 402MSP, and extends horizontally partially along the top of the horizontal portions 402HP.

[0035] Next, in Figure 6C , a dielectric layer 626, such as an IMD, is formed over the structure and also fills the remaining portions of the voids 404 that exist between the vertical portions of the U-shaped third metal portion 624. Thus, after the dielectric is formed in Figure 6C , each inward-facing (towards the void 404) side of the third metal portion 624 contacts the dielectric layer 626, each laterally outward-facing side of the third metal portion 624 contacts the sidewall portions 402MSP, and the lower horizontal surface of the third metal portion 624 contacts the upper surface of the horizontal portions 402HP.

[0036] Figure 7 A flowchart of an example method 700 that outlines various of the above-described steps for fabricating the semiconductor device 100, such as those shown in Figure 5B and 6B . The method 700 begins at step 702, where Figure 1Semiconductor substrate 102. The semiconductor substrate 102 at this stage can be a bare wafer or can have one or more semiconductor features formed thereon. The semiconductor substrate 102 also includes one or more regions where it is desired to form devices (such as transistors) containing semiconductors or silicon or III-N, or one or more electrical structures adjacent to such regions. Next, in step 704, a layer stack is formed over the semiconductor substrate. For example, the layer stack can include a GaN layer 106 along the upper surface 102US, and one or more of an aluminum gallium nitride (AlGaN) barrier layer 108 and a passivation layer 110. Next, in step 706, at least one contact pad is formed in the III-N layer. For example, the contact pad can be either a source terminal 114 or a drain terminal 116. Next, in step 708, a first dielectric layer is formed over the III-N layer. For example, the first dielectric layer can be a second PMD layer 202( Figure 2 ). Next, in step 710, a first metal contact is formed through the first dielectric layer. For example, the first metal contact can be either a first metal contact 502 or a second metal contact 504( Figure 5A ) or either a first metal contact 602 or a second metal contact 604( Figure 6A ). Next, in step 712, a second metal contact is formed that contacts the semiconductor substrate, where a first side of the second metal contact contacts the first dielectric layer and a second side of the second metal contact contacts a second dielectric layer. For example, the second metal contact can be a metal sidewall portion 402MSP( Figure 5B ; Figure 6B ). Finally, step 714 generally represents that after step 712, additional structures can be formed in combination with the transistors (and possibly other devices and interconnects to and from such devices) associated with the semiconductor substrate 102.

[0037] As can be seen from the above, those skilled in the art should understand that examples are provided such as with respect to semiconductor manufacturing of an IC that includes a III-N layer and contacts to a substrate proximate to the III-N layer (e.g., below in a side view). Such examples provide various benefits, some of which are described above and still include other benefits. Within the scope of the appended claims, other additional modifications to the described examples are possible, and other examples are possible.

Claims

1. A semiconductor device comprising: Semiconductor substrate; A III-N semiconductor layer located above the semiconductor substrate; a contact pad located on the III-N semiconductor layer; a first dielectric layer located above the III-N semiconductor layer; a first metal contact passing through the first dielectric layer and contacting the contact pad; and A second metal contact includes a first side contacting the first dielectric layer and a second side contacting the second dielectric layer, and contacts the semiconductor substrate. 2 . The semiconductor device according to claim 1 , wherein a thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.

3. The semiconductor device according to claim 1: wherein the first dielectric layer is aligned along a first plane; wherein the III-N semiconductor layer is aligned along a second plane; and The second dielectric layer extends from the first plane to the second plane. 4 . The semiconductor device of claim 1 , further comprising a third metal contact, the third metal contact including a first side contacting the first dielectric layer and a second side contacting the second dielectric layer, and contacting the semiconductor substrate. 5 . The semiconductor device according to claim 4 , further comprising a metal member extending along the substrate and contacting the second metal contact and the third metal contact. 6 . The semiconductor device of claim 4 , further comprising a metal member extending over the first dielectric layer and the second dielectric layer and contacting the second metal contact and the third metal contact.

7. The semiconductor device of claim 4, wherein a surface of the first metal contact, a surface of the second metal contact, a surface of the third metal contact, and a surface of the first dielectric layer are aligned along a common plane.

8. The semiconductor device of claim 4, wherein a surface of the first metal contact, a surface of the second metal contact, a surface of the third metal contact, and a surface of the first dielectric layer are aligned along a conformal surface of the first dielectric layer.

9. The semiconductor device according to claim 1: wherein the first metal contact has a first length passing through the first dielectric layer and a first width orthogonal to the length; and wherein the second metal contact has a second length parallel to the first length and a second width orthogonal to the second length; and The second width is greater than the first width. 10 . The semiconductor device according to claim 9 , wherein the second width is two to five times as large as the first width.

11. The semiconductor device of claim 1, wherein a surface of the first metal contact, a surface of the second metal contact, and a surface of the first dielectric layer are aligned along a common plane. 12 . The semiconductor device of claim 1 , wherein the III-N semiconductor layer comprises gallium nitride.

13. A semiconductor device comprising: Semiconductor substrate; A III-N semiconductor layer located above the semiconductor substrate; a transistor source contact pad located on the III-N semiconductor layer; a transistor drain contact pad located on the III-N semiconductor layer; a first dielectric layer over each of the III-N semiconductor layer, the transistor source pad, and the transistor drain pad; a first metal contact passing through the first dielectric layer and contacting the transistor source contact pad; A second metal contact passing through the first dielectric layer and contacting the transistor drain contact pad; and A third metal contact includes a first side contacting the first dielectric layer and a second side contacting a second dielectric layer different from the first dielectric layer, and contacts the semiconductor substrate. 14 . The semiconductor device of claim 13 , further comprising a fourth metal contact, the fourth metal contact including a first side contacting the first dielectric layer and a second side contacting the second dielectric layer, and contacting the semiconductor substrate. 15 . The semiconductor device of claim 14 , wherein the second dielectric layer contacts the semiconductor substrate and extends between the first side of the third metal contact and the first side of the fourth metal contact. 16 . The semiconductor device of claim 14 , further comprising a metal member extending between the third metal contact and the fourth metal contact. 17 . The semiconductor device of claim 14 , further comprising a metal member contacting the semiconductor substrate and extending between the third metal contact and the fourth metal contact.

18. A method of forming a semiconductor device, comprising: forming a III-N semiconductor layer over a semiconductor substrate; forming a contact pad on the III-N semiconductor layer; forming a first dielectric layer over the III-N semiconductor layer; forming a first metal contact passing through the first dielectric layer and contacting the contact pad; as well as A second metal contact is formed contacting the semiconductor substrate, the second metal contact including a first side contacting the first dielectric layer and a second side contacting a second dielectric layer.

19. The method of claim 18, wherein the second dielectric layer comprises a conformal non-planarized dielectric layer, and the method further comprises: A third metal contact is formed to contact the semiconductor substrate, the third metal contact including a first side contacting the first dielectric layer and a second side contacting the conformal non-planarization dielectric layer.

20. The method of claim 18, further comprising: forming a third metal contact contacting the semiconductor substrate, the third metal contact including a first side contacting the first dielectric layer and a second side contacting the second dielectric layer; as well as After forming the third metal contact, upper surfaces of the first metal contact, the second metal contact, the third metal contact, and the second dielectric layer are planarized.

21. The method according to claim 18: wherein forming the first metal contact comprises forming the first metal contact through a hole having a first width in the first dielectric layer; and Wherein forming the second metal contact comprises forming the second metal contact through a second hole having a second width in the first dielectric layer, wherein the second width is at least twice as wide as the first width.

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