Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure includes a transistor. The transistor comprises a vertical channel, a first source / drain electrode, a second source / drain electrode, a first grid electrode and a second grid electrode, a first sacrificial layer removal area is arranged between the first source / drain electrode and the second source / drain electrode in the vertical direction, the vertical channel is located in the first sacrificial layer removal area and provided with a first end and a second end which are oppositely arranged in the vertical direction, the first source / drain electrode is located at the first end and electrically connected with the first end, and the second source / drain electrode is located at the second end and electrically connected with the second end. The second source / drain electrode is positioned at the second end and is electrically connected with the second end; the first gate insulator is over the first source / drain and covers a first sidewall of the vertical channel in an insulating manner. The second gate insulator is over the first source / drain and covers a second sidewall of the vertical channel in an insulating manner. The performance and uniformity of the memory can be improved, so that the performance of the memory is further improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the development of memories, there is a continuous pursuit for memories with higher integration density and larger storage capacity. The traditional double-gate structure transistor is a planar structure with the channel parallel to the in-plane, making it difficult to achieve a high-density array, while the vertical-channel transistor helps to increase the array density of transistors. However, the process flow of traditional vertical-channel transistors is difficult to precisely control the channel length and gate alignment, resulting in poor performance and uniformity of the memory. Thus, it affects the further improvement of the memory performance. Summary of the Invention

[0003] Based on this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are conducive to precisely controlling the channel length and gate alignment to further improve the performance and uniformity of the memory.

[0004] According to some embodiments, the present disclosure provides a semiconductor structure on one hand, including a plurality of transistors arranged in an array; the transistor includes:

[0005] A first source / drain;

[0006] A second source / drain, having a removal region of a first sacrificial layer in the vertical direction between it and the first source / drain;

[0007] A vertical channel, located within the removal region of the first sacrificial layer, and having a first end and a second end oppositely arranged in the vertical direction; the first source / drain is located at the first end and is electrically connected to the first end; the second source / drain is located at the second end and is electrically connected to the second end;

[0008] A first gate, insulatingly located above the first source / drain and insulatingly covering a first sidewall of the vertical channel;

[0009] A second gate, insulatingly located above the first source / drain and insulatingly covering a second sidewall of the vertical channel; wherein, the first sidewall and the second sidewall are opposite in a first horizontal direction.

[0010] According to some embodiments, the second end has an extension portion extending away from the first end in the vertical direction; the second source / drain is located on a sidewall of the extension portion and is electrically connected to the second end.

[0011] According to some embodiments, the materials of the first gate and the second gate are the same or different.

[0012] According to some embodiments, the top surfaces of the first gate and the second gate facing away from the first source / drain are flush with the surface of the non-extension region in the second end.

[0013] According to some embodiments, the semiconductor structure further includes: a plurality of bit lines; the bit lines are located on the surface of the first source / drain facing away from the vertical channel and extend along a first horizontal direction, and each bit line is electrically connected to the first source / drain of a row of transistors arranged along the first horizontal direction.

[0014] According to some embodiments, the semiconductor structure further includes: a plurality of word lines extending along a second horizontal direction, and each word line is electrically connected to the first gate or the second gate of a column of transistors arranged along the second horizontal direction; or, the semiconductor structure further includes: a plurality of first word lines and second word lines that are arranged in parallel at intervals and extend along the second horizontal direction, each first word line is electrically connected to the first gate of a column of transistors arranged along the second horizontal direction, each second word line is electrically connected to the second gate of a column of transistors arranged along the second horizontal direction, and there is an isolation air gap between adjacent first word lines and second word lines; wherein, the second horizontal direction intersects with the first horizontal direction.

[0015] According to some embodiments, another aspect of the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps:

[0016] Provide a substrate, and sequentially form a first source / drain, a vertical channel, and a second source / drain on the substrate in a vertical direction; wherein, there is a removal region of a first sacrificial layer between the first source / drain and the second source / drain in the vertical direction; the vertical channel is located in the removal region of the first sacrificial layer; the vertical channel has a first end and a second end that are oppositely arranged in the vertical direction, and the second end has an extension portion extending away from the first end in the vertical direction; the first source / drain is located at the first end and is electrically connected to the first end; the second source / drain is located on the sidewall of the extension portion and is electrically connected to the second end;

[0017] Form a first gate above the first source / drain to insulate and cover the first sidewall of the vertical channel;

[0018] Form a second gate above the first source / drain to insulate and cover the second sidewall of the vertical channel; wherein, the first sidewall and the second sidewall are opposite to each other in the first horizontal direction.

[0019] According to some embodiments, the method for manufacturing a semiconductor structure further includes: before sequentially forming a first source / drain, a vertical channel, and a second source / drain on the substrate in a vertical direction, form a bit line extending along the first horizontal direction in the substrate; wherein, the first source / drain is located above the bit line and is electrically connected to the bit line.

[0020] According to some embodiments, forming a bit line extending along the first horizontal direction in the substrate includes the following steps:

[0021] A first semiconductor layer, a first sacrificial layer, and a second semiconductor layer are sequentially stacked in a vertical direction on a substrate;

[0022] The first semiconductor layer, the first sacrificial layer, and the second semiconductor layer are patterned to form a plurality of first trenches arranged in parallel at intervals, and the first trenches extend along a first horizontal direction; the first semiconductor layer between adjacent first trenches constitutes a first source / drain;

[0023] A protective layer is formed on the inner wall of the first trench;

[0024] Using the sidewall of the protective layer to self-align and etch the protective layer and the substrate at the bottom of the first trench, a second trench is formed in the substrate;

[0025] A metal silicidation process is performed on the surface of the substrate exposed in the second trench to form bit lines in the substrate between adjacent second trenches.

[0026] According to some embodiments, using the sidewall of the protective layer to self-align and etch the protective layer and the substrate at the bottom of the first trench to form a second trench in the substrate further includes the following steps:

[0027] Using the outer sidewall of the protective layer to self-align and etch the protective layer and the substrate at the bottom of the first trench to form an initial second trench in the substrate;

[0028] A first isolation structure is formed at the bottom of the initial second trench;

[0029] Using the top surface of the first isolation structure to self-align and etch the sidewall of the substrate exposed in the initial second trench along a second horizontal direction to form a second trench; the second horizontal direction intersects with the first horizontal direction.

[0030] Wherein, performing a metal silicidation process on the surface of the substrate exposed in the second trench to form bit lines in the substrate between adjacent second trenches further includes the following steps:

[0031] A metal material is filled in the second trench;

[0032] An annealing process is performed to perform metal silicidation treatment on the surface of the substrate exposed in the second trench to form bit lines;

[0033] The remaining metal material is removed.

[0034] According to some embodiments, forming a first source / drain, a vertical channel, and a second source / drain in sequence in a vertical direction on a substrate further includes the following steps:

[0035] The protective layer is removed;

[0036] A second isolation structure is formed on the sidewalls of the first semiconductor layer in the second trench and the first trench;

[0037] An insulating layer filling the first trench is formed on top of the second isolation structure;

[0038] The insulating layer, the second semiconductor layer, and the first sacrificial layer are patterned to form a plurality of third trenches arranged in parallel at intervals. The third trenches extend along a second horizontal direction; the second horizontal direction intersects the first horizontal direction;

[0039] The sidewalls of the first sacrificial layer exposed in the third trenches are etched along the first horizontal direction to form first accommodation grooves;

[0040] The sidewalls of the second semiconductor layer exposed in the third trenches are etched along the first horizontal direction to form second accommodation grooves; the second accommodation grooves communicate with the first accommodation grooves, and the depth of the second accommodation grooves in the first horizontal direction is less than the depth of the first accommodation grooves in the first horizontal direction;

[0041] Vertical channels are formed in the first accommodation grooves and the second trenches; wherein, the extending portions of the vertical channels are located in the second accommodation grooves.

[0042] According to some embodiments, forming a first gate insulating the sidewalls of the vertical channels above the first source / drain includes the following steps:

[0043] A first gate dielectric layer and a first gate material layer are sequentially formed in the third trenches;

[0044] The first gate material layer is etched back along the vertical direction to a target height to form an initial first gate;

[0045] An insulating layer covering the initial first gate is formed.

[0046] According to some embodiments, forming a second gate insulating the sidewalls of the vertical channels above the first source / drain includes the following steps:

[0047] The insulating layer, the second semiconductor layer, and the first sacrificial layer between adjacent third trenches are patterned to form a fourth trench and make the remaining second semiconductor layer constitute a second source / drain; the fourth trench extends along the second horizontal direction;

[0048] The remaining first sacrificial layer is removed to form a third accommodation groove;

[0049] A second gate dielectric layer and a second gate are sequentially formed in the third accommodation groove.

[0050] According to some embodiments, forming a second gate dielectric layer and a second gate sequentially in the third accommodation groove further includes the following steps:

[0051] A second gate dielectric material layer and a second gate material layer are sequentially formed on the sidewalls of the insulating layer and the second semiconductor layer and the inner wall of the third accommodation groove;

[0052] Etch back the second gate dielectric material layer and the second gate material layer in the vertical direction to a target height to form a second gate dielectric layer and an initial second gate;

[0053] Form a second sacrificial layer that conformally covers the sidewalls of the insulating layer and the second semiconductor layer and the top surfaces of the initial first gate and the initial second gate;

[0054] Self-align etch the initial first gate and the initial second gate using the outer sidewalls of the second sacrificial layer to form a first gate and a second gate respectively on the sidewalls of the vertical channels on both sides of the third trench and both sides of the fourth trench, and an isolation air gap located between adjacent first gates and second gates.

[0055] According to some embodiments, the method for manufacturing a semiconductor structure further includes: forming a third isolation structure on top of the isolation air gap; the third isolation structure closes the isolation air gap.

[0056] According to some embodiments, the method for manufacturing a semiconductor structure further includes: forming a contact structure on top of the extension and the second source / drain, and the contact structure is electrically connected to both the extension and the second source / drain.

[0057] The embodiments of the present disclosure may / at least have the following advantages:

[0058] In the embodiments of the present application, the transistor employs a vertical channel, and the vertical channel has a first end and a second end that are oppositely disposed in the vertical direction. The first source / drain is located at the first end and is electrically connected to the first end, and the second source / drain is located on the sidewall of the extension and is electrically connected to the second end. There is a removal area of the first sacrificial layer between the first source / drain and the second source / drain in the vertical direction, and the vertical channel is located within the removal area of the first sacrificial layer. Thus, a heterojunction stack is formed by using the first source / drain, the first sacrificial layer, and the second source / drain, and a vertical channel is formed in the removal area of the first sacrificial layer between the first source / drain and the second source / drain, which is beneficial to accurately control the length of the vertical channel and helps to avoid the short-channel effect. Moreover, both the first gate and the second gate in the transistor are located above the first source / drain and are both insulated from the opposite sidewalls of the vertical channel in the first horizontal direction. In this way, through the strong electrostatic control ability of the double gates on the channel, the short-channel effect of the transistor can be further suppressed, which further helps to improve the memory performance. Further, the transistor structure adopted above enables the transistor to have a smaller area occupancy ratio, increases the density of the transistor, and further improves the integration degree of the memory.

[0059] In addition, a first gate and a second gate are respectively formed above the first source / drain, and both are insulated and located on the opposite sidewalls of the vertical channel in the first horizontal direction. In this way, it is beneficial to improve the alignment accuracy between the first gate and the second gate and the vertical channel, making it convenient to control the core electrical parameters, easy to control the electrical performance uniformity, improving the performance and uniformity of the memory, and further enhancing the performance of the memory. Description of the Drawings

[0060] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0061] Figure 1 Structural schematic diagram of a semiconductor structure provided in some embodiments;

[0062] Figure 2 Structural schematic diagram of another semiconductor structure provided in some embodiments;

[0063] Figure 3 Flow schematic diagram of a method for manufacturing a semiconductor structure provided in some embodiments;

[0064] Figure 4 Flow schematic diagram of forming a bit line extending in the first horizontal direction in a method for manufacturing a semiconductor structure provided in some embodiments;

[0065] Figure 5 Flow schematic diagram of forming a first source / drain, a vertical channel, and a second source / drain in a method for manufacturing a semiconductor structure provided in some embodiments;

[0066] Figure 6 Structural schematic diagram of the structure obtained in step S101 in a method for manufacturing a semiconductor structure provided in some embodiments;

[0067] Figure 6a For Figure 6 Cross-sectional schematic diagram of the shown structure on the C1 section;

[0068] Figure 7 Structural schematic diagram of the structure obtained after forming a first mask layer in a method for manufacturing a semiconductor structure provided in some embodiments;

[0069] Figure 7a For Figure 7 Cross-sectional schematic diagram of the shown structure on the C1 section;

[0070] Figure 8 Schematic diagram of the structure obtained in step S102 in a method for preparing a semiconductor structure provided in some embodiments;

[0071] Figure 8a For Figure 8 Schematic cross-sectional view of the shown structure on the C1 cross-section;

[0072] Figure 9 Schematic diagram of the structure obtained in step S103 in a method for preparing a semiconductor structure provided in some embodiments;

[0073] Figure 9a For Figure 9 Schematic cross-sectional view of the shown structure on the C1 cross-section;

[0074] Figure 10 Schematic diagram of the structure obtained in step S1041 in a method for preparing a semiconductor structure provided in some embodiments;

[0075] Figure 10a For Figure 10 Schematic cross-sectional view of the shown structure on the C1 cross-section;

[0076] Figure 11 Schematic diagram of the structure obtained after forming the initial first isolation structure in a method for preparing a semiconductor structure provided in some embodiments;

[0077] Figure 11a For Figure 11 Schematic cross-sectional view of the shown structure on the C1 cross-section;

[0078] Figure 12 Schematic diagram of the structure obtained in step S1042 in a method for preparing a semiconductor structure provided in some embodiments;

[0079] Figure 12a For Figure 12 Schematic cross-sectional view of the shown structure on the C1 cross-section;

[0080] Figure 13 Schematic diagram of the structure obtained in step S1043 in a method for preparing a semiconductor structure provided in some embodiments;

[0081] Figure 13a For Figure 13 Schematic cross-sectional view of the shown structure on the C1 cross-section;

[0082] Figure 14 Schematic diagram of the structure obtained in step S1051 in a method for preparing a semiconductor structure provided in some embodiments;

[0083] Figure 14a is Figure 14 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0084] Figure 15 a schematic structural view of the structure obtained in step S1053 in a method for preparing a semiconductor structure provided in some embodiments;

[0085] Figure 15a is Figure 15 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0086] Figure 16 a schematic structural view of the structure obtained in step S11 in a method for preparing a semiconductor structure provided in some embodiments;

[0087] Figure 16a is Figure 16 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0088] Figure 17 a schematic structural view of the structure obtained after forming the initial second isolation structure in a method for preparing a semiconductor structure provided in some embodiments;

[0089] Figure 17a is Figure 17 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0090] Figure 18 a schematic structural view of the structure obtained in step S12 in a method for preparing a semiconductor structure provided in some embodiments;

[0091] Figure 18a is Figure 18 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0092] Figure 19 a schematic structural view of the structure obtained in step S13 in a method for preparing a semiconductor structure provided in some embodiments;

[0093] Figure 19a is Figure 19 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0094] Figure 20 a schematic structural view of the structure obtained after forming the second mask layer in a method for preparing a semiconductor structure provided in some embodiments;

[0095] Figure 20a is Figure 20 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0096] Figure 20b isFigure 20 The schematic cross-sectional view of the structure shown on the C2 section;

[0097] Figure 21 It is the schematic structural view of the structure obtained in step S14 in a method for manufacturing a semiconductor structure provided in some embodiments;

[0098] Figure 21a It is Figure 21 The schematic cross-sectional view of the structure shown on the C1 section;

[0099] Figure 21b It is Figure 21 The schematic cross-sectional view of the structure shown on the C2 section;

[0100] Figure 22 It is the schematic structural view of the structure obtained in step S15 in a method for manufacturing a semiconductor structure provided in some embodiments;

[0101] Figure 22a It is Figure 22 The schematic cross-sectional view of the structure shown on the C1 section;

[0102] Figure 22b It is Figure 22 The schematic cross-sectional view of the structure shown on the C2 section;

[0103] Figure 23 It is the schematic structural view of the structure obtained in step S16 in a method for manufacturing a semiconductor structure provided in some embodiments;

[0104] Figure 23a It is Figure 23 The schematic cross-sectional view of the structure shown on the C1 section;

[0105] Figure 23b It is Figure 23 The schematic cross-sectional view of the structure shown on the C2 section;

[0106] Figure 24 It is the schematic structural view of the structure obtained after forming the trench material layer in a method for manufacturing a semiconductor structure provided in some embodiments;

[0107] Figure 24a It is Figure 24 The schematic cross-sectional view of the structure shown on the C1 section;

[0108] Figure 24b It is Figure 24 The schematic cross-sectional view of the structure shown on the C2 section;

[0109] Figure 25 It is the schematic structural view of the structure obtained in step S17 in a method for manufacturing a semiconductor structure provided in some embodiments;

[0110] Figure 25a is Figure 25 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0111] Figure 25b is Figure 25 a schematic cross-sectional view of the structure shown in the C2 cross-section;

[0112] Figure 26 is a schematic diagram of the structure obtained in step S21 of a method for fabricating a semiconductor structure provided in some embodiments;

[0113] Figure 26a is Figure 26 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0114] Figure 26b is Figure 26 a schematic cross-sectional view of the structure shown in the C2 cross-section;

[0115] Figure 27 is a schematic diagram of the structure obtained in step S22 of a method for fabricating a semiconductor structure provided in some embodiments;

[0116] Figure 27a is Figure 27 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0117] Figure 27b is Figure 27 a schematic cross-sectional view of the structure shown in the C2 cross-section;

[0118] Figure 28 is a schematic diagram of the structure obtained in step S31 of a method for fabricating a semiconductor structure provided in some embodiments;

[0119] Figure 28a is Figure 28 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0120] Figure 28b is Figure 28 a schematic cross-sectional view of the structure shown in the C2 cross-section;

[0121] Figure 29 is a schematic diagram of the structure obtained in step S32 of a method for fabricating a semiconductor structure provided in some embodiments;

[0122] Figure 29a is Figure 29 a schematic cross-sectional view of the structure shown in the C1 cross-section;

[0123] Figure 29b isFigure 29 The schematic cross-sectional view of the structure shown on a C2 section;

[0124] Figure 30 It is the schematic diagram of the structure obtained in step S331 of a method for manufacturing a semiconductor structure provided in some embodiments;

[0125] Figure 30a It is Figure 30 The schematic cross-sectional view of the structure shown on a C1 section;

[0126] Figure 30b It is Figure 30 The schematic cross-sectional view of the structure shown on a C2 section;

[0127] Figure 31 It is the schematic diagram of the structure obtained in step S332 of a method for manufacturing a semiconductor structure provided in some embodiments;

[0128] Figure 31a It is Figure 31 The schematic cross-sectional view of the structure shown on a C1 section;

[0129] Figure 31b It is Figure 31 The schematic cross-sectional view of the structure shown on a C2 section;

[0130] Figure 32 It is the schematic diagram of the structure obtained in step S333 of a method for manufacturing a semiconductor structure provided in some embodiments;

[0131] Figure 32a It is Figure 32 The schematic cross-sectional view of the structure shown on a C1 section;

[0132] Figure 32b It is Figure 32 The schematic cross-sectional view of the structure shown on a C2 section;

[0133] Figure 33 It is the schematic diagram of the structure obtained in step S334 of a method for manufacturing a semiconductor structure provided in some embodiments;

[0134] Figure 33a It is Figure 33 The schematic cross-sectional view of the structure shown on a C1 section;

[0135] Figure 33b It is Figure 33 The schematic cross-sectional view of the structure shown on a C2 section;

[0136] Figure 34 It is the schematic diagram of the structure obtained in step S40 of a method for manufacturing a semiconductor structure provided in some embodiments;

[0137] Figure 34a is Figure 34 a schematic cross-sectional view of the structure shown on the C1 section;

[0138] Figure 34b is Figure 34 a schematic cross-sectional view of the structure shown on the C2 section;

[0139] Figure 35 is a schematic diagram of the structure obtained after forming the fourth isolation structure in a method for manufacturing a semiconductor structure provided in some embodiments;

[0140] Figure 35a is Figure 35 a schematic cross-sectional view of the structure shown on the C1 section;

[0141] Figure 35b is Figure 35 a schematic cross-sectional view of the structure shown on the C2 section.

[0142] Explanation of reference numerals:

[0143] 1 - vertical channel, 111 - trench material layer, 11 - extension, 21 - first source / drain, 22 - second source / drain, 31 - first gate, first gate material layer 310, 32 - second gate; 320 - initial second gate, 3200 - second gate material layer, 41 - first gate dielectric layer, 410 - first gate dielectric material layer, 42 - second gate dielectric layer, 420 - second gate dielectric material layer,

[0144] A - first end, B - second end, S - substrate, M - metal material, Q1 - isolation air gap, BL - bit line, WL - word line; WL1 - first word line, WL2 - second word line,

[0145] L11 - first semiconductor layer, L12 - second semiconductor layer, L21 - first sacrificial layer, L3 - protective layer,

[0146] Y1 - first mask layer, Y2 - second mask layer, Y21 - polysilicon mandrel, Y22 - sidewall,

[0147] G1 - first trench, G20 - initial second trench, G2 - second trench, G3 - third trench, G4 - fourth trench,

[0148] C1 - first receiving groove, C2 - second receiving groove, C3 - third receiving groove,

[0149] 510 - Initial first isolation structure, 51 - First isolation structure, 520 - Initial second isolation structure, 52 - Second isolation structure, 53 - Third isolation structure, 54 - Fourth isolation structure, 6 - Insulating layer, 71 - First filling layer, 72 - Second filling layer, 8 - Contact structure. Detailed implementation manners

[0150] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant accompanying drawings. Embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure will be thorough and complete.

[0151] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure belongs. The terms used in the description of the present disclosure in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0152] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part.

[0153] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the attached drawings is flipped, an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0154] As used herein, the singular forms "a", "an" and "the" may also include the plural unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be ascertained, but one or more other features, integers, steps, operations, elements, components and / or groups thereof are not precluded from existence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0155] As used herein, the "deposition" process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0156] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. It is to be expected that variations in the shapes as a result of, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the particular shapes of regions shown herein but include shape deviations resulting, for example, from manufacturing techniques. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or implantation concentration gradients rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic in nature, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0157] With the development of memories, there is a continuous pursuit for memories with higher integration density and larger storage capacity. Conventional vertical-channel transistors help to increase the transistor array density and reduce the limitations of memory scaling on geometric parameters such as channel length, source / drain size, etc. Certain oxide semiconductor materials have a high carrier mobility and do not form a low dielectric constant interface when acting as the channel material, which is of great help in improving the device performance of transistors. Dual-gate transistors, due to the simultaneous formation of a top gate and a back gate, have a strong electrostatic control ability over the channel and help to avoid the short-channel effect.

[0158] Conventional dual-gate structure transistors are planar structures with channels parallel to the in-plane direction and it is difficult to achieve a high-density array, while vertical-channel transistors help to increase the array density of transistors. However, the process flow of conventional vertical-channel transistors is difficult to accurately control the channel length and gate alignment, resulting in poor performance and uniformity of the memory. This thus affects the further improvement of memory performance.

[0159] Some embodiments of the present disclosure provide a semiconductor structure. Please refer to Figure 1 , the semiconductor structure includes a plurality of transistors arranged in an array. The transistor includes: a vertical channel 1, a first source / drain 21, a second source / drain 22, a first gate 31, and a second gate 32. There is a removal region of a first sacrificial layer between the first source / drain 21 and the second source / drain 22 in the vertical direction (e.g., the Z direction). The vertical channel 1 is located within the removal region of the first sacrificial layer and has a first end A and a second end B that are oppositely arranged in the vertical direction (e.g., the Z direction). The first source / drain 21 is located at the first end A and is electrically connected to the first end A. The second source / drain 22 is located at the second end B and is electrically connected to the second end B. The first gate 31 is insulated above the first source / drain 21 and insulates and covers the first sidewall of the vertical channel 1. The second gate 32 is insulated above the first source / drain 21 and insulates and covers the second sidewall of the vertical channel 1. Among them, the first sidewall and the second sidewall are opposite in the first horizontal direction (e.g., the X direction).

[0160] In the embodiments of the present application, the transistor employs a vertical channel 1, and the vertical channel 1 has a first end A and a second end B oppositely arranged in the vertical direction. The first source / drain 21 is located at the first end A and is electrically connected to the first end A. The second source / drain 22 is located at the second end B and is electrically connected to the second end B. There is a removal region of the first sacrificial layer between the first source / drain 21 and the second source / drain 22 in the vertical direction (such as the Z direction), and the vertical channel 1 is located within the removal region of the first sacrificial layer. In this way, a heterojunction stack is formed by the first source / drain 21, the first sacrificial layer, and the second source / drain 22, and the vertical channel 1 is formed in the removal region of the first sacrificial layer between the first source / drain 21 and the second source / drain 22, which is beneficial to accurately control the length of the vertical channel 1 and helps to avoid the short-channel effect. Moreover, the first gate 31 and the second gate 32 in the transistor are both located above the first source / drain 21 and are both insulated on the opposite sidewalls of the vertical channel 1 in the first horizontal direction (such as the X direction). In this way, through the strong electrostatic control ability of the double gate on the channel, the short-channel effect of the transistor can be further suppressed, which in turn helps to improve the memory performance. Further, the above-mentioned vertical channel 1 adopted makes the transistor have a smaller area ratio, improves the density of the transistor, and further improves the integration degree of the memory.

[0161] In some examples, please continue to refer to Figure 1 , the second end B has an extension 11 extending away from the first end A in the vertical direction (such as the Z direction). The second source / drain 22 is located on the sidewall of the extension 11 and is electrically connected to the second end B.

[0162] In some examples, the transistor further includes: a first gate dielectric layer 41 and a second gate dielectric layer 42. The first gate dielectric layer 41 is located between the first gate 31 and the vertical channel 1 and between the first gate 31 and the first source / drain 21; the second gate dielectric layer 42 is located between the second gate 32 and the vertical channel 1 and between the second gate 32 and the first source / drain 21.

[0163] Exemplarily, the first gate dielectric layer 41 and the second gate dielectric layer 42 can be formed by the same process steps.

[0164] Exemplarily, the thicknesses of the first gate dielectric layer 41 and the second gate dielectric layer 42 can be the same.

[0165] In some examples, the orthographic projection shape of the first source / drain 21 includes but is not limited to a rectangle. For example, it can be a circle, an ellipse, a polygon, etc.

[0166] In some examples, please continue to refer to Figure 1, the outer sidewalls of the first gate 31 (i.e., the sidewalls facing away from the vertical channel 1) are flush with the sidewalls of the first source / drain 21 in the same direction. The outer sidewalls of the second gate 32 (i.e., the sidewalls facing away from the vertical channel) are flush with the sidewalls of the first source / drain 21 in the same direction.

[0167] According to some embodiments, the materials of the first gate 31 and the second gate 32 are the same or different.

[0168] Here, it should be particularly noted that the first gate 31 and the second gate 32 can be formed by different process steps.

[0169] According to some embodiments, the top surfaces of the first gate 31 and the second gate 32 facing away from the first source / drain 21 are flush with the surface of the non-extension region in the second end B.

[0170] In the embodiments of the present application, the top surfaces of the first gate 31 and the second gate 32 facing away from the first source / drain 21 are flush with the surface of the non-extension region in the second end B. In this way, the alignment accuracy between the first gate 31 and the second gate 32 and the vertical channel 1 can be further improved.

[0171] In some examples, the dimensions of the first gate 31 and the second gate 32 in the vertical direction (e.g., the Z direction) are substantially the same as the dimension of the spacing between the first end A and the second end B of the vertical channel 1 in the vertical direction (e.g., the Z direction).

[0172] Exemplarily, the difference between the dimension of the first gate 31 in the vertical direction (e.g., the Z direction) and the dimension of the spacing between the first end A and the second end B of the vertical channel 1 in the vertical direction (e.g., the Z direction) is the thickness of the first gate dielectric layer 41; the difference between the dimension of the second gate 32 in the vertical direction (e.g., the Z direction) and the dimension of the spacing between the first end A and the second end B of the vertical channel 1 in the vertical direction (e.g., the Z direction) is the thickness of the second gate dielectric layer 42.

[0173] According to some embodiments, please continue to refer to Figure 1 , the semiconductor structure further includes: a plurality of bit lines BL. The bit lines BL are located on the surface of the first source / drain 21 facing away from the vertical channel 1 and extend along the first horizontal direction (e.g., the X direction). Each bit line BL is electrically connected to the first source / drain 21 of a row of transistors arranged along the first horizontal direction (e.g., the X direction).

[0174] In some examples, the material of the bit line BL may include, but is not limited to, metal silicide, metal, etc.

[0175] In some examples, the cross-sectional shape of the bit line BL includes an inverted T shape.

[0176] Exemplarily, the vertical portion of the inverted T-shaped bit line BL is located on the side of the horizontal portion close to the first source / drain 21 and is connected to the first source / drain 21.

[0177] According to some embodiments, the semiconductor structure further includes: a plurality of word lines WL extending along the second horizontal direction (e.g., the Y direction). Each word line WL is electrically connected to the first gate 31 or the second gate 32 of a column of transistors arranged along the second horizontal direction (e.g., the Y direction). For example, please continue to refer to Figure 1 that the word line WL is electrically connected to the first gate 31, and the word line WL and the first gate 31 are of an integral structure.

[0178] Alternatively, according to some other embodiments, please refer to Figure 2 that the semiconductor structure further includes: a plurality of first word lines WL1 and second word lines WL2 that are arranged in parallel at intervals and extend along the second horizontal direction (e.g., the Y direction). Each first word line WL1 is electrically connected to the first gate 31 of a column of transistors arranged along the second horizontal direction (e.g., the Y direction), and the first word line WL1 and the first gate 31 are of an integral structure. Each second word line WL2 is electrically connected to the second gate 32 of a column of transistors arranged along the second horizontal direction (e.g., the Y direction), and the second word line WL2 and the second gate 32 are of an integral structure. And there is an isolation air gap between adjacent first word lines WL1 and second word lines WL2. Wherein, the second horizontal direction (e.g., the Y direction) intersects with the first horizontal direction (e.g., the X direction).

[0179] Some embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure for manufacturing the semiconductor structure as described in the above embodiments. The technical advantages of the above semiconductor structure are also possessed by this manufacturing method. Please refer to Figure 3 that the method for manufacturing the semiconductor structure includes the following steps.

[0180] S10: Provide a substrate, and sequentially form a first source / drain, a vertical channel, and a second source / drain on the substrate in the vertical direction; wherein, the first source / drain and the second source / drain have a removal area of the first sacrificial layer in the vertical direction; the vertical channel is located within the removal area of the first sacrificial layer; the vertical channel has a first end and a second end that are oppositely arranged in the vertical direction, and the second end has an extension portion extending away from the first end in the vertical direction; the first source / drain is located at the first end and is electrically connected to the first end; the second source / drain is located on the side wall of the extension portion and is electrically connected to the second end.

[0181] S20: Form a first gate on the first source / drain to insulate and cover the first side wall of the vertical channel.

[0182] S30: Form a second gate on the first source / drain to insulate and cover the second side wall of the vertical channel; wherein, the first side wall and the second side wall are opposite to each other in the first horizontal direction.

[0183] In the embodiments of the present application, there is a removal region of the first sacrificial layer between the first source / drain 21 and the second source / drain 22 in the vertical direction (e.g., the Z direction), and the vertical channel 1 is located in the removal region of the first sacrificial layer. In this way, a heterojunction stack is formed by using the first source / drain 21, the first sacrificial layer, and the second source / drain 22, and the vertical channel 1 is formed in the removal region of the first sacrificial layer between the first source / drain 21 and the second source / drain 22, which is beneficial to accurately control the length of the vertical channel 1 and helps to avoid the short-channel effect. And by forming a first gate and a second gate respectively above the first source / drain, and both are insulated and located on the opposite sidewalls of the vertical channel in the first horizontal direction. In this way, it is beneficial to improve the alignment accuracy between the first gate and the second gate and the vertical channel, making the core electrical parameters easy to control and the electrical performance uniformity easy to control, improving the performance and uniformity of the memory, so as to further improve the performance of the memory.

[0184] According to some embodiments, step S20 of forming a first gate that insulates and covers the first sidewall of the vertical channel above the first source / drain includes the following steps:

[0185] S21: Sequentially form a first gate dielectric layer and a first gate material layer in the third trench;

[0186] S22: Etch back the first gate material layer in the vertical direction to a target height to form an initial first gate, and form an insulating layer covering the initial first gate.

[0187] According to some embodiments, step S30 of forming a second gate that insulates and covers the second sidewall of the vertical channel above the first source / drain includes the following steps:

[0188] S31: Pattern the insulating layer, the second semiconductor layer, and the first sacrificial layer between adjacent third trenches to form a fourth trench and make the remaining second semiconductor layer form the second source / drain; the fourth trench extends in the second horizontal direction;

[0189] S32: Remove the remaining first sacrificial layer to form a third accommodation groove;

[0190] S33: Sequentially form a second gate dielectric layer and a second gate in the third accommodation groove.

[0191] According to some embodiments, step S33 of sequentially forming a second gate dielectric layer and a second gate in the third accommodation groove further includes the following steps:

[0192] S331: Sequentially form a second gate dielectric material layer and a second gate material layer on the sidewalls of the insulating layer and the second semiconductor layer and the inner wall of the third accommodation groove;

[0193] S332: Etch the second gate dielectric material layer and the second gate material layer vertically back to the target height to form a second gate dielectric layer and an initial second gate;

[0194] S333: Form a second sacrificial layer that conformally covers the sidewalls of the insulating layer and the second semiconductor layer and the top surfaces of the initial first gate and the initial second gate;

[0195] S334: Self-align etch the initial first gate and the initial second gate with the outer sidewalls of the second sacrificial layer to form a first gate and a second gate respectively on the sidewalls of the vertical channels on both sides of the third trench and both sides of the fourth trench, and an isolation air gap located between adjacent first gates and second gates.

[0196] Based on this, according to some embodiments, the method for fabricating a semiconductor structure further includes:

[0197] S40: Form a third isolation structure on top of the isolation air gap; the third isolation structure closes the isolation air gap.

[0198] According to some embodiments, the method for fabricating a semiconductor structure further includes:

[0199] S50: Form a contact structure on top of the extension and the second source / drain, and the contact structure is electrically connected to both the extension and the second source / drain.

[0200] It should be noted that in the above embodiments, the execution of each step in the method does not have a strict order limit. These steps may not necessarily be executed in the described order and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily need to be executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps. The method is limited to being able to achieve the fabrication of the corresponding semiconductor structure.

[0201] Based on this, for the fabrication methods provided in the above some embodiments, the following some embodiments of the present disclosure illustrate some methods as some possible implementation manners of the above manufacturing method.

[0202] In some embodiments, before step S10 of sequentially forming a first source / drain, a vertical channel, and a second source / drain vertically on a substrate, the method for fabricating a semiconductor structure further includes:

[0203] S100: Form a bit line extending in a first horizontal direction in the substrate. Wherein, the first source / drain is located above the bit line and is electrically connected to the bit line.

[0204] According to some embodiments, refer to Figure 4 , step S100 forms bit lines extending along a first horizontal direction in a substrate, including the following steps:

[0205] S101: Stack a first semiconductor layer, a first sacrificial layer, and a second semiconductor layer on the substrate in a vertical direction in sequence;

[0206] S102: Pattern the first semiconductor layer, the first sacrificial layer, and the second semiconductor layer to form a plurality of first trenches arranged in parallel and spaced apart, the first trenches extending along the first horizontal direction; the first semiconductor layer between adjacent first trenches constitutes a first source / drain;

[0207] S103: Form a protective layer on the inner wall of the first trenches;

[0208] S104: Self-aligningly etch the protective layer at the bottom of the first trenches and the substrate with the sidewalls of the protective layer to form second trenches in the substrate;

[0209] S105: Perform a salicide process on the surface of the substrate exposed in the second trenches to form bit lines in the substrate between adjacent second trenches.

[0210] Based on this, in some embodiments, refer to Figure 5 , step S10 forms a first source / drain, a vertical channel, and a second source / drain on the substrate in a vertical direction in sequence, and further includes the following steps:

[0211] S11: Remove the protective layer;

[0212] S12: Form a second isolation structure on the sidewalls of the second trenches and the first semiconductor layer in the first trenches;

[0213] S13: Form an insulating layer filling the first trenches on top of the second isolation structure;

[0214] S14: Pattern the insulating layer, the second semiconductor layer, and the first sacrificial layer to form a plurality of third trenches arranged in parallel and spaced apart, the third trenches extending along a second horizontal direction; the second horizontal direction intersects the first horizontal direction;

[0215] S15: Etch the sidewalls of the first sacrificial layer exposed in the third trenches along the first horizontal direction to form a first accommodation groove;

[0216] S16: Etch the sidewalls of the second semiconductor layer exposed in the third trenches along the first horizontal direction to form a second accommodation groove; the second accommodation groove communicates with the first accommodation groove, and the depth of the second accommodation groove in the first horizontal direction is less than the depth of the first accommodation groove in the first horizontal direction;

[0217] S17: Form a vertical channel in the first receiving groove and the second groove; wherein, the extending portion of the vertical channel is located in the second receiving groove.

[0218] According to some embodiments, step S104 etches the protective layer and the substrate at the bottom of the first groove with the side wall of the protective layer self-aligned, and forms a second groove in the substrate, and further includes the following steps:

[0219] S1041: Etch the protective layer and the substrate at the bottom of the first groove with the outer side wall of the protective layer self-aligned to form an initial second groove in the substrate.

[0220] S1042: Form a first isolation structure at the bottom of the initial second groove.

[0221] S1043: Etch the side wall of the substrate exposed in the initial second groove with the top surface of the first isolation structure self-aligned along the second horizontal direction to form a second groove; the second horizontal direction intersects with the first horizontal direction.

[0222] Wherein, step S105 performs a salicide process on the surface of the substrate exposed in the second groove to form bit lines in the substrate between adjacent second grooves, and further includes the following steps:

[0223] S1051: Fill a metal material in the second groove.

[0224] S1052: Perform an annealing process to perform salicide treatment on the surface of the substrate exposed in the second groove to form bit lines.

[0225] S1053: Remove the residual metal material.

[0226] To more clearly illustrate the method for preparing the semiconductor structure provided in the above embodiments, the following is combined with Figures 6 to 35b The method for preparing the semiconductor structure is described in detail.

[0227] In step S101, please refer to Figure 6 and Figure 6a , stack a first semiconductor layer L11, a first sacrificial layer L21, and a second semiconductor layer L12 on the substrate S in a vertical direction (for example, the Z direction) in sequence.

[0228] Exemplarily, the substrate S can be composed of a semiconductor material, an insulating material, a conductive material, or any combination of their material types. The substrate S can be a single-layer structure or a multi-layer structure. For example, the substrate S can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate S can be a layered substrate including a stack such as Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0229] Here, the materials of the first semiconductor layer L11 and the second semiconductor layer L12 can be the same, and there is a high wet etching selectivity between the materials of the first semiconductor layer L11 and the second semiconductor layer L12 and the first sacrificial layer L21.

[0230] Exemplarily, the materials of the first semiconductor layer L11 and the second semiconductor layer L12 can both include, but are not limited to, silicon.

[0231] Exemplarily, the material of the first sacrificial layer L21 can include, but is not limited to, silicon germanide or silicon oxide. For the sake of understanding, in the subsequent steps, the material of the first sacrificial layer L21 is taken as an example of silicon germanide for illustration.

[0232] In some examples, before sequentially stacking the first semiconductor layer L11, the first sacrificial layer L21, and the second semiconductor layer L12 on the substrate S in the vertical direction (e.g., the Z direction), it further includes: forming a first doping region and a second doping region in the substrate S in the vertical direction (e.g., the Z direction). The first doping region and the second doping region have different doping types.

[0233] Correspondingly, in some examples, the step S101 of sequentially stacking the first semiconductor layer L11, the first sacrificial layer L21, and the second semiconductor layer L12 on the substrate S in the vertical direction (e.g., the Z direction) includes: sequentially stacking the first semiconductor layer L11, the first sacrificial layer L21, and the second semiconductor layer L12 on the second doping region in the vertical direction (e.g., the Z direction).

[0234] Wherein, the first doping region is a P-type doping region, the second doping region is an N-type doping region, and the first semiconductor layer L11 is N-type doped; or the first doping region is an N-type doping region, the second doping region is a P-type doping region, and the first semiconductor layer L11 is P-type doped.

[0235] In the embodiments of the present application, by forming doping regions with different doping types in the substrate S to form a PN junction in the substrate S, in this way, the transistor structures between adjacent bit lines can be effectively isolated, thereby improving the leakage problem.

[0236] Exemplarily, after the first doped region and the second doped region are sequentially formed in the substrate S in the vertical direction (e.g., the Z direction), the substrate S can be annealed to repair the lattice of the substrate S.

[0237] Here, the first semiconductor layer L11, the first sacrificial layer L21, and the second semiconductor layer L12 can be formed by deposition processes respectively.

[0238] In addition, please refer to Figure 7 and Figure 7a After sequentially stacking the first semiconductor layer L11, the first sacrificial layer L21, and the second semiconductor layer L12, a first mask layer Y1 with a specific pattern can be formed on the upper surface of the second semiconductor layer L12 as required, such as a photoresist layer and / or a hard mask layer, so as to facilitate etching the first semiconductor layer L11, the first sacrificial layer L21, and the second semiconductor layer L12 based on the mask pattern in the first mask layer Y1 subsequently.

[0239] In step S102, please refer to Figure 8 and Figure 8a Pattern the first semiconductor layer L11, the first sacrificial layer L21, and the second semiconductor layer L12 to form a plurality of first trenches G1 arranged in parallel and spaced apart, and the first trenches G1 extend in the first horizontal direction (e.g., the X direction). The first semiconductor layer L11 between adjacent first trenches G1 constitutes the first source / drain 21.

[0240] Exemplarily, a dry etching process can be used to etch the first semiconductor layer L11, the first sacrificial layer L21, and the second semiconductor layer L12 based on the first mask layer Y1.

[0241] Here, the time needs to be controlled to ensure etching to the surface of the substrate S.

[0242] In step S103, please refer to Figure 9 and Figure 9a Form a protective layer L3 on the inner wall of the first trench G1.

[0243] Exemplarily, the protective layer L3 can be formed by atomic layer deposition.

[0244] Exemplarily, the material of the protective layer L3 can include but is not limited to silicon oxide.

[0245] In some examples, forming the protective layer L3 on the inner wall of the first trench G1 includes: the protective layer L3 conformally covers the inner wall of the trench G1.

[0246] Here, the protective layer L3 conformally covers the inner wall of the trench G1, which means that: the protective layer L3 is a thin layer structure, and the surface of the protective layer L3 mimics the surface of the inner wall of the trench G1, so that the surface shape of the protective layer L3 is similar to the surface shape of the inner wall of the trench G1.

[0247] In step S1041, refer to Figure 10 and Figure 10a , and etch the protective layer L3 and the substrate S at the bottom of the first trench G1 with the outer sidewall of the protective layer L3 self-aligned, to form an initial second trench G20 in the substrate S.

[0248] In some examples, the outer sidewall of the protective layer L3 is the sidewall located in the vertical direction (such as the Z direction) and facing away from the stacked layers such as the first semiconductor layer L11.

[0249] In step S1042, refer to Figure 11 , Figure 11a , Figure 12 and Figure 12a , to form a first isolation structure 51 at the bottom of the initial second trench G20, including:

[0250] Refer to Figure 11 and Figure 11a , fill the initial second trench G20 to form an initial first isolation structure 510;

[0251] Refer to Figure 12 and Figure 12a , etch back the initial first isolation structure 510 to form the first isolation structure 51.

[0252] Exemplarily, the initial first isolation structure 510 can be formed by a chemical vapor deposition process or an atomic layer deposition process.

[0253] Further exemplarily, a grinding process can be used to ensure the surface of the initial first isolation structure 510 is flat. The grinding process includes but is not limited to chemical mechanical polishing (abbreviated as CMP).

[0254] Exemplarily, the material of the first isolation structure 51 can include but is not limited to silicon nitride.

[0255] Here, refer to Figure 12a , the dimension H1 of the first isolation structure 51 in the vertical direction (such as the Z direction) is less than half of the depth H2 of the initial second trench G20.

[0256] In step S1043, refer to Figure 13 and Figure 13a, etch the sidewalls of the substrate S exposed in the initial second trench G20 along the top surface of the first isolation structure 51 self-alignedly in the second horizontal direction (e.g., the Y direction) to form the second trench G2; the second horizontal direction (e.g., the Y direction) intersects with the first horizontal direction (e.g., the X direction).

[0257] Exemplarily, a re-etch process can be used to etch the sidewalls of the substrate S exposed in the initial second trench G20 to form the second trench G2.

[0258] In step S1051, please refer to Figure 14 and Figure 14a , and fill the second trench G2 with a metal material M.

[0259] Exemplarily, the material of the metal material M can include but is not limited to tungsten.

[0260] In step S1052, please refer to Figure 15 and Figure 15a , perform an annealing process to perform metal silicidation on the surface of the substrate S exposed in the second trench G2 to form the bit line BL.

[0261] In step S1053, please refer to Figure 15 and Figure 15a , and remove the residual metal material M.

[0262] Exemplarily, a wet cleaning process can be used to remove the residual metal material M.

[0263] In step S11, please refer to Figure 16 and Figure 16a , and remove the protective layer L3.

[0264] Exemplarily, a wet etching process can be used to remove the protective layer L3.

[0265] In some examples, after removing the protective layer L3, it further includes: removing the first mask layer Y1.

[0266] Here, a grinding process can be used to remove the first mask layer Y1.

[0267] In step S12, please refer to Figure 17 , Figure 17a , Figure 18 and Figure 18a , forming the second isolation structure 52 on the sidewalls of the first semiconductor layer L11 in the second trench G2 and the first trench G1 includes:

[0268] Please refer to Figure 17 and Figure 17a , filling the voids between the sidewalls of the stacked layers such as the first semiconductor layer L11 (i.e., the first source / drain 21) to form the initial second isolation structure 520.

[0269] Please refer to Figure 18 and Figure 18a , etch back the initial second isolation structure 520 to form the second isolation structure 52.

[0270] Exemplarily, the initial second isolation structure 520 can be formed by a chemical vapor deposition process, an atomic layer deposition process, or a furnace tube process.

[0271] Here, the etch back stops at the surface where the first sacrificial layer L21 and the first semiconductor layer L11 are in contact.

[0272] In step S13, please refer to Figure 19 and Figure 19a , an insulating layer 6 filling the first trench G1 is formed on top of the second isolation structure 52.

[0273] Exemplarily, the insulating layer 6 filling the first trench G1 can be formed on top of the second isolation structure 52 by a deposition process.

[0274] Further exemplarily, the insulating layer 6 can be polished by a polishing process so that the surface of the insulating layer 6 facing away from the substrate S is flush with the surface of the second semiconductor layer L12 facing away from the substrate S. The polishing process includes but is not limited to CMP.

[0275] In step S14, please refer to Figures 20 to 21b , the insulating layer 6, the second semiconductor layer L12, and the first sacrificial layer L21 are patterned to form a plurality of third trenches G3 arranged in parallel and spaced apart, and the third trenches G3 extend along the second horizontal direction (e.g., the Y direction). The second horizontal direction (e.g., the Y direction) intersects the first horizontal direction (e.g., the X direction).

[0276] In some examples, please refer to Figure 20 , Figure 20a and Figure 20b , before patterning the insulating layer 6, the second semiconductor layer L12, and the first sacrificial layer L21, a second mask layer Y2 with a specific pattern can be formed on the upper surface of the second semiconductor layer L12 as required for subsequent self-aligned double patterning or self-aligned quadruple patterning processes. Here, the second mask layer Y2 includes a polysilicon core axis Y21 extending along the second horizontal direction (e.g., the Y direction) and sidewalls Y22 on both sides. Among them, the polysilicon core axis Y21 is used to define the formation region of the subsequent fourth trench G4.

[0277] Exemplarily, please refer to Figure 21 , Figure 21a and Figure 21b , the insulating layer 6, the second semiconductor layer L12, and the first sacrificial layer L21 are patterned to form a plurality of third trenches G3 arranged in parallel and spaced apart, and the third trenches G3 extend along the second horizontal direction (e.g., the Y direction).

[0278] Here, based on the second mask Y2 , the insulating layer 6 , the second semiconductor layer L12 and the first sacrificial layer L21 are patterned by selective dry etching, so that the etching stops at the surface of the first sacrificial layer L21 close to the first semiconductor layer L11 .

[0279] In step S15, refer to Figure 22 , Figure 22a and Figure 22b , the sidewall of the first sacrificial layer L21 exposed in the third trench G3 is etched along a first horizontal direction (eg, X direction) to form a first containing groove C1.

[0280] For example, an atomic layer etching process may be used to etch the sidewall of the first sacrificial layer L21 exposed in the third trench G3 along a first horizontal direction (eg, X direction) to form the first containing groove C1.

[0281] In step S16, refer to Figure 23 , Figure 23a and Figure 23b , the sidewall of the second semiconductor layer L12 exposed in the third groove G3 is etched along the first horizontal direction (for example, the X direction) to form a second containing groove C2; ​​the second containing groove C2 is connected to the first containing groove C1, and the depth of the second containing groove C2 in the first horizontal direction (for example, the X direction) is less than the depth of the first containing groove C1 in the first horizontal direction (for example, the X direction).

[0282] For example, etching the sidewall of the second semiconductor layer L12 exposed in the third trench G3 along the first horizontal direction (eg, X direction) also includes etching the surface of the first source / drain 21 away from the substrate S along the vertical direction (eg, Z direction).

[0283] In step S17, refer to Figure 24 , Figure 24a , Figure 24b , Figure 25 , Figure 25a and Figure 25b , a vertical channel 1 is formed in the first receiving groove C1 and the second groove G2; wherein the extension portion 11 of the vertical channel 1 is located in the second receiving groove C2.

[0284] Illustratively, forming the vertical channel 1 includes:

[0285] See also Figure 24 , Figure 24a , Figure 24b , depositing a trench material layer 111 on the surface of the second isolation structure 52 facing away from the substrate S;

[0286] See also Figure 25 , Figure 25a ,Figure 25b Etch the trench material layer 111 to form a vertical channel 1 in the first accommodation groove C1 and the second trench G2.

[0287] Exemplarily, a deposition process may be used to deposit the trench material layer 111 on the surface of the second isolation structure 52 facing away from the substrate S.

[0288] Exemplarily, the material of the trench material layer 111 may be an indium gallium zinc oxide (IGZO) layer, but is not limited thereto.

[0289] Among them, the vertical channel 1 has a first end A and a second end B oppositely arranged in the vertical direction (for example, the Z direction), and the second end B has an extension 11 extending away from the first end A in the vertical direction (for example, the Z direction). The first source / drain 21 is located at the first end A and is electrically connected to the first end A.

[0290] In step S21, please refer to Figure 26 、 Figure 26a 、 Figure 26b , sequentially form a first gate dielectric material layer 410 and a first gate material layer 310 in the third trench G3.

[0291] In step S22, please refer to Figure 27 、 Figure 27a 、 Figure 27b , etch the first gate material layer 310 back to the target height in the vertical direction (for example, the Z direction) to form an initial first gate 3100.

[0292] Exemplarily, when etching the first gate material layer 310 back to the target height in the vertical direction (for example, the Z direction) to form the initial first gate 3100, the first gate dielectric material layer 410 is etched back to the target height in the vertical direction (for example, the Z direction) to form the first gate dielectric layer 41.

[0293] Exemplarily, when etching the first gate material layer 310 back to the target height in the vertical direction (for example, the Z direction) to form the initial first gate 3100, it further includes: etching the first gate dielectric layer 41 back to be flush with the first gate material layer 310 in the vertical direction (for example, the Z direction) to form the first gate dielectric layer 41.

[0294] Exemplarily, after forming the initial first gate 3100, it further includes: filling the third trench G3 to form a first filling layer 71.

[0295] Exemplarily, a deposition process may be used to fill the third trench G3 to form the first filling layer 71.

[0296] Further illustratively, a grinding process may be employed to grind the first filling layer 71 such that the surface of the first filling layer 71 facing away from the substrate S is flush with the surface of the second mask layer Y2 facing away from the substrate S. The grinding process includes, but is not limited to, CMP.

[0297] Illustratively,

[0298] Illustratively, the dimension of the initial first gate 3100 in the vertical direction (e.g., the Z direction) is substantially the same as the dimensions of the first and second ends A and B of the vertical channel 1 in the vertical direction (e.g., the Z direction).

[0299] In some examples, forming the initial first gate 3100 further includes: synchronously forming a first word line WL connected to the initial first gate 3100.

[0300] Here, reference may be made to Figure 2 for understanding that the first word line WL1 extends along the second horizontal direction (e.g., the Y direction) and is electrically connected to the initial first gate 3100.

[0301] In step S31, please refer to Figure 28 、 Figure 28a 、 Figure 28b , pattern the second semiconductor layer L12 and the first sacrificial layer L21 between adjacent third trenches G3 to form a fourth trench G4 and cause the remaining second semiconductor layer L12 to constitute the second source / drain 22; the fourth trench G4 extends along the second horizontal direction (e.g., the Y direction).

[0302] Illustratively, before patterning the second semiconductor layer L12 and the first sacrificial layer L21 between adjacent third trenches G3, it further includes removing the polysilicon mandrel Y21.

[0303] Further illustratively, pattern the second semiconductor layer L12 and the first sacrificial layer L21 between adjacent third trenches G3 based on the sidewall Y22 to form a fourth trench G4.

[0304] In step S32, please refer to Figure 29 、 Figure 29a 、 Figure 29b , remove the remaining first sacrificial layer L21 to form a third receiving groove C3.

[0305] In step S331, please refer to Figure 30 、 Figure 30a 、 Figure 30b , sequentially form a second gate dielectric material layer 420 and a second gate material layer 3200 on the sidewall of the sidewall Y22 and the second semiconductor layer L12 and the inner wall of the third receiving groove C3.

[0306] In step S332, please refer to Figure 31 、 Figure 31a 、Figure 31b Etch the second gate dielectric material layer 420 and the second gate material layer 3200 vertically (e.g., in the Z direction) to a target height to form the second gate dielectric layer 42 and the initial second gate 320.

[0307] Exemplarily, after forming the second gate dielectric layer 42, it further includes: filling the third trench G4 to form the second filling layer 72.

[0308] Exemplarily, a deposition process can be used to fill the third trench G3 to form the second filling layer 72.

[0309] Further exemplarily, a polishing process can be used to polish the insulating layer 6 so that the surface of the second filling layer 72 facing away from the substrate S is flush with the surface of the first filling layer 71 facing away from the substrate S. The polishing process includes but is not limited to CMP.

[0310] Exemplarily, the material of the second filling layer 72 can include but is not limited to silicon oxide.

[0311] In step S333, refer to Figure 32 、 Figure 32a 、 Figure 32b to form a second sacrificial layer L22 that conformally covers the sidewalls of the insulating layer 6 and the second semiconductor layer L12, and the top surfaces of the initial first gate 3100 and the initial second gate 320.

[0312] Exemplarily, before forming the second sacrificial layer L22, it further includes: etching to remove the first filling layer 71 and the second filling layer 72.

[0313] Exemplarily, an atomic layer deposition process can be used to form the second sacrificial layer L22.

[0314] Exemplarily, the material of the second sacrificial layer L22 can include but is not limited to silicon oxide.

[0315] In step S334, refer to Figure 33 、 Figure 33a 、 Figure 33b to self-align and etch the initial first gate 3100 and the initial second gate 320 using the outer sidewalls of the second sacrificial layer, so as to form a first gate 31 and a second gate 32 on the sidewalls of the vertical channel 1 on both sides of the third trench G3 and the fourth trench G4 respectively, and an isolation air gap Q1 located between adjacent first gates 31 and second gates 32.

[0316] In step S40, refer to Figure 34 、 Figure 34a 、 Figure 34b to form a third isolation structure 53 on the top of the isolation air gap Q1; the third isolation structure 53 closes the isolation air gap Q1.

[0317] In some examples, before forming the third isolation structure 53, it further includes removing the second sacrificial layer L22 and the sidewall Y22.

[0318] In step S50, refer to Figure 35 , Figure 35a , Figure 35b , a contact structure 8 is formed on the tops of the extension portion 11 and the second source / drain 22, and the contact structure 8 is electrically connected to both the extension portion 11 and the second source / drain 22.

[0319] In some examples, after forming the contact structure 8, it further includes: forming a fourth isolation structure 54 on the surface of the third isolation structure 53 facing away from the substrate to cover the outer sidewalls of the contact structure 8.

[0320] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0321] The above-described embodiments only represent several implementation manners of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent shall be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising a plurality of transistors arranged in an array; the transistors comprising: A first source / drain; A second source / drain, having a removal region of a first sacrificial layer therebetween in a vertical direction with respect to the first source / drain; A vertical channel, located within the removal region of the first sacrificial layer, and having a first end and a second end oppositely disposed in a vertical direction; the first source / drain is located at the first end and electrically connected to the first end; the second source / drain is located at the second end and electrically connected to the second end; A first gate, insulatingly located above the first source / drain and insulatingly covering a first sidewall of the vertical channel; A second gate, insulatingly located above the first source / drain and insulatingly covering a second sidewall of the vertical channel; wherein the first sidewall and the second sidewall are opposite to each other in a first horizontal direction.

2. The semiconductor structure according to claim 1, wherein The second end has an extension portion extending away from the first end in the vertical direction; the second source / drain is located on a sidewall of the extension portion and electrically connected to the second end.

3. The semiconductor structure according to claim 1, wherein, The materials of the first gate and the second gate are the same or different.

4. The semiconductor structure according to claim 2, characterized in that, The top surfaces of the first gate and the second gate facing away from the first source / drain are flush with the surface of the region of the second end other than the extension portion.

5. The semiconductor structure according to claim 1, characterized in that, Further comprising: A plurality of bit lines, located on a surface of the first source / drain facing away from the vertical channel, and extending in the first horizontal direction; Each bit line is electrically connected to the first source / drain of a row of transistors arranged in the first horizontal direction.

6. The semiconductor structure according to claim 1, wherein The semiconductor structure further comprises: a plurality of word lines extending in a second horizontal direction; each word line is electrically connected to the first gate or the second gate of a column of the transistors arranged in the second horizontal direction; Alternatively, the semiconductor structure further comprises: a plurality of first word lines and second word lines extending in a second horizontal direction and arranged in parallel and spaced apart; each first word line is electrically connected to the first gate of a column of the transistors arranged in the second horizontal direction; each second word line is electrically connected to the second gate of a column of the transistors arranged in the second horizontal direction; and there is an isolation air gap between adjacent first word lines and second word lines; Wherein, the second horizontal direction intersects with the first horizontal direction.

7. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate, and sequentially forming a first source / drain, a vertical channel, and a second source / drain on the substrate in a vertical direction; wherein, there is a removal region of a first sacrificial layer therebetween in a vertical direction between the first source / drain and the second source / drain; the vertical channel is located within the removal region of the first sacrificial layer; the vertical channel has a first end and a second end oppositely disposed in the vertical direction, and the second end has an extension portion extending away from the first end in the vertical direction; the first source / drain is located at the first end and electrically connected to the first end; the second source / drain is located on a sidewall of the extension portion and electrically connected to the second end; Forming a first gate above the first source / drain to insulatingly cover a first sidewall of the vertical channel; A second gate is formed above the first source / drain to insulate the second sidewall of the vertical channel; wherein, the first sidewall and the second sidewall are opposite to each other in a first horizontal direction.

8. The method for preparing a semiconductor structure according to claim 7, wherein, Further included are: Before forming a first source / drain, a vertical channel, and a second source / drain in sequence along a vertical direction on the substrate, a bit line extending along the first horizontal direction is formed in the substrate; Wherein, the first source / drain is located above the bit line and is electrically connected to the bit line.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein, The forming of the bit line extending along the first horizontal direction in the substrate includes: A first semiconductor layer, the first sacrificial layer, and a second semiconductor layer are sequentially stacked along a vertical direction on the substrate; The first semiconductor layer, the first sacrificial layer, and the second semiconductor layer are patterned to form a plurality of first trenches arranged in parallel and spaced apart from each other, and the first trenches extend along the first horizontal direction; the first semiconductor layer between adjacent first trenches constitutes the first source / drain; A protective layer is formed on the inner wall of the first trench; Using the sidewall of the protective layer to self-align and etch the protective layer and the substrate at the bottom of the first trench to form a second trench in the substrate; A metal silicidation process is performed on the surface of the substrate exposed in the second trench to form the bit line in the substrate between adjacent second trenches.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein, The using of the sidewall of the protective layer to self-align and etch the protective layer and the substrate at the bottom of the first trench to form a second trench in the substrate further includes: Using the outer sidewall of the protective layer to self-align and etch the protective layer and the substrate at the bottom of the first trench to form an initial second trench in the substrate; A first isolation structure is formed at the bottom of the initial second trench; Using the top surface of the first isolation structure to self-align and etch the sidewall of the substrate exposed in the initial second trench along a second horizontal direction to form the second trench; the second horizontal direction intersects with the first horizontal direction. Wherein, the performing of the metal silicidation process on the surface of the substrate exposed in the second trench to form the bit line in the substrate between adjacent second trenches further includes: Filling a metal material in the second trench; Performing an annealing process to perform metal silicidation treatment on the surface of the substrate exposed in the second trench to form the bit line; Removing the remaining metal material.

11. The method for manufacturing a semiconductor structure according to claim 9, wherein The forming of the first source / drain, the vertical channel, and the second source / drain in sequence along a vertical direction on the substrate further includes: Removing the protective layer; A second isolation structure is formed on the sidewall of the first semiconductor layer in the second trench and the first trench; An insulating layer filling the first trench is formed on the top of the second isolation structure; The insulating layer, the second semiconductor layer, and the first sacrificial layer are patterned to form a plurality of third trenches arranged in parallel and spaced apart from each other, and the third trenches extend along a second horizontal direction; the second horizontal direction intersects with the first horizontal direction; Etching the sidewall of the first sacrificial layer exposed in the third trench along the first horizontal direction to form a first accommodation groove; Etch the sidewall of the second semiconductor layer exposed in the third trench along the first horizontal direction to form a second accommodation groove; the second accommodation groove communicates with the first accommodation groove, and the depth of the second accommodation groove in the first horizontal direction is less than the depth of the first accommodation groove in the first horizontal direction; Form the vertical channel in the first accommodation groove and the second trench; wherein, the extending portion of the vertical channel is located in the second accommodation groove.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein Forming a first gate insulatingly covering the first sidewall of the vertical channel above the first source / drain electrode includes: Sequentially form a first gate dielectric layer and a first gate material layer in the third trench; Etch back the first gate material layer in the vertical direction to a target height to form an initial first gate; Form an insulating layer covering the initial first gate.

13. The method for preparing a semiconductor structure according to claim 12, wherein, Forming a second gate insulatingly covering the second sidewall of the vertical channel above the first source / drain electrode includes: Pattern the insulating layer, the second semiconductor layer, and the first sacrificial layer between adjacent third trenches to form a fourth trench and make the remaining second semiconductor layer constitute the second source / drain electrode; the fourth trench extends along the second horizontal direction; Remove the remaining first sacrificial layer to form a third accommodation groove; Sequentially form a second gate dielectric layer and the second gate in the third accommodation groove.

14. The method for preparing a semiconductor structure according to claim 13, wherein Sequentially forming a second gate dielectric layer and the second gate in the third accommodation groove further includes: Sequentially form a second gate dielectric material layer and a second gate material layer on the sidewalls of the insulating layer and the second semiconductor layer and the inner wall of the third accommodation groove; Etch back the second gate dielectric material layer and the second gate material layer in the vertical direction to a target height to form the second gate dielectric layer and an initial second gate; Form a second sacrificial layer conformally covering the sidewalls of the insulating layer and the second semiconductor layer and the top surfaces of the initial first gate and the initial second gate; Self-alignedly etch the initial first gate and the initial second gate with the outer sidewall of the second sacrificial layer to form the first gate and the second gate on the sidewalls of the vertical channel on both sides of the third trench and both sides of the fourth trench, respectively, and an isolation air gap located between adjacent first gates and second gates.

15. The method for manufacturing a semiconductor structure according to claim 14, wherein, Further includes: Form a third isolation structure on the top of the isolation air gap; The third isolation structure closes the isolation air gap.

16. The manufacturing method of the semiconductor structure according to any one of claims 7 to 15, characterized in that, Further includes: Form a contact structure on the top of the extending portion and the second source / drain electrode, and the contact structure is electrically connected to both the extending portion and the second source / drain electrode.

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