Laterally diffused metal oxide semiconductor device and preparation method thereof

Abstract

The invention relates to a laterally diffused metal oxide semiconductor device and a preparation method thereof. The laterally diffused metal oxide semiconductor device includes: a substrate structure; the first doped region is arranged in the substrate structure; the first well region and the drain region are arranged in the first doped region at intervals; the source region is arranged in the first well region; the variable K dielectric layer is embedded in the first doped region and is located between the first well region and the drain region; the dielectric constant of the variable K dielectric layer is gradually increased from the front surface of the substrate structure to the back surface of the substrate structure; and the super junction structure is arranged in the first doped region on one side, close to the back surface of the substrate structure, of the variable K dielectric layer. The device provided by the invention can weaken the concentrated electric field at the corner of the variable K dielectric layer, namely, weaken the concentrated electric field at the corner of the groove, thereby improving the withstand voltage of the device under the condition of not increasing the on resistance of the device.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technologies, and particularly to a lateral diffused metal oxide semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous development of semiconductor technologies, the application of lateral double-diffuse MOS (LDMOS) devices has become increasingly widespread, and at the same time, higher requirements have been put forward for the performance of lateral diffused metal oxide semiconductor devices. In related LDMOS technologies, trenches are provided in the drift region to elongate the drift region, so as to improve the breakdown voltage of the device and shorten the surface area of the device. However, the tip electric field at the trench corners is too concentrated, which is not conducive to improving the device performance. Summary of the Invention

[0003] Based on this, it is necessary to provide a lateral diffused metal oxide semiconductor device and a manufacturing method thereof for the above problems.

[0004] In a first aspect, an embodiment of the present application provides a lateral diffused metal oxide semiconductor device, including:

[0005] A substrate structure;

[0006] A first doped region, disposed in the substrate structure;

[0007] A first well region and a drain region, arranged at intervals in the first doped region;

[0008] A source region, disposed in the first well region;

[0009] A variable-K dielectric layer, embedded in the first doped region and located between the first well region and the drain region; in the direction from the front surface to the back surface of the substrate structure, the dielectric constant of the variable-K dielectric layer gradually increases;

[0010] A superjunction structure, disposed in the first doped region on the side of the variable-K dielectric layer close to the back surface of the substrate structure.

[0011] The lateral diffused metal oxide semiconductor device provided by the embodiment of the present application is provided with a variable-K dielectric layer and a superjunction structure located at the bottom of the variable-K dielectric layer in the first doping region. In this way, on the one hand, an electric field peak can be introduced on the sidewall of the variable-K dielectric layer, thereby raising the average field of the breakdown voltage region and weakening the electric field concentrated at the corner of the variable-K dielectric layer, that is, weakening the electric field concentrated at the trench corner, and further improving the device breakdown voltage without increasing the on-resistance of the device; on the other hand, using a low-K dielectric on the device surface can increase the surface breakdown voltage capacity of the device, and using a high-K dielectric in the device body can assist in depleting the charges in the device body; on the other hand, by introducing a superjunction structure, the superjunction structure and the drift region deplete each other in the off state to optimize the electric field and increase the doping concentration of the drift region, thereby reducing the on-resistance in the on state.

[0012] In one embodiment, the variable-K dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, and the dielectric constant of the first sub-dielectric layer is less than the dielectric constant of the second sub-dielectric layer;

[0013] The first sub-dielectric layer is located on the side of the second sub-dielectric layer close to the front of the substrate structure.

[0014] In one embodiment, the variable-K dielectric layer further includes a third sub-dielectric layer, and the dielectric constant of the third sub-dielectric layer is greater than the dielectric constant of the second sub-dielectric layer; the third sub-dielectric layer is located on the side of the second sub-dielectric layer close to the back of the substrate structure.

[0015] In one embodiment, the superjunction structure is adjacent to the variable-K dielectric layer.

[0016] In one embodiment, the superjunction structure includes a first charge balance region and a second charge balance region, and the first charge balance region is located between the second charge balance region and the variable-K dielectric layer;

[0017] The doping type of the first charge balance region is opposite to the doping type of the first doping region, and the doping type of the second charge balance region is the same as the doping type of the first doping region.

[0018] In one embodiment, at least part of the outer periphery of the variable-K dielectric layer is provided with a second doping region, and the doping type of the second doping region is the same as the doping type of the first doping region.

[0019] In one embodiment, the second doping region is adjacent to the variable-K dielectric layer.

[0020] In one embodiment, the variable-K dielectric layer includes a high-K part and a low-K part, and the second doping region is provided at least partially on the outer periphery of the high-K part.

[0021] In one embodiment, a side edge of the superjunction structure protrudes beyond a sidewall of the variable-K dielectric layer.

[0022] In one embodiment, the second doped region is adjacent to the superjunction structure.

[0023] In a second aspect, an embodiment of the present application provides a method for manufacturing a laterally diffused metal oxide semiconductor device, including:

[0024] Providing a substrate structure;

[0025] Forming a first doped region in the substrate structure, and forming a first well region in the first doped region;

[0026] Forming a superjunction structure in the first doped region;

[0027] Forming a variable-K dielectric layer in the first doped region, and the superjunction structure is located on a side of the variable-K dielectric layer close to the back surface of the substrate structure. In a direction from the front surface to the back surface of the substrate structure, a dielectric constant of the variable-K dielectric layer gradually increases;

[0028] Forming a drain region spaced apart from the first well region in the first doped region, and forming a source region in the first well region, and the variable-K dielectric layer is located between the first well region and the drain region.

[0029] The method for manufacturing a laterally diffused metal oxide semiconductor device provided by the embodiment of the present application includes arranging a variable-K dielectric layer and a superjunction structure at the bottom of the variable-K dielectric layer in a first doped region. In this way, on the one hand, an electric field peak value can be introduced at a sidewall of the variable-K dielectric layer, so as to raise an average field of a breakdown voltage region, weaken an electric field concentrated at a corner of the variable-K dielectric layer, that is, weaken an electric field concentrated at a trench corner, and further improve the device breakdown voltage without increasing a conduction resistance of the device; on the other hand, a low-K dielectric is adopted on a device surface to increase a breakdown voltage capacity of the device surface, and a high-K dielectric is adopted in a device body to assist in depleting charges in the device body; on the still other hand, by introducing a superjunction structure, mutual depletion between the superjunction structure and a drift region is achieved in an off state to optimize an electric field and increase a doping concentration of the drift region, so as to reduce a conduction resistance in an on state. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments or exemplary embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1Schematic diagram of a partial structure of a lateral diffused metal oxide semiconductor device provided by an embodiment of the present application.

[0032] Figure 2 Schematic diagram of a partial structure of another lateral diffused metal oxide semiconductor device provided by an embodiment of the present application.

[0033] Figure 3 Schematic flow chart of a method for manufacturing a lateral diffused metal oxide semiconductor device provided by an embodiment of the present application.

[0034] Description of reference numerals:

[0035] 1. Lateral diffused metal oxide semiconductor device; 11. Substrate structure; 11a. Substrate; 11b. Buried layer; 11c. Top silicon layer; 111. First doping region; 112. Source region; 113. Drain region; 114. Second doping region; 115. First well region; 116. Second well region; 117. Body extraction region; 118. Trench; 12. Variable-K dielectric layer; 121. First sub-dielectric layer; 122. Second sub-dielectric layer; 123. Third sub-dielectric layer; 13. Superjunction structure; 131. First charge balance region; 132. Second charge balance region; 14. Gate; 141. Gate dielectric layer; 142. Gate conductive layer. Detailed implementation manners

[0036] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0038] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be referred to as the second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be a P-type and the second doping type may be an N-type, or the first doping type may be an N-type and the second doping type may be a P-type.

[0039] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0040] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0041] Embodiments of the present application are described with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application, such that variations in the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0042] As described in the background art, in related LDMOS technologies, trenches are provided in the drift region to elongate the drift region in order to improve the device breakdown voltage and reduce the device surface area. However, the electric field peak along the trench surface is relatively low, and at the same time, the tip electric field at the trench corner is too concentrated, which is not conducive to improving the device performance.

[0043] In view of the above problems, embodiments of the present application provide a laterally diffused metal oxide semiconductor device and a manufacturing method thereof, by providing a variable-K dielectric layer and a superjunction structure located at the bottom of the variable-K dielectric layer in a first doped region. Thus, on the one hand, an electric field peak can be introduced on the sidewall of the variable-K dielectric layer, thereby raising the average field of the breakdown voltage region and weakening the concentrated electric field at the corner of the variable-K dielectric layer, that is, weakening the concentrated electric field at the trench corner, and further improving the device breakdown voltage without increasing the on-resistance of the device; on the other hand, a low-K dielectric is used on the device surface to increase the surface breakdown voltage capacity of the device, and a high-K dielectric is used in the device body to assist in depleting the charges in the device body; on the still other hand, by introducing a superjunction structure, the superjunction structure and the drift region are mutually depleted in the off state to achieve the purpose of optimizing the electric field and increasing the doping concentration of the drift region, thereby reducing the on-resistance in the on state.

[0044] In a first aspect, with reference to Figure 1 and Figure 2 shown, embodiments of the present application provide a laterally diffused metal oxide semiconductor device 1. The laterally diffused metal oxide semiconductor device 1 takes an N-type laterally diffused metal oxide semiconductor device 1 as an example, the first doping type is P-type and the second doping type is N-type. In other embodiments, the laterally diffused metal oxide semiconductor device 1 can also be a P-type laterally diffused metal oxide semiconductor device 1, the first doping type is N-type and the second doping type is P-type.

[0045] Specifically, the lateral diffusion metal oxide semiconductor device 1 includes: a substrate structure 11, a first doped region 111, a source region 112, a drain region 113, a first well region 115, a variable-K dielectric layer 12, and a superjunction structure 13. The first doped region 111 is disposed in the substrate structure 11; the first well region 115 and the drain region 113 are arranged at intervals in the first doped region 111, and the source region 112 is disposed in the first well region 115; the variable-K dielectric layer 12 is embedded in the first doped region 111 and is located between the first well region 115 and the drain region 113; wherein, in the direction from the front surface of the substrate structure 11 to the back surface of the substrate structure 11, the dielectric constant of the variable-K dielectric layer 12 gradually increases; the superjunction structure 13 is disposed in the first doped region 111 on the side of the variable-K dielectric layer 12 close to the back surface of the substrate structure 11, that is: the superjunction structure 13 is disposed in the first doped region 111 at the bottom of the variable-K dielectric layer 12.

[0046] It can be understood that a trench 118 is provided in the first doped region 111, and the variable-K dielectric layer 12 is disposed in the trench 118. The trench 118 is located between the source region 112 and the drain region 113 and opens from the surface of the first doped region 111 and extends along the thickness direction of the substrate structure 11.

[0047] In one embodiment, the substrate structure 11 includes a stacked base 11a, a buried layer 11b, and a top silicon layer 11c. Exemplarily, the materials of the base 11a and the top silicon layer 11c can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, or low temperature poly-silicon (LTPS), etc., or other materials known to those skilled in the art. The material of the buried layer 11b can be silicon oxide, silicon nitride, silicon oxynitride, or a dielectric material with a dielectric constant less than that of silicon oxide.

[0048] In the embodiment of the present application, the base 11a, the top silicon layer 11c, and the first well region 115 are of the first doping type, and the first doped region 111, the source region 112, and the drain region 113 are of the second doping type.

[0049] The lateral diffused metal oxide semiconductor device 1 provided in the embodiment of the present application is provided with a variable K dielectric layer 12 and a super junction structure 13 located at the bottom of the variable K dielectric layer 12 in the first doping region 111. In this way, on the one hand, an electric field peak can be introduced into the sidewall of the variable K dielectric layer 12 (or the groove 118), thereby increasing the average field of the withstand voltage region and weakening the electric field concentrated at the corner of the variable K dielectric layer 12, that is, weakening the electric field concentrated at the corner of the groove 118, thereby improving the withstand voltage of the device without increasing the on-resistance of the device; on the other hand, the use of a low-K dielectric on the device surface can increase the withstand voltage capability of the device surface, and the use of a high-K dielectric in the device body can assist in depleting the charge in the device body; on the other hand, by introducing the super junction structure 13, the super junction structure 13 and the drift region are mutually depleted in the off state to achieve the purpose of optimizing the electric field and increasing the doping concentration of the drift region, thereby reducing the on-resistance in the on state.

[0050] In one embodiment, referring to Figure 1 As shown, the variable-K dielectric layer 12 includes a first sub-dielectric layer 121 and a second sub-dielectric layer 122. The dielectric constant of the first sub-dielectric layer 121 is smaller than the dielectric constant of the second sub-dielectric layer 122. The first sub-dielectric layer 121 is located on a side of the second sub-dielectric layer 122 close to the front surface of the substrate structure 11, that is, the first sub-dielectric layer 121 is located on a side of the second sub-dielectric layer 122 close to the opening of the groove 118. In this way, the variable-K dielectric layer 12 is formed by two sub-dielectric layers with different dielectric constants, which can reduce the difficulty of manufacturing the variable-K dielectric layer 12.

[0051] In the embodiment of the present application, by setting the first sub-dielectric layer 121 and the second sub-dielectric layer 122, it can be seen from the continuity of the electric flux that an additional electric field peak will be formed on the side wall of the groove 118, which can increase the average field in the voltage-resistant area and weaken the electric field concentrated at the corner of the groove 118, thereby further improving the device voltage resistance without increasing the device on-resistance.

[0052] In one embodiment, referring to Figure 2 As shown, the variable-K dielectric layer 12 further includes a third sub-dielectric layer 123, and the dielectric constant of the third sub-dielectric layer 123 is greater than the dielectric constant of the second sub-dielectric layer 122. The third sub-dielectric layer 123 is located on a side of the second sub-dielectric layer 122 close to the back of the substrate structure 11, that is, the third sub-dielectric layer 123 is located on a side of the second sub-dielectric layer 122 away from the opening of the groove 118. In this way, the variable-K dielectric layer 12 is formed by three sub-dielectric layers with different dielectric constants, which can reduce the difficulty of manufacturing the variable-K dielectric layer 12.

[0053] In the embodiments of the present application, by providing the first sub-dielectric layer 121, the second sub-dielectric layer 122, and the third sub-dielectric layer 123, according to the continuity of the electric flux, two additional electric field peaks will be formed on the sidewalls of the trench 118, which can effectively increase the average field in the breakdown voltage region, weaken the electric field concentrated at the corners of the trench 118, and further improve the breakdown voltage of the device without increasing the on-resistance of the device.

[0054] In one embodiment, the second sub-dielectric layer 122 is an oxide dielectric layer. Exemplarily, the material of the second sub-dielectric layer 122 is silicon oxide. Thus, taking the dielectric constant of the oxide dielectric layer as a reference, the sub-dielectric layer with a dielectric constant larger than that of the oxide dielectric layer is a high-K dielectric layer, and the high-K dielectric layer is disposed at the bottom of the second sub-dielectric layer 122. The sub-dielectric layer with a dielectric constant smaller than that of the oxide dielectric layer is a low-K dielectric layer, and the low-K dielectric layer is disposed on top of the second sub-dielectric layer 122.

[0055] In one embodiment, as Figure 1 shown, when the variable-K dielectric layer 12 only includes the first sub-dielectric layer 121 and the second sub-dielectric layer 122, the material of the first sub-dielectric layer 121 can be silicon oxide, and the material of the second sub-dielectric layer 122 is a material with a dielectric constant greater than that of silicon oxide.

[0056] In one embodiment, the superjunction structure 13 is adjacent to the variable-K dielectric layer 12, that is: the superjunction structure 13 is adjacent to the trench 118. Thus, it is beneficial to reduce the electric field peak at the corners of the trench 118.

[0057] It should be noted that the superjunction structure 13 and the variable-K dielectric layer 12 may also not be adjacent, that is: the superjunction structure 13 and the trench 118 are spaced apart, and there is a small distance between them. Exemplarily, the distance between the superjunction structure 13 and the trench 118 is not greater than 0.5 μm.

[0058] In one embodiment, the superjunction structure 13 includes a first charge balance region 131 and a second charge balance region 132. The first charge balance region 131 is located between the second charge balance region 132 and the trench 118. The doping type of the first charge balance region 131 is opposite to the doping type of the first doping region 111, and the doping type of the second charge balance region 132 is the same as the doping type of the first doping region 111, that is: the first charge balance region 131 is of the first doping type, and the second charge balance region 132 is of the second doping type.

[0059] Thus, on the one hand, the first charge balance region 131 of the first doping type can reduce the electric field peak at the corners of the trench 118; on the other hand, it can also make the second charge balance region 132 of the second doping type closer to the bottom of the trench 118, which is beneficial to reducing the on-resistance.

[0060] It can be understood that, in another embodiment, the doping type of the first charge balance region 131 may be the same as that of the first doping region 111, and the doping type of the second charge balance region 132 may be different from that of the first doping region 111. The embodiments of the present application do not limit the doping types of the first charge balance region 131 and the second charge balance region 132.

[0061] It can be understood that the first charge balance region 131 and the second charge balance region 132 may be adjacent or spaced apart. If the first charge balance region 131 and the second charge balance region 132 are spaced apart, the distance therebetween may be less than or equal to 0.5 μm.

[0062] In one embodiment, referring to Figure 1 and Figure 2 As shown, a second doping region 114 is provided on at least a part of the outer periphery of the variable-K dielectric layer 12, that is: a second doping region 114 is provided on at least a part of the side outer periphery of the trench 118. Here, at least a part of the outer periphery of the variable-K dielectric layer 12 refers to at least a part of the side outer periphery of the variable-K dielectric layer 12. The doping type of the second doping region 114 is the same as that of the first doping region 111. In this way, a superjunction structure of the second doping region 114 - variable-K dielectric layer 12 is formed on the side wall of the trench 118. On the one hand, it is beneficial to weaken the electric field peak at the bottom corner of the trench 118, and the breakdown voltage can be improved. On the other hand, the on-resistance can be effectively reduced.

[0063] In one embodiment, the drain region 113 and the source region 112 are arranged at intervals along the first direction X, and the first direction X is perpendicular to the thickness direction of the substrate structure 11; second doping regions 114 are provided at both ends of the variable-K dielectric layer 12 along the first direction X, that is: second doping regions 114 are provided at both ends of the trench 118 along the first direction X.

[0064] In one embodiment, second doping regions 114 are provided on the entire circumferential outer periphery of the variable-K dielectric layer 12. In this way, not only can the electric field peak at the bottom corner of the trench 118 be effectively weakened, and the breakdown voltage can be improved, but also the on-resistance can be effectively reduced.

[0065] In one embodiment, the second doping region 114 is adjacent to the variable-K dielectric layer 12, that is: the second doping region 114 is adjacent to the trench 118. In this way, it is beneficial to form a superjunction structure of the second doping region 114 - variable-K dielectric layer 12, thereby being beneficial to weakening the electric field peak at the bottom corner of the trench 118.

[0066] It can be understood that there may also be a small spacing between the second doping region 114 and the variable-K dielectric layer 12. Exemplarily, the spacing between the second doping region 114 and the variable-K dielectric layer 12 is less than or equal to 0.5 μm. In this way, a superjunction structure can also be formed between the second doping region 114 and the variable-K dielectric layer 12 to optimize the electric field lines at the bottom corner of the trench 118.

[0067] In one embodiment, the variable-K dielectric layer 12 includes a high-K portion and a low-K portion, and the second doping region 114 is provided at least partially on the outer periphery of the high-K portion. In this way, on the one hand, a superjunction structure 13 of the second doping region 114 - high-K sub-dielectric layer is formed on the sidewall of the trench 118, which is beneficial to weakening the electric field peak at the bottom corner of the trench 118; on the other hand, it is beneficial to reducing the manufacturing difficulty and cost of the device.

[0068] It can be understood that in Figure 1 the device shown, the low-K portion is the first sub-dielectric layer 121, and the high-K portion is the second sub-dielectric layer 122. In Figure 2 the device shown, the low-K portion is the first sub-dielectric layer 121, and the high-K portion may only include the third sub-dielectric layer 123, or may include both the second sub-dielectric layer 122 and the third sub-dielectric layer 123.

[0069] It should be noted that the second doping region 114 may also extend to the outer periphery of the low-K portion side. In this way, it is beneficial to reducing the on-resistance of the device.

[0070] In one embodiment, in Figure 1 the device shown, the second doping regions 114 are provided at both ends of the second sub-dielectric layer 122 along the first direction X, and the height of the second doping region 114 is not less than the thickness of the second sub-dielectric layer 122. Here, the height of the second doping region 114 is the dimension of the second doping region 114 along the thickness direction of the substrate structure 11, and the thickness of the second sub-dielectric layer 122 is the dimension of the second sub-dielectric layer 122 along the thickness direction of the substrate structure 11. In this way, a superjunction structure 13 of the second doping region 114 - high-K sub-dielectric layer is formed on the sidewall of the trench 118, which is beneficial to weakening the electric field peak at the bottom corner of the trench 118.

[0071] In a preferred embodiment, the height of the second doping region 114 is equal to the thickness of the second sub-dielectric layer 122. It can be understood that when the height of the second doping region 114 is greater than the thickness of the second sub-dielectric layer 122, the depletion effect of the excess part is relatively limited. Therefore, by making the height of the second doping region 114 equal to the thickness of the second sub-dielectric layer 122, the height of the second doping region 114 can be made smaller while ensuring the effect, reducing the manufacturing difficulty and cost of the device.

[0072] In one embodiment, inFigure 2 In the device shown, second doping regions 114 are provided at both ends of the third sub-dielectric layer 123 along the first direction X, and the height of the second doping regions 114 is not less than the thickness of the third sub-dielectric layer 123. Here, the height of the second doping regions 114 is the dimension of the second doping regions 114 along the thickness direction of the substrate structure 11, and the thickness of the third sub-dielectric layer 123 is the dimension of the third sub-dielectric layer 123 along the thickness direction of the substrate structure 11. Thus, a superjunction structure 13 of the second doping regions 114 - high-K sub-dielectric layer is formed on the sidewalls of the trench 118, which is beneficial to weakening the electric field peak at the bottom corner of the trench 118.

[0073] In a preferred embodiment, the height of the second doping regions 114 is equal to the thickness of the third sub-dielectric layer 123. It can be understood that when the height of the second doping regions 114 is greater than the thickness of the third sub-dielectric layer 123, the depletion effect of the excess part is relatively limited. Therefore, by making the height of the second doping regions 114 equal to the thickness of the third sub-dielectric layer 123, the height of the second doping regions 114 can be made smaller while ensuring the effect, reducing the manufacturing difficulty and cost of the device.

[0074] In one of the embodiments, the side edges of the superjunction structure 13 protrude from the sidewalls of the variable-K dielectric layer 12, that is: the side edges of the superjunction structure 13 protrude from the sidewalls of the trench 118. Thus, on the one hand, it is convenient to fabricate the second doping regions 114 above the superjunction structure 13; on the other hand, the second doping regions 114 and the first charge balance region 131 can also form a superjunction structure, which is beneficial to improving the performance of the device.

[0075] In one of the embodiments, the edges of the superjunction structure 13 along the first direction X protrude from the sidewalls of the variable-K dielectric layer 12, that is: the edges of the superjunction structure 13 along the first direction X protrude from the sidewalls of the trench 118. Thus, on the one hand, it is convenient to fabricate the second doping regions 114 above the superjunction structure 13; on the other hand, the second doping regions 114 and the first charge balance region 131 can also form a superjunction structure, which is beneficial to improving the performance of the device.

[0076] In one of the embodiments, the second doping regions 114 are adjacent to the superjunction structure 13. Thus, it is beneficial to weakening the electric field peak at the bottom corner of the trench 118 without affecting the current path.

[0077] It can be understood that there may be a spacing between the second doping regions 114 and the superjunction structure 13. The embodiments of the present application do not limit the positional relationship between the second doping regions 114 and the superjunction structure 13.

[0078] In one of the embodiments, the lateral diffusion metal oxide semiconductor device 1 further includes a second well region 116, a body extraction region 117, and a gate 14.

[0079] Among them, the body extraction region 117 is of the first doping type, and the second well region 116 is of the second doping type. The first well region 115 and the second well region 116 are arranged at intervals in the first doping region 111. The body extraction region 117 is arranged in the first well region 115, and the drain region 113 is arranged in the second well region 116. The gate 14 is arranged on the surface of the substrate structure 11 and covers at least part of the first well region 115 and part of the first doping region 111.

[0080] In one embodiment, the gate 14 includes a gate conductive layer 142 and a gate dielectric layer 141. The gate dielectric layer 141 is arranged on the surface of the substrate structure 11, and the gate conductive layer 142 is arranged on the surface of the gate dielectric layer 141 away from the substrate structure 11.

[0081] In one embodiment, the first doping region 111 is an N-type drift region, the first well region 115 is a P well, and the second well region 116 is an N well.

[0082] In a second aspect, as shown in Figure 3 The embodiment of the present application provides a method for manufacturing a laterally diffused metal oxide semiconductor device, which specifically includes the following steps:

[0083] S100: Provide a substrate structure. Exemplarily, the substrate structure includes a substrate, a buried layer, and a top silicon layer arranged in a stacked manner.

[0084] S200: Form a first doping region in the substrate structure and form a first well region in the first doping region. Exemplarily, the first doping region can be formed in the top silicon layer by an ion implantation process. It can be understood that in this step, the second well region can be formed synchronously.

[0085] S300: Form a superjunction structure in the first doping region.

[0086] S400: Form a variable-K dielectric layer in the first doping region, and the superjunction structure is located on the side of the variable-K dielectric layer close to the back surface of the substrate structure. In the direction from the front surface of the substrate structure to the back surface of the substrate structure, the dielectric constant of the variable-K dielectric layer gradually increases.

[0087] S500: Form a drain region spaced from the first well region in the first doping region, and form a source region in the first well region, and the variable-K dielectric layer is located between the first well region and the drain region. It can be understood that in this step, the body extraction region can be formed synchronously.

[0088] The manufacturing method of the lateral diffused metal oxide semiconductor device provided by the embodiment of the present application sets a variable-K dielectric layer and a superjunction structure at the bottom of the variable-K dielectric layer in the first doping region. In this way, on the one hand, an electric field peak can be introduced on the sidewall of the variable-K dielectric layer, thereby raising the average field in the breakdown voltage region and weakening the electric field concentrated at the corner of the variable-K dielectric layer, that is, weakening the electric field concentrated at the trench corner, and then improving the device breakdown voltage without increasing the on-resistance of the device; on the other hand, using a low-K dielectric on the device surface can increase the breakdown voltage capacity of the device surface, and using a high-K dielectric in the device body can assist in depleting the charges in the device body; on the other hand, by introducing a superjunction structure, the superjunction structure and the drift region deplete each other in the off state to achieve the purpose of optimizing the electric field and increasing the doping concentration of the drift region, thereby reducing the on-resistance in the on state.

[0089] It should be noted that since ion implantation will damage the substrate structure, greatly reducing the mobility and lifetime of electron-hole pairs. In addition, most of the implanted ions do not occupy lattice positions in the substitutional form. In order to activate the ions and restore the original mobility, the substrate structure must be annealed at an appropriate temperature. Annealing can repair lattice defects and also move impurity atoms to lattice sites to activate the impurities. Generally, about 450-550 °C is required to repair lattice defects, and 900-1000 °C is required to activate the impurities. The activation of impurities is related to time and temperature. The longer the time and the higher the temperature, the more fully the impurities are activated. Commonly used annealing methods for the substrate structure are high-temperature thermal annealing and rapid thermal annealing (RTA). Exemplarily, a high-temperature thermal annealing process can be used for annealing treatment. Specifically, the silicon wafer is heated to 800-1000 °C in a high-temperature furnace and held for 20-40 min. It can be understood that a rapid thermal annealing process can also be used for annealing treatment. Compared with the high-temperature thermal annealing process, the rapid thermal annealing process has a shorter annealing time, which can avoid the diffusion of doping ions caused by long-term high temperature and reduce the transient enhanced diffusion of doping ions.

[0090] In one of the embodiments, S300 specifically includes the following steps:

[0091] S310: Form a mask layer on the front surface of the substrate structure.

[0092] S320: Pattern the mask layer to obtain a patterned mask layer. The patterned mask layer has an opening that exposes the substrate structure and defines the shape and position of the trench.

[0093] S330: Etch the substrate structure based on the patterned mask layer to form a trench in the substrate structure.

[0094] S340: Remove the patterned mask layer.

[0095] S350: Form a superjunction structure in the first doping region at the bottom of the trench. Exemplarily, high-energy implantation forms a first charge balance region and a second charge balance region. It should be noted that in S350, a second doping region can also be fabricated synchronously. Exemplarily, after the first charge balance region and the second charge balance region are formed, the second doping region is formed by an ion implantation process.

[0096] In one embodiment, S400 specifically includes the following steps:

[0097] S420: Form a second sub-dielectric layer in the trench.

[0098] S430: Form a first sub-dielectric layer on the second sub-dielectric layer. Among them, the dielectric constant of the first sub-dielectric layer is less than that of the second sub-dielectric layer.

[0099] In one embodiment, before S420, the following steps are included:

[0100] S410: Form a third sub-dielectric layer in the trench. Among them, the dielectric constant of the third sub-dielectric layer is greater than that of the second sub-dielectric layer.

[0101] In one embodiment, before S500, the following steps are further included:

[0102] S440: Form a gate on the substrate structure.

[0103] It should be understood that in the embodiments of the present application, although the steps in the flowchart of the drawings are sequentially shown according to the indication of the arrows, these steps do not necessarily need to be executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, at least a part of the steps in the drawings may include multiple steps or multiple stages. These steps or stages do not necessarily need to be executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps in other steps.

[0104] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0105] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0106] The above-described embodiments only express several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A lateral diffused metal oxide semiconductor device, characterized in that Comprising: A substrate structure; A first doped region disposed within the substrate structure; A first well region and a drain region spaced apart within the first doped region; A source region disposed within the first well region; A variable-K dielectric layer embedded within the first doped region and located between the first well region and the drain region, and the dielectric constant of the variable-K dielectric layer gradually increases in the direction from the front surface to the back surface of the substrate structure; A superjunction structure disposed within the first doped region on the side of the variable-K dielectric layer close to the back surface of the substrate structure.

2. The lateral diffusion metal oxide semiconductor device according to claim 1, characterized in that, The variable-K dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, and the dielectric constant of the first sub-dielectric layer is less than that of the second sub-dielectric layer; The first sub-dielectric layer is located on the side of the second sub-dielectric layer close to the front surface of the substrate structure.

3. The lateral diffusion metal oxide semiconductor device according to claim 2, wherein The variable-K dielectric layer further includes a third sub-dielectric layer, and the dielectric constant of the third sub-dielectric layer is greater than that of the second sub-dielectric layer; the third sub-dielectric layer is located on the side of the second sub-dielectric layer close to the back surface of the substrate structure.

4. The lateral diffusion metal oxide semiconductor device according to claim 1, wherein The superjunction structure is adjacent to the variable-K dielectric layer.

5. The lateral diffused metal oxide semiconductor device according to claim 4, wherein The superjunction structure includes a first charge balance region and a second charge balance region, and the first charge balance region is located between the second charge balance region and the variable-K dielectric layer; The doping type of the first charge balance region is opposite to that of the first doped region, and the doping type of the second charge balance region is the same as that of the first doped region.

6. The lateral diffusion metal oxide semiconductor device according to any one of claims 1-5, characterized in that, At least a part of the outer periphery of the variable-K dielectric layer is provided with a second doped region, and the doping type of the second doped region is the same as that of the first doped region.

7. The lateral diffused metal oxide semiconductor device according to claim 6, wherein The second doped region is adjacent to the variable-K dielectric layer.

8. The lateral diffusion metal oxide semiconductor device according to claim 6, wherein The variable-K dielectric layer includes a high-K part and a low-K part, and at least a part of the outer periphery of the high-K part is provided with the second doped region.

9. The lateral diffused metal oxide semiconductor device according to claim 6, wherein The side edge of the superjunction structure protrudes from the side wall of the variable-K dielectric layer.

10. The lateral diffusion metal oxide semiconductor device according to claim 9, characterized in that, The second doped region is adjacent to the superjunction structure.

11. A method for fabricating a lateral diffused metal oxide semiconductor device, characterized in that, Comprising: Providing a substrate structure; Forming a first doped region within the substrate structure and forming a first well region within the first doped region; Forming a superjunction structure within the first doped region; Forming a variable-K dielectric layer within the first doped region, and the superjunction structure is located on the side of the variable-K dielectric layer close to the back surface of the substrate structure, and the dielectric constant of the variable-K dielectric layer gradually increases in the direction from the front surface to the back surface of the substrate structure; Forming a drain region spaced apart from the first well region within the first doped region and forming a source region within the first well region, and the variable-K dielectric layer is located between the first well region and the drain region.

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