Laterally diffused metal oxide semiconductor device and preparation method thereof

Abstract

The invention relates to a laterally diffused metal oxide semiconductor device and a preparation method thereof. The laterally diffused metal oxide semiconductor device comprises a substrate structure, a first well region is arranged in the substrate structure, a second well region and a drain region which are arranged at an interval are arranged in the first well region, and a source region is arranged in the second well region; the first doped region is arranged in the first well region and is positioned between the second well region and the drain region; the at least one second doped region is arranged in the first well region and located between the second well region and the drain region, and the second doped region is further located on the side, close to the back face of the substrate structure, of the first doped region; the third doped region is arranged in the first well region and located between the second well region and the drain region, and the third doped region is further located on the side, close to the back face of the substrate structure, of the second doped region; and the at least one internal field plate is arranged in the first well region and located between the second well region and the drain region, and the internal field plate is at least embedded in the first doped region. According to the invention, the contradictory relation between the breakdown voltage and the on-resistance can be effectively optimized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a lateral diffused metal oxide semiconductor device and a method for manufacturing the same. Background Art

[0002] With the continuous development of semiconductor technology, the application of lateral double-diffused MOS (LDMOS) devices has become increasingly widespread, and at the same time, higher requirements have been put forward for the performance of lateral diffused metal oxide semiconductor devices. However, for lateral diffused metal oxide semiconductor devices, there is inevitably a technical contradiction between reducing the on-resistance and ensuring a higher breakdown voltage, making it difficult to further improve the device performance. Summary of the Invention

[0003] Based on this, it is necessary to provide a lateral diffused metal oxide semiconductor device and a method for manufacturing the same in view of the above problems.

[0004] In a first aspect, this application provides a lateral diffused metal oxide semiconductor device, including:

[0005] A substrate structure, in which a first well region is provided. A second well region and a drain region are arranged at intervals in the first well region, and a source region is provided in the second well region;

[0006] A first doping region, which is provided in the first well region and is located between the second well region and the drain region;

[0007] At least one second doping region, which is provided in the first well region and is located between the second well region and the drain region, and the second doping region is located on a side of the first doping region close to the back surface of the substrate structure;

[0008] A third doping region, which is provided in the first well region and is located between the second well region and the drain region, and the third doping region is located on a side of the second doping region close to the back surface of the substrate structure;

[0009] At least one in-body field plate, which is provided in the first well region and is located between the second well region and the drain region, and the in-body field plate is at least embedded in the first doping region;

[0010] Wherein, the second well region, the first doping region, and the third doping region are of a first doping type, and the first well region, the source region, the drain region, and the second doping region are of a second doping type.

[0011] In one embodiment, one second doping region is provided between the first doping region and the third doping region;

[0012] The second doped region is spaced apart from the first doped region and from the third doped region.

[0013] In one embodiment, a plurality of the second doped regions are provided between the first doped region and the third doped region; the plurality of the second doped regions are arranged at intervals along the thickness direction of the substrate structure.

[0014] In one embodiment, in the direction from the first doped region to the third doped region, the doping concentration of each of the second doped regions gradually decreases.

[0015] In one embodiment, two of the second doped regions are provided between the first doped region and the third doped region, wherein one of the second doped regions is adjacent to the first doped region and the other second doped region is adjacent to the third doped region.

[0016] In one embodiment, the in - body field plate extends along the thickness direction of the substrate structure and is further embedded in the second doped region and the third doped region.

[0017] In one embodiment, the in - body field plate includes a first part and a second part, the first part is embedded in the first doped region, and the second part is at least embedded in the second doped region;

[0018] The outer diameter of the second part is smaller than the outer diameter of the first part.

[0019] In one embodiment, the in - body field plate further includes a third part, and the third part is embedded in the third doped region;

[0020] The outer diameter of the second part is smaller than the outer diameter of the third part.

[0021] In one embodiment, the laterally diffused metal - oxide - semiconductor device includes a first buried layer, the first buried layer is disposed in the substrate structure at the bottom of the first well region, and at least a part of the positive projection of the second well region on the substrate structure coincides with the positive projection of the first buried layer on the substrate structure;

[0022] The first buried layer is of a first doping type.

[0023] In one embodiment, the laterally diffused metal - oxide - semiconductor device includes a second buried layer, the second buried layer is disposed in the substrate structure at the bottom of the first well region; at least a part of the positive projection of the drain region on the substrate structure coincides with the positive projection of the second buried layer on the substrate structure;

[0024] The second buried layer is of a second doping type.

[0025] In a second aspect, the present application also provides a method for manufacturing a laterally diffused metal oxide semiconductor device, including:

[0026] Providing a substrate structure;

[0027] Forming a first well region of a second doping type within the substrate structure;

[0028] Forming at least one in-body field plate within the first well region, and forming a second well region within the first well region;

[0029] Forming a first doping region, at least one second doping region, and a third doping region within the first well region; wherein, the second doping region is located on a side of the first doping region close to the back surface of the substrate structure, the third doping region is located on a side of the second doping region close to the back surface of the substrate structure, and the in-body field plate is at least embedded in the first doping region; the first doping region and the third doping region are of a first doping type, and the second doping region is of a second doping type;

[0030] Forming a drain region within the first well region, and forming a source region within the second well region; wherein, the second well region and the drain region are arranged at intervals, and the first doping region, the second doping region, and the in-body field plate are all located between the second well region and the drain region; the second well region is of a first doping type, and the source region and the drain region are of a second doping type.

[0031] For the laterally diffused metal oxide semiconductor device and the method for manufacturing the same provided by the present application, by providing at least one second doping region within the first well region, it helps to reduce the on-resistance of the device. By respectively providing a first doping region and a third doping region at the top and bottom of the second doping region, the doping concentration of the second doping region can be increased, thereby helping to further reduce the on-resistance of the device. By making the in-body field plate at least embedded in the first doping region, since the in-body field plate will assist in depleting the first doping region, during the process of manufacturing the first doping region and the second doping region, the dose of the first doping region can be appropriately greater than that of the second doping region to overcome the problem that the device is too sensitive to the charge balance between the first doping region and the second doping region, thereby improving the problem that the breakdown voltage is affected by charge imbalance when using the first doping region, the second doping region, and the third doping region to reduce the on-resistance, and further effectively optimizing the contradictory relationship between the breakdown voltage and the on-resistance. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments or exemplary embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0033] Figure 1 This is a schematic diagram of a partial structure of a laterally diffused metal oxide semiconductor device provided by an embodiment of the present application.

[0034] Figure 2 This is a schematic diagram of a partial structure of another laterally diffused metal oxide semiconductor device provided by an embodiment of the present application.

[0035] Figure 3 This is a schematic diagram of a partial structure of yet another laterally diffused metal oxide semiconductor device provided by an embodiment of the present application.

[0036] Figure 4 This is a schematic diagram of the arrangement of the in-body field plate of a laterally diffused metal oxide semiconductor device provided by an embodiment of the present application from a top-down perspective.

[0037] Figure 5 This is a schematic flow diagram of a method for manufacturing a laterally diffused metal oxide semiconductor device provided by an embodiment of the present application.

[0038] Explanation of reference numerals:

[0039] 1. Laterally diffused metal oxide semiconductor device; 11. Substrate structure; 11a. Substrate; 11b. Epitaxial layer; 1101. First well region; 1102. Source region; 1103. Drain region; 1104. First doped region; 1105. Second doped region; 1106. Third doped region; 1107. First buried layer; 1108. Second buried layer; 1109. Second well region; 1110. Third well region; 1111. Body extraction region; 12. In-body field plate; 12a. First part; 12b. Second part; 12c. Third part; 121. First dielectric layer; 122. First conductive layer; 13. Gate; 14. Second dielectric layer; 15. First electrical connection structure. Detailed implementation manners

[0040] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0042] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0043] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0044] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have", etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0045] The embodiments of the present application are described with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0046] In a first aspect, with reference to Figure 1 as shown, an embodiment of the present application provides a laterally diffused metal oxide semiconductor device 1. Taking the N-type laterally diffused metal oxide semiconductor device 1 as an example, the first doping type is P-type and the second doping type is N-type. In other embodiments, the laterally diffused metal oxide semiconductor device 1 can also be a P-type laterally diffused metal oxide semiconductor device 1, with the first doping type being N-type and the second doping type being P-type.

[0047] Specifically, the laterally diffused metal oxide semiconductor device 1 includes a substrate structure 11, a first doping region 1104, at least one second doping region 1105, a third doping region 1106, and at least one in-body field plate 12. A first well region 1101 is provided in the substrate structure 11. A second well region 1109 and a drain region 1103 are provided in the first well region 1101 and are arranged at intervals. A source region 1102 is provided in the second well region 1109; the first doping region 1104 is provided in the first well region 1101 and is located between the second well region 1109 and the drain region 1103; the second doping region 1105 is provided in the first well region 1101 and is located between the second well region 1109 and the drain region 1103; the second doping region 1105 is also located on the side of the first doping region 1104 closer to the back surface of the substrate structure 11; the third doping region 1106 is provided in the first well region 1101 and is located between the second well region 1109 and the drain region 1103; the third doping region 1106 is also located on the side of the second doping region 1105 closer to the back surface of the substrate structure 11; the in-body field plate 12 is provided in the first well region 1101 and is located between the second well region 1109 and the drain region 1103; the in-body field plate 12 is at least embedded in the first doping region 1104;

[0048] Among them, the second well region 1109, the first doping region 1104, and the third doping region 1106 are of the first doping type, and the first well region 1101, the source region 1102, the drain region 1103, and the second doping region 1105 are of the second doping type.

[0049] Here, as Figure 1 shown, the top surface of the substrate structure 11 is the front surface of the substrate structure 11, and the bottom surface of the substrate structure 11 is the back surface of the substrate structure 11.

[0050] In one embodiment, the substrate structure 11 may include a substrate 11a and an epitaxial layer 11b disposed on the substrate 11a, and both the substrate 11a and the epitaxial layer 11b are of the first doping type. Exemplarily, the material of the substrate 11a may be single-crystalline silicon, polycrystalline silicon, amorphous silicon, germanium-silicon compound, Silicon-On-Insulator (SOI), or Low-Temperature Poly-Silicon (LTPS), etc., or other materials known to those skilled in the art.

[0051] In one embodiment, the body field plate 12 is a longitudinal floating field plate. Here, longitudinal refers to the thickness direction of the substrate structure 11.

[0052] The lateral diffused metal oxide semiconductor device 1 provided by the embodiments of the present application, by disposing at least one second doping region 1105 in the first well region 1101, helps to reduce the on-resistance of the device. By respectively disposing the first doping region 1104 and the third doping region 1106 at the top and bottom of the second doping region 1105, the doping concentration of the second doping region 1105 can be increased, thereby helping to further reduce the on-resistance of the device. By embedding the body field plate 12 at least in the first doping region 1104, since the body field plate 12 will assist in depleting the first doping region 1104, during the process of fabricating the first doping region 1104 and the second doping region 1105, the dose of the first doping region 1104 can be appropriately greater than that of the second doping region 1105 to overcome the problem that the device is too sensitive to the charge balance between the first doping region 1104 and the second doping region 1105, thereby improving the problem that the breakdown voltage is affected by charge imbalance when using the first doping region 1104, the second doping region 1105, and the third doping region 1106 to reduce the on-resistance, and further effectively optimizing the contradictory relationship between the breakdown voltage and the on-resistance.

[0053] In one of the embodiments, the first doping region 1104 extends from the surface of the first well region 1101 towards the inside of the first well region 1101.

[0054] In one embodiment, a second doping region 1105 is provided between the first doping region 1104 and the third doping region 1106; the second doping region 1105 is spaced apart from the first doping region 1104 and is also spaced apart from the third doping region 1106.

[0055] In this way, the first doping region 1104 and the first well region 1101 form a superjunction structure, and the third doping region 1106 and the first well region 1101 form a superjunction structure. This can make the conduction path of the device wider, avoid current concentration on the surface of the substrate structure 11, make the device less likely to burn out, and thus is beneficial to improving the HTRB (High Temperature Reverse Bias Test) reliability of the device.

[0056] In one embodiment, a plurality of second doping regions 1105 are provided between the first doping region 1104 and the third doping region 1106; the plurality of second doping regions 1105 are arranged at intervals along the thickness direction of the substrate structure 11. In this way, the doping concentration of each second doping region 1105 can be made lower, which is beneficial to reducing the manufacturing difficulty.

[0057] It should be noted that when the number of the second doping regions 1105 is one, the doping concentration of the second doping region 1105 is relatively high, and when the number of the second doping regions 1105 is multiple, the doping concentration of each second doping region 1105 is relatively low, that is: the doping concentration of the second doping region 1105 when the second doping region 1105 is one is greater than the doping concentration of the second doping region 1105 when the second doping region 1105 is multiple.

[0058] In one embodiment, in the direction from the first doping region 1104 to the third doping region 1106, the doping concentration of each second doping region 1105 gradually decreases. In this way, it is equivalent to making the doping concentration of all the second doping regions 1105 gradually decrease from top to bottom. Exemplarily, it is assumed that there are three second doping regions 1105 between the first doping region 1104 and the third doping region 1106. Among them, the doping concentration of the second doping region 1105 located at the top is the largest, the doping concentration of the second doping region 1105 located in the middle is the second largest, and the doping concentration of the second doping region 1105 located at the bottom is the smallest.

[0059] In this way, it is not only beneficial to reducing the manufacturing difficulty of the second doping region 1105, but also can make the effect of reducing the on-resistance better.

[0060] In one embodiment, there are two second doping regions 1105 between the first doping region 1104 and the third doping region 1106. Among them, one second doping region 1105 is adjacent to the first doping region 1104, and the other second doping region 1105 is adjacent to the third doping region 1106.

[0061] Thus, the first doping region 1104 and the second doping region 1105 adjacent to itself form a superjunction structure, and the third doping region 1106 and the second doping region 1105 adjacent to itself form a superjunction structure. In this way, within the device body, the effect of double depletion of the in-body field plate 12 and the superjunction structure can be formed, so that the doping concentrations of the first doping region 1104 and the third doping region 1106 can be further increased, which is conducive to reducing the on-resistance of the device.

[0062] It can be understood that the second doping region 1105 adjacent to the first doping region 1104 can also be spaced apart from the first doping region 1104. The second doping region 1105 adjacent to the third doping region 1106 can also be spaced apart from the third doping region 1106.

[0063] In one embodiment, the in-body field plate 12 extends along the thickness direction of the substrate structure 11 and is also embedded in the second doping region 1105 and the third doping region 1106. In this way, the depletion effect of the in-body field plate 12 can be stronger, which is conducive to improving the performance of the device.

[0064] In one embodiment, referring to Figure 3 As shown, the in-body field plate 12 includes a first part 12a and a second part 12b. The first part 12a is embedded in the first doping region 1104, and the second part 12b is at least embedded in the second doping region 1105; the outer diameter of the second part 12b is smaller than the outer diameter of the first part 12a. It should be noted that the outer diameter of the first part 12a can be the dimension of the first part 12a along the first direction X, and the outer diameter of the second part 12b can be the dimension of the second part 12b along the first direction X. Further, the outer diameter of the first part 12a can also be understood as the width of the first part 12a, and the outer diameter of the second part 12b can also be understood as the width of the second part 12b.

[0065] Further, referring to Figure 3 As shown, the distance between the first parts 12a of two adjacent in-body field plates 12 along the first direction X is a first distance, and the distance between the second parts 12b of two adjacent in-body field plates 12 along the first direction X is a second distance, and the first distance is smaller than the second distance. In this way, it is equivalent to arranging a relatively dense field plate structure in the first doping region 1104 that needs to be assisted in depletion, so that the depletion effect of the in-body field plate 12 on the first doping region 1104 is stronger; it is equivalent to adopting a relatively narrow and wide-spacing field plate structure in the conductive region (the second doping region 1105), making the conduction path of the device wider, which is conducive to reducing the on-resistance of the device.

[0066] Here, it should also be noted that the outer diameter of the first part 12a in the first doped region 1104 is greater than the outer diameter of the second part 12b in the second doped region 1105. Since the depletion effect of the first part 12a on the first doped region 1104 is stronger, during the fabrication process of the first doped region 1104 and the second doped region 1105, the dose of the first doped region 1104 can be appropriately greater than that of the second doped region 1105, thereby overcoming the problem that the device is overly sensitive to the charge balance between the first doped region 1104 and the second doped region 1105, and further improving the problem that the charge imbalance in the device body affects the breakdown voltage when reducing the on-resistance.

[0067] It can be understood that the second part 12b is also embedded in the first well region 1101 between the first doped region 1104 and the second doped region 1105.

[0068] In one embodiment, the body field plate 12 further includes a third part 12c, and the third part 12c is embedded in the third doped region 1106; the outer diameter of the second part 12b is smaller than the outer diameter of the third part 12c. It should be noted that the outer diameter of the third part 12c can be the dimension of the third part 12c along the first direction X. Further, the outer diameter of the third part 12c can also be understood as the width of the third part 12c. It can be understood that the second part 12b is also embedded in the first well region 1101 between the second doped region 1105 and the third doped region 1106.

[0069] In this way, strong depletion is adopted in the first doped region 1104 and the third doped region 1106. In the second doped region 1105, the field plate structure can be avoided from occupying a wide path. The second doped region 1105 is surrounded by the first doped region 1104 and the third doped region 1106 above and below respectively, and the left and right directions of the second doped region 1105 are depleted by the body field plate 12, thereby forming a superjunction structure and a three-dimensional double depletion structure of the body field plate 12, which is beneficial to improving the performance of the device.

[0070] In one embodiment, referring to Figures 1-3 As shown, the lateral diffused metal oxide semiconductor device 1 includes a first buried layer 1107. The first buried layer 1107 is disposed in the substrate structure 11 at the bottom of the first well region 1101. At least a part of the positive projection of the second well region 1109 on the substrate structure 11 coincides with the positive projection of the first buried layer 1107 on the substrate structure 11. The first buried layer 1107 is of the first doping type. Exemplarily, as Figure 1 shown, the first buried layer 1107 is disposed below the second well region 1109.

[0071] By providing the first buried layer 1107, the first well region 1101 can be assisted in depletion, thereby improving the performance of the device.

[0072] In one embodiment, referring to Figures 1-3 As shown, the laterally diffused metal oxide semiconductor device 1 includes a second buried layer 1108 disposed in a substrate structure 11 at the bottom of a first well region 1101 and spaced apart from a first buried layer 1107; the positive projection of a drain region 1103 on the substrate structure 11 coincides with at least a part of the positive projection of the second buried layer 1108 on the substrate structure 11. The second buried layer 1108 is of a second doping type. Exemplarily, as Figure 1 shown, the second buried layer 1108 is disposed below the drain region 1103.

[0073] By providing the second buried layer 1108, the breakdown voltage of the device can be improved.

[0074] In one embodiment, the laterally diffused metal oxide semiconductor device 1 includes a plurality of in-body field plates 12, and the plurality of in-body field plates 12 are arranged at intervals within the first well region 1101. In this way, the depletion effect of the in-body field plates 12 can be stronger, which is beneficial to improving the performance of the device.

[0075] In one embodiment, referring to Figure 4 As shown, the in-body field plates 12 in the laterally diffused metal oxide semiconductor device 1 can be arranged in the arrangement schematic shown in the figure. Among them, all the in-body field plates 12 can be arranged in multiple columns along a first direction X, and the multiple columns of in-body field plates 12 are arranged at intervals in a second direction Y in sequence, and the in-body field plates 12 in odd columns and the in-body field plates 12 in even columns are arranged in a staggered manner in the second direction Y.

[0076] It can be understood that the in-body field plates 12 can also be arranged in other arrangement forms, and the embodiments of the present application do not limit this.

[0077] In one embodiment, referring to Figures 1-3 As shown, the in-body field plate 12 includes a first conductive layer 122 and a first dielectric layer 121, and the first dielectric layer 121 is disposed on the side surface and the bottom surface of the first conductive layer 122. Exemplarily, the material of the first conductive layer 122 is polysilicon, and the material of the first dielectric layer 121 is silicon oxide.

[0078] In one embodiment, referring to Figures 1-3 As shown, the laterally diffused metal oxide semiconductor device 1 further includes a third well region 1110, a body extraction region 1111, a gate 13, a second dielectric layer 14, and a first electrical connection structure 15.

[0079] Among them, the body lead-out region 1111 is disposed within the second well region 1109. The third well region 1110 is of a second doping type, and the third well region 1110 is disposed within the first well region 1101. The drain region 1103 is disposed within the third well region 1110. The second buried layer 1108 is disposed within the substrate structure 11 below the third well region 1110. The gate 13 is disposed on the surface of the substrate structure 11 and covers at least a part of the second well region 1109, a part of the first well region 1101, and a part of the source region 1102. The second dielectric layer 14 is disposed on the surface of the substrate structure 11, and the first electrical connection structure 15 passes through the second dielectric layer 14 and is electrically connected to the body field plate 12. Exemplarily, the second dielectric layer 14 may be a field oxide layer.

[0080] In one embodiment, the gate 13 includes a gate conductive layer (not labeled in the figure) and a gate dielectric layer (not labeled in the figure). The gate dielectric layer is disposed on the front surface of the substrate structure 11, and the gate conductive layer is disposed on a surface of the gate dielectric layer away from the substrate structure 11.

[0081] In one embodiment, the first well region 1101 is a deep N well, the second well region 1109 is a P well, the third well region 1110 is an N well, the first buried layer 1107 is a P-type buried layer, and the second buried layer 1108 is an N-type buried layer.

[0082] Second, referring to Figure 5 As shown, an embodiment of the present application further provides a method for manufacturing a laterally diffused metal oxide semiconductor device, which specifically includes the following steps:

[0083] S100: Provide a substrate structure. Exemplarily, the substrate structure may include a substrate and an epitaxial layer disposed on the substrate, and both the substrate and the epitaxial layer are of a first doping type.

[0084] S200: Form a first well region of a second doping type within the substrate structure. Exemplarily, the first well region may be formed within the substrate structure by an ion implantation process.

[0085] S300: Form at least one body field plate within the first well region, and form a second well region of a first doping type within the first well region. It should be noted that the body field plate is disposed within a trench, and before forming the body field plate, a trench needs to be etched on the substrate structure.

[0086] S400: Form a first doped region, at least one second doped region, and a third doped region in the first well region. Among them, the second doped region is located on the side of the first doped region closer to the back surface of the substrate structure, the third doped region is located on the side of the second doped region closer to the back surface of the substrate structure, and the body field plate is at least embedded in the first doped region; the first doped region and the third doped region are of the first doping type, and the second doped region is of the second doping type. Exemplarily, the first doped region, the second doped region, and the third doped region can be formed in the first well region by an ion implantation process.

[0087] S500: Form a drain region in the first well region and form a source region in the second well region; among them, the second well region and the drain region are arranged at intervals; the first doped region, the second doped region, and the body field plate are all located between the second well region and the drain region; the source region and the drain region are of the second doping type. Exemplarily, the second well region, the source region, and the drain region can be formed by an ion implantation process. It can be understood that in this step, the body lead region can be formed synchronously.

[0088] In the manufacturing method of the lateral diffusion metal oxide semiconductor device provided by this application, by setting at least one second doped region in the first well region, it helps to reduce the on-resistance of the device. By setting the first doped region and the third doped region at the top and bottom of the second doped region respectively, the doping concentration of the second doped region can be increased, which thus helps to further reduce the on-resistance of the device. By making the body field plate at least embedded in the first doped region, since the body field plate will assist in depleting the first doped region, during the process of manufacturing the first doped region and the second doped region, the dose of the first doped region can be appropriately larger than that of the second doped region to overcome the problem that the device is too sensitive to the charge balance between the first doped region and the second doped region, thereby improving the problem that the breakdown voltage is affected by charge imbalance when using the first doped region, the second doped region, and the third doped region to reduce the on-resistance, and further effectively optimizing the contradictory relationship between the breakdown voltage and the on-resistance.

[0089] In one embodiment, S100 is specifically the following steps:

[0090] S110: Provide a substrate.

[0091] S120: Form a first buried layer and a second buried layer on the substrate and perform heat treatment on the substrate.

[0092] S130: Form an epitaxial layer on the substrate, and the epitaxial layer and the substrate together form a substrate structure.

[0093] In one embodiment, S300 specifically includes the following steps:

[0094] S310: Etch the substrate structure to form a trench.

[0095] S320: Form a first dielectric layer on the sidewall of the trench.

[0096] S330: Form a first conductive layer on the first dielectric layer to form a body field plate.

[0097] S340: Form a second well region within the first well region. It can be understood that in this step, a third well region can be formed synchronously.

[0098] In one embodiment, after S400 and before S500, the following steps are further included:

[0099] S450: Form a second dielectric layer on the substrate structure.

[0100] S460: Form a gate on the substrate structure.

[0101] In one embodiment, after S500, the following steps are further included:

[0102] S600: Form a first electrical connection structure, a second electrical connection structure, a third electrical connection structure, and a fourth electrical connection structure on the substrate structure. The first electrical connection structure is electrically connected to the body field plate, the second electrical connection structure is electrically connected to the gate, the third electrical connection structure is electrically connected to the drain region, and the fourth electrical connection structure is electrically connected to the source region and the body lead-out region.

[0103] It should be understood that in the embodiments of the present application, although the steps in the flowchart of the accompanying drawings are sequentially shown according to the indication of the arrows, these steps do not necessarily need to be executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, at least a part of the steps in the accompanying drawings may include multiple steps or multiple stages. These steps or stages do not necessarily need to be executed at the same moment, but can be executed at different moments. The execution order of these steps or stages does not necessarily need to be sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0104] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or features described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0105] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0106] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patented application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A lateral diffused metal oxide semiconductor device, characterized in that, Comprising: A substrate structure, within which a first well region is provided. In the first well region, a second well region and a drain region are arranged at intervals, and a source region is provided within the second well region; A first doping region, provided within the first well region and located between the second well region and the drain region; At least one second doping region, provided within the first well region and located between the second well region and the drain region, and the second doping region is located on the side of the first doping region closer to the back surface of the substrate structure; A third doping region, provided within the first well region and located between the second well region and the drain region, and the third doping region is located on the side of the second doping region closer to the back surface of the substrate structure; At least one in-body field plate, provided within the first well region and located between the second well region and the drain region, and the in-body field plate is at least embedded in the first doping region; Wherein, the second well region, the first doping region and the third doping region are of a first doping type, and the first well region, the source region, the drain region and the second doping region are of a second doping type.

2. The lateral diffusion metal oxide semiconductor device according to claim 1, wherein One second doping region is provided between the first doping region and the third doping region; The second doping region is spaced from the first doping region and spaced from the third doping region.

3. The lateral diffusion metal oxide semiconductor device according to claim 1, wherein, A plurality of the second doping regions are provided between the first doping region and the third doping region; the plurality of second doping regions are arranged at intervals along the thickness direction of the substrate structure.

4. The lateral diffused metal oxide semiconductor device according to claim 1, wherein In the direction from the first doping region to the third doping region, the doping concentration of each of the second doping regions gradually decreases.

5. The lateral diffused metal oxide semiconductor device according to claim 3, wherein Two second doping regions are provided between the first doping region and the third doping region. Among them, one second doping region is adjacent to the first doping region, and the other second doping region is adjacent to the third doping region.

6. The lateral diffusion metal oxide semiconductor device according to claim 1, wherein The in-body field plate extends along the thickness direction of the substrate structure and is also embedded in the second doping region and the third doping region.

7. The lateral diffusion metal oxide semiconductor device according to claim 6, characterized in that, The in-body field plate includes a first part and a second part. The first part is embedded in the first doping region, and the second part is at least embedded in the second doping region; The outer diameter of the second part is smaller than the outer diameter of the first part.

8. The lateral diffused metal oxide semiconductor device according to claim 7, wherein, The in-body field plate further includes a third part, and the third part is embedded in the third doping region; The outer diameter of the second part is smaller than the outer diameter of the third part.

9. The lateral diffusion metal oxide semiconductor device according to any one of claims 1-8, characterized in that, The lateral diffused metal oxide semiconductor device includes a first buried layer, and the first buried layer is provided in the substrate structure at the bottom of the first well region. At least a part of the positive projection of the second well region on the substrate structure coincides with the positive projection of the first buried layer on the substrate structure; The first buried layer is of a first doping type.

10. The lateral diffusion metal oxide semiconductor device according to any one of claims 1-8, characterized in that, The lateral diffused metal oxide semiconductor device includes a second buried layer, and the second buried layer is provided in the substrate structure at the bottom of the first well region; at least a part of the positive projection of the drain region on the substrate structure coincides with the positive projection of the second buried layer on the substrate structure; The second buried layer is of a second doping type.

11. A method for manufacturing a lateral diffused metal oxide semiconductor device, characterized in that, Comprising: Providing a substrate structure; Forming a first well region of a second doping type within the substrate structure; At least one in - body field plate is formed in the first well region, and a second well region of a first doping type is formed in the first well region; A first doped region, at least one second doped region, and a third doped region are formed in the first well region; wherein, the second doped region is located on a side of the first doped region close to the back surface of the substrate structure, the third doped region is located on a side of the second doped region close to the back surface of the substrate structure, and the in - body field plate is at least embedded in the first doped region; the first doped region and the third doped region are of the first doping type, and the second doped region is of the second doping type; A drain region is formed in the first well region, and a source region is formed in the second well region; wherein, the second well region and the drain region are arranged at intervals, and the first doped region, the second doped region, and the in - body field plate are all located between the second well region and the drain region; the source region and the drain region are of the second doping type.

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