LDMOS edge termination for improved safe operating area

Abstract

The invention relates to an LDMOS edge termination for improved safe operating area. An electronic device (100) includes a semiconductor layer (104) having majority carriers of a first dopant type (P), a transistor finger structure (F) extending along a first direction (X) and including drain fingers (D) and source fingers (S), and a well region (DWELL) (110) including majority carrier dopants of the first type (P) in the semiconductor layer (104), the source finger (S) has majority carriers of a second type (N) and is laterally spaced apart from opposite sides of the drain finger (D) along a second direction (Y), the source finger (S) extends in respective portions of the well region (110), and the well region (110) extends laterally around and surrounds the finger structure (F).

Description

Technical Field

[0001] This application generally relates to semiconductors, and more particularly to an LDMOS edge termination for improving the safe operating area. Background Art

[0002] A laterally diffused metal oxide semiconductor (LDMOS) transistor is a drain extension transistor used in power switching circuits and other applications, and can provide benefits for high voltage operation. However, even when the source and the buried layer are both grounded, a high di / dt induced inductively during operation may raise the source potential above the buried layer, thus triggering parasitic bipolar transistor action. Due to the triggering of the parasitic bipolar transistor, a lower or non-uniform voltage breakdown at the edge of the device may limit the reverse bias snapback current capability and reduce the safe operating area (SOA) for the LDMOS transistor. Summary of the Invention

[0003] In one aspect, an electronic device includes a semiconductor layer, a transistor finger structure, and a well region. The semiconductor layer has sides extending in a plane of orthogonal first and second directions and includes a majority carrier dopant of a first type. The transistor finger structure extends longitudinally along the first direction and includes drain fingers and source fingers. The drain fingers have opposite drain finger ends spaced apart from each other along the first direction in the semiconductor layer and include a majority carrier dopant of a second type. The source fingers are laterally spaced from opposite sides of the drain fingers along the second direction in the semiconductor layer and include a majority carrier dopant of a second type. The well region includes a majority carrier dopant of the first type in the semiconductor layer, the source fingers extend in corresponding portions of the well region, and the well region extends laterally around and encloses the finger structure.

[0004] In another aspect, an electronic device includes a semiconductor layer, a transistor finger structure, a well region, an implantation region, and a conductive contact. The semiconductor layer has sides extending in a plane of orthogonal first and second directions and includes a majority carrier dopant of a first type. The transistor finger structure extends longitudinally along the first direction and includes a drain finger and a source finger. The drain finger has opposing drain finger ends spaced apart from each other along the first direction in the semiconductor layer and includes a majority carrier dopant of a second type. The source finger is laterally spaced from an opposing side of the drain finger along the second direction in the semiconductor layer and includes a majority carrier dopant of a second type. The well region includes a majority carrier dopant of the first type in the semiconductor layer, and the second well region extends laterally around the finger structure and surrounds the finger structure. The implantation region includes a majority carrier dopant of the first type in an end portion of the well region spaced apart from the transistor finger structure along the first direction, and the conductive contact extends from the implantation region to a metallization structure.

[0005] In another aspect, an electronic device includes a semiconductor layer, a transistor finger structure, a deep trench isolation structure, and a deep well. The semiconductor layer has sides extending in a plane of orthogonal first and second directions and includes a majority carrier dopant of a first type. The transistor finger structure extends longitudinally along the first direction and includes a drain finger and a source finger. The drain finger has opposing drain finger ends spaced apart from each other along the first direction in the semiconductor layer and includes a majority carrier dopant of a second type. The source finger is laterally spaced from an opposing side of the drain finger along the second direction in the semiconductor layer and includes a majority carrier dopant of a second type. The buried layer includes a majority carrier dopant of the second type in the semiconductor layer and is spaced apart from the side of the semiconductor layer along a third direction orthogonal to the first and second directions. The deep trench isolation structure laterally surrounds the transistor finger structure in the semiconductor layer, and the deep trench isolation structure extends through the semiconductor layer along the third direction to a semiconductor substrate. The deep well laterally surrounds a portion of the deep trench isolation structure in the semiconductor layer and is adjacent to a portion of the buried layer. The deep well is connected to the source finger through a metallization structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a partial cross-sectional end view of an electronic device taken along line 1-1 of Figure 1A .

[0007] Figure 1A is Figure 1 a partial top plan view of the electronic device of

[0008] Figure 1B is a partial cross-sectional side view of the electronic device taken along line 1B-1B of Figure 1A .

[0009] Figure 1C is surrounded by an isolation structure Figure 1-1B Partial top plan view of a dual - transistor finger structure of an electronic device.

[0010] Figure 1D is Figure 1-1C Partial top plan view of the first metallization level of a dual - transistor finger structure of an electronic device.

[0011] Figure 1E is Figure 1-1D Partial top plan view of the second metallization level of a dual - transistor finger structure of an electronic device.

[0012] Figure 1F is Figure 1-1E Partial top plan view of the third metallization level of a dual - transistor finger structure of an electronic device.

[0013] Figure 1G is Figure 1C-1F Partial cross - sectional end view of an electronic device taken along line 1G - 1G.

[0014] Figure 1H is Figure 1C-1F Partial cross - sectional end view of an electronic device taken along line 1H - 1H. DETAILED DESCRIPTION

[0015] In the figures, like reference numerals always refer to like elements, and the various features are not necessarily drawn to scale. Also, the terms "couple / couples" include indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or couples with a second device, the connection may be a direct electrical connection or an indirect electrical connection via one or more intermediate devices and connections. One or more operating characteristics of various circuits, systems, and / or components are described below in a functional context, which in some cases are produced by the configuration and / or interconnection of various structures when the circuit system is powered on and operating. In the following discussion and claims, the terms "including / includes", "having / has", "with" or variations thereof are intended to be inclusive in a manner similar to the term "comprising" and should therefore be interpreted to mean "including (but not limited to)".

[0016] Unless otherwise stated, "about", "substantially", or "generally" in front of a value means + / - 10% of the stated value. Various operational characteristics of one or more circuits, systems, and / or components are described below in the context of functionality, which in some cases are produced by the configuration and / or interconnection of various structures when the circuit system is powered on and operating. Drain extension transistors may include drain extension NMOS (DENMOS), drain extension PMOS (DEPMOS), and / or laterally diffused MOS (LDMOS) transistors, as well as groups of DENMOS and DEPMOS, referred to as complementary drain extension MOS or DECMOS transistors. The described examples include doped regions of various semiconductor structures, which may be characterized as p-doped and / or n-doped regions or portions, and include regions having a majority carrier dopant of a particular type (e.g., n-type dopant or p-type dopant). For ease of description in connection with specific figures, one or more structures, features, aspects, components, etc. may be referred to herein as first, second, third, etc., such as first and second terminals, first, second, and third wells, etc., where these should not be construed as limitations on the claims. The various disclosed structures and methods of the present disclosure may be advantageously applied to the manufacture of electronic devices such as integrated circuits. While such examples may be expected to provide various improvements, the present disclosure does not require specific results unless expressly recited in the specific claims.

[0017] Figure 1-1H An electronic device 100 is shown having a semiconductor substrate 102, which is or includes silicon or other suitable semiconductor material, and includes a majority carrier dopant of a first type (e.g., p-type or P, labeled "P substrate" in Figure 1 ). The electronic device 100 includes an LDMOS transistor formed on and / or in a semiconductor layer 104 (e.g., epitaxial silicon, epitaxial semiconductor layer), which extends above the semiconductor substrate 102, as shown in Figure 1 , 1B , 1G, and 1H. The electronic device 100 is shown in an example three-dimensional space having a first direction X (e.g., Figure 1A-1F ), a second direction Y (orthogonal) to the first direction X ( Figure 1 , 1A , 1C - 1H), and a third direction Z (orthogonal) to the respective first direction X and second direction Y ( Figure 1 , 1B , 1G, and 1H). Structures or features along any two of these directions are orthogonal to each other. The semiconductor layer 104 has a top surface or side extending in the plane of the first direction X and the second direction Y, and an upper portion of the semiconductor layer 104 includes a majority carrier dopant of a first type (e.g., p-type, labeled "P-EPI" in Figure 1 ).

[0018] The LDMOS transistor has one or more transistor finger structures F( Figure 1 、 1A and 1C-1F). The illustrated example has two parallel drain-centered transistor finger structures F, which are surrounded by a deep trench isolation structure 105 that includes trench structures( Figure 1 、 1A 、1C-1H). In other embodiments, any number of one or more transistor finger structures may be used. In one example, the trench structure 105 (or deep trench isolation structure 105) includes sidewall liners and is filled with doped polysilicon. The electronic device 100 includes a buried layer 106 of the semiconductor layer 104 (e.g., n-type, labeled "NBL" in Figure 1 、 1B 、1G and 1H). The buried layer 106 includes majority carrier dopants of the opposite second type (e.g., n-type or N). The deep trench isolation structure and its trench structure 105 extend through the buried layer 106 of the semiconductor layer 104 and into the semiconductor substrate 102. The deep well 107( Figure 1 、 1G and 1H) includes majority carrier dopants of the second type (e.g., labeled "DEEPN" in Figure 1 ) and laterally surrounds a portion of the deep trench isolation structure 105, and has a portion adjacent to a portion of the buried layer 106 in the semiconductor layer 104.

[0019] The corresponding transistor finger structures F extend longitudinally along a first direction X and include drain fingers D, the drain fingers having opposite drain finger ends spaced apart from each other along the first direction X in the semiconductor layer 104. The corresponding drain fingers include majority carrier dopants of the second type N and are laterally centered with respect to the corresponding transistor finger structures F. The corresponding transistor finger structures also include two source fingers S laterally spaced apart from opposite sides of the corresponding drain finger D along a second direction Y in the semiconductor layer 104. The source fingers S include majority carrier dopants of the second type N. As Figure 1G shown, the source fingers S are electrically connected to the deep well 107 through a metallization structure.

[0020] The electronic device 100 shown also includes a reduced surface field implant region 108 in the semiconductor layer 104 above the buried layer 106 having majority carriers of the first type (e.g., p-type) (e.g., in Figure 1labeled “PRSRF”). In some instances, the reduced surface field implant region 108 includes a distributed doping concentration to facilitate full reverse bias depletion of the drift region (e.g., the drift region 112 described herein). In a power switch circuit implementation (e.g., a DC-DC converter), the high-side switch and the low-side switch may be fabricated as drain extension transistors. In the illustrated example, the corresponding transistor finger structure includes an integrated back-gate terminal (e.g., labeled “IBG” in Figure 1 electrically connected to the source finger S via a metallization structure. In addition, the IBG is coupled to the deep well 107, the buried layer 106, and the substrate 102, as Figure 1G shown.

[0021] As Figure 1-1B shown in FIGS. 1G and 1H, the electronic device 100 includes a well region 110 (e.g., labeled “DWELL” in Figure 1 ), which includes a majority carrier dopant of a first type (e.g., p-type) in the semiconductor layer 104. The transistor source finger S extends in a corresponding portion of the well region 110. Additionally, the well region 110 extends laterally around the finger structure F and encloses the finger structure, as Figure 1A shown. As Figure 1A and 1B further shown, the lateral ends of the well region 110 have a first width WDW1 along a first direction X, and the lateral top portion of the well region 110 has a second width WDW2 along a second direction Y ( Figure 1A ). In one instance, the first width WDW1 is greater than the second width WDW2. Additionally, as Figure 1A and 1B further shown, the well region 110 extends laterally outward along the first direction X beyond the outer boundary 109 of the semiconductor active region (in which the respective elements of the LDMOS transistor, such as the source (S), drain (D), NDRIFT, etc., are formed, which may also be referred to as a “deep trench” in some cases) by an overlap distance labeled DWOL in Figure 1A .

[0022] As Figure 1 , 1B , 1G and 1H shown, the corresponding transistor finger structure F of the LDMOS transistor also includes a second type (e.g., n-type, in Figure 1The drift region 112 of majority carrier dopants (labeled "NDRIFT" in []) of the LDMOS transistor. The LDMOS transistor can be combined with other components (not shown) in the implementation of the electronic device 100, for example, to form a power switching circuit or other circuits, where high-voltage transistors are integrated with logic and other low-voltage transistors on a single integrated circuit (IC). The extended drain structure of the transistor finger structure F can facilitate effective operation as a low-side switch in a switched-mode power supply, providing a low source-drain resistance (RDSON) during the on state, and the ability to block or withstand the high off-state voltage between the drain D and the source S or the gate G. The extended drain provides a relatively lightly doped drift region to extend the drain D away from the edge of the channel region. The drift region 112 can increase the reverse blocking voltage to exceed the rated voltage of the gate oxide in a specific process.

[0023] As Figure 1 , 1B , 1G, and 1H further show that, in one example, the source finger S includes a second well region 114 (e.g., Figure 1 the shallow well region labeled "SPWELL" in []) that extends in a corresponding portion of the well region 110 in the semiconductor layer 104. The second well region 114 includes a majority carrier dopant of a first type (e.g., a shallow p-well with p-type carriers). The second well region 114 extends laterally around the finger structure F and encloses the finger structure. As Figure 1B shown, the second well region 114 has an end portion that extends beyond the lateral ends of the well region 110 along the first direction X. In one example, the end portion of the second well region 114 has a width WSPW ( Figure 1B ), which is wider than the first width WDW1 of the lateral ends of the well region 110 along the first direction X (e.g., WSPW is greater than WDW1). In addition, as Figure 1B also shown, the well region 110 (DWELL) extends into the semiconductor layer 104 along the third direction Z, and the well region 110 is deeper than the second well region 114 (SPWELL) along the third direction Z. In addition, as Figure 1 shown, a portion of the deep trench isolation structure 105 and the deep well 107 is adjacent to a portion of the second well region 114 (SPWELL) along the second direction Y.

[0024] In one example, the electronic device 100 includes a shallow trench isolation (STI) structure 118, where an insulator material is formed in trenches extending into the top side of the epitaxial semiconductor layer 104. The LDMOS transistor has an oxide structure 120 (e.g., a field oxide structure, field oxide, in Figure 1An extended drain structure (labeled "FOX" in []) that extends along the top side of the epitaxial semiconductor layer 104 and extends under the polysilicon gate fingers 122 (e.g., in Figure 1 labeled "G" in []). Figure 1 Also shown in [] are polysilicon dummy gate fingers (e.g., labeled "DG" in Figure 1 []). In the illustrated example, the field oxide structure 120 is a local oxidation of silicon (LOCOS) structure. The field oxide 120 can provide a field gap for the laterally diffused extended drain. An example drain-centered transistor includes gate and source finger structures that extend laterally around the drain finger D, but not all possible embodiments require this. In one example, the oxide structure 120 laterally surrounds the drain finger D of the corresponding transistor finger structure F. As Figure 1 shown, the nitride liner layer 124 extends along portions of the top and sidewalls of the oxide structure 120 and the polysilicon gate and dummy gate structures 122 (e.g., labeled "nitride" in Figure 1 []).

[0025] As Figure 1 , 1B , 1G, and 1H show, the LDMOS transistor also includes a shallow first source-drain implant region 126 (e.g., labeled "PSD" in Figure 1 []). The first source-drain implant region 126 includes a majority carrier dopant of a first type (e.g., p-type) having a higher concentration than that of the second well region 114, thereby providing, for example, an electrical coupling to the p-doped portion (P-EPI) of the semiconductor layer 104. Additionally, the LDMOS transistor also includes a shallow source-drain implant region (not designated by a number) having a majority carrier dopant of a second type (e.g., n-type) (e.g., providing the source and drain of the LDMOS transistor).

[0026] The electronic device 100 also includes a multi-level metallization structure having a pre-metal dielectric (PMD) layer 130 over the top side of the epitaxial semiconductor layer 104 and the polysilicon structure 122. The multi-level metallization structure also includes tungsten or other conductive metal contacts 132 ( Figure 1 ), as well as a first inter-level or inter-layer dielectric (ILD) layer 140 and patterned metal trace features 142 (or metallization structure 142) (e.g., labeled "M1" in Figure 1 [] and also see the top view of Figure 1D ), and a first metal via (e.g., Figure 1B , 1G , and 1H, not designated by a number).

[0027] The second level of the metallization structure includes a second ILD layer 150 and patterned metal trace features 152 (e.g., inFigure 1 labeled as "M2" in, also see Figure 1E top view of), and a second metal via (e.g., Figure 1 , 1B , 1G, and 1H, not shown numerically).

[0028] The final top (e.g., third) level of the metallization structure includes a top-side metal feature 162 (e.g., labeled as M3 in Figure 1 also see Figure 1F top view of), which forms an externally accessible terminal of the semiconductor die of the electronic device 100, such as a die pad or bond pad (not shown) suitable for wire bond interconnection and / or a conductive metal pillar or stud configured for flip-chip soldering to a lead frame or substrate (not shown).

[0029] The LDMOS transistor terminals include conductive contacts 132 (e.g., tungsten), which extend to the top side of the epitaxial semiconductor layer 104 and are electrically connected to corresponding source-drain implant regions to provide electrical interconnection of the transistor terminals to the metallization structure. The transistor finger structure F includes p-type source-drain implant regions 126 and n-type source-drain implant regions in the upper portion of the second well region 114 of the source finger S and the integrated back-gate terminal IBG. The drain finger D of the corresponding transistor finger structure F includes n-type source-drain implant regions (not shown numerically) along the top side of the n-type drift region 112, which are electrically connected to the associated drain conductive contact 132. The interface between the source-drain implant region and the associated tungsten contact 132 may include a conductive metal silicide (not shown).

[0030] As Figure 1A and 1C further shown in -1F, the LDMOS transistor includes a polysilicon gate finger 122 (e.g., labeled as "G" in Figure 1A that laterally surrounds or encircles the corresponding transistor drain finger D, and a polysilicon pseudo-gate finger 122 (e.g., labeled as "DG" in Figure 1A that is laterally spaced outward from the transistor finger structure F along the second direction Y. The deep trench isolation structure 105 and the deep well 107 in the semiconductor layer 104 laterally surround (e.g., encircle) the transistor finger structure F and the polysilicon gate finger 122. As Figure 1 , 1G and 1H show, the deep trench isolation structure 105 extends through the semiconductor layer 104 along the third direction Z to the semiconductor substrate 102. As Figure 1As shown, the deep trench isolation structure 105 and the deep well 107 are laterally spaced apart by a distance D1 from the second well region 114 (SPWELL) along the first direction X, where the distance D1 can be determined according to the rated breakdown voltage of the electronic device 100. For example, the larger the rated breakdown voltage, the larger the distance D1.

[0031] As Figure 1 and 1C best shown in, the electronic device 100 includes conductive contacts (e.g., tungsten contacts 132 of the initial layer of the metallization structure), where a first group of contacts C1 are connected to the p-type source / drain implant regions 126 and the associated portions (e.g., Figure 1C the top and bottom in) that are laterally outward from the pseudo-gate polysilicon structure 122 of the shallow p-type well region 114 (SPWELL), and a second group of contacts C2 are laterally outward from the transistor finger structure F. As Figure 1B shown, the source / drain implant regions 126 (PSD) are in the end portions of the second well region 114, and the conductive contacts C2 132 extend from the source / drain implant regions 126 to the metallization structure 142. Also as Figure 1 and 1D -1H shown, the second source / drain implant regions in the lateral top portion (and the lateral bottom portion) of the second well region 114 are spaced apart from the transistor finger structure F along the second direction Y, and the second conductive contacts C1 132 extend from the second source / drain implant regions 126 to the metallization structure 142.

[0032] Figure 1D Shows a portion of the first metal layer trace feature 142 (M1), which includes connections to the first group of contacts C1 and the second group of contacts C2 to provide an electrical connection of the metallization structure to the shallow second well region 114 (and in some instances, to the well region 110) at the periphery of the isolation portion surrounding the semiconductor layer 104. As Figure 1D shown, a portion of the metallization structure 142 connects the second well region 114 to the pseudo-gate fingers of the LDMOS transistor. Figure 1D Shows another portion of the metallization structure 142 connected to the contacts to the polysilicon gate 122. In addition, Figure 1D shows another portion of the metallization structure 142 connected to the contacts to the drain fingers.

[0033] Figure 1EFurther shown are metal trace features 152 of the second level (M2), which include trace features that provide connections (e.g., via respective first metal trace features 142) to the drain and source fingers of the transistor. As described above, the deep well (DEEPN) 107 laterally surrounds a portion of the deep trench isolation structure 105, and the deep well 107 is adjacent to a portion of the buried layer 106 in the semiconductor layer 104. Additionally, the deep well 107 is connected to the source finger S via a metallization structure, as Figure 1G shown. In this example, a first contact 132 to the metallization structure is connected to a portion of the deep well 107 along the top side of the semiconductor layer 104, and a second contact 132 of the metallization structure is connected to one of the source fingers S, where the metal traces and via features of the metallization structure electrically connect the source finger S and the integrated back gate finger IBG to the deep well 107 and the buried layer 106.

[0034] Additionally, as Figure 1F shown, the third metal trace feature 162 (M3) provides a pair of interleaved comb structures, each comb structure having a first portion extending along a first direction X and a second portion extending from the first portion along a second direction Y (e.g., comb fingers). In this example, Figure 1F the lower comb structure in Figure 1G provides source and back gate connections to the deep well 107 and the buried layer 106, as further shown in the cross-sectional view of Figure 1F . Additionally, Figure 1H the upper comb structure in Figure 1E and 1F provides drain finger interconnects to the metallization structure, as further shown in the cross-sectional view of

[0035] For clarity and simplicity, various metal via structures (e.g., metal vias that connect the M1 metal trace features to the M2 metal trace features, metal vias that connect the M2 metal trace features to the M3 metal trace features) are not explicitly shown in the top-down plan view (e.g., in the top-down plan views of Figure 1C The LDMOS transistor including the transistor finger structure F in the electronic device 100 can significantly improve the snapback current capability and breakdown voltage performance in transistor operation - for example, in some instances, due to a reduction in the reverse bias recovery time. For example, Figure 1C) provides significant advantages in terms of increased snapback current capability and improved breakdown voltage performance. For example, in some embodiments, the transistor can support a roughly 25% improvement in the maximum drain voltage.

[0036] The described examples provide an extension of the well region 110 to surround the transistor finger structure F (e.g., surrounding the drain center active cell finger structure as shown above) either individually or in combination with guard ring contacts (e.g., the first set of contacts C1, the second set of contacts C2, or both sets of contacts C1, C2) around the pseudo gate fingers DG and around the lateral ends to the second well region 114. Figure 1A As shown above. Figure 1B In addition, the second well region 114 can be wider than the well region 110 (as shown, WSPW>WDW1), such that the transistor can support an increased snapback current and thus can have improved breakdown voltage performance.

[0037] The described examples and various embodiments can also include further benefits associated with customizing the spacing of the second well region 114 to the deep trench isolation structure 105 and the deep well 107 ( Figure 1 D1 in) and the spacing and overlap between the shallow n-type third well region 116 and the field oxide 120 according to the device rated breakdown voltage of a given design.

[0038] The described examples and other embodiments can advantageously provide a metallization connection between the buried layer 106 and the source finger S (e.g., as well as the integrated back gate finger IBG) to further facilitate an enhanced snapback current capability in transistor operation. These performance benefits and advantages can be achieved individually or further enhanced by extending the well region 110 beyond the outer boundary 109 of the semiconductor active region (which can be referred to as the "deep trench") along the first direction X (e.g., Figure 1A the overlap distance DWOL in, e.g., approximately 0.2 μm), where the second direction dimension overlaps or aligns with the edge of the corresponding polysilicon pseudo gate finger DG.

[0039] Certain embodiments can also benefit from having a sufficient width of the second well region 114 along the first direction X for the contact 132 to the metallization structure 142 (e.g., Figure 1B contact C2 in). For example, for a 20V rated breakdown voltage, Figure 1B WSPW in is approximately 2.0 microns. In addition, in some embodiments, an improved breakdown voltage performance can be achieved by providing a metallization structure that forms a ring connection around the transistor finger structure F (e.g., Figure 1Dthe metallization structure 142 and associated contacts 132) to facilitate snapback current improvement. The metallization structure provides low-resistance interconnection of the source S and integrated backgate fingers IBG to the buried layer 106, e.g., to accommodate the high di / dt inductively sensed while alleviating the rise of the transistor source potential above the buried layer 106. In this way, the described example embodiments can mitigate or avoid parasitic bipolar transistor triggering, e.g., Figure 1 the parasitic NPN bipolar transistor shown in dashed lines therein, having a collector formed by the n-type drift region 112, a p-type base formed by the p-doped portion of the epitaxial semiconductor layer 104, and an n-type collector formed by the n-type third well region 116.

[0040] The benefits described above can be achieved by implementing one or more of the above-described features and aspects of the electronic device 100, thereby mitigating or preventing lateral bipolar transistor triggering and providing increased and more uniform voltage breakdown performance, particularly at the device edges, to facilitate reverse bias snapback current and improve the safe operating area (SOA).

[0041] Within the scope of the claims, modifications may be made in the described embodiments, and other embodiments are possible.

Claims

1. An electronic device, comprising: a semiconductor layer having sides extending in a plane of orthogonal first and second directions and containing a majority carrier dopant of a first type; a transistor finger structure extending longitudinally along the first direction and comprising drain fingers and source fingers, the drain fingers having opposite drain finger ends spaced apart from each other along the first direction in the semiconductor layer and comprising a majority carrier dopant of a second type, the source fingers spaced apart laterally from opposite sides of the drain fingers along the second direction in the semiconductor layer and comprising a majority carrier dopant of the second type; as well as A well region includes majority carrier dopants of the first type in the semiconductor layer, the source fingers extending in respective portions of the well region, and the well region extending laterally around and enclosing the finger structure.

2. An electronic device according to claim 1, wherein the source finger includes a second well region extending in the corresponding portion of the well region, the second well region contains the first type of majority carrier dopant in the semiconductor layer, the second well region extends laterally around the finger structure and surrounds the finger structure, and the second well region has an end portion extending beyond the lateral end of the well region along the first direction. 3 . The electronic device of claim 2 , wherein the lateral end portion of the well region has a first width along the first direction, and the end portion of the second well region is wider than the first width along the first direction.

4. The electronic device of claim 2, comprising an implanted region containing majority carrier dopants of the first type in the end portion of the second well region and a conductive contact extending from the implanted region to a metallization structure.

5. The electronic device of claim 4 , comprising a second implant region and a second conductive contact, wherein the second implant region contains the first type of majority carrier dopant in a lateral top portion of the second well region spaced apart from the transistor finger structure along the second direction, and the second conductive contact extends from the second implant region to a metallization structure.

6. An electronic device according to claim 2, comprising an implantation region and a conductive contact, wherein the implantation region contains the first type of majority carrier dopant in a lateral top portion of the second well region spaced apart from the transistor finger structure along the second direction, and the conductive contact extends from the implantation region to the metallization structure. 7 . The electronic device of claim 1 , wherein a lateral end portion of the well region has a first width along the first direction, a lateral top portion of the well region has a second width along the second direction, and the first width is greater than the second width.

8. An electronic device comprising: a semiconductor layer having sides extending in a plane of orthogonal first and second directions and containing a majority carrier dopant of a first type; a transistor finger structure extending longitudinally along the first direction and comprising drain fingers and source fingers, the drain fingers having opposite drain finger ends spaced apart from each other along the first direction in the semiconductor layer and comprising a majority carrier dopant of a second type, the source fingers spaced apart laterally from opposite sides of the drain fingers along the second direction in the semiconductor layer and comprising a majority carrier dopant of the second type; a well region comprising the first type of majority carrier dopant in the semiconductor layer, the second well region extending laterally around and enclosing the finger structure; an implanted region comprising majority carrier dopants of the first type in end portions of the well region spaced apart from the transistor finger structures along the first direction; as well as A conductive contact extends from the implant region to the metallization structure.

9. An electronic device according to claim 8, comprising a second implant region and a second conductive contact, wherein the second implant region contains the first type of majority carrier dopant in a lateral top portion of the well region spaced apart from the transistor finger structure along the second direction, and the second conductive contact extends from the second implant region to the metallization structure.

10. The electronic device of claim 8, wherein the source fingers extend in corresponding portions of a second well region in the semiconductor layer that includes majority carrier dopants of the first type. 11 . The electronic device of claim 10 , wherein the second well region extends into the semiconductor layer along a third direction orthogonal to the first and second directions, and the second well region is deeper than the well region along the third direction.

12. The electronic device according to claim 8 comprises a deep trench isolation structure in the semiconductor layer that laterally surrounds the transistor finger structure, the deep trench isolation structure extends through the semiconductor layer to the semiconductor substrate along a third direction orthogonal to the first and second directions, and the deep trench isolation structure is laterally spaced apart from the well region along the first direction. 13 . The electronic device of claim 12 , wherein the deep trench isolation structure is adjacent to a portion of the well region along the second direction.

14. An electronic device according to claim 13, comprising a second implant region and a second conductive contact, wherein the second implant region contains the first type of majority carrier dopant in a lateral top portion of the well region spaced apart from the transistor finger structure along the second direction, and the second conductive contact extends from the second implant region to the metallization structure.

15. An electronic device according to claim 12, comprising a second implant region and a second conductive contact, wherein the second implant region contains the first type of majority carrier dopant in a lateral top portion of the well region spaced apart from the transistor finger structure along the second direction, and the second conductive contact extends from the second implant region to the metallization structure.

16. An electronic device comprising: a semiconductor layer having sides extending in a plane of orthogonal first and second directions and containing a majority carrier dopant of a first type; a transistor finger structure extending longitudinally along the first direction and comprising drain fingers and source fingers, the drain fingers having opposite drain finger ends spaced apart from each other along the first direction in the semiconductor layer and comprising a majority carrier dopant of a second type, the source fingers spaced apart laterally from opposite sides of the drain fingers along the second direction in the semiconductor layer and comprising a majority carrier dopant of the second type; a buried layer comprising a second type of majority carrier dopant in the semiconductor layer and spaced apart from the side of the semiconductor layer along a third direction orthogonal to the first and second directions; a deep trench isolation structure laterally surrounding the transistor finger structure in the semiconductor layer, the deep trench isolation structure extending through the semiconductor layer along the third direction to the semiconductor substrate; as well as A deep well laterally surrounds a portion of the deep trench isolation structure in the semiconductor layer and is adjacent to a portion of the buried layer, the deep well being connected to the source finger through a metallization structure.

17. The electronic device according to claim 16, comprising: a first contact of the metallization structure connected to a portion of the deep well along the side of the semiconductor layer; as well as A second contact of the metallization structure is connected to one of the source fingers.

18. The electronic device of claim 16, wherein the transistor finger structure comprises a back gate connected to the deep well and the source finger through the metallization structure.

19. The electronic device of claim 18, wherein the metallization structure comprises a conductive metal feature having a first portion extending along the first direction and a second portion extending from the first portion along the second direction to connect to the source finger and the back gate.

20. The electronic device of claim 16, wherein the metallization structure comprises a conductive metal feature having a first portion extending along the first direction and a second portion extending from the first portion along the second direction to connect to the source finger.

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