Hybrid high-voltage LDMOS device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor high-voltage devices, in particular to a hybrid high-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. According to the hybrid high-voltage LDMOS device, the shallow trench isolation region is arranged in the N-type drift region, the thick oxide layers are arranged on the surfaces of the P-type drift region and the N-type drift region, and the shallow trench isolation layer and the thick oxide layer on the surface of the field plate are mixed, so that an electric field between the source electrode and the drain electrode is influenced by the combined action of the shallow trench isolation region and the thick oxide layer; longitudinal electric field distribution is remarkably improved, so that the hybrid high-voltage LDMOS device obtains breakdown voltage superior to that of a pure shallow trench isolation field plate structure or a pure oxide layer field plate structure, and has lower on resistance and longer hot carrier injection life compared with pure shallow trench isolation and pure oxide layer structures. The problem of short service life of a hot carrier injection effect based on a pure oxide layer structure is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor high voltage devices, and in particular to a hybrid high voltage LDMOS device and a preparation method thereof. Background Art

[0002] The performance optimization of High Voltage Laterally Diffused Metal Oxide Semiconductor (HV-LDMOS) devices needs to focus on three core indicators: high breakdown voltage (BVD), low on-resistance (Rdson), and long hot carrier injection (HCI) life. Among them, the breakdown voltage determines the voltage resistance of the device under high voltage, the on-resistance directly affects energy efficiency and heat generation, and the hot carrier injection life is related to long-term reliability. Currently, for high-voltage LDMOS with an operating voltage higher than 20V, the mainstream designs are divided into two categories: The first is a field plate structure based on shallow trench isolation (STI). This structure introduces deep trench oxide isolation in the drift region and combines field plate technology to optimize the surface electric field distribution, improve breakdown voltage and hot carrier injection life, and is suitable for industrial power supplies, automotive electronics and other scenarios with strict reliability requirements. However, its lateral resistance is relatively high, resulting in a relatively large on-resistance (Rdson), which is difficult to meet the application of products with low power consumption requirements.

[0003] The second is a field plate structure based on a thick oxide layer (RESURF Oxide, ROX) on the surface of semiconductor silicon. This structure uses ROX technology and charge balance effect to reduce the peak electric field on the field plate surface and increase the breakdown voltage; it also expands the depletion region laterally to reduce the current path resistance, thereby significantly reducing the on-resistance. However, the hot carrier injection life of the ROX structure is short, making it difficult to meet product applications with high life requirements.

[0004] Therefore, how to design a high-voltage LDMOS device with both low on-resistance and long hot carrier injection lifetime has become a technical problem to be solved urgently in this field. Summary of the invention

[0005] The present invention aims to provide a hybrid high-voltage LDMOS device and a preparation method thereof, so as to solve the technical problems of large on-resistance and short hot carrier injection lifetime of the existing field plate structure, so that the high-voltage LDMOS device has both low on-resistance and long hot carrier injection lifetime.

[0006] To achieve the above object, a first aspect of the present invention provides a hybrid high-voltage LDMOS device, including a substrate, a P-type drift region, a P-type body region, a high-concentration P-type doping region, an N-type drift region, a shallow trench isolation region, a thick oxide layer, a source electrode, a gate electrode, and a drain electrode, wherein: the P-type drift region is located on one side of the substrate surface, the N-type drift region is located on the other side of the substrate surface, and the P-type drift region is connected to the N-type drift region; the P-type body region is located inside the P-type drift region; the high-concentration P-type doping region and the source electrode are located inside the P-type body region; the high-concentration P-type doping region is connected to the source electrode; the drain electrode is located inside the N-type drift region; The shallow trench isolation region is located inside the N-type drift region, and the shallow trench isolation region is located between the source electrode and the drain electrode; The thick oxide layer is located on the surfaces of the P-type drift region and the N-type drift region; The gate electrode is located on the surfaces of the P-type drift region and the thick oxide layer.

[0007] While the above hybrid high-voltage LDMOS device is provided with a shallow trench isolation region inside the N-type drift region, a thick oxide layer is provided on the surfaces of the P-type drift region and the N-type drift region, mixing the shallow trench isolation layer and the thick oxide layer on the surface of the field plate, so that the shallow trench isolation region and the thick oxide layer jointly affect the electric field between the source electrode and the drain electrode, significantly improving the longitudinal electric field distribution, enabling the hybrid high-voltage LDMOS device to achieve a breakdown voltage superior to that of a pure shallow trench isolation field plate structure or a pure oxide layer field plate structure, and having a lower on-resistance and a longer hot carrier injection lifetime compared with the pure shallow trench isolation and pure oxide layer structures, solving the problem of short hot carrier injection effect lifetime based on the pure oxide layer structure.

[0008] It should be noted that if the shallow trench isolation region and the thick oxide layer are simply combined on the high-voltage LDMOS device, affected by the etching process, there may be a problem of depression in the shallow trench isolation region or thinning of the thick oxide layer at the boundary where the shallow trench isolation region and the thick oxide layer meet, resulting in a breakdown voltage weak point at this part.

[0009] To solve the above technical problem, preferably, the shallow trench isolation region is located directly below the middle of the thick oxide layer.

[0010] In the above-described embodiment, the shallow trench isolation region is disposed directly below the thick oxide layer, such that the top of the shallow trench isolation region and the bottom of the thick oxide layer completely overlap, forming a hybrid drain oxide structure, thereby avoiding the problem of a weak breakdown voltage point generated at the boundary between the shallow trench isolation region and the thick oxide layer. Further, disposing the shallow trench isolation region directly below the middle of the thick oxide layer can improve the hybrid electric field generated by the two. Compared with disposing the shallow trench isolation region below the boundary of the thick oxide layer, its breakdown voltage is greater and the on-resistance is smaller, which is beneficial for product applications that meet low-power requirements and product applications with high-life requirements.

[0011] Preferably, the boundary of the gate is aligned with the center of the thick oxide layer, and the shallow trench isolation region is located directly below the gate.

[0012] The above-described embodiment further optimizes the relative positions among the shallow trench isolation region, the thick oxide layer, and the gate, thereby obtaining a higher breakdown voltage and a lower on-resistance. Specifically, the boundary of the gate is aligned with the center of the thick oxide layer, and the shallow trench isolation region is located directly below the gate, that is, the shallow trench isolation region is not only located directly below the middle of the thick oxide layer but also directly below the gate, and the boundary of the shallow trench isolation region is close to the longitudinal axis in space of the gate boundary.

[0013] A second aspect of the present invention provides a method for manufacturing a hybrid high-voltage LDMOS, which is applicable to manufacturing a hybrid high-voltage LDMOS device according to any one of the first aspects of the present invention, and includes the following steps: Determine a substrate, and then form an N-type drift region on one side of the surface of the substrate. A shallow trench isolation region is provided inside the N-type drift region, and a P-type drift region is formed on the other side of the surface of the substrate; Form a thick oxide layer on the surfaces of the P-type drift region and the N-type drift region; Inject P-type impurities into the P-type drift region to form a P-type body region; Form a gate on the surfaces of the P-type drift region and the thick oxide layer; Inject high-concentration N-type impurities into the P-type body region and the N-type drift region respectively to form a source located inside the P-type body region and a drain located inside the N-type drift region; Inject high-concentration P-type impurities into the P-type body region to form a high-concentration P-type doped region.

[0014] Preferably, the step of determining a substrate, and then forming an N-type drift region on one side of the surface of the substrate, with a shallow trench isolation region provided inside the N-type drift region, and forming a P-type drift region on the other side of the surface of the substrate, includes: Grow an epitaxial layer on the surface of the substrate; Form a shallow trench isolation region in the active region of the epitaxial layer; Inject N-type impurities into one side of the epitaxial layer to form an N-type drift region that wraps the shallow trench isolation region; Inject P-type impurities into the other side of the epitaxial layer to form a P-type drift region.

[0015] Preferably, forming a thick oxide layer on the surfaces of the P-type drift region and the N-type drift region includes: Deposit a first oxide layer on the surfaces of the P-type drift region and the N-type drift region; Perform photolithography on the first oxide layer to form a thick oxide layer pattern; Etch the first oxide structure based on the thick oxide layer pattern, thereby forming the thick oxide layer.

[0016] Preferably, injecting P-type impurities into the P-type drift region to form a P-type body region includes: Perform photolithography on the P-type drift region to form a P-type body doping pattern; Inject P-type impurities into the P-type drift region based on the P-type body doping pattern, thereby forming a P-type body region in the P-type drift region.

[0017] Preferably, forming a gate on the surfaces of the P-type drift region and the thick oxide layer includes: Grow a second oxide layer on the surfaces of the P-type drift region and the thick oxide layer; Deposit a polysilicon layer on the surface of the second oxide layer; Etch the second oxide layer and the polysilicon layer, thereby forming the gate.

[0018] Preferably, injecting high-concentration N-type impurities into the P-type body region and the N-type drift region respectively to form a source electrode inside the P-type body region and a drain electrode inside the N-type drift region includes: Perform photolithography on the P-type body region and the N-type drift region respectively to form a source electrode doping pattern and a drain electrode doping pattern; Inject high-concentration N-type impurities into the P-type body region based on the source electrode doping pattern, thereby forming a source electrode in the P-type body region; Inject high-concentration N-type impurities into the N-type drift region based on the drain electrode doping pattern, thereby forming a drain electrode in the N-type drift region.

[0019] Preferably, injecting high-concentration P-type impurities into the P-type body region to form a high-concentration P-type doping region includes: Perform photolithography on the P-type body region to form a high-concentration P-type doping pattern; Inject P-type impurities into the P-type drift region based on the high-concentration P-type doping pattern, thereby forming a high-concentration P-type doping region in the P-type drift region.

[0020] A hybrid high-voltage LDMOS device and a manufacturing method thereof provided by the present invention have at least the following advantages compared with the prior art: First, while a shallow trench isolation region is provided inside the N-type drift region of the above hybrid high-voltage LDMOS device, a thick oxide layer is provided on the surfaces of the P-type drift region and the N-type drift region, mixing the shallow trench isolation layer and the thick oxide layer on the surface of the field plate. Thus, the shallow trench isolation region and the thick oxide layer jointly act on the electric field between the source and the drain, significantly improving the longitudinal electric field distribution, enabling the hybrid high-voltage LDMOS device to achieve a breakdown voltage superior to that of a pure shallow trench isolation field plate structure or a pure oxide layer field plate structure, and having a lower on-resistance and a longer hot carrier injection lifetime compared with the pure shallow trench isolation and pure oxide layer structures, solving the problem of short hot carrier injection effect lifetime based on the pure oxide layer structure.

[0021] Second, the above hybrid high-voltage LDMOS device arranges the shallow trench isolation region directly below the thick oxide layer, such that the top of the shallow trench isolation region and the bottom of the thick oxide layer completely overlap, forming a hybrid drain oxide structure, thus avoiding the problem of weak breakdown voltage points generated at the boundary between the shallow trench isolation region and the thick oxide layer. Further, arranging the shallow trench isolation region directly below the middle of the thick oxide layer can improve the hybrid electric field generated by the two. Compared with arranging the shallow trench isolation region below the boundary of the thick oxide layer, its breakdown voltage is larger and the on-resistance is smaller, which is beneficial for product applications meeting low-power consumption requirements and product applications with high lifetime requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic diagram of a pure STI type field plate structure provided by an embodiment of the present invention; Figure 2 is a schematic diagram of a pure ROX type field plate structure provided by an embodiment of the present invention; Figure 3 is a structural diagram of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 4 is a structural diagram of another hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 5a is an electric field schematic diagram of a pure STI type field plate structure provided by an embodiment of the present invention; Figure 5b is an electric field schematic diagram of a pure ROX type field plate structure provided by an embodiment of the present invention; Figure 5c is an electric field schematic diagram of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 6aIt is a schematic diagram of a shallow trench isolation region located at the lower left of a thick oxide layer provided by an embodiment of the present invention; Figure 6b It is a schematic diagram of the electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 7a It is a schematic diagram of a shallow trench isolation region located directly below the middle of a thick oxide layer provided by an embodiment of the present invention; Figure 7b It is a schematic diagram of the electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 8a It is a schematic diagram of a shallow trench isolation region located at the lower right of a thick oxide layer provided by an embodiment of the present invention; Figure 8b It is a schematic diagram of the electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 9a It is a schematic diagram of a shallow trench isolation region close to the left side of the gate boundary provided by an embodiment of the present invention; Figure 9b It is a schematic diagram of the electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 10a It is a schematic diagram of a shallow trench isolation region located below the gate boundary provided by an embodiment of the present invention; Figure 10b It is a schematic diagram of the electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 11a It is a schematic diagram of a shallow trench isolation region close to the right side of the gate boundary provided by an embodiment of the present invention; Figure 11b It is a schematic diagram of the electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 12 It is a schematic diagram of the depth of a shallow trench isolation region provided by an embodiment of the present invention; Figure 13a It is a schematic diagram of the electric field of a shallow trench isolation region with a depth of 0.2 um provided by an embodiment of the present invention; Figure 13b It is a schematic diagram of the electric field of a shallow trench isolation region with a depth of 0.3 um provided by an embodiment of the present invention; Figure 13c It is a schematic diagram of the electric field of a shallow trench isolation region with a depth of 0.35 um provided by an embodiment of the present invention; Figure 14 It is a schematic diagram of the width of a shallow trench isolation region provided by an embodiment of the present invention; Figure 15a It is a schematic diagram of the electric field of a shallow trench isolation region with a depth of 0.5 um provided by an embodiment of the present invention; Figure 15b It is a schematic diagram of the electric field with a shallow trench isolation region depth of 0.75um provided by an embodiment of the present invention; Figure 15c It is a schematic diagram of the electric field with a shallow trench isolation region depth of 1.0um provided by an embodiment of the present invention; Figure 16 It is a schematic structural diagram of an intermediate process for manufacturing the first hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 17 It is a schematic structural diagram of an intermediate process for manufacturing the second hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 18 It is a schematic structural diagram of an intermediate process for manufacturing the third hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 19 It is a schematic structural diagram of an intermediate process for manufacturing the fourth hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 20 It is a schematic structural diagram of an intermediate process for manufacturing the fifth hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 21 It is a schematic structural diagram of an intermediate process for manufacturing the sixth hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 22 It is a schematic structural diagram of an intermediate process for manufacturing the seventh hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 23 It is a schematic structural diagram of an intermediate process for manufacturing the eighth hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 24 It is a schematic structural diagram of an intermediate process for manufacturing the ninth hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Figure 25 It is a schematic structural diagram of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention; Wherein: 1. Substrate; 11. N-type buried layer; 12. Epitaxial layer; 2. P-type drift region; 21. P-type body region; 211. High-concentration P-type doping region; 3. N-type drift region; 4. Shallow trench isolation region; 5. Thick oxide layer; 51. First oxide layer; 6. Source electrode; 7. Gate electrode; 71. Second oxide layer; 8. Drain electrode. Detailed implementation manners

[0023] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the following detailed descriptions are all exemplary descriptions, which are intended to provide further detailed descriptions of the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" in the specification and claims of the present application and the above-mentioned description of the drawings and any variations thereof are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0024] The performance optimization of High Voltage Laterally Diffused Metal Oxide Semiconductor (HV-LDMOS) devices needs to focus on three core indicators: high breakdown voltage (BVD), low on-resistance (Rdson), and long hot carrier injection (HCI) life. Among them, the breakdown voltage determines the voltage resistance of the device under high voltage, the on-resistance directly affects energy efficiency and heat generation, and the hot carrier injection life is related to long-term reliability. Currently, for high-voltage LDMOS with an operating voltage higher than 20V, the mainstream designs are divided into two categories: See also Figure 1 The first is a field plate structure based on shallow trench isolation (STI). This structure introduces deep trench oxide isolation in the drift region and combines field plate technology to optimize the surface electric field distribution, improve breakdown voltage and hot carrier injection life, and is suitable for industrial power supplies, automotive electronics and other scenarios with strict reliability requirements. However, its lateral resistance is relatively high, resulting in a relatively large on-resistance (Rdson), which is difficult to meet the application of products with low power consumption requirements.

[0025] See also Figure 2 The second is a field plate structure based on a thick oxide layer (RESURF Oxide, ROX) on the surface of semiconductor silicon. This structure uses ROX technology and charge balance effect to reduce the peak electric field on the field plate surface and increase the breakdown voltage; it also expands the depletion region laterally to reduce the current path resistance, thereby significantly reducing the on-resistance. However, the hot carrier injection life of the ROX structure is short, making it difficult to meet product applications with high life requirements.

[0026] Therefore, how to design a high-voltage LDMOS device with both low on-resistance and long hot carrier injection lifetime has become a technical problem to be solved urgently in this field.

[0027] See alsoFigure 3 , to solve the above technical problems, in the first aspect of the embodiments of the present invention, a hybrid high-voltage LDMOS device is provided, including a substrate 1, a P-type drift region 2, a P-type body region 21, a high-concentration P-type doping region 211, an N-type drift region 3, a shallow trench isolation region 4, a thick oxide layer 5, a source electrode 6, a gate electrode 7, and a drain electrode 8, wherein: the P-type drift region 2 is located on one side of the surface of the substrate 1, the N-type drift region 3 is located on the other side of the surface of the substrate 1, and the P-type drift region 2 is connected to the N-type drift region 3; the P-type body region 21 is located inside the P-type drift region 2; the high-concentration P-type doping region 211 and the source electrode 6 are located inside the P-type body region 21; the high-concentration P-type doping region 211 is connected to the source electrode 6; the drain electrode 8 is located inside the N-type drift region 3; the shallow trench isolation region 4 is located inside the N-type drift region 3, and the shallow trench isolation region 4 is located between the source electrode 6 and the drain electrode 8; the thick oxide layer 5 is located on the surfaces of the P-type drift region 2 and the N-type drift region 3; the gate electrode 7 is located on the surfaces of the P-type drift region 2 and the thick oxide layer 5.

[0028] It should be noted that if the shallow trench isolation region 4 and the thick oxide layer 5 are simply combined on the high-voltage LDMOS device, due to the influence of the etching process, a depression in the shallow trench isolation region 4 or a thinning of the thick oxide layer 5 may occur at the boundary where the shallow trench isolation region 4 and the thick oxide layer 5 meet, resulting in a weak breakdown voltage point at this part.

[0029] See Figure 4 , to solve the above technical problems, preferably, the shallow trench isolation region 4 is located directly below the middle of the thick oxide layer 5; further, the boundary of the gate electrode 7 is aligned with the center of the thick oxide layer 5, and the shallow trench isolation region 4 is located directly below the gate electrode 7.

[0030] In the above embodiment, the shallow trench isolation region 4 is arranged directly below the middle of the thick oxide layer 5, and the shallow trench isolation region 4 is simultaneously located directly below the gate electrode 7 and close to the longitudinal axis of the boundary of the gate electrode 7 in space; this arrangement makes the top of the shallow trench isolation region 4 and the bottom of the thick oxide layer 5 completely overlap, forming a hybrid drain electrode 8 oxide structure, thus avoiding the problem of a weak breakdown voltage point generated at the boundary where the shallow trench isolation region 4 and the thick oxide layer 5 meet. Further, arranging the shallow trench isolation region 4 directly below the middle of the thick oxide layer 5 can improve the hybrid electric field generated by the two. Compared with arranging the shallow trench isolation region 4 below the boundary of the thick oxide layer 5, its breakdown voltage is larger and the on-resistance is smaller, which is beneficial to product applications that meet the requirements of low power consumption and high lifetime requirements.

[0031] To illustrate the technical effects of this embodiment, first, please see Figures 6a - 8b, where ss represents the distance from the high-concentration N-type impurity region in the P-type body region to the shallow trench isolation region. Figure 6a It shows the situation where the shallow trench isolation region 4 is directly below the thick oxide layer 5 and close to the left boundary of the thick oxide layer 5. Figure 6b The magnitude and distribution of the field plate electric field intensity at this time are shown in a heat map (Electric Field), with the unit of volts per centimeter (V / cm). Figure 7a It shows the situation where the shallow trench isolation region 4 is directly below the thick oxide layer 5 and located in the middle of the thick oxide layer 5. Figure 7b The magnitude and distribution of the field plate electric field intensity at this time are shown in a heat map (Electric Field), with the unit of volts per centimeter (V / cm). Figure 8a It shows the situation where the shallow trench isolation region 4 is directly below the thick oxide layer 5 and close to the right boundary of the thick oxide layer 5. Figure 8b The magnitude and distribution of the field plate electric field intensity at this time are shown in a heat map (Electric Field), with the unit of volts per centimeter (V / cm).

[0032] Since the breakdown voltage of the field plate is determined by the uniformity of the electric field distribution and the peak electric field intensity, and the on-resistance of the field plate is related to the carrier mobility between the source and drain, the cross-sectional area and length of the current path between the source and drain. Therefore, by observing and analyzing Figures 6a - 8b it can be seen that Figure 7b the range of the high electric field peak shown is smaller, and the overall electric field magnitude is lower compared to Figure 6b and Figure 8b Its electric field distribution is more uniform. It can be seen that Figure 7b the reduction of the peak electric field and the improvement of the uniformity in Figure 7a and Figure 7b directly increase the threshold value of the field plate breakdown voltage, and the large area of low electric field intensity region effectively improves the carrier mobility between the source and drain and reduces the on-resistance of the field plate; that is,

[0033] It should also be noted that in the experimental data corresponding to this embodiment, Figure 6b the ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.325, Figure 7b the ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.383, Figure 8b the ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.299, which corroborates that when the shallow trench isolation region 4 of the hybrid high-voltage LDMOS device is directly below the thick oxide layer 5 and located in the middle of the thick oxide layer 5, it can have both a relatively high breakdown voltage and a relatively low on-resistance.

[0034] Furthermore, on the basis that the shallow trench isolation region 4 is directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, please refer to Figures 9a - 11b , at this time, the boundary of the gate 7 is aligned with the center of the thick oxide layer 5. Figure 9a shows the case where the shallow trench isolation region 4 is close to the left side of the boundary of the gate 7, Figure 9b and shows the magnitude and distribution of the field plate electric field intensity (Electric Field) at this time in a heat map, with the unit of volts per centimeter (V / cm); Figure 10a shows the case where the shallow trench isolation region 4 is directly below the boundary of the gate 7, Figure 10b and shows the magnitude and distribution of the field plate electric field intensity (Electric Field) at this time in a heat map, with the unit of volts per centimeter (V / cm); Figure 11a shows the case where the shallow trench isolation region 4 is close to the right side of the boundary of the gate 7, Figure 11b and shows the magnitude and distribution of the field plate electric field intensity (Electric Field) at this time in a heat map, with the unit of volts per centimeter (V / cm).

[0035] Since the breakdown voltage of the field plate is determined by the uniformity of the electric field distribution and the peak electric field intensity, and the on-resistance of the field plate is related to the carrier mobility between the source and the drain, the cross-sectional area and the length of the current path between the source and the drain. Therefore, by observing and analyzing Figures 9a - 11b it can be seen that Figure 9b the overall electric field magnitude shown is lower than that of Figure 10b and Figure 11b , the low peak electric field distribution range is wider, and its electric field distribution is more uniform. It can be seen that Figure 9b the wide-range low peak electric field distribution and the improvement of uniformity in Figure 9a and Figure 9b directly increase the threshold value of the breakdown voltage of the field plate, and the wide-range low peak electric field distribution region effectively increases the carrier mobility between the source and the drain and reduces the on-resistance of the field plate; that is,

[0036] It should also be noted that Figure 9b the ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.403, Figure 10b the ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.383, Figure 11bThe ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.294, which proves that on the basis that the shallow trench isolation region 4 is directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, when the shallow trench isolation region 4 is close to the left boundary of the gate 7, the hybrid high-voltage LDMOS device can have both a relatively high breakdown voltage and a relatively low on-resistance.

[0037] Further, on the basis that the shallow trench isolation region 4 is directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, and is close to the left boundary of the gate 7, the depth and width of the shallow trench isolation region 4 are further explored. See Figure 12 , Figure 12 where D in STI represents the depth of the shallow trench isolation region 4. See Figure 14 , Figure 14 where W in STI represents the width of the shallow trench isolation region 4.

[0038] See Figures 13a - 13c , Figure 13a The magnitude and distribution (Electric Field) of the field plate electric field intensity when the depth of the shallow trench isolation region 4 is 0.2 μm are represented by a heat map on the above basis; the unit is volts per centimeter (V / cm); Figure 13b The magnitude and distribution (Electric Field) of the field plate electric field intensity when the depth of the shallow trench isolation region 4 is 0.3 μm are represented by a heat map on the above basis; the unit is volts per centimeter (V / cm); Figure 13c The magnitude and distribution (Electric Field) of the field plate electric field intensity when the depth of the shallow trench isolation region 4 is 0.35 μm are represented by a heat map on the above basis; the unit is volts per centimeter (V / cm).

[0039] Since the field plate breakdown voltage is determined by the uniformity of the electric field distribution and the peak electric field intensity, and the field plate on-resistance is related to the carrier mobility between the source and drain, the cross-sectional area and length of the current path between the source and drain. Therefore, observing and analyzing Figures 13a - 13c it can be seen that Figure 13b the overall electric field magnitude shown is lower than that of Figure 13a and Figure 13c , and the low peak electric field distribution range is wider, and its electric field distribution is more uniform. It can be seen that Figure 13b the wide-range low peak electric field distribution and the improvement of uniformity in Figure 13bAs shown, on the basis that the shallow trench isolation region 4 is located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary, the field plate electric field distribution is optimal when the depth of the shallow trench isolation region 4 is 0.3 um, which can have both a relatively high breakdown voltage and a relatively low on-resistance.

[0040] It should also be noted that Figure 13a The ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.260, Figure 13b The ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.429, Figure 13c The ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.403, which corroborates that on the basis that the shallow trench isolation region 4 is located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary, the shallow trench isolation region 4 can have both a relatively high breakdown voltage and a relatively low on-resistance when its depth is 0.3 um.

[0041] Furthermore, referring to Figures 15a - 15c , Figures 15a - 15c On the basis of setting the shallow trench isolation region 4 to be located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, and when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary with a depth of 0.3 um for the shallow trench isolation region 4, the optimal width of the shallow trench isolation region 4 is further tested. Figure 15a The magnitude and distribution of the field plate electric field strength (Electric Field) when the width of the shallow trench isolation region 4 is 0.5 um on the above basis are represented by a heat map, with the unit of volts per centimeter (V / cm); Figure 15b The magnitude and distribution of the field plate electric field strength (Electric Field) when the width of the shallow trench isolation region 4 is 0.75 um on the above basis are represented by a heat map, with the unit of volts per centimeter (V / cm); Figure 15c The magnitude and distribution of the field plate electric field strength (Electric Field) when the width of the shallow trench isolation region 4 is 1.0 um on the above basis are represented by a heat map, with the unit of volts per centimeter (V / cm).

[0042] Since the field plate breakdown voltage is determined by the uniformity of the electric field distribution and the peak electric field strength, and the field plate on-resistance is related to the carrier mobility between the source and drain, the cross-sectional area and length of the current path between the source and drain. Therefore, observing and analyzing Figures 15a - 15c it can be seen that Figure 15c The overall electric field magnitude shown is lower than Figure 15a and Figure 15b , and the low peak electric field distribution range is wider, and its electric field distribution is more uniform. It can be seen that Figure 15cThe improvement of the low peak electric field distribution and uniformity in a wide range directly increases the threshold value of the field plate breakdown voltage, and the wide range of the low peak electric field distribution region effectively improves the carrier mobility between the source and the drain and reduces the field plate on-resistance; that is Figure 15c As shown, on the basis that the shallow trench isolation region 4 is directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary, the field plate electric field distribution is optimal when the depth of the shallow trench isolation region 4 is 0.3 um and the width is 1.0 um, which can have both a high breakdown voltage and a low on-resistance.

[0043] It should also be noted that Figure 15a The ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.375, Figure 15b The ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.429, Figure 15c The ratio of the corresponding breakdown voltage (V) to the on-resistance (Ω) is 0.484, which proves that for the hybrid high-voltage LDMOS device, on the basis that the shallow trench isolation region 4 is directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary, it can have both a high breakdown voltage and a low on-resistance when the depth of the shallow trench isolation region 4 is 0.3 um and the width is 1.0 um.

[0044] See Figures 5a - 5c , Figure 5a is the electric field schematic diagram of a pure STI-type field plate structure provided by an embodiment of the present invention, which shows the magnitude and distribution of the field plate electric field intensity at this time (Electric Field) in a heat map, and the unit is volts per centimeter (V / cm); Figure 5b is the electric field schematic diagram of a pure ROX-type field plate structure provided by an embodiment of the present invention, which shows the magnitude and distribution of the field plate electric field intensity at this time (Electric Field) in a heat map, and the unit is volts per centimeter (V / cm); Figure 5c is the electric field schematic diagram of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention, which shows the magnitude and distribution of the field plate electric field intensity at this time (Electric Field) in a heat map, and the unit is volts per centimeter (V / cm).

[0045] Since the field plate breakdown voltage is determined by the uniformity of the electric field distribution and the peak electric field intensity, and the field plate on-resistance is related to the carrier mobility between the source and the drain, the cross-sectional area and length of the current path between the source and the drain. Therefore, by observing and analyzing Figures 5a - 5c it can be seen that Figure 5c The overall electric field magnitude shown is lower than that of Figure 5a and Figure 5b , and the low peak electric field distribution range is wider and its electric field distribution is more uniform. It can be seen that Figure 5cThe improvement of the medium-wide low-peak electric field distribution and uniformity directly raises the threshold of the field plate breakdown voltage, and the wide-range low-peak electric field distribution region effectively improves the carrier mobility between the source and the drain and reduces the field plate on-resistance; that is Figure 5c The shown hybrid high-voltage LDMOS device can have both a relatively high breakdown voltage and a relatively low on-resistance compared with a pure STI-type field plate structure or a pure ROX-type field plate structure.

[0046] It should also be noted that Figure 5a The ratio of the breakdown voltage (V) to the on-resistance (Ω) of the shown pure STI-type field plate structure is 0.379, Figure 5b The ratio of the breakdown voltage (V) to the on-resistance (Ω) of the shown pure ROX-type field plate structure is 0.242, Figure 5c The ratio of the breakdown voltage (V) to the on-resistance (Ω) of the shown hybrid high-voltage LDMOS device is 0.484, which proves that the hybrid high-voltage LDMOS device can have both a relatively high breakdown voltage and a relatively low on-resistance compared with a pure STI-type field plate structure or a pure ROX-type field plate structure.

[0047] It can be seen that while the above-mentioned hybrid high-voltage LDMOS device is provided with a shallow trench isolation region 4 inside the N-type drift region 3, a thick oxide layer 5 is provided on the surfaces of the P-type drift region 2 and the N-type drift region 3, mixing the shallow trench isolation layer and the thick oxide layer 5 on the field plate surface, so that the shallow trench isolation region 4 and the thick oxide layer 5 jointly affect the electric field between the source 6 and the drain 8, significantly improving the longitudinal electric field distribution, enabling the hybrid high-voltage LDMOS device to achieve a breakdown voltage superior to that of a pure shallow trench isolation field plate structure or a pure oxide layer field plate structure, and having a lower on-resistance and a longer hot carrier injection lifetime compared with a pure shallow trench isolation and a pure oxide layer structure, solving the problem of the short hot carrier injection effect lifetime based on a pure oxide layer structure.

[0048] The second aspect of the embodiments of the present invention provides a method for manufacturing a hybrid high-voltage LDMOS, which is applicable to manufacturing a hybrid high-voltage LDMOS device according to any one of the first aspect of the present invention, and includes the following steps: Determine a substrate 1, and then form an N-type drift region 3 on one side of the surface of the substrate 1, a shallow trench isolation region 4 is provided inside the N-type drift region 3, and a P-type drift region 2 is formed on the other side of the surface of the substrate 1; Form a thick oxide layer 5 on the surfaces of the P-type drift region 2 and the N-type drift region 3; Inject P-type impurities into the P-type drift region 2 to form a P-type body region 21; Form a gate 7 on the surfaces of the P-type drift region 2 and the thick oxide layer 5; High-concentration N-type impurities are respectively implanted into the P-type body region 21 and the N-type drift region 3 to form a source electrode 6 inside the P-type body region 21 and a drain electrode 8 inside the N-type drift region 3; High-concentration P-type impurities are implanted into the P-type body region 21 to form a high-concentration P-type doped region 211.

[0049] See Figures 16 - 19 , preferably, the determining the substrate 1, and then forming an N-type drift region 3 on one side of the surface of the substrate 1, a shallow trench isolation region 4 is provided inside the N-type drift region 3, and a P-type drift region 2 is formed on the other side of the surface of the substrate 1, including: Determine the substrate 1, and implant an N-type buried layer 11 on the surface of the substrate 1; Grow an epitaxial layer 12 on the surface of the N-type buried layer 11; Form a shallow trench isolation region 4 in the active region of the epitaxial layer 12; Inject N-type impurities into one side of the epitaxial layer 12 to form an N-type drift region 3 surrounding the shallow trench isolation region 4; Inject P-type impurities into the other side of the epitaxial layer 12 to form a P-type drift region 2.

[0050] See Figures 19 - 21 , preferably, the forming a thick oxide layer 5 on the surfaces of the P-type drift region 2 and the N-type drift region 3, including: Deposit a first oxide layer 51 on the surfaces of the P-type drift region 2 and the N-type drift region 3; Perform photolithography on the first oxide layer 51 to form a thick oxide layer pattern; Etch the first oxide structure based on the thick oxide layer pattern, thereby forming the thick oxide layer 5.

[0051] See Figures 21 - 22 , preferably, the injecting P-type impurities into the P-type drift region 2 to form a P-type body region 21, including: Perform photolithography on the P-type drift region 2 to form a P-type body doping pattern; Inject P-type impurities into the P-type drift region 2 based on the P-type body doping pattern, thereby forming a P-type body region 21 in the P-type drift region 2.

[0052] See Figures 22 - 24 , preferably, the forming a gate electrode 7 on the surfaces of the P-type drift region 2 and the thick oxide layer 5, including: Grow a second oxide layer 71 on the surfaces of the P-type drift region 2 and the thick oxide layer 5; Deposit a polysilicon layer on the surface of the second oxide layer 71; Etch the second oxide layer 71 and the polysilicon layer to form the gate 7.

[0053] See Figures 24 - 25 , preferably, the step of separately injecting high-concentration N-type impurities into the P-type body region 21 and the N-type drift region 3 to form a source electrode 6 inside the P-type body region 21 and a drain electrode 8 inside the N-type drift region 3 includes: Perform photolithography on the P-type body region 21 and the N-type drift region 3 respectively to form a source doping pattern and a drain doping pattern; Inject high-concentration N-type impurities into the P-type body region 21 based on the source doping pattern, thereby forming a source electrode 6 in the P-type body region 21; Inject high-concentration N-type impurities into the N-type drift region 3 based on the drain doping pattern, thereby forming a drain electrode 8 in the N-type drift region 3.

[0054] See Figures 24 - 25 , preferably, the step of injecting high-concentration P-type impurities into the P-type body region 21 to form a high-concentration P-type doping region 211 includes: Perform photolithography on the P-type body region 21 to form a high-concentration P-type doping pattern; Inject P-type impurities into the P-type drift region 2 based on the high-concentration P-type doping pattern, thereby forming a high-concentration P-type doping region 211 in the P-type drift region 2.

[0055] According to a hybrid high-voltage LDMOS device and a manufacturing method thereof provided by the present invention, compared with the prior art, it has at least the following advantages: First, while a shallow trench isolation region 4 is arranged inside the N-type drift region 3 of the above hybrid high-voltage LDMOS device, a thick oxide layer 5 is arranged on the surfaces of the P-type drift region 2 and the N-type drift region 3, mixing the shallow trench isolation layer and the thick oxide layer 5 on the surface of the field plate, so that the shallow trench isolation region 4 and the thick oxide layer 5 jointly affect the electric field between the source electrode 6 and the drain electrode 8, significantly improving the longitudinal electric field distribution, enabling the hybrid high-voltage LDMOS device to achieve a breakdown voltage superior to that of a pure shallow trench isolation field plate structure or a pure oxide layer field plate structure, and having a lower on-resistance and a longer hot carrier injection lifetime compared with the pure shallow trench isolation and pure oxide layer structures, solving the problem of short hot carrier injection effect lifetime based on a pure oxide layer structure.

[0056] Secondly, in the above hybrid high-voltage LDMOS device, the shallow trench isolation region 4 is disposed directly below the thick oxide layer 5, such that the top of the shallow trench isolation region 4 and the bottom of the thick oxide layer 5 completely overlap, forming a hybrid drain 8 oxide structure, thereby avoiding the problem of weak breakdown voltage points generated at the boundary between the shallow trench isolation region 4 and the thick oxide layer 5. Further, disposing the shallow trench isolation region 4 directly below the middle of the thick oxide layer 5 can improve the hybrid electric field generated by the two. Compared with disposing the shallow trench isolation region 4 below the boundary of the thick oxide layer 5, it has a larger breakdown voltage and a smaller on-resistance, which is beneficial to meet the product applications with low power consumption requirements and the product applications with high life requirements.

[0057] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the various embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tapes, floppy disks, flash memories, optical memories, high-density embedded non-volatile memories, resistive random access memories (ReRAMs), magnetoresistive random access memories (MRAMs), ferroelectric random access memories (FRAMs), phase change memories (PCMs), graphene memories, etc. Volatile memories can include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the various embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the various embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logics, data processing logics based on quantum computing, etc., without limitation.

[0058] As used herein, "embodiments" means that the specific features, structures, or characteristics described in connection with the embodiments may be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as falling within the scope recorded in this specification.

[0059] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several improvements and substitutions can be made, and these improvements and substitutions should also be regarded as within the protection scope of the present invention. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A hybrid high-voltage LDMOS device, characterized in that, It includes a substrate, a P-type drift region, a P-type body region, a high-concentration P-type doping region, an N-type drift region, a shallow trench isolation region, a thick oxide layer, a source electrode, a gate electrode, and a drain electrode, where: the P-type drift region is located on one side of the substrate surface, the N-type drift region is located on the other side of the substrate surface, and the P-type drift region is connected to the N-type drift region; the P-type body region is located inside the P-type drift region; the high-concentration P-type doping region and the source electrode are located inside the P-type body region; the high-concentration P-type doping region is connected to the source electrode; the drain electrode is located inside the N-type drift region; the shallow trench isolation region is located inside the N-type drift region, and the shallow trench isolation region is located between the source electrode and the drain electrode; the thick oxide layer is located on the surfaces of the P-type drift region and the N-type drift region; the gate electrode is located on the surfaces of the P-type drift region and the thick oxide layer.

2. The hybrid high-voltage LDMOS device according to claim 1, wherein The shallow trench isolation region is located directly below the middle of the thick oxide layer.

3. A hybrid high-voltage LDMOS device according to claim 2, characterized in that, The boundary of the gate electrode is aligned with the center of the thick oxide layer, and the shallow trench isolation region is located directly below the gate electrode.

4. A method for fabricating a hybrid high-voltage LDMOS, characterized in that, It is applicable to the preparation of a hybrid high-voltage LDMOS device as described in any one of claims 1 to 3, and it includes the following steps: Determine the substrate, and then form an N-type drift region on one side of the substrate surface. A shallow trench isolation region is provided inside the N-type drift region, and a P-type drift region is formed on the other side of the substrate surface; Form a thick oxide layer on the surfaces of the P-type drift region and the N-type drift region; Inject P-type impurities into the P-type drift region to form a P-type body region; Form a gate electrode on the surfaces of the P-type drift region and the thick oxide layer; Inject high-concentration N-type impurities into the P-type body region and the N-type drift region respectively to form a source electrode located inside the P-type body region and a drain electrode located inside the N-type drift region; Inject high-concentration P-type impurities into the P-type body region to form a high-concentration P-type doping region.

5. A method for fabricating a hybrid high-voltage LDMOS according to claim 4, wherein, The step of determining the substrate, and then forming an N-type drift region on one side of the substrate surface. A shallow trench isolation region is provided inside the N-type drift region, and a P-type drift region is formed on the other side of the substrate surface, includes: Grow an epitaxial layer on the substrate surface; Form a shallow trench isolation region in the active region of the epitaxial layer; Inject N-type impurities into one side of the epitaxial layer to form an N-type drift region that wraps the shallow trench isolation region; Inject P-type impurities into the other side of the epitaxial layer to form a P-type drift region.

6. A method for fabricating a hybrid high-voltage LDMOS according to claim 4, wherein The step of forming a thick oxide layer on the surfaces of the P-type drift region and the N-type drift region, includes: Deposit a first oxide layer on the surfaces of the P-type drift region and the N-type drift region; Perform photolithography on the first oxide layer to form a thick oxide layer pattern; Etch the first oxide structure based on the thick oxide layer pattern to form the thick oxide layer.

7. A method for fabricating a hybrid high-voltage LDMOS according to claim 4, wherein The step of injecting P-type impurities into the P-type drift region to form a P-type body region, includes: Perform photolithography on the P-type drift region to form a P-type body doping pattern; Inject P-type impurities into the P-type drift region based on the P-type body doping pattern to form a P-type body region in the P-type drift region.

8. A method for fabricating a hybrid high-voltage LDMOS according to claim 4, wherein The step of forming a gate electrode on the surfaces of the P-type drift region and the thick oxide layer, includes: Grow a second oxide layer on the surface of the P-type drift region and the thick oxide layer; Deposit a polysilicon layer on the surface of the second oxide layer; Etch the second oxide layer and the polysilicon layer to form the gate; 9. A method for fabricating a hybrid high-voltage LDMOS according to claim 4, wherein The steps of respectively implanting high-concentration N-type impurities into the P-type body region and the N-type drift region to form a source electrode inside the P-type body region and a drain electrode inside the N-type drift region include: Perform photolithography on the P-type body region and the N-type drift region respectively to form a source doping pattern and a drain doping pattern; Based on the source doping pattern, implant high-concentration N-type impurities into the P-type body region to form a source electrode in the P-type body region; Based on the drain doping pattern, implant high-concentration N-type impurities into the N-type drift region to form a drain electrode in the N-type drift region; 10. A method for fabricating a hybrid high-voltage LDMOS according to claim 4, characterized in that, The steps of implanting high-concentration P-type impurities into the P-type body region to form a high-concentration P-type doped region include: Perform photolithography on the P-type body region to form a high-concentration P-type doping pattern; Based on the high-concentration P-type doping pattern, implant P-type impurities into the P-type drift region to form a high-concentration P-type doped region in the P-type drift region.

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