Array substrate, preparation method thereof and display device

Abstract

The invention provides an array substrate, a preparation method thereof and a display device, belongs to the technical field of display, and can solve the problem that fan-out wiring of the array substrate is prone to poor corrosion and poor scratch. The preparation method of the array substrate comprises the following steps: exposing a part, corresponding to a display area and a part, corresponding to a fan-out area, of an organic film layer by using a mask plate to respectively form a first opening and a first groove; the transmittance of the mask plate corresponding to the first opening part is different from the transmittance of the mask plate corresponding to the first groove part; performing ashing treatment on the part, corresponding to the first opening, of the first passivation layer and the part, corresponding to the first groove, of the organic film layer by using first plasma gas so as to remove the first passivation layer and reduce the thickness of the organic film layer; performing ashing treatment on the part, corresponding to the first groove, of the organic film layer by using second plasma gas so as to remove the organic film layer and form a second opening; and forming a second passivation layer on one side, deviating from the substrate, of the organic film layer.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] Electronic paper is a paper-like display product. Its working principle is to rely on the electrophoresis of black particles and white particles under the action of voltage to form black and white colors. Due to its reflective display and low power consumption, it has potential application value in the traditional supermarket price tag field and warehouse material management. Summary of the invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides an array substrate and a preparation method thereof, and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a method for preparing an array substrate, wherein the array substrate has a display area and a fan-out area disposed on one side of the display area, and the method for preparing the array substrate comprises:

[0005] providing a substrate base plate;

[0006] A driving circuit layer is formed on the base substrate; the driving circuit layer comprises: a thin film transistor arranged in the display area and a fan-out wiring arranged in the fan-out area;

[0007] Forming a first passivation layer and an organic film layer in sequence on a side of the driving circuit layer away from the base substrate;

[0008] Using a mask plate, the organic film layer corresponding to the display area and the fan-out area are exposed to form a first opening and a first groove respectively; the orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the drain of the thin film transistor on the substrate; the orthographic projection of the first groove on the substrate at least partially overlaps with the orthographic projection of the fan-out wiring on the substrate; the transmittance of the mask plate corresponding to the first opening is different from the transmittance of the mask plate corresponding to the first groove;

[0009] Using a first plasma gas, etching the first passivation layer corresponding to the first opening and the organic film layer corresponding to the first groove, so as to remove the first passivation layer and reduce the thickness of the organic film layer;

[0010] Using a second plasma gas, ashing the portion of the organic film layer corresponding to the first groove to remove the organic film layer to form a second opening;

[0011] A second passivation layer is formed on a side of the organic film layer facing away from the substrate; the second passivation layer covers the driving circuit layer in the display area and the first passivation layer in the fan-out area.

[0012] In some embodiments, after using a second plasma gas to asher the corresponding portion of the organic film layer of the first groove to remove the organic film layer to form a second opening, the method further includes:

[0013] Using a third plasma gas to roughen the surface of the organic film layer.

[0014] In some embodiments, the first passivation layer is formed by a high-temperature deposition process; the second passivation layer is formed by a low-temperature deposition process.

[0015] In some embodiments, the organic film layer is made of a positive organic material, and the transmittance of the mask plate corresponding to the first opening portion is greater than the transmittance corresponding to the first groove portion.

[0016] In some embodiments, the organic film layer is made of a negative organic material, and the transmittance of the mask plate corresponding to the first opening portion is less than the transmittance corresponding to the first groove portion.

[0017] In some embodiments, after forming the second passivation layer on a side of the organic film layer facing away from the substrate, the method further includes:

[0018] Etching the corresponding portion of the second passivation layer of the first opening to form a first via hole to expose the drain electrode of the thin film transistor;

[0019] Forming a pixel electrode in the corresponding display area portion of the second passivation layer; the pixel electrode is connected to the drain electrode of the thin film transistor through the first via hole; the positive projection of the pixel electrode on the substrate at least partially overlaps with the positive projection of the first opening on the substrate.

[0020] In some embodiments, before forming the pixel electrode in the corresponding display area portion of the second passivation layer, the method further includes:

[0021] Forming a metal light-shielding layer in the corresponding display area portion of the second passivation layer; the positive projection of the metal light-shielding layer on the substrate at least partially overlaps with the positive projection of the active layer of the thin film transistor on the substrate.

[0022] In some embodiments, the metal light-shielding layer is attached to a side of the pixel electrode close to the substrate, and the metal light-shielding layer is connected to the drain electrode of the thin film transistor through the first via hole.

[0023] In some embodiments, forming a driving circuit layer on the substrate substrate includes:

[0024] Forming a gate, a gate insulating layer, an active layer, a source electrode, and a drain electrode on the substrate substrate in sequence; the source electrode and the drain electrode are disposed in the same layer and are respectively connected to two ends of the active layer.

[0025] In some embodiments, forming a driving circuit layer on the substrate substrate further includes:

[0026] Forming an auxiliary electrode and a common electrode on the substrate substrate corresponding to the first opening region in sequence; the auxiliary electrode is disposed in the same layer as the gate; the common electrode is disposed in the same layer as the source electrode; the auxiliary electrode is connected to the drain electrode; the positive projection of the common electrode on the substrate substrate at least partially overlaps with the positive projection of the pixel electrode on the substrate substrate; the positive projection of the auxiliary electrode on the substrate substrate at least partially overlaps with the positive projection of the common electrode on the substrate substrate.

[0027] In some embodiments, before forming the source electrode and the drain electrode on the substrate substrate, it further includes:

[0028] Forming a through second via hole in the gate insulating layer; the auxiliary electrode is connected to the drain electrode through the second via hole.

[0029] In a second aspect, an embodiment of the present disclosure provides an array substrate, which has a display area and a fan-out area disposed on one side of the display area, and includes: a substrate substrate, a driving circuit layer, a first passivation layer, an organic film layer, and a second passivation layer that are sequentially stacked on the substrate substrate; the driving circuit layer includes: thin film transistors disposed in the display area and fan-out traces disposed in the fan-out area;

[0030] The organic film layer respectively forms a first opening and a second opening in the display area and the fan-out area;

[0031] The positive projection of the first opening on the substrate substrate at least partially overlaps with the positive projection of the drain electrode of the thin film transistor on the substrate substrate;

[0032] The positive projection of the second opening on the substrate substrate at least partially overlaps with the positive projection of the fan-out trace on the substrate substrate;

[0033] The positive projection of the first passivation layer on the substrate substrate has no overlap with the positive projection of the first opening on the substrate substrate, and at least partially overlaps with the positive projection of the second opening on the substrate substrate;

[0034] The positive projection of the second passivation layer on the substrate substrate at least partially overlaps with the positive projection of the second opening and on the second opening.

[0035] In some embodiments, at the second opening, the sum of the film thicknesses of the first passivation layer and the second passivation layer is greater than or equal to 3500 angstroms.

[0036] In a third aspect, an embodiment of the present disclosure provides a display device, and the display device includes an array substrate provided as in the second aspect above. Description of the Drawings

[0037] Figure 1 It is a schematic structural diagram of an exemplary array substrate.

[0038] Figure 2 It is a schematic flowchart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure.

[0039] Figures 3a to 3h For Figure 2 Schematic diagrams of intermediate structures corresponding to each step in the method for manufacturing the array substrate shown. Detailed Embodiments

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some, but not all, of the embodiments of the present disclosure. The components of the embodiments of the present disclosure described and illustrated herein generally can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure claimed, but merely represents selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure. Without conflict, the various embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0041] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meaning as understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, terms such as "a", "one", or "the" do not denote a quantity limitation, but mean that there is at least one. Terms such as "comprising" or "including" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items.

[0042] As used in this disclosure, "a plurality of" or "several" means two or more. "And / or" describes the relationship between related objects and indicates that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates an "or" relationship between the related objects before and after.

[0043] Figure 1 FIG. is a schematic structural diagram of an exemplary array substrate, as Figure 1 shown, the array substrate has a display area AA and a fan-out area BB disposed on one side of the display area AA. The array substrate includes: a substrate 100, a driving circuit layer, a first passivation layer PVX-0, an organic film layer ORG, a second passivation layer PVX-1, and a pixel electrode Pixel that are sequentially stacked on the substrate 100; the driving circuit layer includes: thin film transistors disposed in the display area AA and fan-out traces Fanout Line disposed in the fan-out area BB.

[0044] In order to increase the storage capacitance Cst of each pixel, usually, a part of the organic film layer ORG in the display area AA and the fan-out area BB is removed to form a first opening O1 and a second opening O2, and the first passivation layer PVX-0 corresponding to the first opening O1 and the second opening O2 is etched to reduce the distance between the pixel electrode Pixel and the common electrode Vcom. It should be noted here that the first opening O1 is in the display area AA, and the organic film layer ORG can be disposed around it. The second opening O2 is in the fan-out area BB. Since the organic film layer ORG needs to be cut off in the fan-out area BB, the second opening O2 can only have the organic film layer ORG disposed on the side close to the display area AA, that is, the second opening O2 is not an actual annular opening.

[0045] However, after the first passivation layer PVX-0 is etched, only a layer of the second passivation layer PVX-1 covers the upper part of the fan-out trace Fanout Line. The thickness of the second passivation layer PVX-1 is small, and the coverage performance is poor. During the reliability process, the fan-out trace Fanout Line is prone to corrosion defects due to water vapor intrusion at the corresponding position of the edge of the organic film layer ORG (i.e., the edge of the second opening O2), and is prone to scratch defects due to external force damage at the position without the organic film layer ORG coverage.

[0046] In order to at least solve one of the above technical problems, an embodiment of the present disclosure provides an array substrate, a preparation method thereof, and a display device. Below, the array substrate, the preparation method thereof, and the display device provided by the embodiment of the present disclosure will be further described in detail with reference to the drawings and specific embodiments.

[0047] In a first aspect, an embodiment of the present disclosure provides a method for preparing an array substrate,Figure 2 Schematic flow chart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure Figures 3a to 3h For Figure 2 Schematic diagrams of intermediate structures corresponding to each step in the method for manufacturing the array substrate shown below. The method for manufacturing the array substrate provided by an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. As Figure 2 shown, the method for manufacturing the array substrate includes the following steps S201 to S207.

[0048] S201, Provide a substrate.

[0049] As Figure 3a shown, the substrate 100 can be made of a rigid material such as glass, which can improve the load-bearing capacity of the substrate 100 for other film layers thereon. Of course, the substrate 100 can also be made of a flexible material such as polyimide (PI), which can improve the anti-bending and anti-stretching properties of the array substrate, and avoid the substrate 100 from breaking due to stress generated during bending, stretching, and twisting, resulting in open-circuit defects. In practical applications, the material of the substrate 100 can be reasonably selected according to actual needs to ensure that the array substrate has good performance.

[0050] S202, Form a driving circuit layer on the substrate; the driving circuit layer includes: thin film transistors disposed in the display area and fan-out traces disposed in the fan-out area.

[0051] As Figure 3b shown, a plurality of pixels will be formed in the display area AA of the array substrate, and each pixel can be arranged according to a certain rule. For example, it can be arranged in a multi-row and multi-column manner, or in other ways. Usually, a pixel driving circuit composed of a plurality of thin film transistors is provided in each pixel to provide a driving signal. The pixel driving circuits in the display area AA of the array substrate can usually be connected to a driving chip through the fan-out traces Fanout Line in the fan-out area BB to transmit the required driving signals.

[0052] Specifically, the thin film transistors of the driving circuit layer formed in this step may include a gate (Gate), an active layer (Active), a source (Source), and a drain (Drain). Among them, the gate (Gate) can be connected to a gate control line (not shown in the figure) to send a control signal by the gate control line, and the source (Source) can be connected to a data line (not shown in the figure) to provide a data signal by the data line. In some embodiments, the preparation process of the thin film transistor specifically includes sequentially forming a gate (Gate), a gate insulating layer (GI), an active layer (Active), a source (Source), and a drain (Drain) on the substrate 100; the source (Source) and the drain (Drain) are arranged on the same layer and are respectively connected to both ends of the active layer (Active). For example, the source (Source) and the drain (Drain) respectively overlap both ends of the above-mentioned active layer (Active).

[0053] S203. A first passivation layer and an organic film layer are sequentially formed on the side of the driving circuit layer facing away from the substrate.

[0054] As Figure 3c shown, the first passivation layer (PVX-0) and the organic film layer (ORG) can play the roles of insulation and planarization. At the same time, the organic film layer (ORG) can improve the anti-bending and anti-stretching properties of the array substrate, and avoid the stress generated during bending, stretching, and twisting from causing the array substrate to break and resulting in an open circuit defect.

[0055] The first passivation layer (PVX-0) can be made of at least one of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., and the organic film layer (ORG) can be made of at least one of organic materials such as parylene, polymethyl methacrylate (PMMA), polytetrafluoroethylene (PTFE), photosensitive resin, etc. In the embodiments of the present disclosure, taking the material of the first passivation layer (PVX-0) as silicon nitride (SiNx) and the material of the organic film layer (ORG) as photosensitive resin as an example for description, wherein, the film thicknesses of the first passivation layer (PVX-0) and the organic film layer (ORG) can be adjusted according to product requirements. For example, the film thickness of the first passivation layer (PVX-0) can be set between 500 angstroms (A) and 10,000 A, preferably, its film thickness can be set to 3500 A. The film thickness of the organic film layer (ORG) can be set between 5000 A and 30,000 A, preferably, its film thickness can be set to 2.2 μm (22,000 A).

[0056] S204. Using a mask plate, the corresponding display area part and the corresponding fan-out area part of the organic film layer are exposed to respectively form a first opening and a first groove.

[0057] As Figure 3dAs shown, when the organic film layer ORG is made of a positive organic material, the corresponding display area AA part of the mask plate used can specifically be a full-tone mask, which is provided with a transparent area and a non-transparent area. The transmittance of the transparent area can be 100%, and the transmittance of the non-transparent area is 0. Align the transparent area in the mask plate with the part of the organic film layer ORG to be etched, and align the non-transparent area with the part of the organic film layer ORG to be retained, then perform exposure, and then perform an annealing treatment. The annealing process conditions are 230°C / 32 min. In this way, a first opening O1 can be formed in the organic film layer ORG, and the first opening O1 can expose the drain of the thin film transistor. At this time, the thickness of the part of the organic film layer ORG to be etched is 0, and the thickness of the part of the organic film layer ORG to be retained is 2.2 μm. The positive projection of the first opening O1 on the substrate 100 and the positive projection of the drain of the thin film transistor on the substrate 100 overlap at least partially to expose the drain of the thin film transistor.

[0058] Continue to refer to Figure 3d , the corresponding fan-out area BB part of the mask plate can specifically be a half-tone mask (Half-tone Mask), which is provided with a partially transparent area and a non-transparent area. The transmittance of the non-transparent area is 0, and the transmittance of the partially transparent area can be adjusted between 5% and 95%. When the transmittance is 20%, the production capacity is the best. Therefore, in the embodiments of the present disclosure, the case where the transmittance is 20% is taken as an example for description. Align the partially transparent area in the mask plate with the part of the organic film layer ORG to be etched, and align the non-transparent area with the part of the organic film layer ORG to be retained, then perform exposure, and then perform an annealing treatment. The annealing process conditions are 230°C / 32 min. Since the transmittance of the partially transparent area of the mask plate is only 20%, the organic film layer ORG cannot be completely etched through. In this way, a first groove can be formed in the organic film layer ORG. Among them, the thickness of the part of the organic film layer ORG to be etched is 0.2 μm (2000 Å), and the thickness of the part of the organic film layer ORG to be retained (inside the first groove) is 2.2 μm. The positive projection of the first groove on the substrate 100 and the positive projection of the fan-out line Fanout Line on the substrate 100 overlap at least partially.

[0059] S205, use the first plasma gas to etch the first opening part of the first passivation layer and the first groove part of the organic film layer to remove the first passivation layer and reduce the thickness of the organic film layer.

[0060] As Figure 3eAs shown, the first plasma gas can be sulfur hexafluoride gas SF6 and oxygen O2. The first plasma gas is used to etch the first opening O1 portion of the first passivation layer PVX-0 and the first groove portion of the organic film layer ORG. It can only remove the thinner first passivation layer PVX-0. Since the etching effect of the first plasma gas is limited, the organic film layer ORG can only be thinned, that is, part of the film thickness of the organic film layer ORG can be removed. This avoids protecting the first passivation layer PVX-0 under the organic film layer ORG in the fan-out area BB, and prevents damage to the first passivation layer PVX-0 in the fan-out area BB.

[0061] S206, using a second plasma gas to perform an ashing process on the portion of the organic film layer corresponding to the first groove to remove the organic film layer and form a second opening.

[0062] like Figure 3f As shown, the second plasma gas can be oxygen O2, and the second plasma gas is used to ash the portion of the organic film layer ORG corresponding to the first groove. Since the etching effect of the second plasma gas is worse than that of the first plasma gas, it can only remove the portion of the organic film layer ORG corresponding to the first groove, and has no effect on the first passivation layer PVX-0 exposed in the first opening O1. In this way, the first passivation layer PVX-0 exposed in the opening O1 can be protected to form the second opening O2 of the organic film layer ORG.

[0063] S207, forming a second passivation layer on the side of the organic film layer facing away from the substrate.

[0064] like Figure 3g As shown, the second passivation layer PVX-1 can be made of at least one of inorganic materials such as silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc. The film thickness of the second passivation layer PVX-1 can be adjusted according to product requirements. For example, the film thickness of the second passivation layer PVX-1 can be set between 500A and 2000A. Preferably, its film thickness can be set to 1500A. The second passivation layer PVX-1 can directly cover the driving circuit layer in the display area AA and the first passivation layer PVX-0 in the fan-out area BB through the first opening O1 and the second opening O2.

[0065] In the method for manufacturing an array substrate provided by an embodiment of the present disclosure, a mask plate exposure and a plasma gas ashing method are used to remove the first passivation layer PVX-0 in the first opening O1 of the organic film layer ORG, and the first passivation layer PVX-0 and the second passivation layer PVX-1 in the second opening O2 are retained. In this way, the fanout line can be covered by a double-layer structure composed of the first passivation layer PVX-0 and the second passivation layer PVX-1 in the second opening O2. When the film thickness of the second passivation layer PVX-1 is small, the film thickness of the first passivation layer PVX-0 can be adjusted so that the overall film thickness of the double-layer structure formed by the two reaches a preset value (for example, 3500 Å). Therefore, the coverage performance of the film layer above the fanout line can be ensured, and it is possible to avoid corrosion defects caused by water vapor intrusion at the corresponding position of the fanout line at the edge of the organic film layer ORG (i.e., the edge of the second opening O2), and at the same time, it is possible to avoid scratch defects caused by external force damage to the fanout line at the position without the coverage of the organic film layer ORG, thereby improving the display effect of the array substrate and enhancing the user experience.

[0066] Here, it should be noted that in the above step S204, taking the case where the organic film layer ORG is made of a positive organic material as an example for illustration, it can be understood that the organic film layer ORG can also be made of a negative organic material.

[0067] As Figure 3d’ shown, when the organic film layer ORG is made of a negative organic material, the corresponding display area AA part of the mask plate used can specifically be a full-tone mask, which is provided with a transparent area and a non-transparent area. The transmittance of the transparent area can be 100%, and the transmittance of the non-transparent area is 0. Align the non-transparent area in the mask plate with the part of the organic film layer ORG that needs to be etched, and align the transparent area with the part of the organic film layer ORG that needs to be retained, and then perform exposure, and then perform an annealing treatment. The annealing process conditions are 230 °C / 32 min. In this way, a first opening O1 can be formed in the organic film layer ORG, and the first opening O1 can expose the drain of the thin film transistor. At this time, the thickness of the part of the organic film layer ORG that needs to be etched is 0, and the thickness of the part of the organic film layer ORG that needs to be retained is 2.2 μm. The positive projection of the first opening O1 on the substrate 100 overlaps at least partially with the positive projection of the drain of the thin film transistor on the substrate 100 to expose the drain of the thin film transistor.

[0068] Continue to refer to Figure 3d’, the BB part of the fan-out area corresponding to the mask plate can specifically be a half-tone mask, which is provided with a partial transparent area and a transparent area. The transmittance of the transparent area is 100%, and the transmittance of the partial transparent area can be adjusted between 5% and 95%. When the transmittance is 20%, the production capacity is the best. Therefore, in the embodiments of the present disclosure, the case where the transmittance is 20% is taken as an example for description. Align the partial transparent area in the mask plate with the part of the organic film layer ORG to be etched, and align the transparent area with the part of the organic film layer ORG to be retained, and then perform exposure, and then perform an annealing treatment. The annealing process conditions are 230°C / 32 min. Since the transmittance of the partial transparent area of the mask plate is only 20%, the organic film layer ORG cannot be completely etched through, so that a first groove can be formed in the organic film layer ORG. Among them, the thickness of the part of the organic film layer ORG to be etched is 0.2 μm (2000 Å), and the thickness of the part of the organic film layer ORG to be retained (inside the first groove) is 2.2 μm. The orthographic projection of the first groove on the substrate 100 overlaps at least partially with the orthographic projection of the fan-out trace Fanout Line on the substrate 100.

[0069] In some embodiments, as Figure 2 shown, in the above step S206, using a second plasma gas, the part of the organic film layer corresponding to the first groove is ashed to remove the organic film layer to form a second opening. After that, it further includes: step S206A, using a third plasma gas, the surface of the organic film layer is roughened.

[0070] In the above step S206A, the third plasma gas can be helium gas He. Using the third plasma gas to roughen the surface of the organic film layer can increase the surface roughness of the organic film layer ORG, enhance the adhesion between the subsequent second passivation layer PVX-1 and the organic film layer ORG, improve the riveting effect of the two, and reduce the intrusion of water vapor.

[0071] In some embodiments, the first passivation layer PVX-0 is formed by a high-temperature deposition process; the second passivation layer PVX-1 is formed by a low-temperature deposition process.

[0072] During the deposition of the first passivation layer PVX-0, due to the absence of the influence of the organic film layer ORG, its deposition density is relatively large, which can improve the coverage performance of the underlying fan-out line. Since the second passivation layer PVX-1 is deposited on the organic film layer ORG, in order to avoid damaging the formed organic film layer ORG during the deposition of the second passivation layer PVX-1, the second passivation layer PVX-1 is formed by a low-temperature deposition process. Taking the example that both the first passivation layer PVX-0 and the second passivation layer PVX-1 are made of silicon nitride SiNx, the high-temperature deposition temperature can be selected from 250 to 400 °C, the high-temperature annealing temperature can be selected from 180 °C to 280 °C, and the annealing duration can be 20 to 40 minutes. For example, the deposition temperature can be selected as 400 °C, the annealing temperature can be 230 °C, and the annealing duration can be 32 minutes.

[0073] In some embodiments, as Figure 2 shown, in step S207 above, a second passivation layer is formed on the side of the organic film layer facing away from the substrate. After that, it further includes: steps S208 to S210.

[0074] S208, etching the corresponding first opening part of the second passivation layer to form a first via hole to expose the drain of the thin-film transistor.

[0075] S209, forming a metal light-shielding layer on the corresponding display area part of the second passivation layer.

[0076] S210, forming a pixel electrode on the side of the metal light-shielding layer facing away from the substrate.

[0077] As Figure 3g shown, by etching the corresponding first opening O1 part of the second passivation layer PVX-1, a first via hole V1 penetrating the second passivation layer PVX-1 can be formed, and the first via hole V1 can expose the drain Drain of the thin-film transistor, facilitating connection with the subsequent pixel electrode.

[0078] As Figure 3h shown, the metal light-shielding layer Metal is attached to the side of the pixel electrode Pixel close to the substrate 100, and the metal light-shielding layer Metal is connected to the drain Drain of the thin-film transistor through the first via hole V1. The positive projection of the metal light-shielding layer Metal on the substrate 100 at least partially overlaps with the positive projection of the active layer Active of the thin-film transistor on the substrate 100, which can play a role in blocking light, preventing ambient light from irradiating the active layer Active of the thin-film transistor, and ensuring the stability of the thin-film transistor.

[0079] As Figure 2 shown, in step S202, when forming a driving circuit layer on the substrate, it further includes: sequentially forming an auxiliary electrode and a common electrode in the corresponding first opening area on the substrate.

[0080] As Figure 3b and Figure 3h shown, in the embodiments of the present disclosure, during the process of forming a thin film transistor, an auxiliary electrode Gate1 and a common electrode Vcom are respectively formed. The auxiliary electrode Gate1 is disposed on the same layer as the gate Gate; the common electrode Vcom is disposed on the same layer as the source Source. The auxiliary electrode Gate1 is connected to the drain Drain, and the orthographic projection of the common electrode Vcom on the substrate 100 at least partially overlaps with the orthographic projection of the pixel electrode Pixel on the substrate 100; the orthographic projection of the auxiliary electrode Gate1 on the substrate 100 at least partially overlaps with the orthographic projection of the common electrode Vcom on the substrate 100, such that the pixel electrode Pixel and the auxiliary electrode Gate1 are respectively located on the upper and lower sides of the common electrode Vcom, so that the sum of the capacitances formed between the two and the common electrode Vcom respectively can be used as the actual storage capacitance, which can significantly increase the size of the storage capacitance.

[0081] In some embodiments, as Figure 3b shown, before forming the source Source and the drain Drain on the substrate 100, it further includes: forming a through second via V2 in the gate insulating layer GI; the auxiliary electrode Gate1 is connected to the drain Drain through the second via V2.

[0082] In a second aspect, the embodiments of the present disclosure provide an array substrate, the structure of which can be as Figure 3h shown. The array substrate has a display area AA and a fan-out area BB disposed on one side of the display area AA, and includes: a substrate 100, a driving circuit layer, a first passivation layer PVX-0, an organic film layer ORG, and a second passivation layer PVX-1 that are sequentially stacked on the substrate 100; the driving circuit layer includes: thin film transistors disposed in the display area AA and fan-out lines Fanout Line disposed in the fan-out area BB; the organic film layer ORG respectively forms a first opening O1 and a second opening O2 in the display area AA and the fan-out area BB; the orthographic projection of the first opening O1 on the substrate 100 at least partially overlaps with the orthographic projection of the drain Drain of the thin film transistor on the substrate 100; the orthographic projection of the second opening O2 on the substrate 100 at least partially overlaps with the orthographic projection of the fan-out line Fanout Line on the substrate 100; the orthographic projection of the first passivation layer PVX-0 on the substrate 100 has no overlap with the orthographic projection of the first opening O1 on the substrate 100, and at least partially overlaps with the orthographic projection of the second opening O2 on the substrate 100; the orthographic projection of the second passivation layer PVX-1 on the substrate 100 at least partially overlaps with the orthographic projections of both the second opening O1 and the second opening O2.

[0083] In some embodiments, at the second opening O2, the sum of the film thicknesses of the first passivation layer PVX-0 and the second passivation layer PVX-1 is greater than or equal to 3500 angstroms.

[0084] As can be seen from the description in the above preparation method, the film thickness of the first passivation layer PVX-0 can be set to 3500 Å, and the second passivation layer PVX- can be set to any film thickness. The sum of the film thicknesses of the double-layer structure formed by the two is greater than 3500 Å to ensure that they effectively cover the underlying fan-out line.

[0085] In the array substrate provided by the embodiments of the present disclosure, the first passivation layer PVX-0 in the first opening O1 of the organic film layer ORG is removed, and both the first passivation layer PVX-0 and the second passivation layer PVX-1 in the second opening O2 are retained. In this way, the fan-out line can be covered by the double-layer structure formed by the first passivation layer PVX-0 and the second passivation layer PVX-1 in the second opening O2. When the film thickness of the second passivation layer PVX-1 is small, the film thickness of the first passivation layer PVX-0 can be adjusted so that the overall film thickness of the double-layer structure formed by the two reaches a preset value (for example, 3500 Å). Therefore, the covering performance of the film layer above the fan-out line can be ensured, avoiding corrosion defects caused by moisture intrusion at the corresponding position of the fan-out line at the edge of the organic film layer ORG (i.e., the edge of the second opening O2), and at the same time avoiding scratch defects caused by external force damage at the position where the fan-out line is not covered by the organic film layer ORG, thereby improving the display effect of the array substrate and enhancing the user experience.

[0086] In a third aspect, embodiments of the present disclosure provide a display device. The display device includes the array substrate provided in any of the above embodiments. The display device may specifically be a mobile phone, a wireless device, a personal digital assistant, a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automotive display (e.g., an odometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, etc. The implementation principle and beneficial effects are the same as those of the above array substrate and will not be elaborated herein.

[0087] It should be noted that in the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or an intermediate layer may be present. Additionally, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or more than one intermediate layer or element may be present. Further, it will be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or more than one intermediate layer or element may also be present. Like reference numerals throughout the specification indicate like elements.

[0088] In several embodiments provided by the embodiments of the present disclosure, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the positions of the components shown are only a logical functional position, and there may be other position arrangements in actual implementation.

[0089] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A method for preparing an array substrate, wherein the array substrate has a display area and a fan-out area arranged on one side of the display area, characterized in that: The method for preparing the array substrate comprises: providing a substrate base plate; A driving circuit layer is formed on the base substrate; the driving circuit layer comprises: a thin film transistor arranged in the display area and a fan-out wiring arranged in the fan-out area; Forming a first passivation layer and an organic film layer in sequence on a side of the driving circuit layer away from the base substrate; Using a mask plate, the organic film layer corresponding to the display area and the fan-out area are exposed to form a first opening and a first groove respectively; the orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the drain of the thin film transistor on the substrate; the orthographic projection of the first groove on the substrate at least partially overlaps with the orthographic projection of the fan-out wiring on the substrate; the transmittance of the mask plate corresponding to the first opening is different from the transmittance of the mask plate corresponding to the first groove; Using a first plasma gas, etching the first passivation layer corresponding to the first opening and the organic film layer corresponding to the first groove, so as to remove the first passivation layer and reduce the thickness of the organic film layer; Using a second plasma gas, ashing the portion of the organic film layer corresponding to the first groove to remove the organic film layer to form a second opening; A second passivation layer is formed on the side of the organic film layer away from the base substrate; the second passivation layer covers the driving circuit layer in the display area and the first passivation layer in the fan-out area.

2. The method for preparing an array substrate according to claim 1, characterized in that: The method further comprises: using a second plasma gas to ash the portion of the organic film layer corresponding to the first groove to remove the organic film layer to form a second opening; and then: The organic film layer is subjected to a surface roughening treatment by using a third plasma gas.

3. The method for preparing an array substrate according to claim 1, characterized in that: The first passivation layer is formed by a high temperature deposition process; and the second passivation layer is formed by a low temperature deposition process.

4. The method for preparing an array substrate according to claim 1, wherein: The organic film layer is made of a positive organic material, and the transmittance of the mask corresponding to the first opening portion is greater than the transmittance of the mask corresponding to the first groove portion.

5. The method for preparing an array substrate according to claim 1, characterized in that: The organic film layer is made of a negative organic material, and the transmittance of the mask corresponding to the first opening portion is smaller than the transmittance of the mask corresponding to the first groove portion.

6. The method for preparing an array substrate according to claim 1, characterized in that: The method further comprises forming a second passivation layer on the side of the organic film layer away from the base substrate, and then: Etching the second passivation layer corresponding to the first opening portion to form a first via hole to expose the drain electrode of the thin film transistor; A pixel electrode is formed in the display area portion corresponding to the second passivation layer; the pixel electrode is connected to the drain of the thin film transistor through the first via hole; the orthographic projection of the pixel electrode on the base substrate at least partially overlaps with the orthographic projection of the first opening on the base substrate.

7. The method for preparing an array substrate according to claim 6, characterized in that: Before forming a pixel electrode on a portion of the display area corresponding to the second passivation layer, the method further comprises: A metal light shielding layer is formed on the portion of the second passivation layer corresponding to the display area; an orthographic projection of the metal light shielding layer on the base substrate at least partially overlaps with an orthographic projection of the active layer of the thin film transistor on the base substrate.

8. The method for preparing an array substrate according to claim 7, characterized in that: The metal light shielding layer is attached to a side of the pixel electrode close to the base substrate, and the metal light shielding layer is connected to the drain electrode of the thin film transistor through the first via hole.

9. The method for preparing an array substrate according to claim 7, characterized in that: The step of forming a driving circuit layer on the base substrate comprises: A gate, a gate insulating layer, an active layer, a source electrode and a drain electrode are sequentially formed on a base substrate; the source electrode and the drain electrode are arranged in the same layer and are respectively connected to two ends of the active layer.

10. The method for preparing an array substrate according to claim 9, characterized in that: The step of forming a driving circuit layer on the base substrate further comprises: An auxiliary electrode and a common electrode are sequentially formed on the base substrate corresponding to the first opening area; the auxiliary electrode is arranged on the same layer as the gate; the common electrode is arranged on the same layer as the source; the auxiliary electrode is connected to the drain; the orthographic projection of the common electrode on the base substrate at least partially overlaps with the orthographic projection of the pixel electrode on the base substrate; the orthographic projection of the auxiliary electrode on the base substrate at least partially overlaps with the orthographic projection of the common electrode on the base substrate.

11. The method for preparing an array substrate according to claim 10, characterized in that: Before forming the source and the drain on the substrate, the method further comprises: A second via hole is formed in the gate insulating layer and penetrates through the gate insulating layer; the auxiliary electrode is connected to the drain electrode through the second via hole.

12. An array substrate, characterized in that: The array substrate has a display area and a fan-out area arranged on one side of the display area, and includes: a base substrate, a driving circuit layer located on the base substrate and stacked in sequence, a first passivation layer, an organic film layer, and a second passivation layer; the driving circuit layer includes: a thin film transistor arranged in the display area and a fan-out wiring arranged in the fan-out area; The organic film layer is respectively formed with a first opening and a second opening in the display area and the fan-out area; The orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the drain of the thin film transistor on the substrate; The orthographic projection of the second opening on the substrate at least partially overlaps with the orthographic projection of the fan-out trace on the substrate; The orthographic projection of the first passivation layer on the base substrate does not overlap with the orthographic projection of the first opening on the base substrate, and at least partially overlaps with the orthographic projection of the second opening on the base substrate; An orthographic projection of the second passivation layer on the base substrate at least partially overlaps with the second opening and an orthographic projection on the second opening.

13. The array substrate according to claim 12, characterized in that: At the second opening, the sum of the film thicknesses of the first passivation layer and the second passivation layer is greater than or equal to 3500 angstroms.

14. A display device, characterized in that: The display device comprises the array substrate as claimed in claim 12 or 13.

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