Display panel, using method and forming method thereof and display device

Abstract

The invention discloses a display panel, a using method and forming method thereof and a display device. The display panel comprises a substrate which comprises a display area; wherein the oxide thin film transistor in the display area is a high-mobility oxide thin film transistor; the high-mobility oxide thin film transistor in the display area comprises a first top gate and a first bottom gate; the first top gate and the first bottom gate are electrically insulated. By adopting the scheme, the image quality of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular, to a display panel, a method for using the same, a method for forming the same, and a display device. Background Art

[0002] With the growth of the demand for high-quality displays, the active matrix driving technology has emerged. As the core of modern display technology, a thin film transistor (TFT) is equipped with an independent thin film transistor as a switch for each pixel, which can accurately control the arrangement of liquid crystal molecules, thereby significantly improving the display quality.

[0003] In the early days, amorphous silicon (a-Si) was used as the semiconductor material for thin film transistors, but its carrier mobility was low, resulting in large transistor size and insufficient light transmittance, which limited the improvement of screen resolution.

[0004] The research and development of oxide thin film transistors (such as IGZO) solved this problem. Its carrier mobility is higher, allowing the transistor size to be reduced while maintaining high performance, thus promoting the panel to achieve high-resolution display, supporting finer pixel control and lower power consumption.

[0005] However, for existing display panels including oxide thin film transistors, the image quality is difficult to meet the requirements. Summary of the Invention

[0006] The technical problem solved by the present invention is to improve the image quality of the display panel.

[0007] To solve the above technical problem, an embodiment of the present invention provides a display panel, which includes: a substrate, and the substrate includes a display area; wherein, the oxide thin film transistor in the display area is a high-mobility oxide thin film transistor; the high-mobility oxide thin film transistor in the display area includes: a first top gate and a first bottom gate; the first top gate and the first bottom gate are electrically insulated from each other.

[0008] An embodiment of the present invention also provides a method for forming a display panel, the method includes: providing a first voltage signal to the first top gate of the high-mobility oxide thin film transistor in the display area, and the voltage of the first voltage signal is less than the turn-on voltage of the first transistor; providing a first gate signal to the first bottom gate of the high-mobility oxide thin film transistor in the display area.

[0009] An embodiment of the present invention also provides a method for forming a display panel, the method includes: providing a substrate, the substrate includes a display area and a non-display area; forming high-mobility oxide thin film transistors in the same layer of the display area and the non-display area.

[0010] An embodiment of the present invention further provides a display device, and the display device includes a display panel of any one of the above embodiments.

[0011] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0012] By using the display panel of the embodiment of the present invention, since the oxide thin film transistor in the display area is a high-mobility oxide thin film transistor, and the first top gate and the first bottom gate of the high-mobility oxide thin film transistor in the display area are electrically insulated, during actual use, different electrical signals can be applied to the first top gate and the first bottom gate respectively. Furthermore, different voltages can be applied to the upper and lower surfaces of the channel layer of the high-mobility oxide thin film transistor in the display area, which makes the channel layer of the high-mobility oxide thin film transistor in the display area divided into two independent upper and lower regions and can be controlled separately. As a result, no channel is formed in the upper region of the channel layer of the high-mobility oxide thin film transistor in the display area, and only a channel is formed in the lower region of the channel layer of the high-mobility oxide thin film transistor in the display area. The upper region of the channel layer can serve as a shielding layer for the lower region of the channel layer, enabling the carriers in the lower region of the channel layer to shield the influence of light, improving the NBTIS reliability of the high-mobility oxide thin film transistor in the display area, and enabling the high-mobility oxide thin film transistor to be applied in the display area. Compared with using a traditional oxide thin film transistor in the display area, using a high-mobility oxide thin film transistor in the display area can increase the current flowing through the transistor, and further shorten the time required to reach a set voltage, thereby increasing the refresh rate of the pixel circuit and improving the image quality of the display panel, making the image quality smoother.

[0013] Furthermore, by making the first top gate of the high-mobility oxide thin film transistor in the display area suitable for accessing a first voltage signal and the first bottom gate suitable for accessing a first gate signal, further, in the direction perpendicular to the surface of the substrate, the voltages applied to the upper and lower surfaces of the channel layer of the high-mobility oxide thin film transistor in the display area are different. In this way, no channel is formed in the upper region of the channel layer of the high-mobility oxide thin film transistor in the display area, and only a channel is formed in the lower region of the channel layer of the high-mobility oxide thin film transistor in the display area. Thus, the upper region of the channel layer can serve as a shielding layer for the lower region of the channel layer, enabling the carriers in the lower region of the channel layer to shield the influence of light, thereby improving the NBTIS reliability of the high-mobility oxide thin film transistor in the display area and enabling the high-mobility oxide thin film transistor to be applied in the display area.

[0014] Furthermore, since the high-mobility oxide thin-film transistors in the display area and the non-display area are arranged on the same layer, during the process of manufacturing the oxide thin-film transistors in the display area and the non-display area, lithography operations can be performed on the display area and the non-display area simultaneously, without separately performing lithography operations on the oxide thin-film transistors in the display area, and without forming an insulating layer for isolating the channel layers of the oxide thin-film transistors in the display area and the non-display area. Therefore, not only can the process cycle be shortened, but the number of photomasks can be saved, and the manufacturing cost of the display panel can be reduced. In addition, since the oxide thin-film transistors in the display area and the non-display area are both high-mobility oxide thin-film transistors, the number of factors to be considered when adjusting the device characteristics is reduced. Therefore, the debugging cycle can be shortened and the debugging cost can be reduced, which can further shorten the process cycle and reduce the manufacturing cost of the display panel. Description of the Drawings

[0015] Figure 1 is a schematic cross-sectional structure diagram of a display panel;

[0016] Figure 2 is a schematic structural diagram of high-mobility oxide thin-film transistors in a display area and a non-display area according to an embodiment of the present invention;

[0017] Figure 3 is Figure 2 a top view of the first transistor in;

[0018] Figure 4 is Figure 2 a top view of the second transistor in;

[0019] Figure 5 is a schematic structural diagram of a 6T1C pixel circuit;

[0020] Figure 6 is Figure 5 a timing diagram of related signals in the pixel circuit shown;

[0021] Figure 7 is a schematic structural diagram of a 7T2C pixel circuit;

[0022] Figure 8 is Figure 7 a timing diagram of related signals in the pixel circuit shown within two working cycles;

[0023] Figure 9 is a flowchart of a method for using a display panel according to an embodiment of the present invention;

[0024] Figure 10 is a flowchart of a method for forming a display panel according to an embodiment of the present invention;

[0025] Figures 11 to 15It is a schematic cross-sectional structure diagram corresponding to the corresponding steps in the formation process of the display panel in the embodiment of the present invention;

[0026] Figure 16 It is a schematic structural diagram of a display device in the embodiment of the present invention. Detailed implementation manners

[0027] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0028] In the following description, many specific details are set forth in order to fully understand the present application, but the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0029] Without departing from the spirit or scope of the present application, various modifications and changes can be made to the present application, which are obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and changes of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0030] In practical applications, the display panel may include a display area (i.e., the AA area) and a non-display area (i.e., the NAA area) outside the display area. A plurality of pixel circuits are arranged in the display area, and two or more signal generation circuits may be arranged in the non-display area. The signal generation circuits in the non-display area can generate required signals and are connected to the pixel circuits in the display area through signal lines, so as to provide signals for the pixel circuits in the display area and realize the driving of the pixel circuits.

[0031] In current display panels, most N-type transistors are oxide thin-film transistors. The carrier mobility of oxide thin-film transistors is higher, allowing the transistor volume to be reduced while maintaining high performance, thereby promoting the panel to achieve high-resolution display, supporting finer pixel control and lower power consumption.

[0032] Traditional oxide thin-film transistors, such as indium gallium zinc oxide thin-film transistors (IGZO TFTs), have a mobility of around 10 cm² / V·s to 20 cm² / V·s. Although the off-current (Ioff) is low, the on-current (Ion) is not large enough, which has certain limitations when applied to medium and large-sized panels and affects the uniformity of medium and large-sized panels.

[0033] To improve the uniformity of medium and large-sized panels, the industry has proposed using high-mobility oxide TFTs (HMO TFTs) as switches for signal generation circuits in the non-display area. The mobility of high-mobility oxide TFTs can reach more than twice that of traditional oxide thin-film transistors, which can effectively increase the on-current of the transistors. Furthermore, each pixel circuit can be accurately driven within a short time, thus effectively improving the uniformity of medium and large-sized panels.

[0034] However, the inventors found that in high-mobility oxide TFTs, the high-mobility oxide material is sensitive to light and has poor negative bias temperature illumination stability (NBTIS). Since there are no light-emitting devices in the non-display area of the display panel, and the anode metal completely covers and blocks the circuit in the non-display area, the light transmittance is very small. Even in some products, the circuit area in the non-display area is bent so that it is basically not affected by light. Therefore, high-mobility oxide TFTs are usually applied to the circuits in the non-display area. However, there are light-emitting devices in the display area of the display panel, and inevitably, some light enters the inside of the TFT device, causing the characteristics of the TFT device to shift and various display defects to occur. Therefore, traditional oxide thin-film transistors are usually used in the circuits in the display area, and it is difficult to use high-mobility oxide thin-film transistors, resulting in a small on-current of the transistors in the display area and a low refresh rate of the display panel, thus affecting the image quality of the display panel.

[0035] Furthermore, the inventors also found that due to the use of TFT devices with different mobilities in the non-display area and the display area of the display panel, the process cycle is long and the manufacturing cost is high.

[0036] The reasons for the high manufacturing cost of the display panel will be explained below in combination with the transistor structure in a specific display panel:

[0037] Figure 1 It is a schematic cross-sectional structure diagram of a display panel in an embodiment. In Figure 1In it, a schematic cross-sectional structure diagram of a first transistor in the display area I on the display panel and a schematic cross-sectional structure diagram of a second transistor in the non-display area II are shown. Among them, the first transistor is an example of a conventional oxide thin film transistor in the display area I, and the second transistor is an example of a high-mobility oxide TFT in the non-display area II.

[0038] Please refer to Figure 1 , the first transistor may include: a first bottom gate 101, a first channel layer 102, and a first top gate 103. In the direction perpendicular to the surface of the substrate 100, the first bottom gate 101 is located below the first channel layer 102, and the first top gate 103 is located above the first channel layer 102.

[0039] The second transistor may include: a second bottom gate 104, a second channel layer 105, and a second top gate 106. In the direction perpendicular to the surface of the substrate 100, the second bottom gate 104 is located below the second channel layer 105, and the second top gate 106 is located above the second channel layer 105.

[0040] In practical applications, the first bottom gate 101 and the second bottom gate 104 are in the same layer and are both covered by the first interlayer dielectric layer ILD1. The first top gate 103 and the second top gate 106 are in the same layer and are both covered by the second interlayer dielectric layer ILD2. The first channel layer 102 and the second channel layer 105 are in different layers. The first channel layer 102 may be covered by the first gate insulating layer GI1, and the second channel layer 105 may be covered by the second gate insulating layer GI2. Among them, the material of the first channel layer 102 may include indium gallium zinc oxide, and the material of the second channel layer 105 may be other oxide materials with a mobility greater than that of indium gallium zinc oxide.

[0041] Since the first channel layer 102 and the second channel layer 105 are located in different layers, the first channel layer 108 and the second channel layer 105 are formed in different steps. Specifically, when forming the first channel layer 102, it is necessary to first form a first channel material layer on the surface of the first interlayer dielectric layer ILD1, then transfer the required pattern to the first channel material layer using a pre-designed first photomask, and etch the area on the first channel material layer that is not covered by the lithographic pattern to form the first channel layer 102. When forming the second channel layer 105, it is necessary to form a second channel material layer on the surface of the first gate insulating layer GI1, then transfer the required pattern to the second channel material layer using a pre-designed second photomask, and etch the area on the second channel material layer that is not covered by the lithographic pattern to form the second channel layer 105. Moreover, after forming the first channel layer 102, it is necessary to first form the first gate insulating layer GI1 covering the first channel layer 102, and then the second channel layer 105 can be formed on the surface of the first gate insulating layer GI1. The first gate insulating layer GI1 is used to isolate the first channel layer 102 and the second channel layer 105. A photomask is also required when forming the first gate insulating layer GI1.

[0042] It can be seen from this that the above process of forming the first channel layer 102 and the second channel layer 105 requires the design and formation of multiple photomasks to separately form the first channel layer 102, the second channel layer 105, and the first gate insulating layer GI1. Not only is the process cycle long, but when adjusting the characteristics, thin-film transistors of two different channel materials need to be considered, resulting in an increase in the debugging cycle and debugging cost. This leads to an extension of the process cycle of the entire display panel and a relatively high manufacturing cost.

[0043] To improve the image quality of the display area, the technical solution of the present invention provides a display panel. In this display panel, the oxide thin-film transistors in the display area are also high-mobility oxide thin-film transistors, and the first top gate and the first bottom gate of the high-mobility oxide thin-film transistors in the display area are electrically insulated from each other, thereby improving the NBTIS reliability of the high-mobility oxide thin-film transistors in the display area, enabling the high-mobility oxide thin-film transistors to be applied in the display area, and improving the image quality of the display area.

[0044] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0045] An embodiment of the present invention provides a display panel, which may include: a substrate. The substrate may include a display area.

[0046] In practical applications, a plurality of pixel circuits are arranged in the display area, and the plurality of pixel circuits are arranged in an array to form a pixel array.

[0047] In an embodiment of the present invention, the oxide thin film transistors in the display area are all high-mobility oxide thin film transistors, and the high-mobility oxide thin film transistors in the display area may include: a first top gate and a first bottom gate; the first top gate and the first bottom gate are electrically insulated from each other.

[0048] Since the first top gate and the first bottom gate are electrically insulated from each other, different electrical signals can be applied to the first top gate and the first bottom gate respectively. Furthermore, different voltages can be applied to the upper and lower surfaces of the channel layer of the high-mobility oxide thin film transistor in the display area. In this way, the channel layer of the high-mobility oxide thin film transistor in the display area is divided into two independent upper and lower regions, and whether channels are formed in the two independent upper and lower regions of the same channel layer can be controlled respectively.

[0049] Specifically, by applying a signal through the first top gate, no channel can be formed in the upper region of the channel layer of the high-mobility oxide thin film transistor in the display area, while by applying a signal on the first bottom gate, a channel can be formed in the lower region of the channel layer of the high-mobility oxide thin film transistor in the display area. Thus, the upper region of the channel layer can serve as a shielding layer for the lower region of the channel layer, enabling the carriers in the lower region of the channel layer to shield the influence of light, improving the NBTIS reliability of the high-mobility oxide thin film transistor in the display area, and enabling the high-mobility oxide thin film transistor to be applied in the display area. Compared with using traditional oxide thin film transistors in the display area, using high-mobility oxide thin film transistors in the display area can increase the current flowing through the transistor, thereby shortening the time required to reach the set voltage, increasing the refresh frequency of the pixel circuit, improving the image quality of the display panel, and making the image quality smoother.

[0050] Among them, a high-mobility oxide thin film transistor refers to a thin film transistor with a mobility greater than that of a traditional oxide thin film transistor. Generally, the mobility of the high-mobility oxide material in the high-mobility oxide thin film transistor is greater than 20 cm² / V·s. For example, the mobility in the high-mobility oxide thin film transistor can be 25 cm² / V·s, 28 cm² / V·s, etc. In some embodiments, the mobility in the high-mobility oxide thin film transistor can reach 30 cm² / V·s to 50 cm² / V·s. In other embodiments, the mobility in the high-mobility oxide thin film transistor can exceed 50 cm² / V·s but be less than or equal to 70 cm² / V·s.

[0051] Generally, the oxide thin film transistor is an N-type transistor. The display area may include multiple pixel circuits. In the pixel circuits, any N-type transistor implemented by an oxide thin film transistor can be implemented by a high-mobility oxide thin film transistor.

[0052] In an embodiment of the present invention, the first top gate is adapted to receive a first voltage signal, the voltage of the first voltage signal being less than the turn-on voltage of the first transistor, and the first bottom gate is adapted to receive a first gate signal.

[0053] Taking the first transistor as a high-mobility oxide thin-film transistor in display region I as an example, in combination with Figure 2 and Figure 3 , the structure of the high-mobility oxide thin-film transistor in display region I will be described. Among them, Figure 2 is a schematic cross-sectional structure diagram of the display panel in the direction perpendicular to the surface of the substrate, Figure 3 and

[0054] is a top view of the first transistor. Figures 2 to 3 Referring to

[0055] , the first transistor may include: a first bottom gate 201, a first channel layer 202, and a first top gate 203. The first bottom gate 201 and the first top gate 203 are located on both sides of the first channel layer 202 in the direction perpendicular to the surface of the substrate 200.

[0056] Since the first top gate receives the first voltage signal, while the first bottom gate 201 receives the first gate signal, and the voltages provided by the first voltage signal and the first gate signal are different. Therefore, in the direction perpendicular to the surface of the substrate 200, the voltages applied to the upper and lower surfaces of the first channel layer 202 are also different. Furthermore, in the direction perpendicular to the surface of the substrate 200, the first channel layer 202 can be divided into upper and lower sub-channel layers.

[0057] In a specific implementation, the first transistor may further include: a first connection structure connecting the first bottom gate 201, the first channel layer 202, and the first top gate 203. Through this first connection structure, the electrical connection of the first bottom gate 201, the first channel layer 202, and the first top gate 203 to the outside can be achieved. Among them, the first connection structure may include: a first plug unit connecting the first bottom gate 201, a second plug unit connecting the first channel layer 202, and a third plug unit connecting the first top gate 203. Among them, the two ends of the first channel layer 202 have a source region and a drain region. The second plug unit may include: a first source region plug sub-unit electrically connected to the source region at one end of the first channel layer 202, and a first drain region plug sub-unit electrically connected to the drain region at the other end of the first channel layer 202. Each plug unit and plug sub-unit includes a plug and a metal connection portion located on the plug.

[0058] Specifically, referring to Figure 2 and Figure 3 , the first plug unit may include: a first bottom gate plug 207 and a first bottom gate metal connection portion 208 located on the first bottom gate plug 207. The third plug unit may include: a first top gate plug 209 and a first top gate metal connection portion 210 located on the first top gate plug 209. The first source region plug sub-unit may include: a first source region plug 211 and a first source region metal connection portion 212 located on the first source region plug 211. The first drain region plug sub-unit may include: a first drain region plug 213 and a first drain region metal connection portion 214 located on the first drain region plug 213.

[0059] In a specific implementation, the first bottom gate metal connection portion 208, the first top gate metal connection portion 210, the first source region metal connection portion 212, and the first drain region metal connection portion 214 may be located within the same metal layer.

[0060] Referring to Figure 3 , in practical applications, the first bottom gate metal connection portion 208 may be connected through the first bottom gate metal wire 31, and then electrically connected to the first bottom gate 201 through the first bottom gate metal connection portion 208 and the first bottom gate plug 207. Thus, a first gate signal can be applied to the first bottom gate 201, and the voltage of the first gate signal may vary according to the functional requirements of the pixel circuit where it is located.

[0061] The first source region metal connection portion 212 is connected through the first source region metal wire 32, and then electrically connected to one end of the first channel layer 202 through the first source region metal connection portion 212 and the first source region plug 211. Thus, the source region of the first transistor can be connected to the circuit.

[0062] The first drain region metal connection portion 214 is connected through the first source region metal wire 33, and then electrically connected to the other end of the first channel layer 202 through the first drain region metal connection portion 214 and the first drain region plug 213, whereby the drain region of the first transistor can be connected to the circuit.

[0063] The first top gate metal connection portion 210 is connected through the first top gate metal wire 34, and then electrically connected to the first top gate 203 through the first top gate metal connection portion 210 and the first top gate plug 209, whereby a first voltage signal can be applied to the first top gate 203. The voltage of the first voltage signal is less than the voltage of the first transistor, whereby a channel cannot be formed in the first sub-channel layer in the first channel layer 202, so that the carriers in the second sub-channel layer in the first channel layer 202 can shield the influence of light.

[0064] In a specific implementation, the specific voltage value provided by the first voltage signal is not limited, as long as the voltage provided by the first voltage signal is less than the turn-on voltage of the first transistor.

[0065] In an embodiment of the present invention, in order to avoid forming a channel in the first sub-channel layer due to voltage fluctuations, the voltage of the first voltage signal can be set to a fixed voltage. This fixed voltage can keep the voltage value unchanged, thereby avoiding non-desired formation of a channel in the first sub-channel layer due to voltage fluctuations. At this time, a fixed voltage is applied to the top gate of the first transistor in the display area, and the bottom gate serves as the gate of the first transistor, which can effectively improve the NBTIS reliability of the first transistor.

[0066] In some embodiments, the voltage provided by the first voltage signal can be negative. For example, the voltage provided by the first voltage signal can be -1V, -1.5V, -2V, etc. A negative voltage can make the state of the first sub-channel layer more stable, so that the performance of the first transistor is more stable.

[0067] In a specific implementation, the substrate may further include a non-display area. The oxide thin film transistor in the non-display area is a high-mobility oxide thin film transistor. Among them, there may be multiple signal generation circuits in the non-display area. Among the multiple signal generation circuits, any N-type transistor implemented by an oxide thin film transistor can be implemented by a high-mobility oxide thin film transistor.

[0068] Taking the second transistor as a high-mobility oxide thin film transistor in the non-display area II as an example, in combination with Figure 2 and Figure 4 , the structure of the high-mobility oxide thin film transistor in the non-display area II is described. Among them, Figure 4 is a top view of the second transistor.

[0069] The second transistor may include: a second bottom gate 204, a second channel layer 205, and a second top gate 206. The second bottom gate 204 and the second top gate 206 are located on both sides of the second channel layer 205 in a direction perpendicular to the surface of the substrate 200.

[0070] The first bottom gate 201 and the second bottom gate 204 are arranged on the same layer, and the first top gate 203 and the second top gate 206 are arranged on the same layer.

[0071] In a specific implementation, the materials of the first channel layer 202 and the second channel layer 205 may both be high-mobility oxide materials, so that the first transistor and the second transistor are both high-mobility oxide thin-film transistors. Among them, the mobility of the high-mobility oxide material is greater than 20 cm² / V·s. For example, the mobility of the high-mobility oxide material can be 25 cm² / V·s, 28 cm² / V·s, etc. Preferably, the mobility in the high-mobility oxide thin-film transistor can reach 30 cm² / V·s to 50 cm² / V·s. In some other embodiments, the mobility in the high-mobility oxide thin-film transistor can exceed 50 cm² / V·s but be less than or equal to 70 cm² / V·s.

[0072] In a specific implementation, the high-mobility oxide material can be a variety of materials, which is not limited here.

[0073] In some embodiments, the high-mobility oxide material may include indium gallium zinc oxide doped with trace elements, and the trace elements include one or more of indium, arsenic, and germanium.

[0074] Specifically, indium, arsenic, or germanium can be doped only in indium gallium zinc oxide, or any two of indium, arsenic, and germanium can be doped in indium gallium zinc oxide. For example, arsenic and germanium can be doped in indium gallium zinc oxide, or indium and arsenic can be doped in indium gallium zinc oxide. Indium, arsenic, and germanium can also be doped in indium gallium zinc oxide simultaneously.

[0075] Among them, the proportion of the doping element can be adjusted according to the actual mobility requirement. The proportion of indium element in indium gallium zinc oxide doped with indium element is higher than that in traditional indium gallium zinc oxide. For example, the proportion of indium element in indium gallium zinc oxide doped with indium element can reach 40%, such as 45%, 50%, 57%, etc.

[0076] In a specific implementation, the channel layer materials of the oxide thin-film transistors in the display area and the non-display area can be different, so that the channel layers of the oxide thin-film transistors in the display area and the non-display area are located in different layers of the display panel (as Figure 1 shown).

[0077] Specifically, referring toFigures 2 to 4 Although the materials of the first channel layer 202 and the second channel layer 205 are both high-mobility oxide materials, the material of the first channel layer 202 can be different from that of the second channel layer 205. By the so-called same material, it means that the elements contained in the materials are the same and the proportions of each element are also the same. The first channel layer 202 and the second channel layer 205 made of different materials can have the same mobility or different mobilities, and the first channel layer 202 and the second channel layer 205 made of different materials are formed in different layers of the display panel.

[0078] For example, it can be set that the materials of the first channel layer 202 and the second channel layer 205 are both indium gallium zinc oxide, but the proportion of indium element is different. Another example is that the material of the first channel layer 202 can be indium gallium zinc oxide doped with arsenic element, while the material of the second channel layer 205 is indium gallium zinc oxide doped with indium element.

[0079] Among them, when the materials of the first channel layer 202 and the second channel layer 205 are different, the mobility of the material of the first channel layer 202 can be the same as or different from that of the material of the second channel layer 205.

[0080] In an embodiment of the present invention, the channel layer materials of the oxide thin-film transistors in the display area and the non-display area can be the same, so that the oxide thin-film transistors in the display area and the non-display area can be arranged in the same layer. By the so-called same-layer arrangement, it means that the semiconductor layers with the same function of the oxide thin-film transistors in the display area and the non-display area are located in the same layer. Here, the "same layer" is relative to the surface of the substrate, that is, the same height area in the direction parallel to the surface of the substrate.

[0081] Specifically, referring to Figures 2 to 4 , the materials of the first channel layer 202 and the second channel layer 205 are the same. For example, the materials of the first channel layer 202 and the second channel layer 205 are both indium gallium zinc oxide and the proportions of each element are the same. At this time, the mobility of the material of the first channel layer 202 is the same as that of the material of the second channel layer 205, and the thicknesses of the first channel layer 202 and the second channel layer 205 are the same. Thus, the first channel layer 202 and the second channel layer 205 can be formed in the same layer of the display panel. Thereby, the process of the display panel can be simplified, the process cycle can be shortened and the manufacturing cost can be reduced. Among them, the thicknesses of the first channel layer 202 and the second channel layer 205 can be set according to the actual mobility requirements of the first transistor and the second transistor.

[0082] In a specific implementation, the width of the first channel layer 202 can be the same as that of the second channel layer 205, so that the currents of the first transistor and the second transistor can be the same.

[0083] In an embodiment of the present invention, based on the driving requirements of the transistors in the pixel circuit, the width of the first channel layer 202 can be set to be greater than the width of the second channel layer 205, whereby the current flowing through the first transistor can be made greater than the current flowing through the second transistor.

[0084] In a specific implementation, the second transistor may further include: a second connection structure connected to the second bottom gate 204, the second channel layer 205, and the second top gate 206. Through this second connection structure, the electrical connection of the second bottom gate 204, the second channel layer 205, and the second top gate 206 to the outside can be achieved. Among them, the second connection structure may include: a fourth plug unit connected to the second bottom gate 204, a fifth plug unit connected to the second channel layer 205, and a sixth plug unit connected to the second top gate 206. Among them, the two ends of the second channel layer 205 have a source region and a drain region. The fifth plug unit may include: a second source region plug sub-unit electrically connected to the source region at one end of the second channel layer 205, and a second drain region plug sub-unit electrically connected to the drain region at the other end of the second channel layer 205. Each plug unit and plug sub-unit includes a plug and a metal connection portion located on the plug.

[0085] Specifically, referring to Figure 2 and Figure 4 , the fourth plug unit may include: a second bottom gate plug 215 and a second bottom gate metal connection portion 216 located on the second bottom gate plug 215. The sixth plug unit may include: a second top gate plug 217 and a second top gate metal connection portion 218 located on the second top gate plug 217. The second source region plug sub-unit may include: a second source region plug 219 and a second source region metal connection portion 220 located on the second source region plug 219. The second drain region plug sub-unit may include: a second drain region plug 221 and a second drain region metal connection portion 222 located on the second drain region plug 221.

[0086] In a specific implementation, the second bottom gate metal connection portion 216, the second top gate metal connection portion 218, the second source region metal connection portion 220, and the second drain region metal connection portion 222 may be located within the same metal layer.

[0087] In a specific implementation, the second bottom gate metal connection portion 216, the second top gate metal connection portion 218, the second source region metal connection portion 220, and the second drain region metal connection portion 222 may be located within the same metal layer as the first bottom gate metal connection portion 208, the first top gate metal connection portion 210, the first source region metal connection portion 212, and the first drain region metal connection portion 214. For example, they may all be located within the second metal layer.

[0088] Referring to Figure 4, in practical applications, the second bottom gate metal line 41 can be connected to the second bottom gate metal connection portion 216, and then electrically connected to the second bottom gate through the second bottom gate metal connection portion 216 and the second bottom gate plug 215. The second bottom gate metal line 41 can also be connected to the second top gate metal connection portion 218, and then electrically connected to the second top gate 206 through the second top gate metal connection portion 218 and the second top gate plug 217. Thus, a second gate signal can be applied to the second bottom gate 204 and the second top gate 206, and then the gate signals applied to the second bottom gate 204 and the second top gate 206 are synchronized, forming a transistor with a double-gate structure, which has a higher mobility and can increase the on-current of the second transistor.

[0089] The second source region metal line 42 is connected to the second source region metal connection portion 220, and then electrically connected to one end of the second channel layer 205 through the second source region metal connection portion 220 and the second source region plug 219. Thus, the source region of the second transistor can be connected to the circuit.

[0090] The second drain region metal line 43 is connected to the second drain region metal connection portion 222, and then electrically connected to the other end of the second channel layer 205 through the second drain region metal connection portion 222 and the second drain region plug 221. Thus, the drain region of the second transistor can be connected to the circuit.

[0091] In a specific implementation, the materials of the first top gate 203 and the second top gate 206 can be the same. Specifically, the materials of the first top gate 203 and the second top gate 206 can both include: metal. The metal can be one or a combination of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

[0092] In a specific implementation, the materials of the first bottom gate 201 and the second bottom gate 204 can be the same. Specifically, the materials of the first bottom gate 201 and the second bottom gate 204 include metal, and the metal includes one or a combination of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

[0093] In a specific implementation, the display panel may further include: a second interlayer dielectric layer ILD2 covering the first top gate 203 and the second top gate 206, a second gate insulating layer GI2 covering the first channel layer 202 and the second channel layer 205, a first interlayer dielectric layer ILD1 covering the first bottom gate 201 and the second bottom gate 204, a first gate insulating layer GI1 located between the second gate insulating layer GI2 and the first interlayer dielectric layer ILD1, and a third interlayer dielectric layer ILD3 located on the surface of the second interlayer dielectric layer ILD2.

[0094] Among them, the material of each of the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the third interlayer insulating layer ILD3 can be an insulating inorganic material such as silicon oxide or silicon nitride. The materials of the first gate insulating layer GI1 and the second gate insulating layer GI2 can be inorganic materials such as silicon oxide, silicon nitride, or metal oxide.

[0095] In a specific implementation, the substrate 200 may include a substrate and at least one dielectric layer on the substrate. The number of dielectric layers on the substrate can be set according to actual needs. Specifically, referring to Figure 2 , the substrate 200 may include: a substrate 223, and a first dielectric layer 224, a second dielectric layer 225, and a third dielectric layer 226 on the substrate 223. The material of the substrate 223 can be glass. The materials of the first dielectric layer 224, the second dielectric layer 225, and the third dielectric layer 226 can be inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride, or organic materials. The first dielectric layer 224, the second dielectric layer 225, and the third dielectric layer 226 are used to block oxygen and moisture.

[0096] In a specific implementation, the display area may include at least one pixel circuit. The pixel circuit may include at least one N-type transistor. At least one N-type transistor in the pixel circuit can be implemented by the high-mobility oxide thin-film transistor in the above embodiment, thereby increasing the on-current of the N-type transistor in the pixel circuit, which is more conducive to improving the image quality of the display panel.

[0097] The following is an illustration in combination with a specific pixel circuit structure:

[0098] Figure 5 It is a schematic structural diagram of a 6T1C (6 transistors and 1 capacitor) pixel circuit. Referring to Figure 5 , the 6T1C pixel circuit may include: a first light-emitting control transistor Q1, a compensation transistor Q2, a driving transistor Q3, a data writing transistor Q4, a second light-emitting control transistor Q5, an anode reset transistor Q6, and a storage capacitor Cst1. Among them:

[0099] The third transistor Q3 serves as the driving transistor for the first light-emitting device PD1, and is connected to the power supply voltage PVDD through the first light-emitting control transistor Q1 and connected to the first light-emitting device PD1 through the second light-emitting control transistor Q5. The gate of the first light-emitting control transistor Q1 is connected to the first light-emitting control signal EM1, and the gates of the second light-emitting control transistor Q5 and the anode reset transistor Q6 are connected to the second light-emitting control signal EM2. The other end of the first light-emitting device PD1 is grounded to PVEE. One end of the anode reset transistor Q6 is connected to the first light-emitting device PD1 and the second light-emitting control transistor Q5, and the other end is connected to the anode reset signal ref. One end of the compensation transistor Q2 is connected to the gate of the driving transistor Q3, and the other end is connected to the first light-emitting control transistor Q1 and one end of the driving transistor Q3, and the gate is connected to the second scan signal S2. One end of the data writing transistor Q4 is connected to the second light-emitting control transistor Q5 and the driving transistor Q3, and the other end is connected to the data signal data, and the gate is connected to the first scan signal S1.

[0100] Figure 6 is Figure 5 a timing diagram of related signals in the pixel circuit shown. Refer to Figure 5 and Figure 6 , before time t1, the pixel circuit is in the light-emitting stage. At time t1, the first light-emitting control signal EM1 is at a low level, the second light-emitting control signal EM2 is at a high level, and the second scan signal S2 is at a high level. As a result, the first light-emitting control transistor Q1 is turned on, the second light-emitting control transistor Q5 is turned off, the anode reset transistor Q6 is turned on, the compensation transistor Q2 is turned on, the first light-emitting device PD1 stops emitting light, and the voltage Vref of the anode reset signal ref is written to the anode of the first light-emitting device PD1 to perform anode reset on the first light-emitting device PD1.

[0101] During the anode reset (from time t1 to time t2), the gate and drain of the driving transistor Q3 are short-circuited, so that the threshold voltage of the driving transistor Q3 can be compensated, and the threshold voltage of the driving transistor Q3 is pulled up to the power supply voltage PVDD. After the anode reset is completed, the voltage across the storage capacitor Cst1 will be reset to a predetermined voltage (PVDD - Vref).

[0102] At time t3, the first scan signal S1 is at a low level, so that the data signal data is written to one end of the second light-emitting control transistor Q5. At time t4, the second scan signal S2 is at a high level, and the first scan signal S1 remains at a low level. The gate and drain of the driving transistor Q3 are short-circuited, and the gate voltage of the driving transistor Q3 is pulled down to (Vdata + Vth), where Vth is the threshold voltage of the driving transistor Q3 and Vdata is the voltage of the data signal data. Thus, the voltage Vdata of the data signal data can be written to the storage capacitor Cst1. At time t5, the second scan signal S2 is at a low level, causing the compensation transistor Q2 to turn off, and the first scan signal S1 is at a high level, stopping data writing. At time t6, both the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a low level, causing the first light-emitting control transistor Q1 and the second light-emitting control transistor Q5 to conduct, so that the pixel circuit emits light again.

[0103] In the above 6T1C pixel circuit, the compensation transistor Q2, the driving transistor Q3, and the anode reset transistor Q6 can all be implemented by high-mobility oxide thin-film transistors, which can increase the refresh rate of the pixel circuit and thus improve the image quality of the display panel.

[0104] Figure 7 It is a schematic structural diagram of a 7T2C (7 transistors and 2 capacitors) pixel circuit. Refer to Figure 7 , the 7T2C pixel circuit may include: a driving transistor T0, a first light-emitting control transistor T1, a second light-emitting control transistor T2, a first capacitor C1, a second capacitor C2, a data writing transistor T5, a threshold grabbing transistor T6, a first reset transistor T3, and a second reset transistor T4. Among them:

[0105] The driving transistor T0 is used to generate a driving current. One end of the driving transistor T0 is connected to the power supply voltage PVDD through the first light-emitting control transistor T1, and the other end is connected to the second light-emitting device PD2 through the second light-emitting control transistor T2. The other end of the second light-emitting device PD2 is grounded to PVEE. The gates of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are connected to the first scan signal S1. One end of the first capacitor C1 is connected to the first light-emitting control transistor T1 and the driving transistor T0, and the other end is connected to the first scan signal S1. One end of the second capacitor C2 is connected to the first light-emitting control transistor T1, and the other end is connected to the gate of the driving transistor T0. One end of the data writing transistor T5 is connected to the first light-emitting control transistor T1 and the driving transistor T0, the other end is connected to the data signal Data, and the gate is connected to the third scan signal S3.

[0106] One end of the first reset transistor T3 is connected to the gate of the driving transistor T0, the other end is connected to the anode reset signal ref, and the gate is connected to the second scan signal. One end of the threshold capture transistor T6 is connected to the driving transistor T0 and the second light-emitting control transistor T2, and the other end is connected to the gate of the driving transistor T0. One end of the second reset transistor T4 is connected to the second light-emitting control transistor T2, the other end is connected to the anode reset signal ref, and the gate is connected to the third scan signal S3. Vref represents the voltage provided by the anode reset signal ref.

[0107] Figure 8 For Figure 7 The timing diagram of relevant signals in the pixel circuit shown within two working cycles T1 and T2. Refer to Figure 7 And Figure 8 , within each working cycle, the pixel circuit can include: a reset stage T01, a data writing stage T02, and a light-emitting stage T03.

[0108] Specifically, in the reset stage T01, the second scan signal S2 is at a high level, the first reset transistor T3 is turned on, and the reset signal transmitted on the anode reset signal ref reaches the gate of the driving transistor T0, thereby resetting the gate of the driving transistor T0.

[0109] In the data writing stage T02, the third scan signal S3 is at a high level, the voltage Vdata of the data signal data is written into the data writing transistor T5, and the threshold capture transistor T6 is turned on, and the voltage Vdata of the data signal data is written into the gate of the driving transistor T0.

[0110] In the light-emitting stage T03, the voltage of the first scan signal S1 alternates between a high level and a low level, thereby a pulse signal can be transmitted in the light-emitting stage, and the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned on and off simultaneously multiple times. Among them, the existence of the first capacitor C1 can make the second scan signal S1 more significantly pull down the potential of the connection end of the driving transistor T0 and the second light-emitting control transistor T2, thereby avoiding the driving transistor T0 from being turned on and avoiding the generation of a circuit flowing from one end of the driving transistor T0 to the other end.

[0111] In the above 7T2C pixel circuit, the 7 transistors can all be implemented by high-mobility oxide thin-film transistors, thereby increasing the refresh rate of the pixel circuit and improving the image quality of the display panel.

[0112] The embodiment of the present invention also provides a usage method of the above display panel. Specifically, refer to Figure 9 , the method can include the following steps:

[0113] Step 91, apply a first voltage signal to the first top gate of the high-mobility oxide thin-film transistor in the display area, where the voltage of the first voltage signal is less than the turn-on voltage of the first transistor.

[0114] In a specific implementation, the high-mobility oxide thin-film transistor in the display area may further include: a first channel layer, and the first top gate is located above the first channel layer.

[0115] In an embodiment of the present invention, in order to avoid forming a channel in the area of the first channel layer close to the first top gate due to voltage fluctuations, the voltage of the first voltage signal may be set to a fixed voltage. This fixed voltage can keep the voltage value unchanged, thereby avoiding undesirably forming a channel in the first sub-channel layer due to voltage fluctuations.

[0116] Preferably, the voltage provided by the first voltage signal may be negative. For example, the voltage provided by the first voltage signal may be -1.8V or the like. A negative voltage can make the state in the area of the first channel layer close to the first top gate more stable, thereby making the performance of the first transistor more stable.

[0117] Step 92, apply a first gate signal to the first bottom gate of the high-mobility oxide thin-film transistor in the display area.

[0118] In a specific implementation, when applying a first gate signal to the first bottom gate, the first gate signal is different from the first voltage signal, and the first gate signal may provide a varying voltage according to the driving requirements of the pixel circuit. For example, when it is necessary to drive a certain transistor in the pixel circuit to conduct, the voltage of the first gate signal may be a high level, and vice versa it may be a low level. In this way, by applying a first gate signal to the first bottom gate, a channel can be formed or not formed in the area of the first channel layer close to the first bottom gate, thereby conducting or disconnecting the transistor.

[0119] It should be noted that step 91 and step 92 may be executed simultaneously or in sequence, as long as a first voltage signal can be applied to the first top gate and a first gate signal can be applied to the first bottom gate.

[0120] In another embodiment of the present invention, the display panel may further include a non-display area, and the oxide thin-film transistor in the non-display area may also be a high-mobility oxide thin-film transistor.

[0121] Specifically, the high-mobility oxide thin-film transistor in the non-display area includes: a second bottom gate, a second channel layer, and a second top gate, and the second bottom gate and the second top gate are located on both sides of the second channel layer in the direction perpendicular to the surface of the substrate.

[0122] At this time, the method may further include:

[0123] Step 93: Provide a second gate signal to the second bottom gate and the second top gate of the high-mobility oxide thin-film transistor in the non-display area.

[0124] In a specific implementation, the second bottom gate and the second top gate of the high-mobility oxide thin-film transistor in the non-display area can be electrically connected through the same metal wire, and then the second gate signal can be applied to the second bottom gate and the second top gate simultaneously through this metal wire.

[0125] The second gate signal is different from the first gate signal and even more different from the first voltage signal. The second gate signal can provide a varying voltage according to the driving requirements of the pixel circuit. For example, when it is necessary to drive a certain transistor in the pixel circuit to conduct, the second gate signal can be at a high level, and vice versa, it can be at a low level. In this way, by providing different second gate signals to the second bottom gate and the second top gate, this transistor can be turned on or off.

[0126] It should be noted that step 93 can be executed simultaneously with step 91 and step 92, or can be executed in a sequential order, and there is no limitation here.

[0127] By using the method for using the display panel in the embodiment of the present invention, it is possible to apply different voltages to the upper and lower surfaces of the channel layer of the high-mobility oxide thin-film transistor in the display area, so that the channel layer of the high-mobility oxide thin-film transistor in the display area is divided into two independent upper and lower regions, and channel control can be performed separately. Thereby, the NBTIS reliability of the high-mobility oxide thin-film transistor in the display area can be improved, so that the high-mobility oxide thin-film transistor can be applied to the display area, and the image quality of the display panel can be improved.

[0128] The embodiment of the present invention also provides a method for forming the display panel in the above embodiment. The method may include the following steps:

[0129] Step 110: Provide a substrate, and the substrate includes a display area and a non-display area.

[0130] Step 120: Form high-mobility oxide thin-film transistors in the same layer of the display area and the non-display area.

[0131] Taking the first transistor as a high-mobility oxide thin-film transistor in display area I and the second transistor as a high-mobility oxide thin-film transistor in non-display area II as an example, forming the first transistor and the second transistor in the same layer of the display area and the non-display area may include:

[0132] Form a first bottom gate above the substrate in the display area and a second bottom gate above the substrate in the non-display area, and the first bottom gate and the second bottom gate are located in the same layer;

[0133] A first channel layer is formed above the first bottom gate, and a second channel layer is formed above the second bottom gate. The first channel layer and the second channel layer are located in the same layer;

[0134] A first top gate is formed above the first channel layer, and a second top gate is formed above the second channel layer. The first top gate and the second top gate are located in the same layer.

[0135] The following combines Figures 11 to 15 and Figure 2 to describe the above formation process as follows:

[0136] Referring to Figure 11 , the substrate 200 in display area I and non-display area II may include: a substrate 223, and a first dielectric layer 224, a second dielectric layer 225, and a third dielectric layer 226 located on the substrate 223. Among them, the material of the substrate 223 may be glass. The materials of the first dielectric layer 224, the second dielectric layer 225, and the third dielectric layer 226 may be inorganic materials or organic materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride. The first dielectric layer 224, the second dielectric layer 225, and the third dielectric layer 226 are used to block oxygen and moisture.

[0137] Referring to Figure 12 , a first bottom gate 201 is formed on the surface of the third dielectric layer 226 in display area I, and a second bottom gate 204 is formed on the surface of the third dielectric layer 226 in non-display area II.

[0138] Specifically, a bottom gate material layer may be first formed on the surface of the third dielectric layer 226 in display area I and non-display area II, and then the bottom gate material layer is etched to form the first bottom gate 201 and the second bottom gate 204.

[0139] Referring to Figure 13 , a first interlayer dielectric layer ILD1 covering the first bottom gate 201 and the second bottom gate 204 is formed. The first interlayer dielectric layer ILD1 also covers a part of the surface of the third dielectric layer 226. For example, a physical layer deposition process may be used to form the first interlayer dielectric layer ILD1. After that, a first gate insulating layer GI1 is formed on the surface of the first interlayer dielectric layer ILD1, and the first gate insulating layer GI1 covers the first interlayer dielectric layer ILD1.

[0140] Continue to refer to Figure 13, a first channel layer 202 is formed on the surface of the first gate insulating layer GI1 in the display region I, and a second channel layer 205 is formed on the surface of the first gate insulating layer GI1 in the non-display region II. Specifically, a channel material layer can be first formed on the surface of the first gate insulating layer GI1 in the display region I and the non-display region II, and the channel material layer completely covers the surface of the first gate insulating layer GI1. Then, the channel material layer is etched to form the first channel layer 202 and the second channel layer 205. After that, a second gate insulating layer GI2 covering the first channel layer 202 and the second channel layer 205 is formed.

[0141] Refer to Figure 14 , a first top gate 203 is formed on the surface of the second gate insulating layer GI2 in the display region I, and a second top gate 206 is formed on the surface of the second gate insulating layer GI2 in the non-display region II. Specifically, a top gate material layer can be first formed on the surface of the second gate insulating layer GI2 in the display region I and the non-display region II, and the top gate material layer completely covers the surface of the second gate insulating layer GI2. Then, the top gate material layer is etched to form the first top gate 203 and the second top gate 206.

[0142] Refer to Figure 15 , a first bottom gate plug 207 connecting the first bottom gate 201, a first source region plug 211 and a first drain region plug 213 connecting the first channel layer 202, and a first top gate plug 209 connecting the second top gate 203 are formed in the display region I.

[0143] Specifically, a first bottom gate plug hole, a first source region plug hole, a first drain region plug hole, and a first top gate plug hole connecting the first bottom gate 201 can be first formed in the display region I, and each plug hole is filled with a material to form the corresponding plug.

[0144] Continue to refer to Figure 15 , a second bottom gate plug 215, a second top gate plug 217, a second source region plug 219, and a second drain region plug 221 are formed in the non-display region II.

[0145] Specifically, a second bottom gate plug hole, a second top gate plug hole, a second source region plug hole, and a second drain region plug hole can be first formed in the non-display region II, and each plug hole is filled with a material to form the corresponding plug.

[0146] Refer to Figure 2 , a first bottom gate metal connection part 208 connecting the first bottom gate plug 207, a first top gate metal connection part 210 connecting the first top gate plug 209, a first source region metal connection part 212 connecting the first source region plug 211, and a first drain region metal connection part 214 connecting the first drain region plug 213 are formed in the display region I.

[0147] In the non-display area II, a second bottom gate metal connection portion 216 connecting the second bottom gate plug 215, a second top gate metal connection portion 218 connecting the second top gate plug 217, a second source region metal connection portion 220 connecting the second source region plug 219, and a second drain region metal connection portion 222 connecting the second drain region plug 221 are formed.

[0148] The second bottom gate metal connection portion 216, the second top gate metal connection portion 218, the second source region metal connection portion 220, and the second drain region metal connection portion 222 may be located in the same metal layer as the first bottom gate metal connection portion 208, the first top gate metal connection portion 210, the first source region metal connection portion 212, and the first drain region metal connection portion 214.

[0149] Subsequently, the second bottom gate metal connection portion 216 and the second top gate metal connection portion 218 may be connected by the same metal wire, and then a second gate signal may be applied to the second bottom gate 204 and the second top gate 206. The first bottom gate metal connection portion 208 and the first top gate metal connection portion 210 are respectively connected by different metal wires, and different signals are applied to the first bottom gate 201 and the first top gate 203, so as to respectively control different regions of the first channel layer 202, so that the high-mobility oxide thin-film transistor can be applied to the display area and the image quality of the display area can be improved.

[0150] An embodiment of the present invention also provides a display device. Figure 16 It is a schematic structural diagram of a display device 1000 in an embodiment of the present invention, as Figure 16 shown, the display device 1000 includes the display panel 1000P in the above embodiment.

[0151] In a specific implementation, the display device includes, but is not limited to, a mobile phone, a computer, a television, etc.

[0152] By using the display device in the embodiment of the present invention, better image quality can be provided.

[0153] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A display panel, characterized in that: include: A substrate, the substrate comprising a display area; Wherein, the oxide thin film transistor in the display area is a high-mobility oxide thin film transistor; the high-mobility oxide thin film transistor in the display area includes: a first top gate and a first bottom gate; The first top gate and the first bottom gate are electrically insulated from each other.

2. The display panel according to claim 1, wherein: The first top gate is used to access a first voltage signal, the voltage of the first voltage signal is less than the turn-on voltage of the transistor, and the first bottom gate is suitable for accessing a first gate signal.

3. The display panel according to claim 2, wherein: The substrate further comprises: a non-display area; the oxide thin film transistor in the non-display area is a high-mobility oxide thin film transistor.

4. The display panel according to claim 3, wherein: The oxide thin film transistors in the display area and the non-display area are arranged in the same layer.

5. The display panel according to claim 3, wherein: The high-mobility oxide thin film transistor in the display area further includes: a first channel layer, the first bottom gate and the first top gate are located on both sides of the first channel layer in a direction perpendicular to the surface of the substrate; The high-mobility oxide thin film transistor in the non-display area comprises: a second bottom gate, a second channel layer and a second top gate, wherein the second bottom gate and the second top gate are located on both sides of the second channel layer in a direction perpendicular to the surface of the substrate; The first bottom gate and the second bottom gate are arranged in the same layer, the first channel layer and the second channel layer are arranged in the same layer, and the first top gate and the second top gate are arranged in the same layer.

6. The display panel according to claim 5, wherein: The second top gate and the second bottom gate are electrically connected.

7. The display panel according to claim 5, wherein: Materials of the first channel layer and the second channel layer both include high-mobility oxide materials, and the mobility of the high-mobility oxide materials is greater than 20 cm² / V·s.

8. The display panel according to claim 7, wherein: The high-mobility oxide material includes: indium gallium zinc oxide doped with trace elements, and the trace elements include one or more of indium, arsenic and germanium.

9. The display panel according to claim 7, wherein: The material and thickness of the first channel layer and the second channel layer are the same.

10. The display panel according to claim 5, wherein: The width of the second channel layer is greater than the width of the first channel layer.

11. The display panel according to claim 5, characterized in that: The first top gate and the second top gate are made of the same material.

12. The display panel according to claim 5, characterized in that: The first bottom gate and the second bottom gate are made of the same material.

13. The display panel according to claim 2, wherein: The voltage of the first voltage signal is a fixed voltage.

14. The display panel according to claim 13, wherein: The voltage of the fixed voltage signal is a negative value.

15. The display panel according to claim 1, wherein: The display area includes a pixel circuit, and the pixel circuit includes at least one transistor which is the high-mobility oxide thin film transistor.

16. A method for using the display panel according to any one of claims 1 to 15, characterized in that: Providing a first voltage signal to a first top gate of a high-mobility oxide thin film transistor in the display area, wherein the voltage of the first voltage signal is less than a turn-on voltage of the transistor; A first gate signal is provided to a first bottom gate of a high-mobility oxide thin film transistor in the display area.

17. The method of use according to claim 16, characterized in that: The display panel further comprises: a non-display area; the high-mobility oxide thin film transistor in the non-display area comprises: a second bottom gate, a second channel layer, and a second top gate, wherein the second bottom gate and the second top gate are located on both sides of the second channel layer in a direction perpendicular to the surface of the substrate; A second gate signal is provided to a second bottom gate and a second top gate of the high-mobility oxide thin film transistor in the non-display area.

18. A method for forming a display panel according to any one of claims 3 to 15, characterized in that: include: Providing a substrate, the substrate comprising a display area and a non-display area; A high-mobility oxide thin film transistor is formed in the same layer of the display area and the non-display area.

19. The method for forming a display panel according to claim 18, wherein: The high-mobility oxide thin film transistor in the display area includes: a first transistor; the high-mobility oxide thin film transistor in the non-display area includes: a second transistor; The first transistor and the second transistor are formed in the same layer of the display area and the non-display area, comprising: Forming a first bottom gate on the substrate in the display area, and forming a second bottom gate on the substrate in the non-display area, wherein the first bottom gate and the second bottom gate are located in the same layer; forming a first channel layer above the first bottom gate, and forming a second channel layer above the second bottom gate, wherein the first channel layer and the second channel layer are located in the same layer; A first top gate is formed above the first channel layer, and a second top gate is formed above the second channel layer, wherein the first top gate and the second top gate are located in the same layer.

20. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 15.

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