Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a buried dielectric layer, a transverse power device, a longitudinal power device and an isolation structure. The buried dielectric layer is arranged in the substrate and comprises a first part with gradient thickness and an opening. The transverse power device is arranged above the first part of the buried dielectric layer and comprises a source electrode region and a drain electrode region which are arranged in a spaced mode in the direction parallel to the substrate. The longitudinal power device comprises a well region, a drift region, a source region and a drain region; wherein the well region is located in the substrate above the opening of the buried dielectric layer; the source region is located in the well region; the drift region penetrates through the opening of the buried dielectric layer and the well region, and comprises a region, located below the buried dielectric layer, of the substrate; the drain region is located at the bottom of the drift region. The isolation structure is located in the substrate between the transverse power device and the longitudinal power device, and the bottom is connected with the buried dielectric layer. According to the invention, the application of the SOI high-voltage integrated circuit is expanded.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method of a semiconductor structure. Background Art

[0002] BCD (Bipolar-CMOS-DMOS) technology is a monolithic integration process technology that can fabricate Bipolar (bipolar transistor) devices, CMOS (metal-oxide-semiconductor field-effect transistor) devices, and DMOS (double-diffused metal-oxide-semiconductor field-effect transistor) devices on the same chip. The devices prepared by this process combine the advantages of bipolar devices with high transconductance and strong load driving ability, and CMOS devices with high integration and low power consumption; at the same time, the DMOS device, as a power device, can carry a larger voltage and has extremely low power consumption when operating in the switching mode, and can transfer high power to the load without an expensive packaging and cooling system. This technology has been widely applied in fields such as automotive electronics, power management, lighting, and radio frequency communication. Among them, the DMOS responsible for the power part is the core of such circuits. Because it needs to carry a relatively large current and voltage, its area often occupies 30%-90% of the entire area and is the key to the entire integrated circuit. However, in related technologies, only power devices with one voltage level can be integrated on one chip, which easily limits the application of SOI high-voltage integrated circuits. Summary of the Invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof.

[0004] In some embodiments of the present disclosure, a semiconductor structure includes: a substrate, a buried dielectric layer, a lateral power device, a vertical power device, and an isolation structure. The buried dielectric layer is disposed in the substrate, includes a first portion with a gradient thickness, and has an opening. The lateral power device is disposed above the first portion of the buried dielectric layer and includes a source region and a drain region spaced apart in a direction parallel to the substrate. The vertical power device includes: a well region, a drift region, a source region, and a drain region; wherein, the well region is located in the substrate above the opening of the buried dielectric layer; the source region is located in the well region; the drift region penetrates through the opening of the buried dielectric layer and the well region and includes a region of the substrate below the buried dielectric layer; the drain region is located at the bottom of the drift region. The isolation structure is located in the substrate between the lateral power device and the vertical power device and is connected to the buried dielectric layer at the bottom.

[0005] In one of the embodiments, the isolation structure includes: an isolation barrier wall connected to the buried dielectric layer at the bottom.

[0006] In another embodiment, the isolation structure includes: a first isolation barrier and a second isolation barrier that are connected to the buried dielectric layer at the bottom and are spaced apart in a direction parallel to the substrate, and a depletion region located between the first isolation barrier and the second isolation barrier.

[0007] In one embodiment, the first part includes: a first sub-part facing the drain region of the lateral power device, and a second sub-part facing the source region of the lateral power device; the minimum thickness of the first sub-part is greater than the maximum thickness of the second sub-part.

[0008] In one embodiment, the upper surface of the buried dielectric layer is parallel to the surface of the substrate. The lower surface of the first part is an inclined surface, and the inclined surface includes; an inclined plane or an inclined curved surface.

[0009] In one embodiment, the buried dielectric layer further includes a second part with a thickness less than or equal to the minimum thickness of the first part. The semiconductor structure further includes: a non-power device. The non-power device is disposed above the second part of the buried dielectric layer.

[0010] In one embodiment, the non-power device is located on a side of the lateral power device away from the vertical power device. The isolation structure includes: a first isolation structure located between the lateral power device and the vertical power device, and a second isolation structure located between the lateral power device and the non-power device.

[0011] In another embodiment, the non-power device is located between the lateral power device and the vertical power device. The isolation structure includes: a third isolation structure located between the non-power device and the vertical power device, and a fourth isolation structure located between the non-power device and the lateral power device.

[0012] In some embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes the following steps. Provide a substrate, and form a hard mask layer on the substrate; the hard mask layer includes a first thickness film layer and a second thickness film layer disposed in the same layer, wherein the thickness of the first thickness film layer has a gradient, and the thickness of the second thickness film layer is greater than the maximum thickness of the first thickness film layer.

[0013] Perform ion implantation on the substrate based on the hard mask layer to form a buried dielectric layer in the substrate. The buried dielectric layer includes a first part with a gradient thickness, and the buried dielectric layer has an opening; wherein, the first part is formed based on the first thickness film layer, and the opening is formed based on the second thickness film layer.

[0014] Remove the hard mask layer.

[0015] Form an isolation structure. The bottom of the isolation structure is connected to the buried dielectric layer and separates out a plurality of active regions.

[0016] A lateral power device is formed. The lateral power device is located in the active region and above the first part of the buried dielectric layer, and includes a source region and a drain region that are spaced apart in a direction parallel to the substrate.

[0017] A vertical power device is formed. The vertical power device includes: a well region, a drift region, a source region, and a drain region; wherein, the well region is located in the active region above the opening of the buried dielectric layer; the source region is located in the well region; the drift region penetrates through the opening of the buried dielectric layer and the well region, and includes a region of the substrate located below the buried dielectric layer; the drain region is located at the bottom of the drift region.

[0018] In one embodiment, the forming of the isolation structure includes: forming a trench in the substrate above the buried dielectric layer, the trench separating the substrate into a plurality of active regions; forming an isolation barrier in the trench to obtain the isolation structure.

[0019] In another embodiment, the forming of the isolation structure includes: forming a trench in the substrate above the buried dielectric layer, the trench separating the substrate into a plurality of active regions and at least one depletion region; forming an isolation barrier in the trench; wherein, the lateral power device and the vertical power device are respectively located on two sides of the depletion region in a direction parallel to the substrate; the depletion region and the isolation barriers on both sides thereof constitute the isolation structure.

[0020] In one embodiment, the forming of the hard mask layer on the substrate includes the following steps.

[0021] Form a hard mask material layer on the substrate.

[0022] Form a first photoresist layer having a first opening pattern on the hard mask material layer.

[0023] Based on the first opening pattern, etch the hard mask material layer to obtain an initial hard mask layer; the initial hard mask layer has a second thickness film layer and an initial third thickness film layer, the thickness of the initial third thickness film layer is less than the thickness of the second thickness film layer, and is greater than or equal to the maximum thickness of the first thickness film layer.

[0024] Remove the first photoresist layer.

[0025] Form a second photoresist layer having a second opening pattern on the initial hard mask layer; the second opening pattern exposes a part of the initial third thickness film layer.

[0026] Based on the second opening pattern, wet-etch the initial hard mask layer to obtain the hard mask layer. The hard mask layer includes: a first thickness film layer, a second thickness film layer, and a third thickness film layer.

[0027] Remove the second photoresist layer.

[0028] In one embodiment, the substrate is a silicon wafer. Ion implantation is performed on the substrate based on the hard mask layer to form a buried dielectric layer in the substrate, including: performing oxygen ion implantation on the substrate based on the hard mask layer; performing a high-temperature treatment on the substrate after the oxygen ion implantation to form the buried dielectric layer.

[0029] In one embodiment, the method for manufacturing a semiconductor structure further includes: forming a non-power device in the active region on the side of the lateral power device away from the vertical power device, or forming a non-power device in the active region between the lateral power device and the vertical power device; wherein, the non-power device is located above the second part of the buried dielectric layer.

[0030] In the above semiconductor structure and its manufacturing method, by providing a buried dielectric layer in the substrate and making the buried dielectric layer include a first part with a gradient in thickness and having an opening, a lateral power device can be formed above the first part of the buried dielectric layer, and a vertical power device can be formed based on the opening of the buried dielectric layer, thereby enabling the integration of different power devices in the same semiconductor structure. Moreover, in the embodiments of the present disclosure, through the opening of the buried dielectric layer, the substrate above and below the buried dielectric layer can be used together to form the drift region of the vertical power device, so as to further improve the breakdown voltage characteristics of the vertical power device. In the embodiments of the present disclosure, through the first part with a gradient in thickness in the buried dielectric layer, the requirements for the breakdown voltage characteristics and heat dissipation characteristics of the lateral power device can also be taken into account simultaneously, so as to further improve the reliability of the lateral power device. In the embodiments of the present disclosure, through the isolation structure provided in the substrate between the lateral power device and the vertical power device and connected to the buried dielectric layer at the bottom, the complete isolation between the lateral power device and the vertical power device can be effectively achieved based on the SOI process, so as to further improve the reliability of the semiconductor structure.

[0031] As described above, the above semiconductor structure and its manufacturing method can effectively improve the device performance and reliability of the semiconductor structure, so as to expand the application of SOI high-voltage integrated circuits. Moreover, the manufacturing method provided by the present disclosure has a simple process and is easy to implement, which is beneficial to improving the production efficiency and yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To better describe and illustrate the embodiments and / or examples of those inventions disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the inventions disclosed, the embodiments and / or examples currently described, and the best mode currently understood of these inventions.

[0033] Figure 1 is a schematic cross-sectional view of a semiconductor structure in some embodiments of the present disclosure;

[0034] Figure 2It is a cross-sectional schematic diagram of another semiconductor structure in some embodiments of the present disclosure;

[0035] Figure 3 It is a cross-sectional schematic diagram of an inclined plane in some buried dielectric layers in some embodiments of the present disclosure;

[0036] Figure 4 It is a cross-sectional schematic diagram of the structures obtained in each step of an epitaxial layer formation process in some embodiments of the present disclosure;

[0037] Figure 5 It is a flowchart of a method for manufacturing a semiconductor structure in some embodiments of the present disclosure;

[0038] Figure 6 It is a flowchart of a step S100 in some embodiments of the present disclosure;

[0039] Figure 7 It is a flowchart of a step S200 in some embodiments of the present disclosure;

[0040] Figure 8 It is a flowchart of a step S400 in some embodiments of the present disclosure;

[0041] Figure 9 It is a flowchart of another step S400 in some embodiments of the present disclosure;

[0042] Figure 10a It is a cross-sectional schematic diagram of the structure obtained after forming a first photoresist layer in some embodiments of the present disclosure;

[0043] Figure 10b It is a cross-sectional schematic diagram of the structure obtained after forming a second photoresist layer in some embodiments of the present disclosure;

[0044] Figure 10c It is a cross-sectional schematic diagram of the structure obtained after forming a hard mask layer in some embodiments of the present disclosure;

[0045] Figure 10d It is a cross-sectional schematic diagram of the structure obtained after forming a buried dielectric layer in some embodiments of the present disclosure;

[0046] Figure 10e It is a cross-sectional schematic diagram of the structure obtained after removing the hard mask layer in some embodiments of the present disclosure;

[0047] Figure 10f It is a cross-sectional schematic diagram of some structures obtained after forming an isolation structure in some embodiments of the present disclosure. Detailed implementation manners

[0048] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0050] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. "Connection" in this specification, if there is an electrical signal or data transfer between the connected circuits, modules, units, etc., should be understood as "electrical connection", "communication connection", etc. It should be understood that although terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part.

[0051] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein for convenience in description to describe the relationship of one element or feature shown in the drawings to other elements or features. It should be understood that, in addition to the orientation shown in the drawings, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawing is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0052] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It will be understood that "at least one" means one or more and "a plurality" means two or more. "At least a portion of an element" means a portion or all of the element. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0053] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shown shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present invention should not be limited to the particular shapes of regions shown herein but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the present invention.

[0054] The semiconductor field vocabulary used herein is the common technical vocabulary of those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentration, simply P+ type represents the P-type with a high doping concentration, P type represents the P-type with a medium doping concentration, P- type represents the P-type with a low doping concentration, N+ type represents the N-type with a high doping concentration, N type represents the N-type with a medium doping concentration, and N- type represents the N-type with a low doping concentration.

[0055] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which can achieve the integration of different power devices in the same semiconductor structure to expand the application of SOI high-voltage integrated circuits.

[0056] Please refer to Figure 1 and Figure 2, in some embodiments of the present disclosure, a semiconductor structure includes: a substrate 1, a buried dielectric layer 2, a lateral power device 3, a vertical power device 4, and an isolation structure 5. The buried dielectric layer 2 is disposed within the substrate 1 and includes: a first portion 22 having a thickness gradient and having an opening 21. The lateral power device 3 is disposed above the first portion 22 of the buried dielectric layer 2 and includes a source region 31 and a drain region 32 spaced apart in a direction parallel to the substrate 1. The vertical power device 4 includes: a well region 41, a drift region 42, a source region 43, and a drain region 44; wherein, the well region 41 is located within the substrate 1 above the opening 21 of the buried dielectric layer 2; the source region 43 is located within the well region 41; the drift region 43 penetrates through the opening 21 of the buried dielectric layer 2 and the well region 41 and includes a region of the substrate 1 below the buried dielectric layer 2; the drain region 44 is located at the bottom of the drift region 43. The isolation structure 5 is located within the substrate 1 between the lateral power device 3 and the vertical power device 4 and is connected to the buried dielectric layer 2 at the bottom.

[0057] Exemplarily, the substrate 1 has a first conductivity type, such as a P-type silicon substrate or an N-type silicon substrate. The buried dielectric layer 2 is a buried oxide layer, and its material may be silicon oxide, such as silicon dioxide. In an embodiment of the present disclosure, the minimum thickness of the buried dielectric layer 2 may range from 1 micron to 8 microns.

[0058] In one of the embodiments, the first portion 22 of the buried dielectric layer 2 having a thickness gradient means that: the thickness of each longitudinal section of the first portion 22 in a direction perpendicular to the substrate 1 may gradually change in a direction parallel to the substrate 1, for example, may exhibit an equal increment change or an equal ratio change, etc.

[0059] In one of the embodiments, please continue to refer to Figure 1 and Figure 2 , the first portion 22 of the buried dielectric layer 2 includes: a first sub-portion 221 facing the drain region 32 of the lateral power device 3, and a second sub-portion 222 facing the source region 31 of the lateral power device 3; the minimum thickness of the first sub-portion 221 is greater than the maximum thickness of the second sub-portion 222.

[0060] In one of the embodiments, as Figure 1 and Figure 2 shown, the upper surface of the buried dielectric layer 2 is parallel to the surface of the substrate 1. The lower surface of the first portion 22 is an inclined surface, and the inclined surface includes; an inclined plane or an inclined curved surface. The inclined curved surface includes, for example, a convex inclined surface or a concave inclined surface. Figure 3 respectively shows the inclined plane S1 in (a), the convex inclined surface S2 in (b), and the concave inclined surface S3 in (c).

[0061] Exemplarily, the lateral power device 3 includes, but is not limited to, an LDMOS (lateral double-diffused MOSFET) device. Figure 1 and Figure 2 respectively take the lateral power device 3 as an LDMOS device as an example for illustration.

[0062] Please continue to refer to Figure 1 and Figure 2 Exemplarily, in the LDMOS device, a drift region 33 and a well region 34 are formed in the substrate 1 above the first part 22 of the buried dielectric layer 2. Among them, the drain region 32 can be formed in the drift region 33, and the source region 31 can be formed in the well region 34. Moreover, the conductive types of the drift region 33 and the well region 34 are different, and the conductive types of the drain region 32 and the source region 31 are different from the conductive type of the well region 34.

[0063] In some examples, as Figure 1 and Figure 2 shown, in the LDMOS device, the drift region 33, the drain region 32, and the source region 31 are all N-type doped regions, and the well region 34 is a P-type doped region; among them, the ion doping concentrations of the drain region 32 and the source region 31 are greater than the ion doping concentration of the drift region 33.

[0064] Please continue to refer to Figure 1 and 2 Exemplarily, the LDMOS device further includes a gate structure 35. The gate structure 35 can be formed above the substrate 1. The orthographic projection of the gate structure 35 on the substrate 1 can be located within the interval between the source region 31 and the drain region 32, or it can not only be located within the interval between the source region 31 and the drain region 32, but also partially overlap with at least one of the source region 31 and the drain region 32.

[0065] Exemplarily, the vertical power device 4 includes, but is not limited to, a VDMOS (Vertical Double-diffused MOSFET) device. For example, the vertical power device 4 can also be an IGBT (insulated gate bipolar transistor) device or an SGT (Shielded Gate Trench) device, etc. Figure 1 and Figure 2 respectively take the vertical power device 4 as a VDMOS device as an example for illustration.

[0066] Please continue to refer to Figure 1 and 2, For example, in a VDMOS device, the drain region 44 and the source region 43 are spaced apart in a direction perpendicular to the substrate 1, and the two source regions 43 can be spaced apart in a direction parallel to the substrate 1 and are respectively located on both sides of the portion of the drift region 42 that penetrates the well region 41. The VDMOS device further includes a gate structure 45 formed above the substrate 1, and the gate structure 45 can cover the drift region 42, a part of the well region 41, a part of the source region 43, etc. Optionally, the gate structure 45 of the VDMOS device can also be set as a trench gate structure.

[0067] In the embodiments of the present disclosure, by providing a buried dielectric layer 2 in the substrate 1 and making the buried dielectric layer 2 include a first part 22 with a gradient thickness and having an opening 21, a lateral power device 3 can be formed above the first part 22 of the buried dielectric layer 2, and a vertical power device 4 can be formed based on the opening 21 of the buried dielectric layer 2, so as to be able to realize the integration of different power devices in the same semiconductor structure (such as the same chip). Moreover, in the embodiments of the present disclosure, through the opening 21 of the buried dielectric layer 2, the substrate 1 above and below the buried dielectric layer 2 can be used together to form the drift region 42 of the vertical power device 4, so as to further improve the breakdown voltage characteristics of the vertical power device 4. In the embodiments of the present disclosure, through the first part 22 with a gradient thickness in the buried dielectric layer 2, the requirements of the lateral power device 3 for breakdown voltage characteristics and heat dissipation characteristics can also be taken into account at the same time, so as to further improve the reliability of the lateral power device 3. In the embodiments of the present disclosure, through the isolation structure 5 provided in the substrate 1 between the lateral power device 3 and the vertical power device 4 and having its bottom connected to the buried dielectric layer 2, the complete isolation between the lateral power device 3 and the vertical power device 4 can also be effectively realized based on the SOI process, so as to further improve the reliability of the semiconductor structure.

[0068] As described above, the embodiments of the present disclosure can effectively improve the device performance and reliability of the semiconductor structure to expand the application of SOI high-voltage integrated circuits.

[0069] In some embodiments, please continue to refer to Figure 1 and Figure 2 , the buried dielectric layer 2 further includes a second part 23 with a thickness less than or equal to the minimum thickness of the first part 22. The semiconductor structure further includes: a non-power device 6. The non-power device 6 is disposed above the second part 23 of the buried dielectric layer 2.

[0070] For example, the non-power device 6 includes but is not limited to a CMOS (Complementary Metal Oxide Semiconductor) device. Figure 1 and Figure 2 show examples with the non-power device 6 being a CMOS device respectively.

[0071] For example, asFigure 1 and Figure 2 As shown in Figure 2 , in a CMOS device, a well region 61 may be formed on top of a substrate 1 above a second portion 23 of a buried dielectric layer 2. A source region 62 and a drain region 63 are located within the same well region 61 and are spaced apart in a direction parallel to the substrate 1. The CMOS device further includes a gate structure 64 formed above the substrate 1.

[0072] In some embodiments, as Figure 1 shown in Figure 1 , a non-power device 6 is located on a side of the lateral power device 3 away from the longitudinal power device 4.

[0073] In some other embodiments, as Figure 2 shown in Figure 2 , the non-power device 6 is located between the lateral power device 3 and the longitudinal power device 4.

[0074] In some embodiments, as Figure 1 shown in Figure 1 , the isolation structure 5 includes: a first isolation structure 51 located between the lateral power device 3 and the longitudinal power device 4, and a second isolation structure 52 located between the lateral power device 3 and the non-power device 6.

[0075] In some other embodiments, as Figure 2 shown in Figure 2 , the isolation structure 5 includes: a third isolation structure 53 located between the non-power device 6 and the longitudinal power device 4, and a fourth isolation structure 54 located between the non-power device 6 and the lateral power device 3.

[0076] Exemplarily, the first isolation structure 51 includes: a first isolation barrier 511 and a second isolation barrier 512 that are connected to the buried dielectric layer 2 at the bottom and are spaced apart in a direction parallel to the substrate 1, and a depletion region 513 located between the first isolation barrier 511 and the second isolation barrier 512. The conductivity type of the depletion region 513 is different from that of the substrate 1. Providing the depletion region 513 can avoid the influence of the electric field lines of the lateral power device 3 and the longitudinal power device 4 on each other.

[0077] Exemplarily, the second isolation structure 52 includes: an isolation barrier connected to the buried dielectric layer 2 at the bottom.

[0078] Exemplarily, both the third isolation structure 53 and the fourth isolation structure 54 include: an isolation barrier connected to the buried dielectric layer 2 at the bottom.

[0079] Optionally, in some of the above embodiments, the isolation barrier for the isolation structure 5 can also be obtained by a method of coating a filler with an insulating dielectric layer, and the material of the filler can be, for example, polysilicon.

[0080] In summary, the CMOS device is a low-voltage device, and the VDMOS device and the LDMOS device are different types of high-voltage devices. Embodiments of the present disclosure can simultaneously integrate different power devices such as VDMOS devices and LDMOS devices and CMOS devices on the same substrate 1 based on the SOI technology, so as to effectively achieve high-density integration and miniaturization of the devices on the basis of meeting the breakdown voltage requirements and heat dissipation characteristics of devices with different voltage levels. Moreover, in the embodiments of the present disclosure, by increasing the thickness of the buried dielectric layer 4 below the drain region 32 of the LDMOS device, voltage coupling between the LDMOS device and adjacent devices can be avoided; in the embodiments of the present disclosure, by reducing the thickness of the buried dielectric layer 4 below the source region 31 of the LDMOS device, heat dissipation can be ensured to the greatest extent; thus, the requirements of the LDMOS device for breakdown voltage characteristics and heat dissipation characteristics are taken into account simultaneously, which is also conducive to the integration of more complex circuits and the miniaturization of the chip.

[0081] It should be added that, in some embodiments, the substrate 1 above the buried dielectric layer 2 can be obtained based on the initial substrate by forming an epitaxial layer above the initial substrate before or after forming the buried dielectric layer 2 in the initial substrate. In this way, the thickness of the substrate 1 above the buried dielectric layer 2 can be obtained by forming epitaxial layers with different thicknesses to match the requirements, so as to effectively extend the application of various high- and low-voltage transistor devices on the substrate 1.

[0082] Here, it is worth mentioning that the epitaxial layer formed above the initial substrate before or after forming the buried dielectric layer 2 in the initial substrate can be formed by selective epitaxy.

[0083] Exemplarily, please refer to Figure 1 , the initial substrate 10 has a first conductivity type. Optionally, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0084] Please combine Figure 1 to understand that before or after forming the buried dielectric region 2, a first epitaxial layer 1-1 can be formed above other regions (including but not limited to at least one of the first part 22, the second part 23, and the region below the depletion region 513) outside the opening 21 in the buried dielectric region 2, and a second epitaxial layer 1-2 can be formed above the opening 21 of the buried dielectric region 2, wherein the conductivity type of the second epitaxial layer 1-2 can be the same as that of the initial substrate 10 and different from that of the first epitaxial layer 1-1.

[0085] Exemplarily, the first conductivity type of the initial substrate 10 is N-type. The conductivity type of the first epitaxial layer 1-1 is P-type. The conductivity type of the second epitaxial layer 1-2 is N-type.

[0086] In addition, the thicknesses of the first epitaxial layer 1-1 and the second epitaxial layer 1-2 can be determined according to the breakdown voltage of the device to be formed (for example, the breakdown voltage of a trench-gate vertical device). In this way, the thicknesses of the first epitaxial layer 1-1 and the second epitaxial layer 1-2 are more convenient to adjust during manufacturing, and the upper limit of the thickness that can be formed is larger, which is convenient for adapting to the designed breakdown voltage of the device, and devices with a larger breakdown voltage can be fabricated, expanding the richness of the entire process.

[0087] Exemplarily, please refer to Figure 4 Figure (a) therein. After forming the buried dielectric layer 2 on the initial substrate 10, the upper surface of the buried dielectric layer 2 and the initial substrate 10 in the opening 21 of the buried dielectric layer 2 can be exposed, and a first epitaxial material layer 1-10, a protective dielectric layer 30, and a photoresist layer 40 can be sequentially formed on the exposed surfaces of the buried dielectric layer 2 and the initial substrate 10.

[0088] Please refer to Figure 4 Figure (b) therein. Based on the opening pattern in the photoresist layer 40, the protective dielectric layer 30 and the first epitaxial material layer 1-10 are patterned to form a protective layer 3 and a first epitaxial layer 1-1, respectively. The etched and removed regions of the protective dielectric layer 30 and the first epitaxial material layer 1-10 expose the initial substrate 10 in the opening 21 of the buried dielectric layer 2. And after forming the protective layer 3 and the first epitaxial layer 1-1, the photoresist layer 40 is removed.

[0089] Exemplarily, the initial substrate 10 has a first conductivity type, and the first epitaxial layer 1-1 has a second conductivity type.

[0090] Exemplarily, the thickness of the first epitaxial material layer 1-10 is 1 to 5 micrometers.

[0091] Please refer to Figure 4 Figure (c) therein. An isolation material layer 50 is formed to cover the sidewalls of the first epitaxial layer 1-1 and extend into the initial substrate 10 and connect to the sidewalls of the buried dielectric layer 2.

[0092] Please refer to Figure 4 Figure (d) therein. A second epitaxial material layer 1-20 is formed on the exposed upper surface of the initial substrate 10.

[0093] Exemplarily, the second epitaxial material layer 1-20 has a first conductivity type.

[0094] Please refer to Figure 4 Figure (e) therein. The protective layer 3 is removed by grinding, so that the upper surface of the first epitaxial layer 1-1 is exposed, and an isolation structure 5 and a second epitaxial layer 1-2 are simultaneously formed. Thus, the substrate 1 is obtained.

[0095] In one embodiment of the present disclosure, the initial substrate 10 may be a silicon substrate with a relatively high doping concentration, which is conducive to forming a narrower depletion region, thereby reducing the distance between two adjacent devices and further reducing the area of the semiconductor structure.

[0096] In one embodiment of the present disclosure, the doping concentration of the initial substrate 10 is controlled such that its resistivity reaches 8 Ω×cm to 45 Ω×cm.

[0097] In one embodiment of the present disclosure, the material of the protective dielectric layer 30 may be silicon oxide, such as silicon dioxide.

[0098] It can be understood that the epitaxial layer formed above the initial substrate 10 may also have other formation processes different from those described in the above embodiments. The embodiments of the present disclosure do not limit this.

[0099] Some embodiments of the present disclosure also provide a manufacturing method of a semiconductor structure for manufacturing the semiconductor structure described in the above embodiments. The manufacturing method also has all the technical advantages of the aforementioned semiconductor structure. For example, it can effectively improve the device performance and reliability of the semiconductor structure to expand the application of SOI high-voltage integrated circuits. Moreover, the manufacturing method provided by the present disclosure has a simple process, is easy to implement, and is also conducive to improving production efficiency and yield.

[0100] Please refer to Figure 5 , and the manufacturing method includes the following steps S100 to S600.

[0101] S100, providing a substrate and forming a hard mask layer on the substrate; the hard mask layer includes a first-thickness film layer and a second-thickness film layer disposed in the same layer, wherein the thickness of the first-thickness film layer has a gradient, and the thickness of the second-thickness film layer is greater than the maximum thickness of the first-thickness film layer.

[0102] S200, performing ion implantation on the substrate based on the hard mask layer to form a buried dielectric layer in the substrate. The buried dielectric layer includes a first part with a gradient in thickness, and the buried dielectric layer has an opening; wherein the first part is formed based on the first-thickness film layer, and the opening is formed based on the second-thickness film layer.

[0103] S300, removing the hard mask layer.

[0104] S400, forming an isolation structure. The bottom of the isolation structure is connected to the buried dielectric layer and separates out a plurality of active regions.

[0105] S500, forming a lateral power device. The lateral power device is located in the active region and above the first part of the buried dielectric layer, and includes a source region and a drain region spaced apart in a direction parallel to the substrate.

[0106] S600 forms a vertical power device. The vertical power device includes: a well region, a drift region, a source region, and a drain region; wherein, the well region is located in the active region above the opening of the buried dielectric layer; the source region is located in the well region; the drift region penetrates through the opening of the buried dielectric layer and the well region, and includes the region of the substrate located below the buried dielectric layer; the drain region is located at the bottom of the drift region.

[0107] In one embodiment, please refer to Figure 6 , in step S100, forming a hard mask layer on the substrate may include the following steps S110 to S170.

[0108] S110, forming a hard mask material layer on the substrate.

[0109] S120, forming a first photoresist layer with a first opening pattern on the hard mask material layer.

[0110] S130, etching the hard mask material layer based on the first opening pattern to obtain an initial hard mask layer; the initial hard mask layer has a second thickness film layer and an initial third thickness film layer, the thickness of the initial third thickness film layer is less than the thickness of the second thickness film layer, and is greater than or equal to the maximum thickness of the first thickness film layer.

[0111] S140, removing the first photoresist layer.

[0112] S150, forming a second photoresist layer with a second opening pattern on the initial hard mask layer; the second opening pattern exposes a part of the initial third thickness film layer.

[0113] S160, wet etching the initial hard mask layer based on the second opening pattern to obtain a hard mask layer. The hard mask layer includes: a first thickness film layer, a second thickness film layer, and a third thickness film layer.

[0114] S170, removing the second photoresist layer.

[0115] In one embodiment, the substrate is a silicon wafer. Please refer to Figure 7 , in step S200, ion implanting the substrate based on the hard mask layer to form a buried dielectric layer in the substrate may include the following steps S210 and S220.

[0116] S210, performing oxygen ion implantation on the substrate based on the hard mask layer.

[0117] S220, performing a high-temperature treatment on the substrate after oxygen ion implantation to form a buried dielectric layer.

[0118] In one embodiment, please refer to Figure 8 , in step S400, forming an isolation structure may include the following steps S410 and S420.

[0119] S410, form trenches in a substrate above a buried dielectric layer, the trenches separating the substrate into a plurality of active regions.

[0120] S420, form isolation barriers in the trenches to obtain an isolation structure.

[0121] In another embodiment, please refer to Figure 9 , step S400 of forming the isolation structure may include the following steps S410' and S420'.

[0122] S410', form trenches in a substrate above a buried dielectric layer, the trenches separating the substrate into a plurality of active regions and at least one depletion region.

[0123] S420', form isolation barriers in the trenches; wherein, a lateral power device and a vertical power device are respectively located on two sides of the depletion region along a direction parallel to the substrate; the depletion region and the isolation barriers on both sides thereof constitute the isolation structure.

[0124] It is worth mentioning that, in some embodiments, the hard mask layer includes: a first thickness film layer, a second thickness film layer, and a third thickness film layer. The buried dielectric layer formed based on the hard mask layer further includes a second portion with a thickness less than or equal to the minimum thickness of the first portion.

[0125] Correspondingly, in one embodiment, the manufacturing method of the semiconductor structure further includes S700.

[0126] S700, form a non-power device in the active region on a side of the lateral power device away from the vertical power device, wherein the non-power device is located above the second portion of the buried dielectric layer.

[0127] Correspondingly, in another embodiment, the manufacturing method of the semiconductor structure further includes S700'.

[0128] S700', form a non-power device in the active region between the lateral power device and the vertical power device, wherein the non-power device is located above the second portion of the buried dielectric layer.

[0129] It should be understood that although the steps in each flowchart of the present disclosure are sequentially shown according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0130] To more clearly illustrate the manufacturing method of the semiconductor structure in some of the above embodiments, the following will be combined with Figures 10a to 10f for understanding.

[0131] In step S100, please refer to Figures 10a to 10c , provide a substrate 1, and form a hard mask layer 11 on the substrate 1; the hard mask layer 11 includes a first thickness film layer R1 and a second thickness film layer R2. Among them, the thickness of the first thickness film layer R1 has a gradient, and the thickness of the second thickness film layer R2 is greater than the maximum thickness of the first thickness film layer R1.

[0132] Exemplarily, step S100 may include steps S110 to S170.

[0133] In steps S110 and S120, as Figure 10a shown, form a hard mask material layer 110 on the substrate 1. Form a first photoresist layer 12 with a first opening pattern K1 on the hard mask material layer 110.

[0134] Exemplarily, the substrate 1 includes but is not limited to a silicon wafer.

[0135] Exemplarily, the hard mask material layer 110 includes but is not limited to an oxide layer, for example, it can be a silicon oxide layer.

[0136] In steps S130 to S150, please combine Figure 10b for understanding. Based on the first opening pattern K1, etch the hard mask material layer 110 to obtain an initial hard mask layer 11A; the initial hard mask layer 11A has a second thickness film layer R2 and an initial third thickness film layer R3'. The thickness of the initial third thickness film layer R3' is less than the thickness of the second thickness film layer R2 and greater than or equal to the maximum thickness of the first thickness film layer R1. Remove the first photoresist layer 12. Form a second photoresist layer 13 with a second opening pattern K2 on the initial hard mask layer 11A; the second opening pattern K2 exposes a part of the initial third thickness film layer R3'.

[0137] In step S160, please combineFigure 10b and Figure 10c It can be understood that, based on the second opening pattern K2, the initial hard mask layer 11A is wet-etched to obtain the hard mask layer 11. The hard mask layer 11 includes: a first thickness film layer R1, a second thickness film layer R2, and a third thickness film layer R3.

[0138] It can be understood that when the initial hard mask layer 11A is wet-etched based on the second opening pattern K2, an inclined surface can be formed on the upper surface of the first thickness film layer R1, and the area, morphology, and the included angle between the inclined surface and the substrate 1 can all match the thickness of the buried dielectric layer 2 to be formed, and relevant process parameters of the wet etching can be set to achieve this. The embodiments of the present disclosure do not expand the description on this.

[0139] In step S170, please refer to Figure 10d , and remove the second photoresist layer 13.

[0140] In step S200, please refer to Figure 10d , based on the hard mask layer 11, ion implantation is performed on the substrate 1 to form a buried dielectric layer 2 in the substrate 1. The buried dielectric layer 2 includes a first part 22 with a gradient in thickness, and the buried dielectric layer 2 has an opening 21; wherein, the first part 22 is formed based on the first thickness film layer R1, and the opening 21 is formed based on the second thickness film layer R2.

[0141] Here, the hard mask layer 11 is an implantation blocking layer. The fact that the first part 22 has a gradient in thickness means that: the thickness D1 of each longitudinal section of the first part 22 along the direction perpendicular to the substrate 1 gradually changes along the direction parallel to the substrate 1, for example, it can show an equal increment change or an equal ratio change, etc.

[0142] Exemplarily, as shown in Figure 10d , the hard mask layer 11 includes a third thickness film layer R3. The buried dielectric layer 2 further includes: a second part 23 with a thickness less than or equal to the minimum thickness of the first part 22. The second part 23 is formed based on the third thickness film layer R3.

[0143] It should be noted that Figure 10d , taking the example that the first part 22 is located on the side of the second part 23 far away from the opening 21, the buried dielectric layer 2 is schematically shown. However, it can be understood that to match the distribution requirements of different types of power devices and other transistor devices, the first part 22, the second part 23, and the opening 21 can have any position distribution, and the embodiments of the present disclosure do not make specific limitations on this.

[0144] Exemplarily, the substrate 1 can be a silicon wafer. Step S200 can include the following steps S210 to S220:

[0145] In step S210, oxygen ion implantation is performed on the substrate 1 based on the hard mask layer 11.

[0146] Here, the implantation depth of oxygen ions is related to the ion implantation concentration and the ion implantation energy, and the implantation of oxygen ions can be achieved by controlling the relevant process parameters.

[0147] In step S220, the substrate 1 after oxygen ion implantation is heat-treated (high-temperature treatment) to form a buried dielectric layer 2.

[0148] Here, the high-temperature treatment can be, for example, an annealing treatment. The treatment temperature of the high-temperature treatment can be set according to the requirements. The embodiments of the present disclosure do not limit this.

[0149] Exemplarily, the buried dielectric layer 2 is a buried oxide layer, and its material can be silicon oxide, such as silicon dioxide.

[0150] In the embodiments of the present disclosure, heat-treating the substrate 1 after oxygen ion implantation can also effectively eliminate internal defects in the buried dielectric layer 2 and the substrate 1.

[0151] As described above, the present disclosure can effectively optimize the electric field lines of the semiconductor structure by using the opening 21 in the buried dielectric layer 2, the thickness D1 gradient of the first part 22, and the second part 23, so as to easily improve the heat dissipation performance of the semiconductor structure while meeting the requirements of high-voltage device characteristics, thereby effectively improving the device performance and reliability of the semiconductor structure. Moreover, the manufacturing method provided by the present disclosure has a simple process and is easy to implement, which is beneficial to improving production efficiency and yield.

[0152] In step S300, please refer to Figure 10e , and remove the hard mask layer 11.

[0153] In some examples, after removing the hard mask layer 11, the foregoing substrate can also be used as the initial substrate to grow an epitaxial layer on the initial substrate, so as to ensure that the thickness of the substrate above the buried dielectric layer 2 can meet the requirements.

[0154] In step S400, please refer to Figure 10f , and form an isolation structure 5. The bottom of the isolation structure 5 is connected to the buried dielectric layer 2 and separates out a plurality of active regions AA.

[0155] Exemplarily, in step S410, a trench can be first formed in the substrate 1 above the buried dielectric layer 2 to separate the substrate 1 into a plurality of active regions AA through the trench. Here, matching different regions of the buried dielectric layer 2, each active region AA can be respectively used to fabricate different power devices or other transistor devices. In step S420, an isolation barrier can be formed in the trench to obtain the isolation structure 5. After that, LDMOS devices, VDMOS devices, CMOS devices, etc. can be respectively fabricated based on each active region AA, so as to obtain the semiconductor structure as Figure 2 described.

[0156] Exemplarily, in step S410', trenches may be formed in the substrate 1 above the buried dielectric layer 2 first, so as to divide the substrate 1 into a plurality of active regions AA and at least one depletion region 513 through the trenches. Here, matching different regions of the buried dielectric layer 2, each active region AA may be respectively used to fabricate different power devices or other transistor devices. In step S420', isolation barriers may be formed in the trenches. After that, LDMOS devices, VDMOS devices, CMOS devices, etc. may be respectively fabricated based on each active region AA, so as to obtain the semiconductor structure as described in Figure 1 wherein, the lateral power device 3 and the vertical power device 4 may be respectively located on both sides of the depletion region 513 along the direction parallel to the substrate 1; the depletion region 513 and the isolation barriers (511 and 512) on both sides thereof together constitute the isolation structure 5.

[0157] It can be understood that the internal structures of different types of power devices or other transistor devices may be different. Thus, matching the internal structures of different devices, there may be various possible implementations for the fabrication processes of each device, and the embodiments of the present disclosure do not limit the fabrication processes of each device. For example, the aforementioned LDMOS devices, VDMOS devices, and CMOS devices may be fabricated independently, or there may be some overlapping or intersecting steps in the fabrication to the extent that each device can be fabricated.

[0158] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0159] The technical features of the above-described embodiments may be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0160] The above-described embodiments only represent several implementation manners of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A buried dielectric layer disposed within the substrate, including a first portion having a gradient in thickness and having an opening; A lateral power device disposed above the first portion of the buried dielectric layer, including a source region and a drain region spaced apart in a direction parallel to the substrate; A vertical power device, including: a well region, a drift region, a source region, and a drain region; wherein, the well region is within the substrate above the opening; the source region is within the well region; the drift region penetrates through the opening and the well region and includes a region of the substrate below the buried dielectric layer; the drain region is at the bottom of the drift region; An isolation structure located within the substrate between the lateral power device and the vertical power device and having a bottom connected to the buried dielectric layer.

2. The semiconductor structure according to claim 1, wherein The isolation structure includes: an isolation barrier wall having a bottom connected to the buried dielectric layer; Or, the isolation structure includes: a first isolation barrier wall and a second isolation barrier wall having bottoms connected to the buried dielectric layer and spaced apart in a direction parallel to the substrate, and a depletion region located between the first isolation barrier wall and the second isolation barrier wall.

3. The semiconductor structure according to claim 1, characterized in that, The first portion includes: a first sub-portion facing the drain region of the lateral power device, and a second sub-portion facing the source region of the lateral power device; Wherein, the minimum thickness of the first sub-portion is greater than the maximum thickness of the second sub-portion.

4. The semiconductor structure according to claim 3, wherein The upper surface of the buried dielectric layer is parallel to the surface of the substrate; the lower surface of the first portion is an inclined surface, and the inclined surface includes; an inclined plane or an inclined curved surface.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The buried dielectric layer further includes a second portion having a thickness less than or equal to the minimum thickness of the first portion; The semiconductor structure further includes: A non-power device disposed above the second portion of the buried dielectric layer; Wherein, the non-power device is located on a side of the lateral power device away from the vertical power device; the isolation structure includes: a first isolation structure located between the lateral power device and the vertical power device, and a second isolation structure located between the lateral power device and the non-power device; Or, the non-power device is located between the lateral power device and the vertical power device; the isolation structure includes: a third isolation structure located between the non-power device and the vertical power device, and a fourth isolation structure located between the non-power device and the lateral power device.

6. A manufacturing method of a semiconductor structure, characterized in that, Comprising: Providing a substrate, and forming a hard mask layer on the substrate; The hard mask layer includes a first thickness film layer and a second thickness film layer provided in the same layer, wherein, the thickness of the first thickness film layer has a gradient, and the thickness of the second thickness film layer is greater than the maximum thickness of the first thickness film layer; Based on the hard mask layer, ion implanting the substrate to form a buried dielectric layer within the substrate; the buried dielectric layer includes a first portion having a gradient in thickness, and the buried dielectric layer has an opening; wherein, the first portion is formed based on the first thickness film layer, and the opening is formed based on the second thickness film layer; Removing the hard mask layer; Form an isolation structure; the bottom of the isolation structure is connected to the buried dielectric layer and separates a plurality of active regions; Form a lateral power device; the lateral power device is located in the active region and above the first part of the buried dielectric layer; the lateral power device includes a source region and a drain region spaced apart in a direction parallel to the substrate; Form a vertical power device; the vertical power device includes: a well region, a drift region, a source region, and a drain region; wherein, the well region is located in the active region above the opening; the source region is located in the well region; the drift region penetrates through the opening and the well region and includes a region of the substrate below the buried dielectric layer; the drain region is located at the bottom of the drift region.

7. The manufacturing method of the semiconductor structure according to claim 6, characterized in that, The forming of the isolation structure includes: Form a trench in the substrate above the buried dielectric layer, the trench separating the substrate into a plurality of the active regions; form an isolation barrier in the trench to obtain the isolation structure; Or, form a trench in the substrate above the buried dielectric layer, the trench separating the substrate into a plurality of the active regions and at least one depletion region; form an isolation barrier in the trench; wherein, the lateral power device and the vertical power device are respectively located on two sides of the depletion region in a direction parallel to the substrate; the depletion region and the isolation barriers on both sides thereof constitute the isolation structure.

8. The manufacturing method of the semiconductor structure according to claim 6, characterized in that, The forming of the hard mask layer on the substrate includes: Form a hard mask material layer on the substrate; Form a first photoresist layer having a first opening pattern on the hard mask material layer; Based on the first opening pattern, etch the hard mask material layer to obtain an initial hard mask layer; the initial hard mask layer has the second thickness film layer and an initial third thickness film layer; the thickness of the initial third thickness film layer is less than the thickness of the second thickness film layer and greater than or equal to the maximum thickness of the first thickness film layer; Remove the first photoresist layer; Form a second photoresist layer having a second opening pattern on the initial hard mask layer; the second opening pattern exposes a part of the initial third thickness film layer; Based on the second opening pattern, wet-etch the initial hard mask layer to obtain the hard mask layer; the hard mask layer includes: the first thickness film layer, the second thickness film layer, and a third thickness film layer; Remove the second photoresist layer.

9. The manufacturing method of the semiconductor structure according to claim 6, wherein, The substrate is a silicon wafer; the forming of the buried dielectric layer in the substrate by ion implantation based on the hard mask layer includes: Perform oxygen ion implantation on the substrate based on the hard mask layer; Perform a high-temperature treatment on the substrate after the oxygen ion implantation to form the buried dielectric layer.

10. The manufacturing method of the semiconductor structure according to any one of claims 6 to 9, characterized in that, It further includes: Form a non-power device in the active region on the side of the lateral power device away from the vertical power device, or form a non-power device in the active region between the lateral power device and the vertical power device; Wherein, the non-power device is located above the second part of the buried dielectric layer.

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