Integrated circuit device and manufacturing method thereof

Abstract

A back-end-of-line (BEOL) transistor includes a source electrode vertically stacked over a drain electrode and spaced apart from the drain electrode by a dielectric spacer between a first horizontal conductive layer and a second horizontal conductive layer. A semiconductor layer extends vertically between the source electrode and the drain electrode along sidewalls of the dielectric spacer. The drain electrode provides a channel for the transistor. A gate dielectric layer and a gate electrode are disposed over the channel. This structure allows the transistor to be manufactured without performing an etching process that may introduce defects into the semiconductor layer. The source electrode may extend laterally to provide a bottom electrode of a memory cell integrated with the BEOL transistor. The embodiment of the invention also relates to an integrated circuit device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to integrated circuit devices and methods of manufacturing the same. Background Art

[0002] Integrated circuit devices may include millions or billions of transistors. The transistors are configured to function as switches and / or provide power gain to implement logic functions for the integrated chip (e.g., form a processor configured to perform logic functions). The integrated chip may also include a large number of passive devices, such as capacitors, resistors, inductors, varactors, etc. The passive devices are widely used to control the characteristics of the integrated chip, such as gain, time constant, etc. The active and passive devices may be used to provide memory in a large-scale array. Summary of the Invention

[0003] Embodiments of the present disclosure provide an integrated circuit device, including: a semiconductor substrate; a metal interconnect structure located above the semiconductor substrate; and a first transistor located within the metal interconnect structure; wherein the first transistor includes a first source / drain electrode, a second source / drain electrode, a channel, a gate dielectric, and a gate electrode; the second source / drain electrode is vertically stacked above the first source / drain electrode and is separated from the first source / drain electrode by a dielectric spacer; the dielectric spacer has sidewalls extending from the second source / drain electrode to the first source / drain electrode; the channel is provided by a semiconductor layer forming a coating on the sidewalls; and the gate dielectric is located between the gate electrode and the channel.

[0004] Another embodiment of the present disclosure provides an integrated circuit device, including: a semiconductor substrate; a metal interconnect structure located above the semiconductor substrate; an electrode stack including a second electrode layer above a dielectric spacer above a first electrode layer, wherein the electrode stack is located within the metal interconnect structure and has sidewalls including the second electrode layer and the dielectric spacer; an oxide semiconductor layer located above the sidewalls; and a gate stack including a high-k dielectric layer and a gate electrode, wherein the gate stack is disposed above the oxide semiconductor layer; wherein the electrode stack and the gate stack form a transistor, and the second electrode layer and the first electrode layer provide source and drain electrodes for the transistor.

[0005] Another embodiment of the present disclosure provides a method of manufacturing an integrated circuit device, the method comprising: forming a metallization layer over a semiconductor substrate including a first region and a second region; forming a first source / drain electrode layer over the metallization layer; forming a spacer layer over the first source / drain electrode layer; forming a second source / drain electrode layer over the spacer layer; forming a first mask; etching through the second source / drain electrode layer and the spacer layer, wherein the etching forms sidewalls aligned with the edges of the first mask, the sidewalls comprising the second source / drain electrode layer and the spacer layer, and the sidewalls are located in the first region; forming a semiconductor layer covering the sidewalls; forming a gate dielectric layer over the semiconductor layer; and depositing a gate electrode layer over the gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 3 Cross-sectional views of integrated circuit (IC) devices in accordance with various embodiments of the present disclosure are shown.

[0008] Figures 4A to 4C Patterns of depressions in bottom electrodes of memory cells in accordance with various embodiments are shown.

[0009] Figure 5A Cross-sectional views of an IC device in accordance with another embodiment are shown, and Figure 5B A plan view of an IC device in accordance with another embodiment is shown.

[0010] Figures 6 to 17 A series of cross-sectional views illustrating an embodiment of a method of forming an IC device of the present disclosure is shown.

[0011] Figures 18 to 22 Shows Figures 6 to 17 a variation of the method that provides an embodiment of another method of forming an IC device of the present disclosure.

[0012] Figures 23 to 41B A series of views illustrating an embodiment of a method of forming an IC device of the present disclosure is shown. The figures without a letter suffix or with a suffix of "A" are cross-sectional views. The figures with a suffix of "B" are plan views.

[0013] Figures 42 to 44 Flowcharts providing various embodiments of a method of forming an IC device in accordance with the present disclosure are shown. DETAILED DESCRIPTION

[0014] Numerous different embodiments or examples are provided below to implement different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming the first component above or on the second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the embodiments and / or configurations being discussed.

[0015] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. In addition to the orientation shown in the figures, the spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0016] Front-end-of-line (FEOL) transistors may be a bottleneck in the development towards higher density non-volatile memories (NVMs). High density random access memories may require write currents greater than 200 μA / μm. Larger transistors or multiple transistors operating in parallel may be required to support currents of this magnitude. For example, some designs propose using two or more transistors per memory cell to provide sufficient drive current. These methods incur a significant FEOL area penalty.

[0017] To avoid this penalty, back-end-of-line (BEOL) transistors may be used as access control devices for memory cells. The BEOL transistors and the memory cells are disposed in a metal interconnect structure above a semiconductor substrate. Placing the access control device within the metal interconnect structure releases space at the surface of the semiconductor substrate and thus provides additional flexibility for device integration.

[0018] BEOL transistors within the metal interconnects typically have a channel provided by an oxide semiconductor layer. The gate for the BEOL transistor may be located below the oxide semiconductor and may be separated from the oxide semiconductor by a gate dielectric. Source electrode vias and drain electrode vias contact the upper surface of the oxide semiconductor layer. The source electrode via may be connected to the bottom electrode of the memory cell above the BEOL transistor.

[0019] The inventors have found that the damascene process used to form source electrode vias and drain electrode vias may damage the oxide semiconductor layer and may reduce the reliability of BEOL transistors. In particular, the damascene process includes etching via openings for the source electrode vias and drain electrode vias. The oxide semiconductor layer is exposed through the via openings. Etch chemical residues on the oxide semiconductor layer, damage caused by over-etching, or absorption of hydrogen / water through the via openings may create potential problems. These problems may lead to the generation of oxygen defects, additional donor states, or other phenomena that manifest as a deviation of the threshold voltage of the BEOL transistors from the design target or variability of the threshold voltage between a group of BEOL transistors.

[0020] The present disclosure provides BEOL transistors that can be easily fabricated without the problematic etching processes discussed above. The BEOL transistor includes a source electrode vertically stacked above a drain electrode and spaced apart from the drain electrode by a dielectric spacer. The channel is provided by a semiconductor layer that vertically extends between the source electrode and the drain electrode along the sidewalls of the dielectric spacer. A gate dielectric layer is disposed above the semiconductor layer, and a gate electrode is located above the gate dielectric layer. This approach results in improved quality of the oxide semiconductor layer in BEOL transistors in a memory array, reduced source / drain contact resistance, and higher reliability for memory devices. Additional benefits have been achieved, including avoidance of film stack stress that occurred in the old methods.

[0021] In some embodiments, the drain electrode protrudes from below the dielectric spacer, and the semiconductor layer has a lower horizontal portion located on the protruding portion of the drain electrode. In some embodiments, the drain electrode protrudes on all sides of the dielectric spacer. The semiconductor layer may have an upper horizontal portion located above the source electrode. With this structure, the semiconductor layer may not have cut edges or etched surfaces near the channel. In some embodiments, some or all of the cut edges of the semiconductor layer are covered by a high-k dielectric. The high-k dielectric on the cut edges can reduce leakage between the oxide semiconductor layer and the drain electrode. Although the terms "source electrode" and "drain electrode" are used in this specification, it will be understood that the structure described as the "source electrode" may be configured as a drain electrode, and the structure described as the "drain electrode" may also be configured as a source electrode.

[0022] In some embodiments, the memory cell is integrated with the BEOL transistor. In particular, the source electrode can extend laterally to provide a bottom electrode for the memory cell. In some embodiments, the memory cell and the BEOL transistor are disposed between adjacent metallization layer pairs in the metal interconnect structure. In some embodiments, the dielectric layer or the data storage structure of the memory cell is in direct contact with the bottom electrode. In some embodiments, the source electrode is recessed in the region where it provides the bottom electrode, such that the memory cell has a three-dimensional structure. The recess can be circular (such as in a hole), linear (such as in a trench), or any other suitable shape.

[0023] The memory cell can be any type of memory cell having a top electrode and a bottom electrode. In some embodiments, the memory cell is a dynamic random access memory (DRAM) cell, and the internal structure of the memory cell (the portion of the memory cell that is between the bottom electrode and the top electrode) is provided by a dielectric such that the memory cell is a capacitor. In some embodiments, the dielectric is a high-k dielectric. In some embodiments, the memory cell is a ferroelectric random access memory (FeRAM) cell, and the internal structure includes a ferroelectric layer. In some embodiments, the memory cell is a resistive random access memory (ReRAM) cell, and the internal structure includes a resistive switching material. In some embodiments, the memory cell is a magnetoresistive random access memory (MRAM) cell, and the internal structure includes a magnetic tunnel junction (MTJ). In some embodiments, the memory cell is a phase change memory (PCM) cell, and the internal structure includes a phase change material. The internal structures of these memory cells are data storage structures, except in the case of a capacitor, where the internal structure is just a dielectric.

[0024] In some embodiments where the memory cell is a capacitor, the capacitor dielectric is formed simultaneously with the gate dielectric such that the capacitor dielectric and the gate dielectric have the same composition and thickness. In some embodiments, the top electrode of the memory cell is formed simultaneously with the gate electrode of the BEOL transistor. In some embodiments, the top electrode and the gate electrode have the same composition and thickness. In some embodiments, the top electrode and the gate electrode are planarized such that the upper surface of the top electrode is coplanar with the upper surface of the gate electrode.

[0025] In some embodiments, the BEOL transistor is one of a pair of transistors that share a gate electrode. The pair can be symmetric about the gate electrode. In some embodiments, the sidewall of the dielectric spacer of the first of the pair faces the sidewall of the dielectric spacer of the second of the pair. The pair can operate in parallel as one transistor, equivalent to two transistors with twice the width, or can operate as two different transistors.

[0026] Figure 1Illustrated is an IC device 100 that includes a metal interconnect structure 161 located above a substrate 177. A semiconductor device 179 may be disposed on the substrate 177. The metal interconnect structure 161 includes a plurality of stacked metallization layers, and the plurality of stacked metallization layers include metallization layers M1, M X-1 , M X , and M X+1 . The metal interconnect structure 161 may have more or fewer metallization layers than the number shown. The metallization layers M1, M X-1 , M X , and M X+1 include lines 123. A via layer 102 and an etch stop layer 156 are disposed between each pair of adjacent M1, M X-1 , M X , and M X+1 . The lines 123 in adjacent metallization layers may be connected through vias 127 in the via layer 102.

[0027] A BEOL transistor 107 is disposed between adjacent metallization layers M X-1 and M X . The BEOL transistor 107 is formed by a semiconductor layer 114 and a gate stack 106 above a sidewall 110 of an electrode stack 119. The electrode stack 119 includes a first horizontal conductive layer 155, a spacer dielectric 151, and a second horizontal conductive layer 147 in a vertical stack. The gate stack 106 includes a gate dielectric layer 112 and a gate electrode 111. The BEOL transistor 107 includes a source electrode 116 provided by the second horizontal conductive layer 147, a drain electrode 118 provided by the first horizontal conductive layer 155, and a channel 109 provided by a vertical portion 114B of the semiconductor layer 114. The effective channel length of the BEOL transistor 107 is approximately equal to the thickness T1 of the spacer dielectric 151. In some embodiments, the thickness T1 is in the range from about 10 nm to about 100 nm. In some embodiments, the thickness T1 is in the range from about 10 nm to about 30 nm. These thicknesses provide a channel length suitable for a transistor to provide access control for a memory cell. The BEOL transistor 107 can be scaled down by reducing its horizontal dimensions while maintaining a channel length of 10 nm or longer to avoid short-channel effects.

[0028] The sidewall 110 includes a spacer dielectric 151 and a source electrode 116. The drain electrode 118 protrudes from the sidewall 110. The semiconductor layer 114 includes a lower horizontal portion 114C above a protruding portion 117 of the drain electrode 118, a vertical portion 114B on the sidewall 110, and an upper horizontal portion 114A on top of the source electrode 116. The semiconductor layer 114 has a cut edge 115. The cut edge 115 is away from the channel 109.

[0029] Memory cell 137A is integrated with BEOL transistor 107. In particular, memory cell 137A is formed directly above electrode stack 119 such that second-level conductive layer 147 provides source electrode 116 and bottom electrode 149 for memory cell 137A. Source electrode 116 and bottom electrode 149 are substantially a single structure. Memory cell 137A is a capacitor having top electrode 139 and dielectric layer 143 positioned between bottom electrode 149 and top electrode 139. According to some embodiments, dielectric layer 143 has the same composition and thickness as gate dielectric layer 112, and top electrode 139 has the same composition and thickness as gate electrode 111.

[0030] Memory cell 137A can be one of an array (not shown) of memory cells 137A for which BEOL transistor 107 provides access control. Bit lines 173 for the array can be disposed in metallization layer M X-1 and connected to first-level conductive layer 155 via vias 120. Etch stop layer 165 and / or oxide layer 169 can be disposed between bit lines 173 and first-level conductive layer 155. Word lines 101 can travel perpendicular to bit lines 173, can be disposed above gate electrodes 111, and can be connected to gate electrodes 111 via vias 105. Top electrode 139 can be connected to ground rail 131 via via 135. One or more dielectrics (such as interlayer dielectric 159) can surround and insulate these lines and vias.

[0031] Figure 2 IC device 200 is shown. IC device 200 is similar to Figure 1 IC device 100, except that it includes memory cell 137B in place of memory cell 137A. Memory cell 137B has top electrode 139 that can be thicker than gate electrode 111. Top electrode 139 can have upper surface 205 coplanar with upper surface 203 of gate electrode 111. Memory cell 137B has internal structure 201, which can be a dielectric layer or a data storage structure. In either case, internal structure 201 can be in direct contact with bottom electrode 149. The data storage structure can be a ferroelectric layer, a resistive switching material layer, a magnetic tunnel junction (MTJ), a phase change material layer, etc. or any other type of data storage structure. If memory cell 137B is a capacitor and internal structure 201 is a dielectric layer, the dielectric layer can have a different thickness and / or composition from gate dielectric layer 112. In some embodiments, internal structure 201 extends onto sidewall 207 of top electrode 139.

[0032] Figure 3 Shown is similar to Figure 2IC device 300 of IC device 200, except that it includes memory cell 137C instead of memory cell 137B, and in IC device 300, bottom electrode 149 has an inner sidewall 303 that defines a recess 301. In memory cell 137C, internal structure 201 and top electrode 139 extend into recess 301 such that memory cell 137C has a three-dimensional structure.

[0033] Figure 4A A plan view 400 showing bottom electrode 149 according to the first embodiment is provided. In the first embodiment, recess 301 has an elliptical cross-section and is formed in an array having n rows and m columns. Each of m and n can be selected individually and can be in the range from about 1 to about 500. In some embodiments, m and n are in the range from 2 to about 100. The depth of recess 301 can be, for example, in the range from about 1 nm to about 100 nm. In some embodiments, the depth of recess 301 is in the range from about 1 nm to about 20 nm. In some embodiments, the depth of recess 301 is in the range from about 20 nm to about 100 nm. In some embodiments, the depth of recess 301 is less than the thickness of the second horizontal conductive layer 147 (see Figure 3 ).

[0034] Recess 301 can be circular with a diameter D1 and a pitch S1. The diameter D1 can be, for example, in the range from about 1 nm to about 100 nm. In some embodiments, diameter D1 is in the range from about 1 nm to about 20 nm. In some embodiments, diameter D1 is in the range from about 20 nm to about 100 nm. The pitch S1 can be less than the diameter D1. In some embodiments, pitch S1 is half or less of the diameter D1. In some embodiments, recess 301 is non-circular. If recess 301 is elliptical but non-circular, they can have a ratio of major access to minor access in the range from about 1:1 to about 2:1.

[0035] Figure 4B A plan view 410 showing bottom electrode 149 according to the second embodiment is provided. Figure 4B The second embodiment of is similar to Figure 4A the first embodiment of, except that in Figure 4B the embodiment of, the rows of recesses 301 are staggered to provide a narrower pitch. Figure 4C A plan view 420 showing bottom electrode 149 according to the third embodiment is provided. In the third embodiment, recess 301 takes the form of a trench.

[0036] Figure 5A A cross-sectional view of IC device 500 is provided, and Figure 5B a plan view of IC device 500 is provided. Figure 5AThe cross-sectional view shows a unit cell 502, which is one of an array of similar cells. Figure 5A The cross-sectional view corresponds to Figure 5B line A-A' in the plan view of Figure 5B The plan view shows three unit cells 502. The unit cell 502 includes two BEOL transistors 107 and two memory cells 137C symmetrically arranged around a shared gate electrode 111. The high-k dielectric layer 503 covers the edges 507 of the semiconductor layer 114 and the edges 509 of the drain electrodes 118 to reduce leakage current. The space between the edges 507 may be filled with an oxide layer 505. The BEOL transistors 107 in each pair may be connected in parallel to operate as one transistor.

[0037] Referring to Figure 5B the plan view, the drain electrodes 118 may be wider than the bit lines 173 such that their side edges are offset by a distance D2, and the distance D2 is approximately half of the width difference. The distance D2 may be in the range from about 1 nm to about 100 nm. In some embodiments, the distance D2 is in the range from about 1 nm to about 20 nm. In some embodiments, the distance D2 is in the range from about 20 nm to about 100 nm. This offset allows the BEOL transistors 107 and the memory cells 137C to have a larger area while maintaining the pitch between the bit lines 173. If the offset is too large, the drain electrodes 118 will be too close together. If the offset is too small, the BEOL transistors 107 will be too small, or the pitch between the bit lines 173 will need to be increased, which affects the device density.

[0038] The source electrodes 116 may be narrower than the drain electrodes 118 such that their side edges are offset by a distance D3, and the distance D3 is approximately half of the width difference. The distance D3 may be in the range from about 1 nm to about 100 nm. In some embodiments, the distance D3 is in the range from about 1 nm to about 20 nm. In some embodiments, the distance D3 is in the range from about 20 nm to about 100 nm. If the offset is too large, the BEOL transistors 107 will be too small, or the pitch between the bit lines 173 will need to be increased, which affects the device density. If the offset is too small, the manufacturing process will be difficult to execute.

[0039] Figures 6 to 17 A series of cross-sectional views are provided, illustrating a method of forming an IC device according to some embodiments. Although described with reference to various embodiments of the method Figures 6 to 17 , it will be understood that Figures 6 to 17 the structures shown in Figures 6 to 17 are not limited to the method, but may be separate and independent of the method. Although Figures 6 to 17A specific set of operations is shown and described, but in some embodiments, some of the operations shown and / or described may be omitted. Additionally, operations not shown and / or described may be included. Figures 6 to 17 The method of Figure 1 may provide an IC device 100 of

[0040] As Figure 6 shown in cross-sectional view 600 of X-1 , the method begins after providing a substrate 177, front-end-of-line (FEOL) processing, and forming a first set of metallization layers M1 to M of a metal interconnect structure 161. A bit line 173 is disposed in one of these metallization layers. As Figure 6 shown, the method may begin with forming an oxide layer 169 and an etch stop layer 165 over the metallization layer M X-1 . It will be understood that the oxide layer 169 and the etch stop layer 165 are examples, and different dielectric structures may be used in place of the oxide layer 169 and the etch stop layer 165.

[0041] The substrate 177 may be a semiconductor substrate. The semiconductor substrate may be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. At least an upper portion of the semiconductor substrate is semiconductor. The semiconductor may be silicon (Si), a III-V semiconductor (e.g., GaAs), or some other binary semiconductor, ternary semiconductor (e.g., AlGaAs), higher-order semiconductor, etc., or any other suitable semiconductor. In some embodiments, the semiconductor is silicon (Si), etc. During FEOL processing, semiconductor devices 179 may be formed on the substrate 177. The semiconductor devices 179 may be transistors, diodes, capacitors, memory cells, thyristors, resistors, etc., or any combination thereof.

[0042] The metal interconnect structure 161 may be formed using a damascene or dual damascene process. The bit line 173 and other lines 123 and vias 127 in the metal interconnect structure 161 (see Figure 1) may include one or more layers of copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, alloys of these metals, etc., or any other suitable conductive material. One of the layers may be a diffusion barrier layer, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. The interlayer dielectric 159 may include one or more layers of silicon dioxide (SiO2), low-k dielectric, or ultra-low-k dielectric. A low-k dielectric is a dielectric having a dielectric constant less than that of silicon dioxide (SiO2). Examples of low-k dielectrics include borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), etc. An ultra-low-k dielectric is a material having a dielectric constant of about 2.1 or lower. The ultra-low-k dielectric may be a low-k dielectric having porosity, which reduces its effective dielectric constant.

[0043] The adjacent metallization layers M1-M X-1 may be separated by an etch stop layer 156. The etch stop layer 156 may include one or more layers of aluminum oxide (AlO x ), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxynitride (SiOCN), combinations thereof, etc.

[0044] The oxide layer 169 may be, for example, silicon dioxide (SiO2), low-k dielectric, or ultra-low-k dielectric. The oxide layer 169 may be deposited by ALD, CVD, PVD, etc., or any other suitable process. The etch stop layer 165 may be, for example, aluminum oxide (AlO x ), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), silicon oxynitride (SiOCN), combinations thereof, etc. These layers may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., or other suitable processes.

[0045] As Figure 7 shown in the cross-sectional view 700 of, the method may continue to form a mask 701 and use the mask 701 to etch a via opening 703 through the etch stop layer 165 and the oxide layer 169. The mask 701 and other masks used in the process of the present disclosure may be or include photoresist, hard mask, etc., and may be patterned by photolithography, ion beam lithography, etc., or some other suitable process. The etching process may be dry etching (such as plasma etching, etc.) or some other suitable etching process. After the etching process, the mask 701 may be stripped.

[0046] As shown in cross-sectional view 800 of Figure 8 shown, electrode stack 119 can be deposited over the structure of cross-sectional view 700 of Figure 7 Electrode stack 119 includes a first horizontal conductive layer 155, a spacer dielectric 151, and a second horizontal conductive layer 147. The first horizontal conductive layer 155 can be deposited in opening 703 to provide via 120. The thicknesses of the second horizontal conductive layer 147 and the first horizontal conductive layer 155 can be in the range from about 5 nm to about 100 nm. In some embodiments, the thicknesses of these layers are in the range from about 5 nm to about 25 nm. In some embodiments, the thicknesses of these layers are in the range from about 25 nm to about 100 nm. Each of these layers can include one or more layers of molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), ruthenium (Ru), chromium (Cr), nickel (Ni), titanium nitride (TiN), tantalum nitride (TaN), etc., conductive oxides (such as indium oxide (InO), indium tin oxide (InSnO), etc.), combinations of the foregoing materials, or any other suitable conductive material. In some embodiments, the second horizontal conductive layer 147 includes a top metal layer of titanium nitride (TiN), tantalum nitride (TaN), etc. The thickness of the top metal layer can be in the range from about 5 nm to about 50 nm. The conductive layers can be deposited by PVD, CVD, ALD, electroplating, electroless plating, etc., or any other suitable process.

[0047] Spacer dielectric 151 can be silicon dioxide (SiO2), silicon oxynitride (SiON), etc., or any other suitable dielectric. The thickness of spacer dielectric 151 can be in the range from about 10 nm to about 100 nm. In some embodiments, the thickness of spacer dielectric 151 is in the range from about 10 nm to about 30 nm. In some embodiments, the thickness of spacer dielectric 151 is in the range from about 30 nm to about 100 nm. Spacer dielectric 151 can be deposited by PVD, CVD, ALD, etc., or any other suitable process.

[0048] As shown in cross-sectional view 900 of Figure 9 shown, a mask 901 can be formed and used to pattern electrode stack 119. The patterning process defines drain electrode 118 from the first horizontal conductive layer 155. The patterning process can be dry etching (such as plasma etching, etc.) or some other suitable etching process.

[0049] As shown in cross-sectional view 900 of Figure 10As shown in the cross-sectional view 1000, a mask 1001 can be formed and used to further pattern the upper portion of the electrode stack 119 including the second horizontal conductive layer 147 and the spacer dielectric 151. Optionally, the mask 1001 is formed by trimming the mask 901. This patterning process creates sidewalls 110 that include the second horizontal conductive layer 147 and the spacer dielectric 151. The sidewalls 110 are aligned with the edge 1003 of the mask 1001. This patterning process also forms the source electrode 116 from the second horizontal conductive layer 147, and the source electrode 116 also provides the bottom electrode 149. The shape of the mask 1001 is different from that of the mask 901 (see Figure 9 ) to expose the protruding portion 117 of the drain electrode 118. The patterning process can be a dry etch (such as plasma etching, etc.) or some other suitable etching process. After the etching process, the mask 1001 can be stripped.

[0050] As Figure 11 shown in the cross-sectional view 1100, a semiconductor layer 114 can be formed above the structure shown in the cross-sectional view 1000 of Figure 10 such that the semiconductor layer 114 contacts the source electrode 116 and the drain electrode 118 without causing etching damage to the semiconductor layer 114. As Figure 12 shown in the cross-sectional view 1200, a mask 1201 can be formed and used to pattern the semiconductor layer 114. The patterning removes the semiconductor layer 114 from the second region 185 while leaving a portion of the semiconductor layer 114 in the first region 181. The semiconductor layer 114 can be deposited by PVD, CVD, ALD, etc. or any other suitable process. Optionally, the semiconductor layer 114 is selectively grown in the regions where it is desired.

[0051] The semiconductor layer 114 can be an oxide semiconductor, etc. In some embodiments, the oxide semiconductor has the formula In x Ga y Zn zMO, where M is titanium (Ti), aluminum (Al), silver (Ag), tungsten (W), cerium (Ce), or tin (Sn), and x ranges from 0 to 1, y ranges from 0 to 1, and z ranges from 0 to 1. Examples include indium gallium oxide (IGO), indium zinc oxide (IZO), indium tungsten oxide (IWO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), aluminum zinc tin oxide (AZTO), indium titanium oxide (InTiO), gallium zinc oxide (GZO), indium oxide (InO2), gallium oxide (Ga2O3), etc., with or without tin (Sn) or other dopants. The thickness of the semiconductor layer 114 can range from about 3 nm to about 50 nm. In some embodiments, the thickness ranges from about 3 nm to about 10 nm. In some embodiments, the thickness ranges from about 10 nm to about 50 nm.

[0052] As Figure 13 shown in the cross-sectional view 1300 of Figure 12 the structure shown in the cross-sectional view 1200, the gate stack 106 can be formed over

[0053] The gate electrode layer 1303 can be or include one or more layers of conductors. The conductor can be a metal (such as tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), nickel (Ni), etc.) or a conductive oxide (such as indium oxide (InO), indium tin oxide (InSnO), etc.) or any other suitable conductive material. The thickness of the gate electrode layer 1303 can be in the range from about 5 nm to about 100 nm. In some embodiments, the thickness of the gate electrode layer 1303 is in the range from about 5 nm to about 25 nm. In some embodiments, the thickness of the gate electrode layer 1303 is in the range from about 25 nm to about 100 nm. The gate electrode layer 1303 can be deposited by PVD, CVD, ALD, electroplating, electroless plating, etc. or any other suitable process.

[0054] As Figure 14 shown in the cross-sectional view 1400 of Figure 13 , a mask 1401 can be formed and an etching process can be performed to pattern the gate stack 106. The etching separates the gate electrode 111 from the top electrode 139, both the gate electrode 111 and the top electrode 139 being patterned from the gate electrode layer 1303 (see

[0055] As Figure 15 shown in the cross-sectional view 1500 of Figure 14 ), a layer of interlayer dielectric 159 can be formed over the structure shown in the cross-sectional view 1400 of

[0056] As Figure 16 shown in the cross-sectional view 1600 of Figure 17As shown in the cross-sectional view 1700, the opening 1601 can be filled with metal to provide the vias 105 and 135, the word lines 101, and the ground rails 131. The metal can be copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), etc. or any other suitable metal. The metal can be deposited by CVD, PVD, electroplating, electroless plating, etc. After deposition, the excess metal can be removed by a planarization process such as CVD.

[0057] Figures 18 to 22 A series of cross-sectional views are provided, illustrating Figures 6 to 17 variations of the method shown in the cross-sectional view. Such variations can provide Figure 2 the IC device 200 or some other IC device, where the internal structure 201 of the memory cell has a different composition from the gate dielectric layer 112 (see Figure 2 ).

[0058] The variation can start with the deposited gate stack 106 as shown in the cross-sectional view 1300 such as Figure 13 . As shown in the cross-sectional view 1800 such as Figure 18 , in this variation, the gate stack 106 is patterned with a mask 1801 such that the gate stack 106 is removed from the second region 185. The gate stack 106 can be patterned as an overlay region of the semiconductor layer 114. Optionally, the semiconductor layer 114 is patterned together with the gate stack 106.

[0059] As shown in the cross-sectional view 1900 such as Figure 19 , a layer of interlayer dielectric 159 is formed over the structure shown in the cross-sectional view 1800 such as Figure 18 . As shown in the cross-sectional view 2000 such as Figure 20 , a mask 2001 can be formed and used to etch an opening through the interlayer dielectric 159 above the bottom electrode 149 in the second region 185.

[0060] As shown in the cross-sectional view 2100 such as Figure 21 . The internal structure 201 and the top electrode metal layer 2005 can be deposited to fill the opening 2003. The bottom electrode 149, the internal structure 201, and the top electrode metal layer 2005 together form the memory cell stack 2007. Examples of materials suitable for the top electrode metal layer 2005 include materials suitable for the second-level conductive layer 147 and materials suitable for the gate electrode 111. The composition and thickness of the internal structure 201 depend on the type of memory cell to be formed. If the memory cell is a DRAM memory cell, the internal structure 201 is a dielectric, such as a high-k dielectric.

[0061] If the memory cell is a FeRAM memory cell, the internal structure 201 includes a ferroelectric material. The ferroelectric material can be, for example, a binary oxide, a ternary oxide, or a quaternary oxide. In some embodiments, the ferroelectric material is a binary oxide, such as hafnium oxide (HfO x ) and the like. In some embodiments, the ferroelectric material is a ternary oxide, such as hafnium silicate (HfSiO x ), hafnium zirconate (HfZrO x ), barium titanate (BaTiO3), lead titanate (PbTiO3), strontium titanate (SrTiO3), calcium manganite (CaMnO3), bismuth ferrite (BiFeO3), aluminum scandium nitride (AlScN), aluminum gallium nitride (AlGaN), aluminum yttrium nitrate, silicon-doped hafnium oxide, zirconium-doped hafnium oxide, yttrium-doped hafnium oxide, aluminum-doped hafnium oxide, gadolinium-doped hafnium oxide, strontium-doped hafnium oxide, lanthanum-doped hafnium oxide, scandium-doped hafnium oxide, germanium-doped hafnium oxide, combinations thereof, and the like. In some embodiments, the ferroelectric material is a quaternary oxide, such as lead zirconate, barium strontium titanate (BaSrTiO x ), strontium bismuth tantalate, and the like.

[0062] If the memory cell is a ReRAM memory cell, the internal structure 201 includes a resistive switching material. Examples of the resistive switching material include binary transition metal oxides (such as nickel oxide (NiO), titanium dioxide (TiO2), copper oxide (CuO x ) and the like), transition metal sulfides (such as copper sulfide (CuS) and the like), perovskites (such as strontium titanate (SrTiO), praseodymium calcium manganite (PCMO) and the like), organic charge transfer complexes (such as copper tetracyanoquinodimethane (CuTCNQ) and the like), organic donor-acceptor systems (such as silver-I-dicyanovinylene (AIDCN) and the like).

[0063] If the memory cell is a conductive-bridging (CBRAM) memory cell, the internal structure 201 includes a solid electrolyte. Examples of the solid electrolyte include germanium selenide (GeSe), silver oxide (AgO), and the like.

[0064] If the memory cell is a PCRAM memory cell, the internal structure 201 includes a phase change material. Examples of the phase change material include chalcogenides, such as germanium antimony telluride (GeSbTe), silver indium antimony telluride (AgInSbTe), and the like.

[0065] If the memory cell is an MRAM memory cell, the internal structure 201 includes an MTJ. The MTJ includes two ferromagnetic layers separated by a tunnel barrier layer. The ferromagnetic layers include a fixed layer and a free layer. Examples of materials suitable for the fixed layer include cobalt (Co), iron (Fe), boron (B), nickel (Ni), ruthenium (Ru), iridium (Ir), platinum (Pt), etc. Examples of materials that may be suitable for the tunnel barrier layer include magnesium oxide (MgO), aluminum oxide (AlO), nickel oxide (NiO), gadolinium oxide (GdO), tantalum oxide (TaO), molybdenum oxide (MoO), titanium oxide (TiO), tungsten oxide (WO), etc. Examples of materials that may be suitable for the free layer include cobalt (Co), iron (Fe), boron (B), iron cobalt (FeCo), nickel cobalt (NiCo), cobalt iron boride (CoFeB), iron boride (FeB), iron platinum (FePt), iron palladium (FePd), etc.

[0066] As Figure 22 shown in cross-sectional view 2200 of , a planarization process may be performed to remove a portion of the top electrode metal layer 2005 deposited outside the opening 2003. The portion of the top electrode metal layer 2005 remaining in the opening 2003 provides the top electrode 139. The planarization process may be CMP or the like. Planarization may make the upper surface 205 of the top electrode 139 coplanar with the upper surface 203 of the gate electrode 111.

[0067] Figures 23 to 25 A series of cross-sectional views are provided, illustrating Figures 18 to 22 variations of the method shown in the cross-sectional view of . This variation may provide Figure 3 an IC device 300 of or some other IC device, wherein the memory cell 137C has a three-dimensional structure.

[0068] The variation may begin Figure 20 after etching the opening 2003 as shown in cross-sectional view 2000 of . As Figure 23 shown in cross-sectional view 2300 of , in this variation, another mask 2301 is formed and used to etch a recess 2303 in the second-level conductive layer 147. The recess 2303 may partially or completely penetrate the second-level conductive layer 147. As Figure 24 shown in cross-sectional view 2400 of , when the internal structure 201 and the top electrode metal layer 2005 are deposited in the opening 2003, the internal structure 201 lines the recess 2303, and the top electrode metal layer 2005 extends into the recess 2303. As Figure 25 shown in cross-sectional view 2500 of , the process may continue with planarization.

[0069] Figures 26 to 41B A series of views are provided, illustrating a method of forming an IC device according to some embodiments. Although described with reference to various embodiments of the methodFigures 26 to 41B , but it will be understood that Figures 26 to 41B the structure shown is not limited to the method, but can be separate and independent of the method. Although Figures 26 to 41B described as a series of actions, it will be understood that in other embodiments, the order of the actions can be changed. Although Figures 26 to 41B a specific set of actions is shown and described, in some embodiments, some of the actions shown and / or described can be omitted. Additionally, actions not shown and / or described can be included. Figures 26 to 41B The method of Figure 5A can provide

[0070] As Figure 26 shown in cross-sectional view 2600 of

[0071] As Figure 27 shown in cross-sectional view 2700 of

[0072] As Figure 28A shown in cross-sectional view 2800 of Figure 28B and plan view 2810 of

[0073] As Figure 29 shown in cross-sectional view 2900 of Figure 30A As Figure 30B shown in cross-sectional view 3000 of

[0074] As Figure 31 shown in cross-sectional view 3100 of Figure 30A the structure shown in cross-sectional view 3000 of Figure 32 As

[0075] AsFigure 33A Cross-sectional view 3300 and Figure 33B As shown in the plan view 3310, a mask 3301 can be formed and an etching process can be performed to pattern the semiconductor layer 114. The etching can stop at the etch stop layer 165, such that the patterning process produces an edge 509 of the drain electrode 118 in addition to an edge 507 of the semiconductor layer 114. The etching can form a gap 3305 and separate the drain electrode 118 on the right side from the drain electrode 118 on the left side. Optionally, such separation can be achieved by Figure 28A Cross-sectional view 2800 and Figure 28B the etching shown in the plan view 2810. However, in this alternative process, the semiconductor layer 114 is deposited in the gap 3305. Then, this etching can remove the semiconductor layer 114 from the gap 3305. However, the process sequence of this etching that separates the drain electrodes 118 allows for less etching of the semiconductor layer 114 and can provide a device with lower leakage.

[0076] As Figure 34 shown in the cross-sectional view 3400, additional layers of the high-k dielectric layer 503 and the interlayer dielectric 159 can be deposited over the Figure 33A structure shown in the cross-sectional view 3300. The high-k dielectric layer 503 covers the edge 507 of the semiconductor layer 114 and the edge 509 of the drain electrode 118. The high-k dielectric layer 503 can be as thin as or thinner than the gate dielectric layer 112.

[0077] As Figure 35 shown in the cross-sectional view 3500, a planarization process such as CMP can be performed to provide a planar surface 3501. As Figure 36A shown in the cross-sectional view 3600 and Figure 36B the plan view 3610, a mask 3601 can be formed and an etching process can be performed to form an opening 3603. The etching can stop at the top metal layer 501.

[0078] As Figure 37 shown in the cross-sectional view 3700, a mask 3701 can be formed and an etching process can be performed to form a recess 3703 in the source electrode 116. The etching can also form a gap 3705 between the source electrodes 116. The etching can be a dry etching such as plasma etching or the like.

[0079] As Figure 38 shown in the cross-sectional view 3800, another etching can be performed to expose the gate dielectric layer 112 above the channel 109. The etching process is selective for removing the interlayer dielectric 159 without damaging the gate dielectric layer 112. In some embodiments, this is a wet etching. The top metal layer 501 can protect the source electrode 116 during this etching process.

[0080] As shown Figure 39 in cross-sectional view 3900 of Figure 38 , the internal structure 201 and the top electrode metal layer 2005 are deposited over the structure shown in cross-sectional view 3800 of Figure 40A . The internal structure 201 and the top electrode metal layer 2005 fill the recess 3703 in the source electrode 116. As shown Figure 40B in cross-sectional view 4000 of

[0081] and in plan view 4010 of Figure 41A , a planarization process such as CMP can be performed. After planarization, the first remaining portion of the top electrode metal layer 2005 provides the gate electrode 111, and the second remaining portion of the top electrode metal layer 2005 provides the top electrode 139. Figure 41B As shown

[0082] Figures 42 to 44 in cross-sectional view 4100 of Figures 42 to 44 and in plan view 4110 of

[0083] Figure 42 , an additional layer of the interlayer dielectric 159 can be deposited and a dual damascene process can be performed to form the vias 105 and 135, the word lines 101, and the ground rails 131. Optionally, the word lines 101 and / or the ground rails 131 can be provided in a subsequently formed metallization layer. Figure 6 Figure 26 Cross-sectional views 600 of

[0084] and cross-sectional views 2600 of Figure 8 provide examples. Figure 27 Action 4203 deposits an electrode stack. The electrode stack includes two electrode layers separated by a spacer layer.

[0085] Cross-sectional views 800 of Figure 10 and cross-sectional views 2700 of Figure 30A provide examples.

[0086] Operation 4207 forms a semiconductor layer on the sidewall. Figure 11 Cross-sectional view 1100 of Figure 31 Cross-sectional view 3100 of

[0087] Operation 4209 removes the semiconductor layer from the memory cell region. The memory cell region is the region where memory cells will be formed. Figure 12 Cross-sectional view 1200 of Figure 18 Cross-sectional view 1800 of Figure 36A Cross-sectional view 3600 of

[0088] Operation 4211 is an optional step of etching a recess in the electrode stack within the memory cell region. The depth of the recess can be limited to the uppermost electrode of the electrode stack. Figure 23 Cross-sectional view 2300 of Figure 37 Cross-sectional view 3700 of

[0089] Operation 4213 deposits a gate dielectric layer. Figure 13 Cross-sectional view 1300 of Figure 31 Cross-sectional view 3100 of

[0090] Operation 4215 deposits a gate electrode layer. Figure 13 Cross-sectional view 1300 of Figure 39 Cross-sectional view 3900 of

[0091] Operation 4217 is an etching that separates the gate electrode layer from the top capacitor plate. Figure 14 Cross-sectional view 1400 of

[0092] Figure 43 Process 4300 includes many steps that are the same as Figure 42 Process 4200. The difference in Process 4300 is that it starts with operation 4301, and etching is performed to remove the gate dielectric layer and the gate electrode layer from the memory region. Figure 18 Cross-sectional view 1800 of

[0093] Operation 4303 deposits and planarizes a dielectric filling material. The dielectric filling can be an interlayer dielectric. Figure 19 Cross-sectional view 1900 of Figure 32 Cross-sectional view 3200 of

[0094] Operation 4305 is an etch to expose the electrode stack in the memory cell region. Figure 20 Cross-sectional view 2000 of Figure 36A and cross-sectional view 3600 of

[0095] provide examples. Optionally, operation 4211 is then performed to form a recess in the electrode stack. Figure 21 Cross-sectional view 2100 of Figure 24 and cross-sectional view 2400 of Figure 39 provide examples.

[0096] Operation 4309 forms a top electrode layer. Figures 21 to 22 Cross-sectional views 2100-2200 of Figures 24 to 25 provide an example. Cross-sectional views 2400-2500 of Figures 40A to 41A provide another example. Cross-sectional views 4000-4100 of

[0097] Figure 44 Process 4400 includes many steps that are the same as Figure 42 process 4200 and Figure 43 process 4300. Process 4400 can differ starting from operation 4401, forming a mask and patterning the electrode stack. This patterning can define the edges of the drain electrodes. Figure 28A Cross-sectional view 2800 of Figure 28B and plan view 2810 of

[0098] Operation 4403 trims the mask. Figure 29 Cross-sectional view 2900 of Figure 30A provides an example. Operation 4405 uses the trimmed mask to shape the source electrode and define the sidewalls including the spacer layer. Figure 30B Cross-sectional view 3000 of

[0099] and plan view 3010 of Figure 33A provide examples. Figure 33B Operation 4407 forms a mask and performs an etch to separate two adjacent drain electrodes.

[0100] Cross-sectional view 3300 of Figure 34 provides an example.

[0101] Through operation 4305, the electrode stack is exposed in the memory cell region. Through operation 4307, the internal structure of the memory cell is deposited.

[0102] Operation 4413 is an etch to expose the gate dielectric above the channel. Figure 37 Cross-sectional view 3700 of and Figure 38 Cross-sectional view 3800 of provide examples.

[0103] A top electrode layer is deposited by operation 4309. This deposition can also provide metal for the gate electrode. Operation 4415 planarizes the top electrode layer, and the gate electrode is defined by the metal. Figure 39 Cross-sectional view 3900 of and Figure 40A Cross-sectional view 4000 of provide examples of this process.

[0104] Some aspects of the present disclosure relate to an integrated circuit device, including: a metal interconnect structure located above a semiconductor substrate. A first transistor disposed within the metal interconnect structure includes a first source / drain electrode, a second source / drain electrode, a channel, a gate dielectric, and a gate electrode. The second source / drain electrode is vertically stacked above the first source / drain electrode and is separated from the first source / drain electrode by a dielectric spacer. The dielectric spacer has sidewalls extending from the second source / drain electrode to the first source / drain electrode. The channel is provided by a semiconductor layer that forms a coating on the sidewalls. The gate dielectric is located between the gate electrode and the channel.

[0105] In some embodiments, the semiconductor layer includes an oxide semiconductor and the gate dielectric includes a high-k dielectric. In some embodiments, the semiconductor layer extends above the second source / drain electrode. In some embodiments, the integrated circuit device further includes a second transistor. The second transistor shares the gate electrode with the first transistor, and the first transistor and the second transistor are symmetric with respect to the gate electrode.

[0106] In some embodiments, the integrated circuit device further includes a memory cell, wherein the second source / drain electrode extends laterally to provide a bottom electrode for the memory cell. In some embodiments, the dielectric spacer and the first source / drain electrode extend directly below the memory cell. In some embodiments, the memory cell is a capacitor. In some embodiments, the memory cell includes different layers of materials having the same composition and thickness as the gate dielectric. In some embodiments, the memory cell has a top electrode, and the composition and thickness of the top electrode are the same as those of the gate electrode. In some embodiments, the memory cell has a top electrode, and the top electrode and the gate electrode have coplanar upper surfaces. In some embodiments, the semiconductor layer extends to a height above the bottom electrode of the memory cell. In some embodiments, the metal interconnect structure includes two adjacent metallization layers, and the first transistor and the memory cell are located between the two adjacent metallization layers.

[0107] In some embodiments, the bottom electrode is recessed such that the memory cell has a three-dimensional structure. In some embodiments, the bottom electrode has an inner sidewall that defines a recess having an elliptical horizontal cross-section. In some embodiments, the bottom electrode has an inner sidewall that defines a recess having a circular horizontal cross-section. In some embodiments, the bottom electrode has an inner sidewall that defines a trench.

[0108] Some aspects of the present disclosure relate to an integrated circuit device including: a metal interconnect structure located above a semiconductor substrate. An electrode stack within the metal interconnect structure includes a second electrode layer above a dielectric spacer above a first electrode layer. The electrode stack has sidewalls including the second electrode layer and the dielectric spacer. An oxide semiconductor layer is located above the sidewalls. A gate stack is disposed above the oxide semiconductor layer. The gate stack includes a high-k dielectric layer and a gate electrode. The electrode stack and the gate stack form a transistor, and the second electrode layer and the first electrode layer provide source and drain electrodes for the transistor.

[0109] In some embodiments, the integrated circuit device further includes a memory cell having a data storage structure in direct contact with the second electrode layer. In some embodiments, the integrated circuit device further includes a memory cell having a dielectric layer in direct contact with the second electrode layer.

[0110] Some aspects of the present disclosure relate to a method of manufacturing an integrated circuit device, the method including: forming a metallization layer above a semiconductor, forming a first source / drain electrode layer above the metallization layer, forming a spacer layer above the first source / drain electrode layer, forming a second source / drain electrode layer above the spacer layer, and etching through the second source / drain electrode layer and the spacer layer. The etching forms sidewalls including the second source / drain electrode layer and the spacer layer. The method further includes forming a semiconductor layer covering the sidewalls, forming a gate dielectric layer above the semiconductor layer, and depositing a gate electrode layer above the gate dielectric layer.

[0111] In some embodiments, the method further includes masking a semiconductor layer in a first region during the etching to remove the semiconductor layer from a second region prior to forming the gate dielectric layer. In some embodiments, forming the semiconductor layer includes a selective growth process such that the semiconductor layer is formed in the first region but not in the second region. In some embodiments, the method further includes using a first mask etch to pattern a stack including the first source / drain electrode layer, the spacer layer, and the second source / drain electrode layer, trimming the first mask, and forming the sidewalls using the trimmed mask.

[0112] In some embodiments, the first source electrode and the second source electrode are formed by etching through the second source electrode / drain electrode layer and the spacer layer, and the method further includes depositing a first dielectric above the first source electrode and the second source electrode, etching a first opening between the first source electrode and the second source electrode, wherein the first opening extends through the first dielectric, the gate dielectric layer, and the semiconductor layer, etching the first opening to form sidewalls of the semiconductor layer, and etching the first opening to expose sidewalls of the first source electrode / drain electrode layer, lining the first opening with a high-k dielectric layer, wherein the high-k dielectric layer covers the sidewalls of the semiconductor layer and the sidewalls of the first source electrode / drain electrode layer, and filling the first opening with a second dielectric.

[0113] In some embodiments, etching the first opening divides a first portion of the first source electrode / drain electrode layer into a first drain electrode and a second drain electrode. In some embodiments, the method further includes etching a second opening between the first source electrode and the second source electrode, wherein etching exposes the gate dielectric layer, and a gate electrode layer is deposited in the second opening. In some embodiments, etching the second opening includes an etching process that is selective to etching the first dielectric compared to the high-k dielectric layer. In some embodiments, the first source electrode and the second source electrode are formed by etching through the second source electrode / drain electrode layer and the spacer layer, and the method further includes depositing a first dielectric above the first source electrode and the second source electrode, and etching a first opening between the first source electrode and the second source electrode, wherein the first opening extends through the first dielectric, the gate dielectric layer, the semiconductor layer, and the first source electrode / drain electrode layer, etching to form sidewalls of the semiconductor layer and sidewalls of the source electrode / drain electrode layer, and the first opening separates a first portion of the first source electrode / drain electrode layer below the first source electrode from a second portion of the second source electrode / drain electrode layer below the second source electrode.

[0114] In some embodiments, the second source electrode / drain electrode layer provides a bottom electrode for memory cells in a second region. In some embodiments, the gate electrode layer provides a top electrode for the memory cells. In some embodiments, the memory cells are capacitors, and the gate dielectric layer provides an insulating layer for the capacitors. In some embodiments, the method further includes etching a recess in the second source electrode / drain electrode layer within the second region, wherein the top electrode of the memory cell extends into the recess. In some embodiments, the gate electrode layer is deposited to form the top electrode.

[0115] In some embodiments, the method further includes etching to remove the gate electrode layer and the gate dielectric layer from the second region, and forming a memory cell stack in the second region, wherein the second source electrode / drain electrode layer provides a bottom electrode layer for the memory cell stack. In some embodiments, the method further includes etching a recess in the second source electrode / drain electrode layer within the second region, wherein a portion of the memory cell stack is deposited in the recess.

[0116] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, comprising: Semiconductor substrate; a metal interconnect structure located above the semiconductor substrate; as well as a first transistor disposed within the metal interconnect structure; Wherein, the first transistor comprises a first source electrode / drain electrode, a second source electrode / drain electrode, a channel, a gate dielectric and a gate electrode; The second source / drain electrode is vertically stacked above the first source / drain electrode and is separated from the first source / drain electrode by a dielectric spacer; the dielectric spacer having sidewalls extending from the second source / drain electrode to the first source / drain electrode; The channel is provided by a semiconductor layer coating the sidewalls; and The gate dielectric is located between the gate electrode and the channel.

2. The integrated circuit device according to claim 1, wherein: The semiconductor layer extends over the second source / drain electrodes.

3. The integrated circuit device according to claim 1, further comprising a second transistor, wherein: The second transistor shares the gate electrode with the first transistor, and the first transistor and the second transistor are symmetrical about the gate electrode.

4. The integrated circuit device according to claim 1, further comprising a memory cell, wherein: The second source / drain electrode extends laterally to provide a bottom electrode for the memory cell.

5. The integrated circuit device according to claim 4, wherein: The dielectric spacer and the first source / drain electrodes extend directly beneath the memory cell.

6. The integrated circuit device according to claim 4, wherein: The memory cell is a capacitor.

7. The integrated circuit device according to claim 4, wherein: The memory cell includes a different layer having a composition and thickness equivalent to the gate dielectric.

8. The integrated circuit device according to claim 4, wherein: The memory cell includes a top electrode having a composition and thickness identical to that of the gate electrode.

9. An integrated circuit device comprising: Semiconductor substrate; a metal interconnect structure located above the semiconductor substrate; an electrode stack including a second electrode layer over a dielectric spacer over a first electrode layer, wherein the electrode stack is within the metal interconnect structure and has a sidewall including the second electrode layer and the dielectric spacer; an oxide semiconductor layer located above the sidewall; and a gate stack comprising a high-k dielectric layer and a gate electrode, wherein the gate stack is disposed above the oxide semiconductor layer; The electrode stack and the gate stack form a transistor, and the second electrode layer and the first electrode layer provide a source electrode and a drain electrode for the transistor.

10. A method of manufacturing an integrated circuit device, the method comprising: forming a metallization layer over the semiconductor substrate including the first region and the second region; forming a first source / drain electrode layer above the metallization layer; forming a spacer layer over the first source / drain electrode layer; forming a second source / drain electrode layer over the spacer layer; forming a first mask; etching through the second source / drain electrode layer and the spacer layer, wherein the etching forms a sidewall aligned with an edge of the first mask, the sidewall including the second source / drain electrode layer and the spacer layer, and the sidewall is located in the first region; forming a semiconductor layer covering the sidewalls; forming a gate dielectric layer over the semiconductor layer; and A gate electrode layer is deposited over the gate dielectric layer.

Images