Solar cell and preparation method thereof

Abstract

The invention provides a solar cell and a preparation method of the solar cell. The preparation method comprises the steps that S10, a first carrier collection lamination layer and a blocking layer are sequentially formed on the backlight surface of a silicon substrate, the silicon substrate is further provided with a light receiving surface opposite to the backlight surface, and the backlight surface is pre-divided into a first area, a second area and an isolation area arranged between the first area and the second area; and S20, removing the parts of the first carrier collection lamination layer and the barrier layer in the second area through first laser film opening and alkali texturing, and enabling the exposed parts of the light receiving surface and the backlight surface of the silicon substrate in the second area to form texturing surfaces. And S30, forming a second carrier collection lamination layer on the backlight surface. And S40, removing the parts of the second carrier collection lamination layer and the barrier layer in the first region through second laser film opening and etching cleaning. And S50, sequentially forming a passivation layer and an antireflection layer on the light receiving surface. The silicon substrate and the passive film layer are prevented from being damaged, the cost is reduced, and the cell efficiency is improved.

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and in particular, to a solar cell and a method for manufacturing the same. Background Art

[0002] Currently, IBC cells (Interdigitated back contact cells) have gradually gained popularity due to multiple advantages, such as no light shading and no metal contact recombination on the front side of the cell. How to form product and technology differentiation to further improve the cell efficiency of back contact cells and thus maintain the competitiveness of enterprises in back contact cell products has currently become a huge challenge faced by photovoltaic enterprises.

[0003] The photovoltaic industry urgently needs new back contact cell structures and / or back contact cell manufacturing methods that can further improve the efficiency of back contact cells while taking into account manufacturing costs. Summary of the Invention

[0004] A first aspect of this application provides a method for manufacturing a solar cell, including:

[0005] S10: Sequentially form a first carrier collection stack and a barrier layer on the backlight surface of the silicon substrate. The silicon substrate also has a light-receiving surface opposite to the backlight surface, and the backlight surface is pre-divided into a first region, a second region, and an isolation region provided between the first region and the second region;

[0006] S20: Through the first laser film opening and alkaline texturing, remove the portions of the first carrier collection stack and the barrier layer in the second region, and form a textured surface on the exposed portions of the light-receiving surface and the backlight surface of the silicon substrate in the second region;

[0007] S30: Form a second carrier collection stack on the backlight surface;

[0008] S40: Through the second laser film opening and etching cleaning, remove the portions of the second carrier collection stack and the barrier layer in the first region;

[0009] S50: Then sequentially form a passivation layer and an antireflection layer on the light-receiving surface.

[0010] In some optional embodiments of this application, step S50 includes:

[0011] S51: Form a passivation layer on the light-receiving surface;

[0012] S52: Form a conductive thin film on the backlight surface. The conductive thin film is laid on the first region, the second region, and the isolation region;

[0013] S53: Form an antireflection layer on the side of the passivation layer facing away from the silicon substrate; the first carrier collection stack and the second carrier collection stack have opposite conductivity types.

[0014] In some alternative embodiments of the first aspect of the present application, the passivation layer is formed of an intrinsic silicon-containing thin film material or alumina, or the passivation layer includes a first passivation sublayer formed of an intrinsic silicon-containing thin film material and a second passivation sublayer formed of an n-type doped silicon-containing thin film material.

[0015] In some alternative embodiments of the present application, the antireflection layer includes one or more of alumina, silicon nitride, silicon oxynitride, silicon oxide, and magnesium fluoride.

[0016] In some alternative embodiments of the present application, the antireflection layer includes a plurality of stacked antireflection sublayers, each antireflection sublayer includes at least one of alumina, silicon nitride, silicon oxynitride, silicon oxide, and magnesium fluoride, and the antireflection layer further includes an ultraviolet light conversion layer containing carbon or silicon quantum dots, and the ultraviolet light conversion layer containing carbon or silicon quantum dots is disposed between two adjacent antireflection sublayers, on top of the plurality of stacked antireflection sublayers, or under the plurality of stacked antireflection sublayers.

[0017] In some alternative embodiments of the first aspect of the present application, step S50 includes:

[0018] S51’: Form a passivation layer on the light-receiving surface;

[0019] S52’: Form an antireflection layer on the side of the passivation layer facing away from the silicon substrate;

[0020] S53’: Form a conductive thin film on the backlight surface, and the conductive thin film is laid on the first region, the second region, and the isolation region.

[0021] In some alternative embodiments of the first aspect of the present application, it further includes:

[0022] Step S60: Groove the isolation region along the thickness direction of the silicon substrate to form an isolation groove in the isolation region, and the isolation groove at least penetrates the conductive thin film to insulate the first carrier collection stack in the first region and the second carrier collection stack in the second region.

[0023] In some alternative embodiments of the first aspect of the present application, the isolation groove is grooved and extended from the conductive thin film to the side of the barrier layer facing away from the silicon substrate.

[0024] In some alternative embodiments of the first aspect of the present application, in step S10, the first carrier collection stack includes a tunneling oxide layer and a doped polysilicon layer, and the barrier layer includes a doped silicon glass layer and an insulating isolation layer.

[0025] In some alternative embodiments of the first aspect of the present application, the thickness of the tunneling oxide layer is 0.5 nm to 3.0 nm.

[0026] In some alternative embodiments of the first aspect of the present application, the thickness of the tunneling oxide layer is 0.5 nm to 2.0 nm.

[0027] In some alternative embodiments of the first aspect of the present application, the thickness of the doped polysilicon layer is 50 nm to 300 nm.

[0028] In some alternative embodiments of the first aspect of the present application, the insulating isolation layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0029] In some alternative embodiments of the first aspect of the present application, in step S20:

[0030] The insulating isolation layer, the doped silicon glass layer, and a part of the doped polysilicon layer are removed by the first laser film opening;

[0031] The alkaline texturing step continues to remove the tunneling oxide layer and the remaining part of the doped polysilicon layer, so that the light-receiving surface and the second region of the backlight surface of the silicon substrate are exposed.

[0032] In some alternative embodiments of the first aspect of the present application, in step S30,

[0033] The second carrier collection stack includes an intrinsic silicon-containing film and a doped silicon-containing film.

[0034] In some alternative embodiments of the first aspect of the present application, the intrinsic silicon-containing film is a single-layer silicon-containing film with the same performance or a multi-layer silicon-containing film with different performances formed by any one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide, or,

[0035] The intrinsic silicon-containing film is a stacked silicon-containing film formed by at least two of microcrystalline silicon film, nanocrystalline silicon film, amorphous silicon film, silicon oxide film, and silicon carbide film, or,

[0036] The intrinsic silicon-containing film is a single-layer silicon-containing film formed by mixing at least two of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide.

[0037] In some alternative embodiments of the first aspect of the present application, the film body of the doped silicon-containing film is a single-layer silicon-containing film with the same performance or a multi-layer silicon-containing film with different performances formed by any one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide, or,

[0038] The film body of the doped silicon-containing film is a stacked silicon-containing film formed by at least two of microcrystalline silicon film, nanocrystalline silicon film, amorphous silicon film, silicon oxide film, and silicon carbide film, or,

[0039] The thin film body doped with a silicon-containing thin film is a silicon-containing thin film formed by mixing at least two of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide.

[0040] In some alternative embodiments of the first aspect of the present application, the conductivity type of the doped silicon-containing thin film is opposite to that of the silicon substrate.

[0041] In some alternative embodiments of the first aspect of the present application, in step S40, the doped silicon-containing thin film, the intrinsic silicon-containing thin film, and a part of the barrier layer in the first region are removed by the second laser film opening, and then the remaining part of the barrier layer in the first region is removed by etching and cleaning.

[0042] In some alternative embodiments of the first aspect of the present application, the barrier layer includes a doped silicon glass layer and an insulating isolation layer, a part of the barrier layer is a part of the insulating isolation layer, and the remaining part of the barrier layer is the remaining part of the insulating isolation layer and the doped silicon glass layer.

[0043] In some alternative embodiments of the first aspect of the present application, the preparation method further includes step S70:

[0044] A first metal electrode and a second metal electrode are respectively fabricated on the first region and the second region.

[0045] In some alternative embodiments of the first aspect of the present application, before step S10, it further includes:

[0046] Step S01: Polishing the silicon substrate to remove the cutting damage layer, so that the light-receiving surface and the backlight surface form a polished structure.

[0047] The second aspect of the present application provides a solar cell, which is prepared by using the preparation method of the solar cell in the first aspect of the present application. The solar cell includes:

[0048] A silicon substrate having opposite backlight surface and light-receiving surface, a first region, a second region, and an isolation region provided between the first region and the second region are formed on the backlight surface; a first carrier collection stack is provided in the first region, and a second carrier collection stack is provided in the second region;

[0049] The isolation region is sequentially provided with a first carrier collection layer, a barrier layer, and a part of the second carrier collection layer along the direction away from the silicon substrate;

[0050] A passivation layer and an antireflection layer are sequentially provided on the light-receiving surface.

[0051] In some alternative embodiments of the first aspect of the present application, the first carrier collection stack includes a tunneling oxide layer and a doped polysilicon layer sequentially provided along the direction away from the silicon substrate. A conductive thin film and a first metal electrode electrically connected to the conductive thin film are further provided outside the doped polysilicon layer in the first region.

[0052] In some optional embodiments of the first aspect of the present application, the second carrier collection stack includes an intrinsic silicon-containing thin film and a doped silicon-containing thin film sequentially arranged along the direction away from the silicon substrate. The second region further has a conductive thin film outside the doped silicon-containing thin film and a second metal electrode electrically connected to the conductive thin film.

[0053] In some optional embodiments of the first aspect of the present application, the isolation region includes a first isolation region and two second isolation regions. The first isolation region is disposed between the two second isolation regions.

[0054] At least one layer of the intrinsic silicon-containing thin film, the doped silicon-containing thin film, and the conductive thin film is removed from the first isolation region compared with the second isolation region to form an isolation groove, and the isolation groove extends and is grooved from the conductive thin film towards the silicon substrate.

[0055] Beneficial effects:

[0056] In the first aspect of the present application, by first performing two laser film opening and cleaning processes on the back surface of the solar cell, a first carrier collection stack and a second carrier collection stack are respectively formed in the first region and the second region, and the formation of the passivation layer and the antireflection layer on the light-receiving surface is postponed after the two laser film opening and cleaning processes, thereby adjusting the manufacturing process sequence, avoiding the damage of the passivation layer and the antireflection layer provided on the light-receiving surface by the etching solution (such as HF hydrofluoric acid) in the etching and cleaning process. For example, the damage to the passivation layer including the intrinsic silicon-containing thin film and the n-type silicon-containing thin film is avoided, especially the damage to the oxygen-doped microcrystalline silicon thin film layer is avoided, and further the problem of the reduction of the battery efficiency caused by the damage of the passivation layer and / or the antireflection layer is avoided.

[0057] Since it is no longer necessary to consider thickening the thickness of the passivation layer and / or the antireflection layer in advance due to the use of the etching solution in the etching and cleaning process, the thickness of the passivation layer formed on the light-receiving surface during the preparation of the solar cell is reduced, thereby reducing the production cost and improving the production efficiency. The problem of large differences in the front color caused by uneven floating of the thickness of the passivation and / or antireflection layer on the light-receiving surface of the solar cell is avoided, and good consistency in the color and thickness of the light-receiving surface (also called the front surface) of the solar cell is ensured.

[0058] The solar cell provided by the second aspect of the present application has good passivation effect, good color consistency on the light-receiving surface of the solar cell, high battery efficiency and low preparation cost. Description of the drawings

[0059] Figure 1 It is a schematic diagram of the silicon substrate structure in step S10 of an embodiment of the preparation method of the solar cell provided by the present application;

[0060] Figure 2It is a schematic structural diagram of an intermediate product of a battery chip obtained after the completion of step S10 in an embodiment of the method for manufacturing a solar cell provided by the present application;

[0061] Figure 3 It is a schematic structural diagram of an intermediate product of a battery chip obtained after the completion of the first laser film opening in step S20 in an embodiment of the method for manufacturing a solar cell provided by the present application;

[0062] Figure 4 It is a schematic structural diagram of an intermediate product of a battery chip obtained after the completion of alkaline texturing in step S20 in an embodiment of the method for manufacturing a solar cell provided by the present application;

[0063] Figure 5 It is a schematic structural diagram of an intermediate product of a battery chip obtained after setting a second carrier collection stack in step S30 in an embodiment of the method for manufacturing a solar cell provided by the present application;

[0064] Figure 6 It is a schematic structural diagram of an intermediate product of a battery chip obtained after the completion of the second laser film opening and etching cleaning in step S40 in an embodiment of the method for manufacturing a solar cell provided by the present application;

[0065] Figure 7 It is a schematic structural diagram of an intermediate product of a battery chip obtained after forming a passivation layer in step S51 in step S50 in an embodiment of the method for manufacturing a solar cell provided by the present application;

[0066] Figure 8 It is a schematic structural diagram of an intermediate product of a battery chip obtained after forming a conductive thin film in step S52 in step S50 in an embodiment of the method for manufacturing a solar cell provided by the present application;

[0067] Figure 9 It is a schematic structural diagram of an intermediate product of a battery chip obtained after forming an antireflection layer on the side of the passivation layer facing away from the silicon substrate in step S53 in step S50 in an embodiment of the method for manufacturing a solar cell provided by the present application;

[0068] Figure 10 It is a schematic structural diagram of an intermediate product of a battery chip obtained after the completion of grooving treatment in step S60 in an embodiment of the method for manufacturing a solar cell provided by the present application;

[0069] Figure 11 It is a schematic structural diagram of a battery chip product obtained after the completion of the production of the first metal electrode and the second metal electrode in step S70 in an embodiment of the method for manufacturing a solar cell provided by the present application;

[0070] Figure 12 It is a schematic structural diagram of a battery chip product obtained after the completion of step S52' in step S50 in another embodiment of the method for manufacturing a solar cell provided by the present application;

[0071] Figure 13 It is a schematic diagram of the cell structure obtained after completing step S53' in step S50 of another embodiment of the method for manufacturing a solar cell provided by this application;

[0072] Figure 14 It is a schematic diagram of the layer structure of the solar cell provided by this application.

[0073] Explanation of reference numerals:

[0074] 1 - silicon substrate; 2 - tunneling oxide layer; 3 - doped polysilicon layer; 4 - doped silicon glass layer; 5 - insulating isolation layer; 6 - intrinsic silicon-containing film; 7 - doped silicon-containing film; 8 - passivation layer; 10 - antireflection layer; 9 - conductive film; 11 - isolation groove; 12 - first metal electrode; 13 - second metal electrode; A - first region; B - second region; C - isolation region; C1 - first isolation region; C2 - second isolation region. Detailed implementation manners

[0075] The following will combine with the attached Figures 1 to 14 to elaborate on the technical solutions of this application in detail.

[0076] The inventors have deeply studied and found that in the preparation process of general back-contact solar cells, after the first laser film opening and texturing steps, the intrinsic silicon-containing film 6 and the p-type silicon-containing film on the back surface are grown on the back surface of the silicon wafer by PECVD, and the intrinsic silicon-containing film on the front surface, the n-type silicon-containing film on the front surface, and the antireflection layer are grown on the front surface of the silicon wafer by PECVD. Then, when using HF to clean the remaining mask by a low-damage method with the second laser to first open the intrinsic silicon-containing film, the p-type silicon-containing film, and part of the mask layer on the back surface, it is inevitable to damage the intrinsic silicon-containing film on the front surface and the n-type silicon-containing film on the front surface. At the same time, the thickness of the front antireflection layer will also be reduced. Then, when preparing the front antireflection layer, the film layer thickness needs to be increased, thus increasing the cost. The stability of the HF chemical cleaning process is relatively poor, which easily causes a certain fluctuation in the front thickness, resulting in a large color difference and poor consistency among the front cell wafers of different batches, thereby affecting the efficiency of the solar cell. There are p regions and n regions formed on the back surface of the back-contact cell. An intrinsic silicon-containing film on the front surface and an n-type silicon-containing film on the front surface with the same doping type as the n-type silicon substrate are formed on the front surface of the silicon wafer to reduce surface recombination and form a high-quality passivation layer structure. At the same time, the n-type silicon-containing film on the front surface can optimize the built-in electric field and form a more efficient PN junction electric field in the cell wafer.

[0077]

Embodiment 1

[0078] Combine Figures 1 to 11The process steps of the preparation method of the solar cell in an embodiment of the first aspect of the present application are described in detail and specifically.

[0079] The preparation method of the solar cell in an embodiment of the first aspect of the present application includes:

[0080] S10: A first carrier collection stack and a barrier layer are sequentially formed on the backlight surface of the silicon substrate 1. The silicon substrate 1 also has a light-receiving surface opposite to the backlight surface. The backlight surface is pre-divided into a first region A, a second region B, and an isolation region C provided between the first region A and the second region B;

[0081] S20: Through the first laser film opening and alkali texturing, the parts of the first carrier collection stack and the barrier layer in the second region B are removed, and the light-receiving surface and the backlight surface of the silicon substrate 1 in the exposed parts of the second region B form a textured surface;

[0082] S30: A second carrier collection stack is formed on the backlight surface;

[0083] S40: Through the second laser film opening and etching cleaning, the parts of the second carrier collection stack and the barrier layer in the first region A are removed;

[0084] S50: Then, a passivation layer 8 and an antireflection layer 10 are sequentially formed on the light-receiving surface.

[0085] In some alternative embodiments of the first aspect of the present application, in the extending direction of the main grid of the solar cell, the first region A and the second region B are alternately arranged, and an isolation region C is provided between every two adjacent first region A and second region B.

[0086] In some alternative embodiments of the first aspect of the present application, before step S10, it further includes:

[0087] Step S01: The silicon substrate 1 is polished to remove the cutting damage layer, and the light-receiving surface and the backlight surface form a polished structure.

[0088] In some alternative embodiments of the present application, step S50 includes:

[0089] S51: A passivation layer 8 is formed on the light-receiving surface;

[0090] S52: A conductive thin film 9 is formed on the backlight surface, and the conductive thin film 9 is laid on the first region A, the second region B, and the isolation region C;

[0091] S53: An antireflection layer 10 is formed on the side of the passivation layer 8 facing away from the silicon substrate 1; The first carrier collection stack and the second carrier collection stack have opposite conductivity types.

[0092] In the first aspect of this application, by first performing a secondary laser film opening and cleaning process on the back of the solar cell, a first carrier collection stack and a second carrier collection stack are respectively formed in the first region A and the second region B. Then, the front passivation layer 8 and the antireflection layer 10 are postponed after the above process, adjusting the manufacturing process sequence, and avoiding the damage of the passivation layer 8 and the antireflection layer 10 provided on the light-receiving surface by HF (hydrofluoric acid) in the etching and cleaning process. For example, the damage to the passivation layer 8 including the intrinsic silicon-containing thin film 6 and the n-type silicon-containing thin film is avoided. In some examples, the n-type silicon-containing thin film of the passivation layer 8 adopts an oxygen-doped microcrystalline layer, and hydrofluoric acid can react with oxide components such as silicon dioxide (SiO2) in the oxygen-doped microcrystalline layer, resulting in the decomposition of the material surface and damaging the structural integrity and functionality of the microcrystalline layer. Therefore, the preparation method of the solar cell in the first aspect of this application can avoid the damage to the oxygen-doped microcrystalline silicon thin film layer in the passivation layer 8, and further avoid the problem of reduced battery efficiency caused by the damage of the passivation layer 8 and / or the antireflection layer 10.

[0093] Since it is no longer necessary to consider pre-thickening the thickness of the passivation layer 8 and / or the antireflection layer due to the use of HF in the etching and cleaning process, the thickness of the passivation layer 8 formed on the light-receiving surface during the preparation of the solar cell is reduced, thereby reducing the production cost and improving the production efficiency. It avoids large differences in the front color caused by uneven floating of the thickness of the passivation layer and / or the antireflection layer on the light-receiving surface of the solar cell chip, and ensures good consistency in the color and thickness of the light-receiving surface (also called the front side) of the solar cell chip.

[0094] Briefly, the method for preparing a high-efficiency solar cell in the first aspect of this application reduces the damage of laser and chemical cleaning to the silicon substrate 1 and the passivation film layer during the manufacturing process by the method of selective laser film opening and adjusting the preparation sequence of the front passivation layer 8 and the antireflection layer 10 and the two laser film openings. Thereby, not only the stability of the manufacturing process is improved, but also the battery efficiency is increased, and the production cost can be reduced.

[0095] In some optional embodiments of the first aspect of this application, the passivation layer 8 is formed of an intrinsic silicon-containing thin film material or alumina, or the passivation layer 8 includes a first passivation sub-layer formed of an intrinsic silicon-containing thin film material and a second passivation sub-layer formed of an n-type doped silicon-containing thin film 7 material.

[0096] Specifically, a passivation layer 8 is formed on the light-receiving surface of the silicon substrate 1 by using a plate-type RF (Radio Frequency) process or a plate-type VHF (Very High Frequency) process.

[0097] A conductive thin film 9 is formed on the backlight surface of the silicon substrate 1 by means of equipment such as physical vapor deposition (PVD), reactive plasma deposition (RPD), and magnetron sputtering. Among them, the conductive thin film 9 is a multilayer or laminate or mixture of one or more doped metal oxides or nitrides. The metal oxide can be indium oxide, tin oxide, zinc oxide, cadmium oxide, titanium nitride, and the metal nitride can be titanium nitride. The doping elements can be indium, tin, calcium, aluminum, cadmium, zinc, cerium, fluorine, preferably an ICO thin film.

[0098] In these embodiments, the preparation step of the conductive thin film 9 is set before the preparation step of the antireflection layer 10. When preparing the antireflection layer 10, a similar annealing treatment can be performed on the conductive thin film 9, thereby further improving the performance of the conductive thin film 9, improving the overall efficiency of the solar cell, and realizing the preparation of the solar cell. It can be understood that during the process of growing the antireflection layer, the temperature is at least between 150°C and 250°C for a certain period of time. At this temperature, the conductive thin film 9 is equivalent to being heat-treated (i.e., annealed), which can improve the microstructure of the conductive thin film 9 and reduce defects. Specifically, the annealing treatment can significantly promote grain growth, increase the grain size, increase the grain boundary density, and make the surface morphology more flat, which helps to eliminate defects; it can reduce the resistivity and improve the conductivity; it also makes the microstructure of the conductive thin film 9 denser.

[0099] In some alternative embodiments of the present application, the antireflection layer 10 includes one or more of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, and magnesium fluoride. Using equipment such as tube-type, plate-type PECVD, spin coating, and spraying, the antireflection layer is grown on the surface of the passivation layer 8 of the silicon substrate 1 by a low-temperature growth method.

[0100] In some alternative embodiments of the present application, the antireflection layer 10 includes a plurality of stacked antireflection sub-layers. Each antireflection sub-layer includes at least one of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, and magnesium fluoride. The antireflection layer 10 further includes an ultraviolet light conversion layer containing carbon or silicon quantum dots. The ultraviolet light conversion layer containing carbon or silicon quantum dots is disposed between two adjacent antireflection sub-layers, on top of the plurality of stacked antireflection sub-layers, or under the plurality of stacked antireflection sub-layers.

[0101] The ultraviolet light conversion layer can convert ultraviolet light with a wavelength of 180 nm to 400 nm into visible light with a wavelength of 400 nm to 700 nm.

[0102] In some alternative embodiments of the first aspect of the present application, it further includes:

[0103] Step S60: Grooving the isolation region C in the thickness direction of the silicon substrate 1 to form an isolation groove 11 in the isolation region C. The isolation groove 11 at least penetrates through the conductive thin film 9 to insulate the first carrier collection stack in the first region A and the second carrier collection stack in the second region B.

[0104] In some alternative embodiments of the first aspect of the present application, the isolation groove 11 extends from the conductive thin film 9 to the silicon substrate 1 by grooving and reaches the side of the barrier layer facing away from the silicon substrate 1.

[0105] In some embodiments, laser film opening or mask etching can be used to form the isolation groove 11 by grooving. The isolation groove 11 is used to insulate the first region A and the second region B.

[0106] In some alternative embodiments of the first aspect of the present application, in step S10, the first carrier collection stack includes a tunneling oxide layer 2 and a doped polysilicon layer 3, and the barrier layer includes a doped silicon glass layer 4 and an insulating isolation layer 5.

[0107] In some alternative embodiments of the first aspect of the present application, the thickness of the tunneling oxide layer 2 is 0.5 nm to 3.0 nm, for example, it can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm or 3 nm, etc.

[0108] In some alternative embodiments of the first aspect of the present application, the thickness of the tunneling oxide layer 2 is 0.5 nm to 2.0 nm, for example, it can be 0.5 nm, 0.7 nm, 0.9 nm, 1.1 nm, 1.3 nm, 1.5 nm, 1.7 nm, 1.9 nm or 2 nm, etc.

[0109] In some alternative embodiments of the first aspect of the present application, the thickness of the doped polysilicon layer 3 is 50 nm to 300 nm, for example, it can be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm, etc.

[0110] In some alternative embodiments of the first aspect of the present application, the insulating isolation layer 5 includes at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide.

[0111] In some alternative embodiments of the first aspect of the present application, in step S20:

[0112] The insulating isolation layer 5, the doped silicon glass layer 4 and a part of the doped polysilicon layer 3 are removed by the first laser film opening;

[0113] The tunneling oxide layer 2 and the remaining part of the doped polysilicon layer 3 are continuously removed in the alkali texturing step, so that the second region B on the light-receiving surface and the backlight surface of the silicon substrate 1 is exposed.

[0114] In some embodiments, the silicon substrate 1 is an n-type silicon substrate 1, and the doped polysilicon layer 3 is an n-type polysilicon layer. When forming the n-type polysilicon layer, a phosphorus-doped doped silicon glass layer 4 will be naturally formed. During the phosphorus doping process (such as using POCl3 gas as the phosphorus source), the following reactions occur in a high-temperature environment (800 - 1000 °C): First, gas decomposition: POCl3 decomposes into P, Cl, and O2, where P atoms diffuse into the silicon lattice to form the doped polysilicon layer 3; Second, oxidation reaction: the silicon wafer surface reacts with oxygen to generate SiO2, and at the same time, the excess phosphorus combines with SiO2 to form a phosphosilicate glass layer (PSG), and this phosphosilicate glass layer is the doped silicon glass layer 4.

[0115] In some examples of these embodiments, part of the doped polysilicon layer 3, the entire doped silicon glass layer 4, and the entire insulating isolation layer 5 in the second region are removed by nanosecond or picosecond ultraviolet or green laser selective film opening. In the alkaline texturing process, since the insulating isolation layer 5 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide can, through their chemical stability and corrosion resistance, act as a mask to protect the insulating isolation layer 5 from being corroded by an alkaline solution (such as KOH or NaOH) towards the film layer below the silicon substrate 1. Therefore, during the alkaline texturing process in step S20, the isolation region C and the first region A are protected by the insulating isolation layer 5 from being corroded by the alkaline solution.

[0116] In these embodiments, by the method of selective laser film opening, the number of film layers for film opening is reduced, and the laser film opening controls the removal of part of the film layers in the second region B and then the remaining film layers are removed by the alkaline texturing step, which can greatly reduce the damage to the silicon substrate 1 and each film layer in the passivation structure. Avoiding the damage to the silicon substrate 1 reduces the height difference between the first region A and the second region B, and further reduces the silver consumption when preparing the second metal electrode 13 in the second region B, thereby reducing the production cost.

[0117] Then, the front and back of the intermediate product of the battery wafer are cleaned, polished, cleaned, textured, and cleaned with an alkaline solution, so that the second regions B on the light-receiving surface and the backlight surface of the silicon substrate 1 are exposed to form a textured surface.

[0118] In some optional embodiments of the first aspect of the present application, in step S30,

[0119] The second carrier collection stack includes an intrinsic silicon-containing thin film 6 and a doped silicon-containing thin film 7.

[0120] In some optional embodiments of the first aspect of the present application, the intrinsic silicon-containing film 6 is a single-layer silicon-containing film with the same performance or a multi-layer silicon-containing film with different performances formed by any one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide. The single-layer silicon-containing film with the same performance is, for example, a single microcrystalline silicon film, a single nanocrystalline silicon film, a single amorphous silicon film, a single silicon oxide film, and a single silicon carbide film; a multi-layer silicon-containing film is constructed using a single microcrystalline silicon material. For example, by controlling different crystallization rates of different microcrystalline silicon films in the multi-layer silicon-containing film, a multi-layer silicon-containing film with different performances is formed. By controlling different film thicknesses of different microcrystalline silicon films in the multi-layer silicon-containing film, a multi-layer silicon-containing film with different performances is formed.

[0121] Or,

[0122] The intrinsic silicon-containing film 6 is a laminated silicon-containing film formed by at least two of microcrystalline silicon film, nanocrystalline silicon film, amorphous silicon film, silicon oxide film, and silicon carbide film. For example, a laminated film of microcrystalline silicon film and amorphous silicon film. The microcrystalline silicon film close to the silicon substrate 1 is beneficial for light absorption and carrier transport. The amorphous silicon film disposed on the side of the microcrystalline silicon film facing away from the silicon substrate 1 is beneficial for achieving surface passivation and short-wavelength light absorption.

[0123] Or,

[0124] The intrinsic silicon-containing film 6 is a silicon-containing film formed by mixing at least two of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide. For example, a silicon-containing film is formed by mixing nanocrystalline silicon (with a size of 5 - 10 nm) and amorphous silicon to increase the spectral absorption range. The amorphous silicon further reduces the recombination rate by hydrogen-passivating the interface dangling bonds. The embedding of nanocrystalline silicon relieves the overall network stress of the silicon-containing film and improves the crack resistance of the silicon-containing film.

[0125] In some optional embodiments of the first aspect of the present application, the film body of the doped silicon-containing film 7 is a single-layer silicon-containing film with the same performance or a multi-layer silicon-containing film with different performances formed by any one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide. The single-layer silicon-containing film with the same performance is, for example, a single doped microcrystalline silicon film, a single doped nanocrystalline silicon film, a single doped amorphous silicon film, a single doped silicon oxide film, and a single doped silicon carbide film. A multi-layer silicon-containing film is constructed using a single microcrystalline silicon material. For example, a doped multi-layer silicon oxide film, where each layer uses silicon oxide material as the film body, and the doping concentration of each layer is different to achieve band adjustment and optimize the contact resistance.

[0126] Or,

[0127] The film body of the doped silicon-containing film 7 is a stacked silicon-containing film formed by at least two of microcrystalline silicon film, nanocrystalline silicon film, amorphous silicon film, silicon oxide film, and silicon carbide film. For example, a stacked film of doped amorphous silicon film and silicon oxide film. The doped amorphous silicon film close to the silicon substrate 1 and the doped amorphous silicon film disposed on the side of the doped amorphous silicon film facing away from the silicon substrate 1 can reduce the recombination rate.

[0128] Or,

[0129] The film body of the doped silicon-containing film 7 is a silicon-containing film formed by mixing at least two of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide. For example, the film body is a silicon-containing film formed by mixing microcrystalline silicon and silicon oxide. The microcrystalline silicon mainly provides a carrier transport channel, and the silicon oxide optimizes the passivation performance to inhibit surface recombination.

[0130] Specifically, an intrinsic silicon-containing film 6 and a doped silicon-containing film 7 are sequentially formed on the backlight surface of the silicon substrate 1 by using a plate-type RF or VHF PECVD device. Among them, the doped silicon-containing film 7 has a conductivity type opposite to that of the doped polysilicon layer 3.

[0131] In some alternative embodiments of the first aspect of the present application, the conductivity type of the doped silicon-containing film 7 is opposite to that of the silicon substrate 1. For example, the silicon substrate 1 is an n-type doped silicon substrate, and the doped silicon-containing film 7 is a p-type doped silicon-containing film.

[0132] In some alternative embodiments of the first aspect of the present application, in step S40, the doped silicon-containing film 7, the intrinsic silicon-containing film 6, and a part of the barrier layer in the first region A are removed by the second laser opening of the film, and then the remaining part of the barrier layer in the first region A is removed by etching and cleaning.

[0133] Specifically, the intrinsic silicon-containing film 6, the doped silicon-containing film 7, and a part of the insulating isolation layer 5 on the first region A are selectively removed by nanosecond or picosecond ultraviolet or green laser opening of the film, which can better reduce the damage of the laser to the first carrier collection stack and ensure the passivation effect of the first carrier collection stack in the first region A. Then, through etching and cleaning treatment, the doped silicon glass layer 4 and the remaining insulating isolation layer 5 in the first region A are removed respectively, and the cleanliness of the light-receiving surface of the silicon substrate 1 is ensured.

[0134] In these embodiments, by the method of selective laser opening of the film, the number of layers of the opened film is reduced, and the laser opening of the film controls the removal of some film layers in the first region A, which can greatly reduce the damage to the silicon substrate 1 and each film layer of the first carrier collection stack in the first region A, thereby reducing recombination and improving the performance of the battery.

[0135] In some optional embodiments of the first aspect of the present application, the barrier layer originally includes a doped silicon glass layer 4 and an insulating isolation layer 5, part of the barrier layer in step S40 is part of the insulating isolation layer 5, and the remaining barrier layer is the remaining insulating isolation layer 5 and the doped silicon glass layer 4.

[0136] In some optional embodiments of the first aspect of the present application, a first metal electrode 12 and a second metal electrode 13 are respectively made on the first region A and the second region B. The first metal electrode 12 is electrically connected to the conductive film 9 in the first region A, and the first metal electrode 12 derives the first carrier type in the first region A to be the same as the doping type in the first carrier collection stack. The second metal electrode 13 is electrically connected to the conductive film 9 in the second region B, and the second metal electrode 13 derives the second carrier type in the second region B to be the same as the doping type in the second carrier collection stack.

[0137] In some optional embodiments of the first aspect of the present application, the first metal electrode 12 and the second metal electrode 13 may be manufactured by at least one of screen printing, electroplating or transfer printing.

[0138] [Example 2]

[0139] like Figures 12 to 13 As shown, the difference between Example 2 of the present application and Example 1 is that:

[0140] Step S50 includes:

[0141] S51': forming a passivation layer 8 on the light receiving surface;

[0142] S52': forming an anti-reflection layer 10 on a side of the passivation layer 8 facing away from the silicon substrate 1;

[0143] S53 ′: forming a conductive film 9 on the backlight surface, wherein the conductive film 9 is laid on the first area A, the second area B and the isolation area C.

[0144] That is, compared with Example 1, the front growth is first performed on the light-receiving surface, and then the conductive film 9 is deposited on the backlight surface. In these embodiments, the formation of the passivation layer 8 and the anti-reflection layer 10 is still performed after two laser film opening and cleaning steps, thereby avoiding damage to the passivation layer 8 and the anti-reflection layer 10 by the cleaning process.

[0145] like Figure 14As shown in the figure, the second aspect of the present application provides a solar cell, which is prepared by using the preparation method of the solar cell provided in the first aspect. The solar cell includes: a silicon substrate 1 having an opposite backlight surface and a light-receiving surface, a first region A, a second region B, and an isolation region C provided between the first region A and the second region B are formed on the backlight surface; a first carrier collection stack is provided in the first region A, and a second carrier collection stack is provided in the second region B; the isolation region C is sequentially provided with a first carrier collection layer, a barrier layer, and a part of the second carrier collection stack along the direction away from the silicon substrate 1; a passivation layer 8 and an antireflection layer 10 are sequentially provided on the light-receiving surface.

[0146] Among them, the first carrier collection stack includes a tunneling oxide layer 2 and a doped polysilicon layer 3 sequentially provided along the direction away from the silicon substrate 1. The first region A further has a conductive thin film 9 and a first metal electrode 12 electrically connected to the conductive thin film 9 outside the doped polysilicon layer 3. The second carrier collection stack includes an intrinsic silicon-containing thin film 6 and a doped silicon-containing thin film 7 sequentially provided along the direction away from the silicon substrate 1. The second region B further has a conductive thin film 9 and a second metal electrode 13 electrically connected to the conductive thin film 9 outside the doped silicon-containing thin film 7.

[0147] In the isolation region C, a tunneling oxide layer 2, a doped polysilicon layer 3, a doped silicon glass layer 4, an insulating isolation layer 5, an intrinsic silicon-containing thin film 6, a doped silicon-containing thin film 7, and a conductive thin film 9 are sequentially provided along the direction away from the silicon substrate 1. The isolation region C includes a first isolation region C1 and two second isolation regions C2. The first isolation region C1 is provided between the two second isolation regions C2. At least one layer of the intrinsic silicon-containing thin film 6, the doped silicon-containing thin film 7, and the conductive thin film 9 is removed from the first isolation region C1 compared with the second isolation region C2 to form an isolation groove 11, and the isolation groove 11 extends and is grooved from the conductive thin film 9 towards the silicon substrate 1.

[0148] In some embodiments, the conductive thin film 9 is removed from the first isolation region C1 compared with the second isolation region C2 to form an isolation groove 11 to insulate the first region A and the second region B.

[0149] In some embodiments, the intrinsic silicon-containing thin film 6, the doped silicon-containing thin film 7, and the conductive thin film 9 are removed from the first isolation region C1 compared with the second isolation region C2 to form an isolation groove 11 to insulate the first region A and the second region B.

[0150] The solar cell provided by the second aspect of the present application has a good passivation effect, with good color consistency on the light-receiving surface of the solar cell, high battery conversion efficiency, and low manufacturing cost. In some examples, in the preparation process of the solar cell provided by the second aspect of the present application, the method of selective laser film opening is adopted. The laser film opening controls the removal of part of the film layer in the second region B, and then the remaining film layer is removed by alkali treatment, reducing the number of laser film opening layers and thus reducing the damage to the battery silicon substrate. The height difference between regions A and B can be reduced, thereby reducing the silver consumption in region B and the production cost. At the same time, the energy of the selective laser film opening method preferably acts on the part of the film layer to be removed by laser, reducing the damage to each film layer in the passivation structure of the silicon substrate 1. It does not directly hit the silicon substrate 1 to avoid overheating of the silicon substrate 1 and affecting each film layer in the passivation structure, avoiding film layer peeling or lattice defects, reducing recombination, and improving battery performance.

[0151] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for preparing a solar cell, characterized in that: include: S10: sequentially forming a first carrier collection stack and a barrier layer on a backlight surface of a silicon substrate, wherein the silicon substrate further comprises a light receiving surface opposite to the backlight surface, and the backlight surface is pre-divided into a first region, a second region, and an isolation region disposed between the first region and the second region; S20: removing the first carrier collection stack and the barrier layer in the second region through the first laser film opening and alkali texturing, and forming a texturing surface on the light-receiving surface and the backlight surface of the silicon substrate exposed in the second region; S30: forming a second carrier collection stack on the backlight surface; S40: removing the second carrier collection stack and the portion of the barrier layer in the first region by performing a second laser film opening and etching cleaning; S50: forming a passivation layer and an anti-reflection layer in sequence on the light-receiving surface.

2. The method for preparing a solar cell according to claim 1, characterized in that: The step S50 comprises: S51: forming a passivation layer on the light receiving surface; S52: forming a conductive film on the backlight surface, wherein the conductive film is laid on the first area, the second area and the isolation area; S53: forming the anti-reflection layer on a side of the passivation layer facing away from the silicon substrate; The first carrier collection stack has a conductivity type opposite to that of the second carrier collection stack; Preferably, the passivation layer is formed of an intrinsic silicon-containing thin film material or aluminum oxide, or the passivation layer includes a first passivation sublayer formed of an intrinsic silicon-containing thin film material and a second passivation sublayer formed of an n-type doped silicon-containing thin film material; Preferably, the anti-reflection layer comprises one or more of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, and magnesium fluoride; Preferably, the anti-reflection layer includes a plurality of stacked anti-reflection sub-layers, each anti-reflection sub-layer includes at least one of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, and magnesium fluoride, and the anti-reflection layer also includes an ultraviolet light conversion layer containing carbon or silicon quantum dots, and the ultraviolet light conversion layer containing carbon or silicon quantum dots is arranged between two adjacent anti-reflection sub-layers, on top of the plurality of stacked anti-reflection sub-layers, or under the plurality of stacked anti-reflection sub-layers.

3. The method for preparing a solar cell according to claim 1, characterized in that: The step S50 comprises: S51': forming a passivation layer on the light receiving surface; S52': forming the anti-reflection layer on the side of the passivation layer facing away from the silicon substrate; S53 ′: forming a conductive film on the backlight surface, wherein the conductive film is laid on the first area, the second area and the isolation area.

4. The method for preparing a solar cell according to claim 2 or 3, characterized in that: Also includes: Step S60: Grooving the isolation region along the thickness direction of the silicon substrate to form an isolation groove in the isolation region, wherein the isolation groove at least penetrates the conductive film to insulate the first carrier collection stack in the first region from the second carrier collection stack in the second region; Preferably, the isolation groove is grooved from the conductive film toward the silicon substrate and extends to a side of the barrier layer facing away from the silicon substrate.

5. The method for preparing a solar cell according to claim 1, characterized in that: In the step S10, the first carrier collection stack includes a tunneling oxide layer and a doped polysilicon layer, and the barrier layer includes a doped silicon glass layer and an insulating isolation layer; Preferably, the thickness of the tunnel oxide layer is 0.5 nm to 3.0 nm, preferably, the thickness of the tunnel oxide layer is 0.5 nm to 2.0 nm; Preferably, the thickness of the doped polysilicon layer is 50 nm to 300 nm. Preferably, the insulating isolation layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide; Preferably, in step S20: Removing the insulating isolation layer, the doped silicon glass layer and part of the doped polysilicon layer by the first laser film opening; The alkaline texturing step continues to remove the tunneling oxide layer and the remaining portion of the doped polysilicon layer, so that the light-receiving surface and the second area of ​​the backlight surface of the silicon substrate are exposed.

6. The method for preparing a solar cell according to claim 1, characterized in that: In the step S30, The second carrier collection stack includes an intrinsic silicon-containing film and a doped silicon-containing film; Preferably, the intrinsic silicon-containing film is a single-layer silicon-containing film with the same performance or a multi-layer silicon-containing film with different performances formed by any one of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide and silicon carbide, or, The intrinsic silicon-containing film is a stacked silicon-containing film formed by at least two of a microcrystalline silicon film, a nano silicon film, an amorphous film, a silicon oxide film and a silicon carbide film, or, The intrinsic silicon-containing film is a silicon-containing film formed by mixing at least two of microcrystalline silicon, nano silicon, amorphous silicon, silicon oxide and silicon carbide; Preferably, the film body of the doped silicon-containing film is a single-layer silicon-containing film with the same performance or a multi-layer silicon-containing film with different performances formed by any one of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide and silicon carbide, or, The film body of the doped silicon-containing film is a stacked silicon-containing film formed by at least two of a microcrystalline silicon film, a nano silicon film, an amorphous silicon film, a silicon oxide film and a silicon carbide film, or, The film body of the doped silicon-containing film is a silicon-containing film formed by mixing at least two of microcrystalline silicon, nano silicon, amorphous silicon, silicon oxide and silicon carbide; Preferably, the conductivity type of the doped silicon-containing film is opposite to the conductivity type of the silicon substrate.

7. The method for preparing a solar cell according to claim 6, characterized in that: In the step S40, the doped silicon-containing film, the intrinsic silicon-containing film and part of the barrier layer in the first region are removed by the second laser film opening, and then the remaining barrier layer in the first region is removed by the etching and cleaning; Preferably, the barrier layer comprises a doped silicon glass layer and an insulating isolation layer, the partial barrier layer is a portion of the insulating isolation layer, and the remaining barrier layer is the remaining portion of the insulating isolation layer and the doped silicon glass layer.

8. A solar cell, characterized in that: The solar cell is prepared by the method for preparing a solar cell according to any one of claims 1 to 7, wherein the solar cell comprises: A silicon substrate having an opposite backlight surface and a light receiving surface, wherein a first region, a second region and an isolation region disposed between the first region and the second region are formed on the backlight surface; a first carrier collecting stack is disposed in the first region, and a second carrier collecting stack is disposed in the second region; The isolation region is provided with a first carrier collection layer, a barrier layer and a part of a second carrier collection layer in sequence along a direction away from the silicon substrate; A passivation layer and an anti-reflection layer are sequentially arranged on the light receiving surface.

9. The solar cell according to claim 8, characterized in that The first carrier collection stack comprises a tunneling oxide layer and a doped polysilicon layer sequentially arranged in a direction away from the silicon substrate, and the first region is further provided with a conductive film and a first metal electrode electrically connected to the conductive film on the outside of the doped polysilicon layer; Preferably, the second carrier collection stack includes an intrinsic silicon-containing film and a doped silicon-containing film sequentially arranged in a direction away from the silicon substrate, and the second region is further provided with a conductive film on the outside of the doped silicon-containing film and a second metal electrode electrically connected to the conductive film.

10. The solar cell according to claim 8, characterized in that The isolation region includes a first isolation region and two second isolation regions, wherein the first isolation region is arranged between the two second isolation regions. Compared with the second isolation region, the first isolation region removes at least one layer of an intrinsic silicon-containing film, a doped silicon-containing film and a conductive film to form an isolation groove, and the isolation groove extends from the conductive film to the silicon substrate.

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