MEMS gyroscope closed-loop driving loop

Abstract

The invention relates to the technical field of MEMS, and discloses an MEMS gyroscope closed-loop driving loop, a phase-locked loop circuit outputs a synchronous clock signal, and a clock generation circuit is used for performing gate logic operation, frequency division and layered delay addition on the synchronous clock signal to generate multiple groups of collaborative non-overlapping clock signals; a band-pass delta-sigma modulator, a CV conversion circuit and a digital signal processing module are controlled; meanwhile, through phase locking of a synchronous clock phase, a main sampling switch signal is synchronized with a falling edge of the synchronous clock phase, and the sampling phase is ensured to be 0 degree, so that a digital code stream signal of which the sampling phase is kept at 0 degree is output, and the sampling phase of the band-pass delta-sigma modulator is strictly synchronized with the mechanical vibration phase of the MEMS gyroscope; and phase deviation in the driving loop is eliminated. The digital signal processing module adjusts the amplitude and the phase of a feedback signal of the whole driving loop, so that the stability and the adjustability of the driving loop are improved under the condition that the MEMS gyroscope is driven under a proper condition.

Description

Technical Field

[0001] The present invention relates to the field of MEMS technology, and more particularly to a closed-loop drive circuit for a MEMS gyroscope. Background Art

[0002] As an important application of micro-electro-mechanical systems (MEMS) technology, MEMS gyroscopes play a key role in the field of inertial measurement and are used to detect external rotational angular velocity. Its basic principle is the Coriolis force effect; the angular velocity is converted into a detectable displacement signal by using the Coriolis effect, and its development process reflects the trends of miniaturization, integration, and intelligence. Since MEMS gyroscopes were commercialized in the 1990s, their technical path has undergone a leapfrog upgrade from vibratory to capacitive and from open-loop detection to closed-loop control, gradually solving core problems such as low early accuracy and large temperature drift. At present, most of the gyroscope sensitive structures of various units and research institutes are still in the development stage. To adapt to different gyroscope sensitive structures, customized circuits need to be designed according to corresponding structural parameters. The core of the MEMS gyro drive circuit is to maintain stable vibration of the drive mode through a closed-loop control mechanism; the drive circuit of the MEMS gyro needs to drive the gyro near its mechanical resonance frequency to achieve maximum energy efficiency. The phase-locked loop (PLL) tracks and locks the resonance frequency of the drive mode, and adjusts the drive signal frequency in real time to match the resonance point. At the same time, the PLL compares and synchronizes the input reference oscillation signal with the internal feedback oscillation signal to achieve the function of automatically tracking the phase and frequency of the input signal for the output signal. The loop bandwidth design of the PLL can filter out high-frequency noise, indirectly improve the effective Q value of the system, and enhance the robustness of the parasitic resonance mode of the sensor. The automatic gain control (AGC) is the core module for achieving stable oscillation and anti-interference. Its core function is to extract actual amplitude information from the vibration signal of the drive mode, compare the detected actual amplitude with the set target amplitude, generate an error signal, and convert the error signal into a gain adjustment amount through a PI controller to adjust the loop gain, thereby maintaining a constant vibration amplitude of the drive mode, ensuring the working stability of the gyroscope and the quality of the output signal. The mechanical vibration amplitude of the drive mode needs to be strictly stable to avoid amplitude fluctuations caused by environmental temperature changes, mechanical parameter drifts, or external disturbances, so as to ensure accurate detection of the Coriolis force. The capacitance-voltage (CV) conversion circuit is responsible for converting the capacitance change caused by the mechanical vibration of the drive mode into a processable voltage signal. The amplifier of the CV circuit needs to have a high input impedance and low noise to amplify weak signals. In recent years, amplitude detection and PI control of MEMS gyro drives have been basically digitalized. The analog-to-digital converter (ADC) is also a core module of the MEMS drive circuit, which is responsible for quantifying the voltage signal output by the CV circuit into a digital signal and processing it through a PI controller to achieve stable amplitude oscillation of the loop.

[0003] Amplifiers, power supply fluctuations, and clock jitter in the MEMS drive circuit can all introduce noise, and existing differential drive and filtering technologies are difficult to completely eliminate low-frequency 1 / f noise, which will affect the gyro drive at the resonant frequency. At the same time, the clock of some current gyro drive circuits is generated by an OSC. Although the architecture is stable and simple, considering the special nature of the resonant mode of the gyro, not using a PLL to lock and generate the system clock will affect the robustness of the parasitic resonant mode of the gyro. In addition, in the closed-loop path from detecting the vibration signal to adjusting the drive signal, the cumulative delay in links such as the modulator, comparator, algorithm processing, and DAC may reach hundreds of microseconds, resulting in phase shift and even oscillation.

[0004] The drive mode of the MEMS gyro generally needs to work near the resonant frequency of the mechanical structure to achieve the maximum vibration amplitude and sensitivity. The gyro system is a typical phase-sensitive system, and the phase error of each node will significantly affect the performance of the entire system; for example, in the resonant state, the ideal phase difference between the driving force signal of the gyro structure and the output capacitance change signal should be -90°. If this value shifts due to loop phase shift, that is, the gyro loop is not locked at the resonant frequency with the maximum gain, it will lead to an amplitude detection error of the Coriolis force signal and reduce the sensitivity.

[0005] In summary, the existing MEMS gyro drive circuit relies on a single master clock signal, and delay superposition will occur in multiple links of the circuit. The delay will cause the phase relationship between the drive signal and the mechanical vibration of the gyro to deviate from the ideal 90°, resulting in a decrease in the sensitivity of the MEMS gyro or oscillation. Summary of the Invention

[0006] Therefore, the technical problem to be solved by the present invention is to overcome the problem in the prior art that due to the use of a synchronous clock signal for control, there is a large accumulation of delay on the drive circuit, which in turn leads to phase shift of the drive signal, poor stability of the drive circuit, inability to accurately control the MEMS gyro to work at the resonant frequency with the maximum gain, and a decrease in the detection sensitivity of the MEMS gyro.

[0007] To solve the above technical problem, the present invention provides a MEMS gyro closed-loop drive circuit, including: A CV conversion circuit that converts the capacitance displacement amount inside the MEMS gyro into a voltage change signal and outputs it; A phase-locked loop circuit that generates a synchronous clock signal based on the voltage change signal and a preset reference signal; A clock generation circuit that generates multiple groups of non-overlapping clock signals based on the synchronous clock signal: The third delay signal is used to delay the first half cycle and the second half cycle of the synchronous clock signal respectively, so as to obtain the auxiliary sampling switch signal P1a and the auxiliary integration switch signal P2a whose falling edges are synchronized with the synchronous clock signal; The first delay signal is used to delay P1a and P2a respectively, so as to obtain the main sampling switch signal P1 and the main integration switch signal P2; The D flip-flop is used to process the synchronous clock signal, so as to obtain the frequency division signals A0, B0, I0 and II0; After the second delay signal is used to delay I0 and II0 respectively, and then delayed by the first delay signal, the global control signal I and the inverted global control signal II are obtained; After the second delay signal is used to delay A0 and B0 respectively, and then respectively ANDed with I and II, the integrator input path switch signals AI, BI and the integrator feedback path switch signals AII, BII are generated; The non-overlapping part of I and II is inverted to obtain the duty cycle resistance clock signal PP, which controls the duty cycle resistance in the CV conversion circuit; Among them, the delay time ratios of the first delay signal, the second delay signal and the third delay signal are 1:2:3; The band-pass Δ-Σ modulator composed of two series-connected SaloII-type resonators outputs a digital bit stream signal with the sampling phase maintained at 0° based on the control of multiple groups of non-overlapping clock signals; The digital signal processing module processes the digital bit stream signal to generate an adjustable drive voltage signal to drive the MEMS gyroscope in the resonant mode.

[0008] Preferably, the CV conversion circuit includes: An operational amplifier, whose non-inverting input terminal is connected to one side of the drive-mode capacitor in the MEMS gyroscope, and whose inverting input terminal is connected to one side of the sense-mode capacitor in the MEMS gyroscope; The first duty cycle resistance module includes a plurality of passive resistors connected in series, and a MOS switch is arranged between every two passive resistors; the idle end of its first passive resistor is connected to the inverting input terminal of the operational amplifier, and the idle end of its last passive resistor is connected to the non-inverting output terminal of the operational amplifier; The second duty cycle resistance module includes a plurality of passive resistors connected in series, and a MOS switch is arranged between every two passive resistors; the idle end of its first passive resistor is connected to the non-inverting input terminal of the operational amplifier, and the idle end of its last passive resistor is connected to the inverting output terminal of the operational amplifier.

[0009] Preferably, the band-pass Δ-Σ modulator is a quadruple-frequency double-delay structure, and its transfer function is expressed as: ; Among them, represents the output signal of the band-pass Δ-Σ modulator, represents that the signal passes through the delay of [[X]] clocks, represents the input signal of the band-pass Δ-Σ modulator.

[0010] Preferably, the phase-locked loop circuit includes: a phase-frequency detector that generates UP and DN signals based on the input preset reference signal and the divided-frequency feedback signal; a charge pump that generates a charge-discharge signal based on the UP and DN signals; a loop filter that generates a voltage signal output based on the charge-discharge signal; a voltage-controlled oscillator that generates a fully differential oscillation signal output based on the voltage signal; a differential-to-single-ended circuit that converts the fully differential oscillation signal into a single-ended square wave signal output; a programmable frequency divider that divides the single-ended square wave signal and generates a synchronous clock signal and a divided-frequency feedback signal, and outputs the divided-frequency feedback signal to the phase-frequency detector and the lock detection module; a lock detection module that generates a lock signal based on the input divided-frequency feedback signal and the reference signal and outputs it to the digital signal processing module to control the control mode of the digital signal processing module.

[0011] Preferably, generating a charge-discharge signal based on the UP and DN signals includes: If the UP signal is high and the DN signal is low, the charge pump generates a charging signal to charge the loop filter; When the UP signal is low and the DN signal is high, the charge pump generates a discharging signal to discharge the loop filter.

[0012] Preferably, controlling the control mode of the digital signal processing module based on the lock signal includes: If the phase difference between the divided-frequency feedback signal and the preset reference signal is greater than the preset phase value, the lock is not successful, the output lock signal is a low-level signal, and the digital signal processing module uses open-loop control; If the phase difference between the divided-frequency feedback signal and the preset reference signal is not greater than the preset phase value, the lock is successful, the output lock signal is a high-level signal, and the digital signal processing module uses closed-loop control.

[0013] Preferably, the digital signal processing module uses closed-loop control, including: multiplying the digital bitstream signal by the inverted reference signal FDN with a phase of 180°, performing FIR filtering and PID control to obtain the target signal; Multiply the target signal by a phase reference signal FUP with a phase of 135° to obtain a sine wave signal; Convert the sine wave signal into a square wave signal, perform an equivalent phase shift to obtain an output signal with a phase of 90°, and after passing through a digital-to-analog converter, use it as an adjustable drive voltage signal.

[0014] Preferably, the digital signal processing module adopts closed-loop control, including: Multiply the digital code stream signal by an in-phase reference signal FDN with a phase of 180°, perform FIR filtering and PID control to obtain the target signal; Multiply the target signal by a phase reference signal FUP with a phase of 90° to obtain a sine wave signal; Convert the sine wave signal into a square wave signal, use a D flip-flop controlled by a synchronous clock signal to shift the phase of the square wave signal by 45° to obtain an output signal with a phase of 90°, and after passing through a digital-to-analog converter, generate an adjustable drive voltage signal.

[0015] Preferably, the digital signal processing module adopts closed-loop control, including: Multiply the digital code stream signal by an in-phase reference signal FDN with a phase of 180°, perform FIR filtering and PID control to obtain the target signal; Multiply the target signal by a phase reference signal FUP with a phase of 90° to obtain a sine wave signal; Convert the sine wave signal into a square wave signal to obtain an output signal with a phase of 45°, and after passing through a digital-to-analog converter, generate an adjustable drive voltage signal.

[0016] Preferably, it further includes a hysteresis comparator, whose positive input terminal is connected to the output terminal of the CV conversion circuit, whose negative input terminal is connected to a preset reference signal, and whose output terminal is connected to the phase detector and frequency discriminator of the phase-locked loop, and is used for: When the voltage change signal at the positive input terminal is greater than the preset reference signal at the negative input terminal, the hysteresis comparator outputs a high level as the preset reference signal input to the phase detector and frequency discriminator; When the voltage change signal at the positive input terminal is not greater than the preset reference signal at the negative input terminal, the hysteresis comparator outputs a low level as the preset reference signal input to the phase detector and frequency discriminator.

[0017] The above technical solution of the present invention has the following beneficial effects compared with the prior art: For the MEMS gyro closed-loop drive circuit of the present invention, the synchronous clock signal output by the phase-locked loop circuit is used as the reference clock signal of the drive circuit. The clock generation circuit performs gate logic operations, frequency division, and addition of hierarchical delays on the synchronous clock signal, converting the single synchronous clock signal into multiple groups of cooperative non-overlapping clock signals for controlling the band-pass Δ-Σ modulator and the CV conversion circuit. At the same time, through the phase locking of the synchronous clock phase, the main sampling switch signal is synchronized with the falling edge of the synchronous clock phase, ensuring that the sampling moment is precisely located at the signal zero-crossing point, ensuring that the sampling phase is 0°, eliminating sampling jitter, and improving the signal-to-noise ratio, so as to ensure that the digital bitstream signal output by the band-pass Δ-Σ modulator has a sampling phase maintained at 0°. This makes the sampling phase of the band-pass Δ-Σ modulator strictly synchronized with the mechanical vibration of the MEMS gyro, eliminating the phase shift in the drive circuit, thereby improving the stability of the drive circuit and ensuring the detection accuracy of the MEMS gyro. Moreover, through hierarchical delay in the present invention, P1a and P2a are turned off earlier than P1 and P2, minimizing the influence of charge injection and clock feedthrough of the sampling circuit as much as possible; and clock I and II are turned off later than AI, BI, AII, and BII, thereby improving the stability of the integration circuit.

[0018] The CV conversion circuit of the present invention realizes the duty cycle resistor based on multiple series-connected passive resistors and MOS switches. By adjusting the duty cycle of the duty cycle resistor clock signal, the average current flowing through the MOS switch can be adjusted, that is, the size of the duty cycle resistor can be adjusted; and the duty cycle resistor is controlled by the duty cycle resistor clock signal generated in the clock generation circuit, ensuring the stability and overall phase consistency of the output signal of the CV conversion circuit, avoiding phase shift, and improving the stability of the drive circuit.

[0019] The phase-locked loop circuit of the present invention generates a lock signal output based on the feedback signal input to the lock detection module and the preset reference signal, so as to control the working mode of the digital signal processing module using the lock signal, improving the adaptive ability of the drive circuit; at the same time, the phase-locked loop can track and lock the resonant frequency in real time, ensuring that the drive signal always resonates with the mechanical system, avoiding energy loss or sensitivity degradation caused by frequency mismatch. When the phase-locked loop circuit is not locked, open-loop control is adopted to avoid phase shift caused by unstable closed-loop control, facilitating calibration; when the phase-locked loop circuit is locked, closed-loop control is adopted to ensure steady-state accuracy. At the same time, the phase-locked loop circuit outputs a same-phase clock signal to provide a clock signal for the entire loop, effectively enhancing the robustness of the parasitic resonance mode of the sensor and ensuring the phase stability of the drive signal.

[0020] When the digital signal processing module adopts closed-loop control, the present invention provides three driving modes to achieve high-precision resonance control, adjust the amplitude and phase of the feedback signal of the overall driving loop, ensure that the MEMS gyroscope is driven under suitable conditions, thereby improving the stability and adjustability of the driving loop, and ensuring the long-term driving accuracy of the MEMS gyroscope; Mode 1 realizes 90° phase square wave driving, which is suitable for high-Q MEMS gyroscopes; Mode 2 realizes 90° phase multi-level driving with the help of D flip-flops, which is suitable for low-Q MEMS gyroscopes; Mode 3 realizes 45° phase driving, enabling the gyroscope to operate at the -6dB point, and adapting to MEMS gyroscopes with a wide Q value range. The present invention provides adjustment methods for the phases of multiple modes, compensates for the phase difference through algorithms in the digital domain to ensure phase synchronization, guarantees the phase stability of the gyroscope driving signal, and further guarantees the detection accuracy of the gyroscope. Description of the Drawings

[0021] In order to make the content of the present invention easier to be clearly understood, the following further details the present invention according to specific embodiments of the present invention in conjunction with the drawings, where: Figure 1 is a schematic diagram of the closed-loop driving circuit of the MEMS gyroscope provided by the present invention; Figure 2 is a schematic diagram of the generation principle of the auxiliary sampling switch signal P1a and the auxiliary integration switch signal P2a; Figure 3 is a schematic diagram of the generation principle of the main sampling switch signal P1 and the main integration switch signal P2; Figure 4 is a schematic diagram of the generation principle of the frequency division signals A0, B0, I0 and II0; Figure 5 is a schematic diagram of the generation principle of the global control signal I and the inverted global control signal II; Figure 6 is a schematic diagram of the generation principle of the integrator input path switch signals AI, BI and the integrator feedback path switch signals AII, BII; Figure 7 is a schematic diagram of the generation principle of the duty cycle resistance clock signal PP; Figure 8 is a schematic diagram of the structure of the band-pass Δ-Σ modulator; Figure 9 is a circuit structure diagram of the CV conversion circuit; Figure 10 is a circuit structure diagram of the phase-locked loop circuit; Figure 11 is the driving loop phase diagram corresponding to Mode 1; Figure 12 is the system simulation result diagram of Mode 1; Figure 13 is the system simulation waveform diagram of the driving loop corresponding to Mode 1; Figure 14 It is the phase diagram of the drive circuit corresponding to Mode 2; Figure 15 It is the system simulation result diagram of Mode 2; Figure 16 It is the phase diagram of the drive circuit corresponding to Mode 3; Figure 17 It is the detailed structure diagram of the MEMS gyro closed-loop drive circuit; Figure 18 It is the waveform diagram of the clock generation circuit of the MEMS drive circuit. Specific embodiments

[0022] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the embodiments cited are not intended to limit the present invention.

[0023] Referring to Figure 1 as shown, the schematic diagram of the MEMS gyro closed-loop drive circuit provided by the present invention specifically includes: A CV conversion circuit that converts the capacitance displacement amount inside the MEMS gyro into a voltage change signal and outputs it; A phase-locked loop circuit that generates a synchronous clock signal based on the voltage change signal and a preset reference signal; A clock generation circuit that generates multiple groups of non-overlapping clock signals based on the synchronous clock signal: Using the third delay signal to delay the first half cycle and the second half cycle of the synchronous clock signal respectively to obtain the auxiliary sampling switch signal P1a and the auxiliary integration switch signal P2a whose falling edges are synchronized with the synchronous clock signal; Using the first delay signal to delay P1a and P2a respectively to obtain the main sampling switch signal P1 and the main integration switch signal P2; Using a D flip-flop to process the synchronous clock signal to obtain the frequency division signals A0, B0, I0 and II0; After using the second delay signal to delay I0 and II0 respectively and then delaying through the first delay signal, the global control signal I and the inverted global control signal II are obtained; After using the second delay signal to delay A0 and B0 respectively and then passing them through an AND gate with I and II respectively, the integrator input path switches AI, BI and the integrator feedback path switches AII, BII are generated; Taking the inverse of the non-overlapping part of I and II to obtain the duty cycle resistance clock signal PP to control the duty cycle resistance in the CV conversion circuit; Among them, the ratio of the delay times of the first delay signal, the second delay signal and the third delay signal is 1:2:3; A band-pass Δ-Σ modulator composed of two cascaded SaloII-type resonators, based on the control of multiple groups of non-overlapping clock signals, outputs a digital bitstream signal with the sampling phase maintained at 0°. A digital signal processing module processes the digital bitstream signal to generate an adjustable drive voltage signal to drive the MEMS gyroscope into a resonant mode.

[0024] In the closed-loop drive circuit of the MEMS gyroscope according to the present invention, the synchronous clock signal output by the phase-locked loop circuit is used as the reference clock signal of the drive circuit. The clock generation circuit performs gate logic operations, frequency division, and addition of hierarchical delays on the synchronous clock signal to convert the single synchronous clock signal into multiple groups of cooperative non-overlapping clock signals for controlling the band-pass Δ-Σ modulator and the CV conversion circuit. At the same time, through the phase locking of the synchronous clock phase, the main sampling switch signal is synchronized with the falling edge of the synchronous clock phase, ensuring that the sampling moment is precisely located at the signal zero-crossing point, ensuring that the sampling phase is 0°, eliminating sampling jitter, and improving the signal-to-noise ratio to ensure that the band-pass Δ-Σ modulator outputs a digital bitstream signal with the sampling phase maintained at 0°, making the sampling phase of the band-pass Δ-Σ modulator strictly synchronized with the mechanical vibration of the MEMS gyroscope, eliminating the phase shift in the drive circuit, thereby improving the stability of the drive circuit and ensuring the detection accuracy of the MEMS gyroscope. And in the present invention, through hierarchical delay, P1a and P2a are turned off earlier than P1 and P2 to minimize the influence of charge injection and clock feedthrough of the sampling circuit as much as possible; the clocks I and II are turned off later than AI, BI, AII, and BII, thereby improving the stability of the integration loop.

[0025] Specifically, in the clock generation circuit of this embodiment, the generation of multiple groups of non-overlapping clock signals specifically includes: the synchronous clock signal comes in, and through NAND gates, delays, D flip-flops, etc., 11 kinds of signals are generated. Among them, pp is the duty cycle resistor for the CV conversion circuit, and the other 10 are for the modulator, responsible for sampling or integration in the modulator; in this embodiment, according to the sampling point of P1a and is consistent with the falling edge, so the sampling position phase of the input signal is the same as that of the falling edge phase is the same. Also, because the phase is generated by the output of the CV conversion circuit through a comparator and a phase-locked loop, and no phase shift occurs in this process, which is in the same phase. Therefore, the sampling point of P1a and the falling edge phase is the same, which is 0°.

[0026] Refer to Figure 2 shown for the schematic diagram of the generation of the auxiliary sampling switch signal P1a and the auxiliary integration switch signal P2a; refer to Figure 3 shown for the schematic diagram of the generation of the main sampling switch signal P1 and the main integration switch signal P2.

[0027] Reference Figure 4 As shown, it is a schematic diagram for generating frequency-divided signals A0, B0, I0, and II0. Among them, the D flip-flop uses as the clock input. After frequency division by two, it outputs A0 and B0. Then, taking A0 as the clock input of the D flip-flop, after frequency division by two, it outputs I0 and II0.

[0028] Reference Figure 5 As shown, it is a schematic diagram for generating global control signal I and inverted global control signal II. Refer to Figure 6 As shown, it is a schematic diagram for generating integrator input path switch signals AI, BI and integrator feedback path switch signals AII, BII. Refer to Figure 7 As shown, it is a schematic diagram for generating the duty cycle resistance clock signal PP.

[0029] Specifically, refer to Figure 8 As shown, it is a structural schematic diagram of a band-pass Δ-Σ modulator. The band-pass Δ-Σ modulator in this embodiment consists of two series-connected SaloII-type resonators. Each SaloII-type resonator includes: A sampling switch module, including two identical branches. One branch has its input terminal connected to VIP1, and the other branch has its input terminal connected to VIN1. Each branch includes: a main sampling switch, a sampling capacitor, and a main integration switch connected in series, as well as an auxiliary sampling switch and an auxiliary integration switch. One end of the auxiliary integration switch is connected to VCM, and the other end is connected to the line connecting the main sampling switch and the sampling capacitor. One end of the auxiliary sampling switch is connected to VCM, and the other end is connected to the line connecting the sampling capacitor and the main integration switch. An integrator module, including: An operational amplifier, whose non-inverting input terminal and inverting input terminal are respectively connected to the output terminals of the two branches in the sampling switch module. Completely identical upper and lower branches. Each branch includes: Two integrator input path switches, one end of each of which is connected to the inverting input terminal of the operational amplifier. Two integrator feedback path switches, one end of each of which is connected to the non-inverting input terminal of the operational amplifier, and the other end of each of which is connected to the other end of its corresponding integrator input path switch as a common terminal. Two integration capacitors, one end of each of which is respectively connected to the corresponding common terminal, and the other ends are connected as the capacitor output terminal. A global control module, including: A first control switch, one end of which is connected to the capacitor output terminal of the upper branch, and the other end is connected to the positive-phase output terminal of the operational amplifier. A second control switch, one end of which is connected to the positive-phase output terminal of the operational amplifier, and the other end is connected to the capacitor output terminal of the lower branch. A third control switch, one end of which is connected to the capacitor output terminal of the upper branch, and the other end of which is connected to the inverting output terminal of the operational amplifier; A fourth control switch, one end of which is connected to the inverting output terminal of the operational amplifier, and the other end of which is connected to the capacitor output terminal of the lower branch.

[0030] In this embodiment, the auxiliary sampling switch signal P1a, the auxiliary integration switch signal P2a, the main sampling switch signal P1, the main integration switch signal P2, the global control signal I, the inverted global control signal II, the integrator input path switch signals AI and BI, and the integrator feedback path switch signals AII and BII generated by the clock generation circuit are used to control the switches in the band-pass Δ-Σ modulator. Specifically, the auxiliary sampling switch signal P1a controls the auxiliary sampling switch, the auxiliary integration switch signal P2a controls the auxiliary integration switch, the main sampling switch signal P1 controls the main sampling switch, and the main integration switch signal P2 controls the main integration switch; the integrator input path switch signals AI and BI control the integrator input path switch, and the integrator feedback path switch signals AII and BII control the integrator feedback path switch; the global control signal I controls the first control switch and the fourth control switch, and the inverted global control signal II controls the second control signal and the third control signal.

[0031] The transfer function of the band-pass Δ-Σ modulator in this embodiment is expressed as: ; Wherein, represents the output signal of the band-pass Δ-Σ modulator, represents that the signal passes through delays of clocks, represents the input signal of the band-pass Δ-Σ modulator.

[0032] Specifically, referring to Figure 9 shown, it is the circuit structure diagram of the CV conversion circuit. For the CV conversion circuit proposed by the present invention, considering that the CV conversion circuit needs a feedback resistor to provide a common-mode level, and for the drive loop of the present invention, it is desired that the phase shift of the gyro drive signal is as small as possible during the CV conversion stage. Therefore, the circuit requires a large feedback resistor. If a passive resistor is used, it will occupy a large layout area. Therefore, a switching resistor is used instead of a passive resistor as a technical means. The duty cycle resistor scheme consists of an on-chip passive resistor and a MOS switch in series. The feedback resistor is evenly divided into five parts and controlled by 4 MOS switches. The switching pulse signal is generated by the PLL and applied to the gate of the MOS switch to control the turn-off of the switch. By adjusting the duty cycle of the switching pulse signal, the average current flowing through the switch, that is, the size of the feedback resistor, can be adjusted. If the duty cycle is taken as 0.5%, an equivalent resistance of An equivalent feedback resistor of 200 times. The CV conversion circuit includes: An operational amplifier, whose non-inverting input terminal is connected to one side of the driving mode capacitor in the MEMS gyroscope, and whose inverting input terminal is connected to one side of the detection mode capacitor in the MEMS gyroscope; A first duty cycle resistor module, including a plurality of passive resistors connected in series, and a MOS switch is arranged between every two passive resistors; the idle end of its first passive resistor is connected to the inverting input terminal of the operational amplifier, and the idle end of its last passive resistor is connected to the non-inverting output terminal of the operational amplifier; A second duty cycle resistor module, including a plurality of passive resistors connected in series, and a MOS switch is arranged between every two passive resistors; the idle end of its first passive resistor is connected to the non-inverting input terminal of the operational amplifier, and the idle end of its last passive resistor is connected to the inverting output terminal of the operational amplifier.

[0033] The CV conversion circuit of the present invention realizes the duty cycle resistor based on a plurality of series-connected passive resistors and MOS switches. By adjusting the duty cycle of the duty cycle resistor clock signal, the average current flowing through the MOS switch can be adjusted, that is, the size of the duty cycle resistor can be adjusted; and the duty cycle resistor is controlled by the duty cycle resistor clock signal generated in the clock generation circuit, which ensures the stability and overall phase consistency of the output signal of the CV conversion circuit, avoids phase shift, and improves the stability of the drive loop.

[0034] Specifically, referring to Figure 10 As shown, it is the structure diagram of the phase-locked loop circuit, which specifically includes: A phase-frequency detector, which generates and outputs an UP signal and a DN signal based on the input preset reference signal and the frequency-divided feedback signal; A charge pump, which generates a charge-discharge signal based on the UP signal and the DN signal; A loop filter, which generates and outputs a voltage signal based on the charge-discharge signal; A voltage-controlled oscillator, which generates and outputs a fully differential oscillation signal based on the voltage signal; A dual-to-single circuit, which converts the fully differential oscillation signal into a single-ended square wave signal and outputs it; A programmable frequency divider, which divides the single-ended square wave signal and generates a synchronous clock signal and a frequency-divided feedback signal, and outputs the frequency-divided feedback signal to the phase-frequency detector and the lock detection module; A lock detection module, which generates a lock signal based on the input frequency-divided feedback signal and the reference signal and outputs it to the digital signal processing module to control the control mode of the digital signal processing module.

[0035] Among them, generating a charge-discharge signal based on the UP signal and the DN signal includes: When the UP signal is at a high level and the DN signal is at a low level, the charge pump generates a charging signal to charge the loop filter; When the UP signal is at a low level and the DN signal is at a high level, the charge pump generates a discharging signal to discharge the loop filter.

[0036] Among them, the control method for controlling the digital signal processing module based on the locking signal includes: If the phase difference between the frequency division feedback signal and the preset reference signal is greater than the preset phase value, the locking is not successful, the output locking signal is a low-level signal, and the digital signal processing module adopts open-loop control; If the phase difference between the frequency division feedback signal and the preset reference signal is not greater than the preset phase value, the locking is successful, the output locking signal is a high-level signal, and the digital signal processing module adopts closed-loop control.

[0037] The phase-locked loop circuit of the present invention generates a locking signal output based on the feedback signal input to the locking detection module and the preset reference signal, so as to control the working mode of the digital signal processing module by using the locking signal, improving the adaptive ability of the driving loop; at the same time, the phase-locked loop can track and lock the resonant frequency in real time, ensuring that the driving signal always resonates with the mechanical system, and avoiding energy loss or sensitivity decline caused by frequency mismatch. When the phase-locked loop circuit is not locked, open-loop control is adopted to avoid phase shift caused by unstable closed-loop control, which is convenient for calibration; when the phase-locked loop circuit is locked, closed-loop control is adopted to ensure steady-state accuracy. At the same time, the phase-locked loop circuit outputs a same-phase clock signal to provide a clock signal for the entire loop, effectively improving the robustness of the parasitic resonance mode of the sensor and ensuring the phase stability of the driving signal.

[0038] When the digital signal processing module adopts closed-loop control, the present invention provides three driving modes to achieve high-precision resonance control; Mode 1 realizes 90° phase square wave driving, which is suitable for high-Q MEMS gyroscopes; Mode 2 realizes 90° phase multi-level driving with the help of D flip-flops, which is suitable for low-Q MEMS gyroscopes; Mode 3 realizes 45° phase driving, enabling the gyroscope to work at the -6dB point, adapting to MEMS gyroscopes with a wide Q value range. The present invention provides a phase adjustment method for multiple modes, compensating for the phase difference through an algorithm in the digital domain to ensure phase synchronization, guaranteeing the phase stability of the gyroscope driving signal, and thus ensuring the detection accuracy of the gyroscope. Specifically, the digital processing logics of the three modes include ① Mode 1, including: After multiplying the digital code stream signal by the inverted reference signal FDN with a phase of 180°, perform FIR filtering and PID control to obtain the target signal; Multiply the target signal by the phase reference signal FUP with a phase of 135° to obtain a sine wave signal; Convert the sine wave signal into a square wave signal, and perform equivalent phase shift to obtain an output signal with a phase of 90°. After passing through a digital-to-analog converter, it serves as an adjustable drive voltage signal.

[0039] Specifically, referring to Figure 11 as shown, it is the phase diagram of the drive loop corresponding to Mode 1; referring to Figure 12 as shown, it is the system simulation result diagram of Mode 1; with the Gyro output signal at 0°, the signal passes through the CV conversion circuit. The CV conversion circuit adopts a duty cycle feedback resistor scheme to ensure that the phase shift of the gyro drive signal is as small as possible, so the output signal of the CV conversion circuit is also 0°. According to the transfer function of the band-pass Δ-Σ modulator, it can be obtained that the signal passes through the band-pass Δ-Σ modulator with a phase shift of -180°. For the convenience of understanding, 360° is added here, so the output signal phase of the band-pass Δ-Σ modulator is 180°. Then this signal is multiplied by the FDN with a phase of 180°. The resulting signal at 0° is filtered by FIR and controlled by PID, and then multiplied by the FUP with a phase of 135°. Since the effective signal of the square wave is in the middle, the sine wave is converted into a square wave, generating a 45° phase shift. Therefore, the final output signal phase is 90°. When the gyro is in the resonant working state, there is a 90° phase lag between the input excitation signal and the output response signal. Because when the mechanical vibration amplitude of the drive mode reaches the peak, the Coriolis force response signal of the detection mode forms an orthogonal phase relationship with it in the time domain. Therefore, when the final VC with a phase of 90° is input to the gyro, the gyro Gyro output signal is 0°, achieving a closed loop of the drive system, ensuring that the gyro drive is at the highest peak of the resonant point, and enhancing the robustness of the parasitic resonance mode of the drive loop.

[0040] Based on Figure 12 it can be seen that the output of the gyro Gyro, that is, CVIN, is in phase with the output of the CV conversion circuit, that is, CVOUT, and is in phase with maintaining the same phase. The output drive voltage VC of the digital module has a phase of 90° at point M6. Input this excitation signal to the gyro, and the gyro drive is at the highest peak of the resonant peak. Then exactly the gyro output signal is at 0 phase. At the same time, the excitation signal VC given to the gyro in this mode is a simple 01, so the design of the DAC circuit is greatly simplified, providing great convenience. After normalization calculation, assuming the driving ability under this drive signal VC is , it will be compared with the following Mode 2.

[0041] Referring to Figure 13As shown in the figure, it is the system simulation waveform diagram of the drive circuit corresponding to Mode 1. The circuit is implemented using a typical 130nm CMOS process, where VC is the gyro output signal, VOP1 / VON1 is the output signal of the CV conversion circuit, DRV_OUT is the drive signal fed back from the digital module to the gyro, and Lock is the lock signal. It can be seen that the drive system reaches lock after 4ms. After locking, the amplitude is controlled by the internal PID. When the drive system is stable, the output of the CV conversion circuit is approximately 660mv. At the same time, the drive signal of the corresponding digital module and the output of the CV conversion circuit achieve a 90° phase shift, ensuring that the gyro drive is at the highest point of the resonance peak, greatly reducing the phase error and improving the stability of the system.

[0042] ② Mode 2, including: Multiply the digital code stream signal by the inverted reference signal FDN with a phase of 180°, perform FIR filtering and PID control to obtain the target signal; Multiply the target signal by the phase reference signal FUP with a phase of 90° to obtain a sine wave signal; Convert the sine wave signal into a square wave signal, and use a D flip-flop controlled by the synchronous clock signal to shift the phase of the square wave signal by 45° to obtain an output signal with a phase of 90°. After passing through the digital-to-analog converter, an adjustable drive voltage signal is generated.

[0043] Refer to Figure 14 As shown in the figure, it is the phase diagram of the drive circuit corresponding to Mode 2; Refer to Figure 15 As shown in the figure, it is the system simulation result diagram of Mode 2; The difference between Mode 2 and Mode 1 is that the FUP signal is changed to 90°. Therefore, after multiplying the signal passing through the PID by FUP, the phase is 45°. In order to make the signal have a 90° phase shift, add a D flip-flop controlled by, thus generating a 45° phase shift. Therefore, the output signal has a 90° phase shift. After passing through the Gyro gyro, another 90° phase shift is generated, and finally the output signal has a 0° phase shift, completing the system closed-loop to ensure that the gyro drive is at the highest point of the resonance point.

[0044] From Figure 15 It can be seen that the output of the gyro Gyro, that is, CVIN, is in phase with the output of the CV conversion circuit, that is, CVOUT, and is in phase with Keep in phase. The output drive voltage VC of the digital module has a phase of 90° at point M3. Input this excitation signal to the gyro, and the gyro drive is at the highest point of the resonance peak. Then exactly the output signal of the gyro is at 0 phase. In this mode, the excitation signal VC given to the gyro is 10 - 1. Therefore, compared with Mode 1, the DAC requires a more complex circuit. After normalization calculation, compared with Mode 1, the driving ability under this drive signal VC is 1. The advantage of Mode 2 is that it can drive the gyro with a weaker driving force.

[0045] ③ Mode 3, including: After multiplying the digital bitstream signal by the inverted reference signal FDN with a phase of 180°, perform FIR filtering and PID control to obtain the target signal; Multiply the target signal by the phase reference signal FUP with a phase of 90° to obtain a sine wave signal; Convert the sine wave signal into a square wave signal to obtain an output signal with a phase of 45°. After passing through a digital-to-analog converter, generate an adjustable drive voltage signal.

[0046] Refer to Figure 16 As shown, it is the drive loop phase diagram corresponding to Mode 3; the rest is the same as Mode 2. The only difference is that the D flip-flop is not used. Therefore, the phase of the digital module output signal VC is 45°. To ensure the accuracy of the loop phase, at the same time, the band-pass Δ-Σ modulator clock generation circuit ensures that the point of the modulator sampling signal is at 0 phase. According to the system loop calculation, the signal passes through the Gyro gyro to generate a 45° phase shift. Therefore, the gyro is not at the highest point of the resonance peak, but at the -6dB point 45° off. In this mode, the gyro drive is at a position 45° off the highest point of the resonance peak, which is compatible with gyros of different q values and can drive the gyro with a weaker driving force. Similarly, the driving ability under this drive signal VC is 1.

[0047] The drive mode of the MEMS gyro usually needs to work near the resonance frequency of the mechanical structure to achieve the maximum vibration amplitude and sensitivity. However, the resonance frequency will drift due to temperature changes, mechanical stress, or aging. The PLL can track and lock the resonance frequency in real time to ensure that the drive signal always resonates with the mechanical system, avoiding energy loss or sensitivity degradation caused by frequency mismatch. This drive loop generates the system clock frequency by using the PLL to lock, and at the same time compensates for the phase difference in the digital domain through an algorithm to ensure phase synchronization, and there are multiple modes to adjust the phase. Compared with the traditional clock generation circuit, it simplifies the circuit structure and ensures the phase stability of the gyro drive signal.

[0048] In the embodiment of the present invention, the signal phase control in the MEMS drive loop includes: the CV conversion circuit due to the large feedback resistor In the presence of [[ID=]], the signal has almost no phase shift. The band-pass Δ-Σ modulator generates an accurate 180° phase shift. The phase control of the digital module can precisely control the phase shift of the signal by configuring FUD and FDN. Therefore, the phase of the overall drive loop is precisely controllable, and the drive loop can be made to operate in different modes by configuring the digital module. For example, in Mode 1, the excitation signal VC for the gyro is simply 01 in this mode, which greatly simplifies the design of the DAC circuit and provides great convenience. For example, in Mode 3, the gyro is driven at a position 45° off the peak of the resonance peak, that is, at the -6 dB position, which improves the universality and expandability of this drive loop. The amplitude control of the drive signal is not completed by a single system, but is controlled by a lock signal. When the lock signal is at a low level, the digital module uses open-loop control, skips the PID control, and directly processes the signal, which is convenient for system calibration. When the PLL successfully locks and the lock signal is at a high level, the system is then in closed-loop control. The output signal is adjusted by the PID algorithm and finally generates a VC control signal, which improves the stability during the startup stage of the gyro and the long-term stability of the system.

[0049] In this embodiment, the MEMS gyro closed-loop drive loop further includes a hysteresis comparator. Its positive input terminal is connected to the positive output terminal of the CV conversion circuit, its negative input terminal is connected to the negative output terminal of the CV conversion circuit, and its output terminal is connected to the phase-frequency detector of the phase-locked loop, and is used for: when the in-phase input terminal is greater than the anti-phase input terminal, the hysteresis comparator outputs a high level; when the in-phase input terminal is less than the anti-phase input terminal, the hysteresis comparator outputs a low level. Overall, the hysteresis comparator locks and tracks the output of the CV conversion circuit and converts it into a co-directional square wave and inputs it to the phase-locked loop; the setting of the hysteresis voltage is used to resist noise when switching states.

[0050] In the embodiment of the present invention, the drive loop of the overall MEMS gyro is a closed-loop system. Refer to Figure 17 As shown, it is a detailed structure diagram of the MEMS gyro closed-loop drive loop, which includes a CV conversion circuit, a comparator (CMP), a phase-locked loop (PLL), a band-pass Δ-Σ modulator, and a digital signal processing part. Gyro is the MEMS gyro.

[0051] ①The CV conversion circuit converts the internal capacitance displacement of the MEMS gyro into a voltage change. The CV conversion circuit adopts a duty cycle feedback resistor scheme to ensure that the phase shift of the gyro drive signal is as small as possible. At the same time, the duty cycle resistance control signal in the CV conversion circuit comes from the non-overlapping signal generated by the system clock passing through the clock module, ensuring the stability and phase consistency of the system signal.

[0052] ② The CMP is a hysteresis comparator. After comparing the output signal of the CV conversion circuit, it is sent to the PLL. The magnitude of the hysteresis voltage is 3 mV. The magnitude of the hysteresis voltage should be set larger than the noise floor of the output of the CV conversion circuit to avoid noise phase error. At the same time, the magnitude of the hysteresis voltage should not be set too large to cause excessive delay in the system.

[0053] ③ The phase-locked loop (PLL) is a charge pump phase-locked loop with good phase noise performance, strong robustness, and high frequency accuracy. It adopts a fully analog, narrowband, programmable integer frequency division, and charge pump form to generate the clock for the gyro closed-loop drive circuit and outputs a co-phase clock signal to provide clocks for the band-pass Δ-Σ modulator, the phase-locked loop, and the digital module. At the same time, in the digital domain, the phase difference is compensated through an algorithm to ensure phase synchronization, effectively improving the robustness of the parasitic resonance mode of the sensor, ensuring the phase stability of the drive signal, and then significantly improving the long-term stability, environmental adaptability, and signal-to-noise ratio of the gyroscope.

[0054] ④ The band-pass Δ-Σ modulator has a quadruple-frequency double-delay structure, and its center frequency is consistent with the gyro resonance frequency. It is responsible for processing the output signal of the CV conversion circuit into a 1-bit bitstream for digital processing. The clock generation circuit of the band-pass Δ-Σ modulator generates a series of precise non-overlapping clocks through the configuration of logic gates, D flip-flops, and delays, which not only ensures that the sampling of the input signal by the band-pass Δ-Σ modulator is at the 0° phase position, but also ensures the high effective number of bits and low noise of the band-pass Δ-Σ modulator itself. At the same time, by providing a clock for the duty cycle resistor, the synchronous cooperation between the CV conversion circuit and the band-pass Δ-Σ modulator is achieved, improving the long-term phase stability of the drive circuit.

[0055] ⑤ The digital processing part uses signal modulation, FIR filtering, PID control algorithm, and demodulation to process the gyro drive signal, and finally generates an adjustable drive voltage VC to feedback to the gyro, ensuring that the gyro drive is in the resonance mode while ensuring the stability and gain of the loop.

[0056] Specifically, the charge pump phase-locked loop of this embodiment mainly consists of a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a dual-to-single circuit, a 5-bit programmable frequency divider, and a lock detection module. Its working principle includes: When the input reference signal arrives, the phase-frequency detector compares the reference signal with the feedback signal output by the frequency divider to perform phase and frequency comparison and generate a path of signal and a path of signal. The signal and the signal reflect the comparison situation of phase and frequency to control the charge and discharge of the charge pump; when the signal is at a high level and When the signal is at a low level, the charge pump charges the loop filter; while when the signal is at a low level and the signal is at a high level, the charge pump discharges from the loop filter.

[0057] When the charge pump charges and discharges the loop filter, the loop filter outputs a voltage signal to the voltage-controlled oscillator. At this time, the voltage-controlled oscillator generates a fully differential oscillation signal whose frequency is controlled by the input voltage The double-to-single circuit, as a buffer stage, converts the fully differential voltage-controlled oscillator output signal into a single-ended square wave signal and inputs it to the programmable frequency divider; The programmable frequency divider is controlled by the trimming bits for the division multiple. After dividing the output signal of the double-to-single circuit, it is fed back to the input terminals of the phase-frequency detector and the lock detection module. At the same time, the programmable frequency divider divides out each required clock signal 、 、 、 and and sends them to the drive circuit.

[0058] The lock detection module compares the reference signal with the feedback signal of the frequency divider output for lock detection. Before successful locking, the lock detection module outputs a low-level control signal, while after successful locking, the lock detection module outputs a high-level control signal, and the lock signal will be input to the digital module; When the lock signal is at a low level, the digital module adopts open-loop control, skips the PID control, and directly processes the signal for system calibration. When the PLL is successfully locked and the lock signal is at a high level, the system is in closed-loop control at this time, and the output signal is adjusted by the PID algorithm to finally generate a VC control signal.

[0059] It is used to provide clocks for the digital module and the band-pass Δ-Σ modulator. The non-overlapping clocks PP generated by the internal clock circuit of the band-pass Δ-Σ modulator will provide clocks for the duty cycle resistor.

[0060] In the embodiment of the present invention, multiple groups of non-overlapping clock signals input to the band-pass Δ-Σ modulator are generated by the signal locked by the phase-locked loop input to the clock generation module. After processing, clocks are generated for the band-pass Δ-Σ modulator and the duty cycle resistor. At the same time the clock also provides clocks for the phase-locked loop and the digital module. With this clock configuration, it can be ensured that the sampling of the input signal by the band-pass Δ-Σ modulator remains at the 0° phase, ensuring the phase stability of the overall drive circuit.

[0061] Specifically, signals such as P1, P2, P1a, and P2a are used to control the sampling switches in the resonator circuit, where P1a controls the frontmost sampling switch, while AI, BI, AII, and BII control the integrator path connection switches, and I and II respectively represent the sign flip signals of the integrator. Delay1, Delay2, and Delay3 respectively represent time delays of Δt, 2Δt, and 3Δt. The input After being processed by the clock circuit, non-overlapping clock signals P1, P2, P1a, P2a and their inverted signals are generated. To ensure correct timing, other clock signals are divided by D flip-flops from signals. Signals I and II and their inverted signals are generated by dividing the signal by four, and then through the same time delay and logical operations. AI, BI, AII, BII and their inverted signals are obtained by dividing the CLK signal by two, and then through the same time delay and logical operations with signals I and II. PP is obtained by inverting the non-overlapping part of signals I and II, and PP provides a clock for the duty cycle resistor.

[0062] Refer to Figure 18 As shown, it is the waveform diagram of the MEMS drive loop clock generation circuit. The falling edge of P1a is the position of the signal sampling point, ensuring that the phase of the sampling signal is 0°. It should be noted that P1a and P2a are turned off earlier than P1 and P2 to minimize the influence of charge injection and clock feedthrough in the sampling circuit. At the same time, clocks I and II are turned off later than AI, BI, AII, and BII, thereby improving the stability of the integration loop. Before the rising edge of P2, the switches in the integration loop have been switched in advance. The PP signal is generated from the non-overlapping part of I and II.

[0063] This embodiment is based on a quadruple-frequency synchronous clock. Through a uniquely designed zero-phase-error synchronous non-overlapping clock circuit and a synchronous multi-phase adjustable variable-frequency clock circuit, the problem of phase error is solved. At the same time, this design can achieve an additional gain adjustment function for the resonant loop in addition to PI control through flexible phase adjustment, increasing the flexibility of the system. By using a PLL to lock the drive frequency to generate a system synchronous clock, and at the same time compensating for the phase difference through a unique multi-phase clock algorithm in the digital domain to ensure phase synchronization, the long-term stability of the phase of the gyro drive signal is guaranteed. The gyro drive loop clock is generated by PLL locking, enhancing the stability and followability of the system clock.

[0064] In the MEMS gyro closed-loop drive circuit of the present invention, the synchronous clock signal output by the phase-locked loop circuit is used as the reference clock signal of the drive circuit. The clock generation circuit performs gate logic operations, frequency division, and adds hierarchical delays to the synchronous clock signal, converting the single synchronous clock signal into multiple groups of cooperative non-overlapping clock signals for controlling the band-pass Δ-Σ modulator and the CV conversion circuit. At the same time, through the phase locking of the synchronous clock phase, the main sampling switch signal is synchronized with the falling edge of the synchronous clock phase, ensuring that the sampling moment is precisely located at the signal zero-crossing point, ensuring that the sampling phase is 0°, eliminating sampling jitter, and improving the signal-to-noise ratio, so as to ensure that the digital code stream signal output by the band-pass Δ-Σ modulator has a sampling phase maintained at 0°, making the sampling phase of the band-pass Δ-Σ modulator strictly synchronized with the mechanical vibration of the MEMS gyro, eliminating the phase shift in the drive circuit, thereby improving the stability of the drive circuit and ensuring the detection accuracy of the MEMS gyro. Moreover, in the present invention, through hierarchical delays, P1a and P2a are turned off earlier than P1 and P2, minimizing the influence of charge injection and clock feedthrough of the sampling circuit as much as possible; the clocks I and II are turned off later than AI, BI, AII, and BII, thereby improving the stability of the integration circuit.

[0065] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program code.

[0066] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0067] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means implement the functions in the process Figure 1One or more processes and / or blocks Figure 1 The functions specified in one or more blocks.

[0068] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 One or more processes and / or blocks Figure 1 The steps of the functions specified in one or more blocks.

[0069] Obviously, the above embodiments are only examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A closed-loop drive circuit for a MEMS gyroscope, characterized in that, Including: A CV conversion circuit that converts the capacitance displacement inside the MEMS gyro into a voltage change signal for output; A phase-locked loop circuit that generates a synchronous clock signal based on the voltage change signal and a preset reference signal; A clock generation circuit that generates multiple groups of non-overlapping clock signals based on the synchronous clock signal: Using the third delay signal to delay the first half cycle and the second half cycle of the synchronous clock signal respectively to obtain the auxiliary sampling switch signal P1a and the auxiliary integration switch signal P2a whose falling edges are synchronized with the synchronous clock signal; Using the first delay signal to delay P1a and P2a respectively to obtain the main sampling switch signal P1 and the main integration switch signal P2; Using D flip-flops to process the synchronous clock signal to obtain frequency division signals A0, B0, I0 and II0; After using the second delay signal to delay I0 and II0 respectively and then using the first delay signal for delay, obtaining the global control signal I and the inverted global control signal II; After using the second delay signal to delay A0 and B0 respectively and then passing them through AND gates with I and II respectively, generating the integrator input path switch signals AI, BI and the integrator feedback path switch signals AII, BII; Taking the inverse of the non-overlapping part of I and II to obtain the duty cycle resistance clock signal PP to control the duty cycle resistance in the CV conversion circuit; Among them, the delay time ratios of the first delay signal, the second delay signal and the third delay signal are 1:2:3; A band-pass Δ-Σ modulator composed of two series-connected SaloII-type resonators that outputs a digital bit stream signal with the sampling phase maintained at 0° based on the control of multiple groups of non-overlapping clock signals; A digital signal processing module that processes the digital bit stream signal to generate an adjustable drive voltage signal to drive the MEMS gyro into the resonant mode.

2. The MEMS gyro closed-loop drive circuit according to claim 1, wherein The CV conversion circuit includes: An operational amplifier whose non-inverting input terminal is connected to one side of the drive-mode capacitor in the MEMS gyro, and whose inverting input terminal is connected to one side of the sense-mode capacitor in the MEMS gyro; The first duty cycle resistance module includes multiple passive resistors connected in series, and a MOS switch is arranged between every two passive resistors; the idle end of its first passive resistor is connected to the inverting input terminal of the operational amplifier, and the idle end of its last passive resistor is connected to the non-inverting output terminal of the operational amplifier; The second duty cycle resistance module includes multiple passive resistors connected in series, and a MOS switch is arranged between every two passive resistors; the idle end of its first passive resistor is connected to the non-inverting input terminal of the operational amplifier, and the idle end of its last passive resistor is connected to the inverting output terminal of the operational amplifier.

3. The MEMS gyro closed-loop drive circuit according to claim 1, characterized in that The band-pass Δ-Σ modulator is a quadruple-frequency double-delay structure, and its transfer function is expressed as: ； Among them, represents the output signal of the bandpass Δ-Σ modulator, represents that the signal passes through delays of represents the input signal of the bandpass Δ-Σ modulator.

4. The MEMS gyro closed-loop drive circuit according to claim 1, wherein The phase-locked loop circuit includes: A phase-frequency detector that generates UP signals and DN signals for output based on the input preset reference signal and the frequency division feedback signal; A charge pump that generates a charge and discharge signal based on the UP signal and the DN signal; A loop filter that generates a voltage signal for output based on the charge and discharge signal; A voltage-controlled oscillator that generates a fully differential oscillation signal for output based on the voltage signal; A differential-to-single-ended circuit that converts the fully differential oscillation signal into a single-ended square wave signal for output; A programmable frequency divider divides a single-ended square wave signal and generates a synchronous clock signal and a frequency division feedback signal, and outputs the frequency division feedback signal to a phase detector / frequency discriminator and a lock detection module; A lock detection module generates a lock signal based on the input frequency division feedback signal and a reference signal and outputs it to a digital signal processing module to control the control mode of the digital signal processing module.

5. The MEMS gyro closed-loop drive circuit according to claim 4, wherein Based on the UP signal and the DN signal, a charge / discharge signal is generated, including: When the UP signal is at a high level and the DN signal is at a low level, the charge pump generates a charging signal to charge the loop filter; When the UP signal is at a low level and the DN signal is at a high level, the charge pump generates a discharging signal to discharge the loop filter.

6. The MEMS gyro closed-loop drive circuit according to claim 4, wherein Controlling the control mode of the digital signal processing module based on the lock signal, including: If the phase difference between the frequency division feedback signal and a preset reference signal is greater than a preset phase value, the lock is not successful, the output lock signal is a low level signal, and the digital signal processing module adopts open-loop control; If the phase difference between the frequency division feedback signal and a preset reference signal is not greater than a preset phase value, the lock is successful, the output lock signal is a high level signal, and the digital signal processing module adopts closed-loop control.

7. The MEMS gyro closed-loop drive circuit according to claim 6, wherein The digital signal processing module adopts closed-loop control, including: Multiplying the digital code stream signal by an inverted reference signal FDN with a phase of 180°, performing FIR filtering and PID control to obtain a target signal; Multiplying the target signal by a phase reference signal FUP with a phase of 135° to obtain a sine wave signal; Converting the sine wave signal into a square wave signal and performing an equivalent phase shift to obtain an output signal with a phase of 90°, and after passing through a digital-to-analog converter, it is used as an adjustable drive voltage signal.

8. The MEMS gyro closed-loop drive circuit according to claim 6, wherein The digital signal processing module adopts closed-loop control, including: Multiplying the digital code stream signal by an inverted reference signal FDN with a phase of 180°, performing FIR filtering and PID control to obtain a target signal; Multiplying the target signal by a phase reference signal FUP with a phase of 90° to obtain a sine wave signal; Converting the sine wave signal into a square wave signal, using a D flip-flop controlled by the synchronous clock signal to shift the phase of the square wave signal by 45° to obtain an output signal with a phase of 90°, and after passing through a digital-to-analog converter, an adjustable drive voltage signal is generated.

9. The MEMS gyro closed-loop drive circuit according to claim 6, characterized in that The digital signal processing module adopts closed-loop control, including: Multiplying the digital code stream signal by an inverted reference signal FDN with a phase of 180°, performing FIR filtering and PID control to obtain a target signal; Multiplying the target signal by a phase reference signal FUP with a phase of 90° to obtain a sine wave signal; Converting the sine wave signal into a square wave signal to obtain an output signal with a phase of 45°, and after passing through a digital-to-analog converter, an adjustable drive voltage signal is generated.

10. The MEMS gyro closed-loop drive circuit according to claim 4, characterized in that, It further includes a hysteresis comparator, whose positive input terminal is connected to the output terminal of the CV conversion circuit, whose negative input terminal is connected to a preset reference signal, and whose output terminal is connected to the phase detector / frequency discriminator of the phase-locked loop, and is used for: When the voltage change signal at the positive input terminal is greater than the preset reference signal at the negative input terminal, the hysteresis comparator outputs a high level as the preset reference signal input to the phase detector / frequency discriminator; When the voltage change signal at the positive input terminal is not greater than the preset reference signal at the negative input terminal, the hysteresis comparator outputs a low level, which serves as the preset reference signal for the input phase discriminator and frequency discriminator.

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