Method for improving security of multi-tenant memory module

Abstract

The invention relates to a method for improving security of a multi-tenant memory module. An example system includes a host computing device configured to host a first tenant and a second tenant; a non-volatile memory configured to store data of the first tenant and data of the second tenant; and a memory controller including a cache memory of a volatile memory, the cache memory is configured to store a first encryption key associated with a first tenant for accessing data stored at the non-volatile memory and a second encryption key associated with a second tenant for accessing data stored at the non-volatile memory. The memory controller further includes a processor having encryption logic configured to detect an attack of a first tenant on a portion of the cache memory that stores a second encryption key, and erase the stored second encryption key from the cache memory in response to detecting the attack.

Description

Technical Field

[0001] This application relates to methods, apparatuses, and systems for enhancing the security of multi-tenant memory modules. Background Art

[0002] Emerging memory architectures are designed to handle a range of memory access requests and may include memories with different characteristics. For example, memories may include dynamic random access memory (DRAM) and phase change memory (PCM). Non-volatile memories can be highly non-uniform. For example, some NAND flash memories (e.g., based on page type) can read or write faster than other NAND flash memories, where the latency changes as they wear out, or have different levels of cells among different NAND flash memories (e.g., multi-level cells (MLC)). Emerging memory architectures can also utilize non-volatile dual in-line memory modules (NVDIMMs), such as NVDIMM-P or NVDIMM-F. NVDIMMs typically include both non-volatile and volatile memory devices. In some applications, memory can be allocated for multiple tenants or users on a particular NVDIMM to more efficiently use the memory, such as in data center applications. However, there may be situations where malicious tenants or users can attack adjacent memory portions allocated to different tenants. Summary of the Invention

[0003] In one aspect, this application provides a method that includes: writing a first encryption key associated with a first tenant of a non-volatile memory device coupled to a volatile memory device to a cache memory coupled to the volatile memory device; writing a second encryption key associated with a second tenant of a non-volatile memory device coupled to the volatile memory device to the cache memory coupled to the volatile memory device; and in response to detecting an attack by the first tenant on a portion of the cache memory storing the second encryption key, erasing the stored second encryption key from the cache memory.

[0004] In another aspect, this application provides an apparatus that includes: a cache memory of a volatile memory configured to store a first encryption key associated with a first tenant for accessing a non-volatile memory and a second encryption key associated with a second tenant for accessing the non-volatile memory; and a processor having encryption logic configured to detect an attack by the first tenant on a portion of the cache memory storing the second encryption key and, in response to detecting the attack, erase the stored second encryption key from the cache memory.

[0005] In another aspect, the present application provides a system comprising: a host computing device configured to host a first tenant and a second tenant; a non-volatile memory configured to store data of the first tenant and data of the second tenant; and a memory controller comprising: a cache memory of the volatile memory configured to store a first encryption key associated with the first tenant for accessing data stored at the non-volatile memory and a second encryption key associated with the second tenant for accessing data stored at the non-volatile memory; and a processor having encryption logic configured to detect an attack by the first tenant on a portion of the cache memory storing the second encryption key, and to erase the stored second encryption key from the cache memory in response to detecting the attack. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic illustration of a memory system interacting according to examples described herein.

[0007] Figure 2 is a schematic illustration of a memory system interacting according to examples described herein.

[0008] Figure 3 is a schematic illustration of a method according to examples described herein. DETAILED DESCRIPTION

[0009] Cryptographic methods may use block ciphers to provide security for data, for example, using cryptographic keys to authenticate data. For example, a cryptographic key may convert data from plaintext to ciphertext when encrypting; and convert data from ciphertext to plaintext when decrypting. Block ciphers provide block transitions of information bits to encrypt data (or conversely, to decrypt data). For example, Advanced Encryption Standard (AES) or quantum cryptography are types of block ciphers. In addition, block ciphers may operate in different modes within a cryptographic device / method, for example, as a "stream cipher" using a counter. For example, a counter may be used to change the underlying cryptographic key used by a block cipher so that the cryptographic key changes over time; in turn, changing the basis for the data in the encrypted data stream. For example, Galois / Counter Mode (GCM) is a type of stream cipher.

[0010] It can be complex and cumbersome to ensure the security of NVDIMM devices. In a multi-tenant user scenario, this task may become even more difficult. For example, in some data centers, multiple users (or tenants) can access a single computing device to store data on non-volatile memory devices. To prevent accidental or unauthorized access to a specific area of the memory in the non-volatile memory device, a key can be generated for a specific memory access request of a specific user to access data on the non-volatile memory device or at least a specific area of the memory of the non-volatile memory device. Thus, the key of a specific user can be used only by that user (e.g., tenant) to access the data stored on the non-volatile memory device.

[0011] In some instances, during operation, the key can be stored in volatile memory (e.g., cache memory). Volatile memory can be vulnerable to certain types of attacks from malicious actors, including the rowhammer attack. For example, in a multi-tenant application, physically adjacent memory portions can be allocated to two tenants. In this instance, a malicious tenant may be able to attack the volatile memory of an adjacent tenant.

[0012] Examples of the systems and methods described herein allow for the erasure of encryption keys used for data access to non-volatile memory devices in a multi-tenant application when an attack by a malicious actor is detected. A computing device that regularly accesses the memory device can perform this operation through a memory controller. For example, a host computing device can generate a memory access request that is routed through a memory controller that controls access to each coupled memory device, which can be a non-volatile or volatile memory device. Generally, a memory access request can be or include a command and an address, such as a memory command and a memory address. In various embodiments, the memory access request can be or include a command and an address for a read operation, a write operation, an activation operation, or a refresh operation at a coupled non-volatile memory device. Generally, the received command and address can facilitate the execution of a memory access operation at the coupled memory device, such as a read operation, a write operation, an activation operation, and / or a refresh operation of the coupled memory device.

[0013] Using the systems and methods described herein, a memory controller can generate a corresponding encryption key for each tenant, and the encryption key can be used to access data stored in one or more non-volatile memory devices. For example, the encryption key can be written to a shared cache coupled to the volatile memory device or as a shared cache of the volatile memory device. To provide security for data stored on the non-volatile memory device, the memory controller can store the encryption key of each tenant in the local cache of the memory controller. For example, the local cache at the memory controller can be a volatile memory device. In an example, because the key is stored in the shared cache, a malicious actor may attack a portion of the shared cache of an adjacent tenant in an attempt to steal the key. Therefore, to mitigate these types of attacks, the encryption logic can include circuitry to detect a malicious attack and circumvent the attack (such as by blocking memory access of a malicious tenant, flushing the victim row, and / or erasing the encryption key from the volatile memory / shared cache).

[0014] Accordingly, in the absence of the encryption key, the data stored on the non-volatile memory device of the attacked tenant cannot be accessed. Thus, advantageously, the example systems and methods described herein provide security for data stored on non-volatile memory devices accessed by a memory controller. In some examples, the non-volatile memory device can be a NAND memory implemented as a NVDIMM that interacts with the memory controller according to a NVDIMM protocol (such as NVDIMM-P or NVDIMM-F).

[0015] Generally, a memory controller provides access to data stored on a non-volatile memory device. In the examples described herein, the memory controller may use a respective encryption key for each tenant to provide authenticated access to data stored on the non-volatile memory device. In some embodiments, an encryption key may be generated specifically for the data to be accessed stored on the non-volatile memory device. For example, the memory controller may generate an encryption key for data associated with a received memory access request. Based on the memory access request, the generated encryption key may be used, for example, to access in an authenticated manner data read or written by a host computing device to various non-volatile memory devices. For example, the provided key may be encrypted according to an AES cipher or a quantum cipher, for example, encrypted as a cryptographic key. The authentication logic of the memory controller may utilize a pseudo-random value from a pseudo-random value generator and the provided key (e.g., a disk encryption key (DEK)) to generate an encryption key, such as a cryptographic key. In an example implementation of the AES cipher, the pseudo-random value may be used as the initialization vector (IV) of the AES cipher. In an alternative embodiment, a quantum cipher may be used. As described herein, for simplicity, the generated encryption key may be referred to as the key for one or more non-volatile memory devices. Advantageously, the key may provide security for the specific data accessed by the memory controller to the non-volatile memory device. For example, the key may be used to encrypt or decrypt the data being accessed (e.g., read or written) (e.g., as plaintext or ciphertext).

[0016] Figure 1 FIG. 4 is a schematic illustration of a system 100 arranged according to the examples described herein. System 100 includes a computing device 102 that includes a memory controller 104 that may control one or more non-volatile memory devices 108. Memory controller 104 includes a processor that may be used (e.g., with reference to Figure 2An encryption logic 106 implemented by way of its example, and a cache memory 110. The computing device 102 can be configured to serve data access requests from two tenants 120 and 122 to store corresponding data. It should be understood that including two tenants is exemplary, and additional tenants can be included without departing from the scope of the present disclosure. The cache memory 110 can be implemented using volatile memory devices. The memory controller 104 is coupled to the non-volatile memory device 108 via a corresponding memory bus 112. In operation, the encryption logic 106 can generate a key 116 for tenant 120 and a key 118 for tenant 122, and the keys can each be encrypted and can be used to access data on the non-volatile memory device 108. For example, the key 116 can be used by the memory controller 104 to authenticate tenant 120's access to the non-volatile memory device 108, and the key 118 can be used by the memory controller 104 to authenticate tenant 122's access to the non-volatile memory device 108. The encryption logic 106 can store the key 116 and the key 118 in the cache memory 110.

[0017] Because the encryption keys 116 and 118 are stored in the shared cache memory 110, there may be a situation where a malicious tenant 120 or 122 may attempt to attack the volatile nature of the cache memory 110 to retrieve the key 116 or 118 of another tenant 120 or 122 (such as via a row hammer type of attack). Therefore, the encryption logic 106 can include circuitry for detecting these malicious attacks and circumventing the attacks (such as by blocking the memory access of the malicious tenant 120 or 122, refreshing the victim row, and / or erasing the target key 116 or 118 from the cache memory 110). Erasing the target key 116 or 118 can prevent it from falling into the wrong hands, and thus prevent unauthorized access to the encrypted data stored at the non-volatile memory device 108.

[0018] The non-volatile memory device 108 may store data retrieved and / or accessed by the computing devices 102 on behalf of the tenants 120 and 122. As some examples, the computing devices 102 may be servers located in a data center or laptops located in a data center, and the computing devices 102 may process data sets (e.g., image or content data sets) for use by one or more neural networks hosted on the computing devices 102. The data sets for each of the tenants 120 and 122 may be stored in one or more of the non-volatile memory devices 108 (e.g., one or both of the data sets may be allocated among the non-volatile memory devices 108). In some embodiments, one or both of the data sets may contain personally identifiable information (PII) such that the operator of the server may desire the data stored on the non-volatile memory device 108 to be secure. For example, if a malicious tenant 120 or 122 attempts to access the keys 116 or 118 in an attempt to obtain the PII data stored on the non-volatile memory device 108 for another tenant 120 or 122, then when the memory controller 104 detects an attack on the cache 110, the keys 116 or 118 used to access the target data stored on the non-volatile memory device 108 will be erased from the cache 110 of the memory controller 104; thereby making it difficult for the malicious tenant 120 or 122 to access the data stored on the non-volatile memory device 108. Although PII has been provided as an example of data that may require security, any data, including proprietary data, sensitive data, or confidential data, may be protected in accordance with the examples described herein.

[0019] The memory controller 104 may be a NVDIMM memory controller implemented in the computing device 102. For example, the computing device 102 may be a host computing device coupled to the memory controller 104 via a host bus (not depicted). In an instance of a NVDIMM memory controller, the host bus may operate according to a NVDIMM protocol, such as NVDIMM-F, NVDIMM-N, NVDIMM-P, or NVDIMM-X. In such an implementation, the non-volatile memory device 108 may be a NAND memory device or a 3D XPoint memory device. Thus, the non-volatile memory device 108 may also operate as a persistent storage device for a cache memory, which may be a volatile memory device, and / or as a persistent storage device for any volatile memory on the memory controller 104 or the computing device 102. Generally, compared to non-volatile memory, volatile memory may have some improved characteristics (e.g., volatile memory may be faster). The non-volatile memory device 108 may also include one or more types of memory, including but not limited to: DRAM, SRAM, three-level cell (TLC) NAND, single-level cell (SLC) NAND, SSD, or 3D XPoint memory device. Data stored in the non-volatile memory device 108 or data to be accessed from the non-volatile memory device 108 may be transferred from the memory controller 104 via the memory bus 112. For example, the memory bus 112 may be a PCIe bus.

[0020] The computing devices described herein (such as, Figure 1 the computing device 102 shown in Figure 1 ) may generally be implemented using any computing device 102 device that requires computing capabilities that use non-volatile memory devices. For example, the computing device 102 may be implemented using a smart phone, a smart watch, a computer (e.g., a server, a laptop computer, a tablet computer, a desktop computer), a wearable computing device, a vehicle, an appliance, or an Internet of Things (IoT) computing device. Although

[0021] Figure 2 not explicitly shown in Figure 2In which, components with similar names may have similar operations or functions as described with respect to Figure 1 For example, the encryption logic 208 may operate as described for the encryption logic 106 with respect to Figure 1 In some instances, the non-volatile memory device 210 may operate as described for the non-volatile memory device 108 with respect to Figure 1 The memory system 200 includes a host computing device 204 that is coupled to a memory controller 202 that can control one or more non-volatile memory devices 210. In some instances, the memory controller 202 is embodied in the host computing device 204 or is an element of the host computing device 204. In such cases, the host computing device 204 can be a SOC, CPU, GPU, FPGA, etc., and the memory controller 202 can be the logic, circuitry, or component of this SOC, CPU, GPU, or FPGA. In some instances, the host computing device 204 is a single physical device and the memory controller 202 is a separate physical device (e.g., each physical device can be a die in a chiplet system). In some cases, the memory controller 202 and the non-volatile memory device 210 are elements of a module (e.g., DIMM, card, or drive), and the host computing device 204 is a separate processor.

[0022] The memory controller 202 may include a host interface 212 that can be coupled to a host bus 220 for connection to the host computing device 204. The host interface 212 is coupled to a processor 206 or processing resource, which can be a SOC, ASIC, FPGA, etc., and can be separate from or an element of the host computing device 204 (as described above). The processor 206 may include encryption logic 208. The host interface 212 and the processor 206 are also coupled to a cache memory 214 via, for example, an internal memory controller bus. The processor 206 is coupled to the non-volatile memory device 210 via a memory interface 216 and a corresponding memory bus 218. The memory interface 216 is also coupled to the cache memory 214 via, for example, an internal memory controller bus. The memory controller 202 further includes a pseudo-random number generator (PRNG) 222 that generates a pseudo-random value 226 and provides the pseudo-random value 226 to the encryption logic 208.

[0023] In an example implementation, processor 206 may include any type of microprocessor, central processing unit (CPU), ASIC, digital signal processor (DSP) implemented as part of a field programmable gate array (FPGA), system on a chip (SoC), or other hardware. For example, processor 206 may be implemented using discrete components such as application specific integrated circuits (ASICs) or other circuitry, or the components may reflect functionality provided by circuitry within memory controller 202, which may not have a discrete physical form separate from other portions of memory controller 202. Portions of processor 206 may be implemented by a combination of discrete components. For example, encryption logic 208 may be implemented as an ASIC, while other processor functionality (e.g., memory access request processing / queuing) may be implemented as an FPGA having various stages in a specified configuration. Although shown as a component within memory controller 202 in Figure 2 processor 206 may be located outside of memory controller 202, or may have several components located within memory controller 202 and several components located outside of memory controller 202.

[0024] The non-volatile memory device 210 can store and provide information (e.g., data and instructions) for each of tenants 220 and 222 in response to memory access requests received from the memory controller 202 (e.g., memory access requests routed or processed by the processor 206 from the host computing device 204). In operation, the non-volatile memory device 210 can process the memory access requests to store and / or retrieve information based on the memory access requests originating from tenants 220 and 222. For example, the host computing device 204 can include a host processor that can execute a user application of tenant 220 or tenant 222, and the user application requests stored data and / or stored instructions (and / or stores data / instructions) at the non-volatile memory device 210. When executed, the user application can generate a memory access request to access data or instructions in the non-volatile memory device 210. Generally speaking, as described above, the memory access request can be or include a command and an address, e.g., a memory command and a memory address. In various embodiments, the memory access request can be or include a command and an address for a read operation, a write operation, an activation operation, or a refresh operation at the non-volatile memory device 210. Generally speaking, the received command and address can facilitate the execution of a memory access operation at the non-volatile memory device 210, e.g., a read operation, a write operation, an activation operation, and / or a refresh operation for the non-volatile memory device 210. Thus, the memory access request can be or include one or more memory addresses of one or more of the non-volatile memory devices 210. In an example of a write operation, in addition to the command and the address, the memory access request can further include, for example, data. The memory access request from the host computing device 204 is provided to the processor 206 via the host bus 220 and the host interface 212. For example, the host bus 220 can be a PCIe bus, and the host interface 212 can be a PCIe interface for the processor 206.

[0025] Advantageously, when a memory access request is received at the memory controller 202, the memory system 200 facilitates the generation of encryption keys, such as key 228 of tenant 220 and key 229 of tenant 222, to access data stored on the non-volatile memory device 210. For example, when a memory access request from tenant 220 is received at the processor 206, the processor 206 may provide an encryption indication to the encryption logic 208 such that an encryption key 228 is generated for the specific memory access request. A similar arrangement may be made to generate key 229 for a request from tenant 222. For example, after receiving the encryption indication, the encryption logic 208 may identify the memory address in the received memory access request that corresponds to the memory address of at least one of the non-volatile memory devices 210. Once identified, the encryption logic 208 may generate an encryption key 228 or 229 for the data associated with the memory access request. In an example of a write operation, an encryption key 228 may be generated to secure the data written to the memory address at the non-volatile memory device 210 for tenant 220. The written data may be accessed only when the encryption key 228 is used to access the data (e.g., write or read another memory access request). Thus, in an example, the key 228 may be provided to the non-volatile memory device 210 along with the received memory access request for encrypting the written data. In this case, the encryption key 228 or 229 may be referred to as being associated with specific data written to the memory address of the received memory access request based on tenant 220 or 222. Thus, the memory controller 202 uses the encryption logic 208 to generate encryption keys 228 and 229 for the non-volatile memory device 210.

[0026] In operation, the encryption logic 208 can generate keys 228 or 229, which are encrypted and used to access data stored on the non-volatile memory device 210. The encryption logic 208 can receive the pseudo-random value 226 from the PRNG 222 and encrypt the key 228 or 229 based in part on the pseudo-random value 226 and the corresponding provided key. For example, the provided key can be the DEK stored in the register of the memory controller 202 or the cache 214. The keys 228 or 229 can be used by the memory controller 202 to authenticate access to the non-volatile memory device 210. The encryption logic 208 can store the keys 228 and 229 at the cache 214. For example, the cache 214 can include registers for data storage, and the keys 228 and 229 can be stored in the registers of the cache 214. In this case, the cache 214 can be referred to as being associated with the encryption logic 208. For example, the encryption logic 208 can be configured to provide the generated encrypted keys 228 and 229 to the cache 214 for storage, or to a specific register of the cache 214 for storage. The cache 214 can be a RAM device, such as an SRAM or DRAM storage device. In various embodiments, the cache 214 can be a dynamic memory device, such as a DRAM, and can interact with the processor 206. For example, the cache 214 can be a data cache that includes or corresponds to one or more cache levels of L1, L2, L3, L4 (e.g., as a multi-level cache) or any other cache level. In some embodiments, the encryption logic 208 can also store the key 228 in a register (e.g., a data register) of the memory controller 202.

[0027] To generate the encrypted keys 228 and 229, the PRNG 222 can generate the pseudo-random value 226. In various embodiments, the PRNG 222 can be a linear feedback shift register (LFSR) such that the output of the PRNG 222 is a random value. For example, the LFSR can include a combination of one or more XOR logic units (also referred to as XOR logic gates) that receive feedback as an input such that the output of the combination of one or more XOR logic units is the pseudo-random value 226. Thus, as depicted in Figure 2 the pseudo-random value 226 is provided to the encryption logic 208 to be used as an initialization vector (IV) in the encryption logic 208.

[0028] The memory controller 202 may use the pseudorandom value 226 as an initialization vector for an authenticated stream cipher to generate encryption keys 228. After the processor 206 receives the pseudorandom value 226, the processor may route the pseudorandom value 226 to the encryption logic 208, where the encryption logic 208 may use the pseudorandom value 226 as an initialization vector (IV) for an authenticated stream cipher. For example, the authenticated encryption logic 208 may include an AES Galois Counter Mode (AES-GCM) pipeline such that the authenticated encryption logic 208 generates keys 228 and 229 based on the authenticated stream cipher using the pseudorandom value 226 as the IV and / or the provided key (e.g., DEK) from tenant 220 or 222. For example, GCM may use a base key (e.g., DEK) to generate an authentication tag for the encryption keys 228 and 229. Thus, in the context of a write operation on the received memory access requests obtained, keys 228 and 229 may be used to encrypt the data to be written as plaintext into ciphertext for each respective tenant 220 and 222. Although AES-GCM is described in some instances, it should be understood that other authenticated stream ciphers or other types of ciphers (e.g., quantum ciphers) may also be used in the encryption logic 208 to generate encryption keys, such as keys 228 and 229.

[0029] In instances where the received memory access request includes a read command associated with one of tenants 220 or 222, memory system 200 also advantageously facilitates the retrieval of an encryption key, such as key 228 or 229, to read data on non-volatile memory device 210. For example, in response to receiving a memory access request at processor 206, processor 206 may provide an encryption indication (e.g., an encryption signal) to encryption logic 208. In response to the encryption indication, encryption logic 208 may retrieve encryption key 228 or 229 for the particular memory access request based on the memory address in the received memory access request. For example, after receiving the encryption indication, encryption logic 208 may identify the memory address in the received memory access request that corresponds to a memory address of at least one of the non-volatile memory devices in non-volatile memory device 210. Once identified, encryption logic 208 may retrieve encryption key 228 for the data associated with the memory access request. Keys 228 and 229 may be used to securely retrieve or read corresponding data at the memory address of a particular non-volatile memory device in non-volatile memory device 210. The data to be read may only be accessed when encryption key 228 or 229 is used to access the data. For example, once the read data is retrieved from non-volatile memory device 210, processor 206 may use encryption logic 208 and key 228 or 229 to decrypt the read data. As an example, encryption logic 208 may apply an inverse decryption algorithm to the encryption algorithm used to encrypt key 228 or 229. In an implementation of the AES-GCM pipeline, key 228 or 229 may be used to decrypt the retrieved read data, which is in ciphertext, into plaintext. In this case, encryption keys 228 and 229 may be referred to as being associated with the corresponding data to be read from the corresponding memory address of the received memory access request that may be associated with one of tenants 220 or 222. Thus, memory controller 202 uses encryption logic 208 to retrieve encryption keys 228 and 229 of non-volatile memory device 210.

[0030] Because encryption keys 228 and 229 are stored in shared cache 214, there may be cases where malicious tenant 221 or 222 may attempt to attack the volatile nature of cache 214 to retrieve the key 228 or 229 of another tenant 221 or 222 (such as via a row hammer type of attack). Thus, encryption logic 208 may include circuitry to detect these malicious attacks and circumvent the attacks (such as by blocking the memory access of malicious tenant 221 or 222, flushing the victim row, and / or erasing target key 228 or 229 from cache 214). Erasing target key 228 or 229 may prevent it from falling into the wrong hands and thus prevent unauthorized access to the encrypted data stored at non-volatile memory device 210.

[0031] The non-volatile memory device 210 may store data retrieved and / or accessed by computing devices 204 on behalf of tenants 221 and 222. As some examples, the computing devices 204 may be servers located in a data center or laptop computers located in a data center, and the computing devices 204 may process data sets (e.g., image or content data sets) for use by one or more neural networks hosted on the computing devices 204. The data sets of each tenant 221 and 222 may be stored in one or more of the non-volatile memory devices 210 (e.g., one or both of the data sets may be allocated among the non-volatile memory devices 210). In some embodiments, one or both of the data sets may contain personally identifiable information (PII), such that the operator of the server may require the data stored on the non-volatile memory device 210 to be secure. For example, if malicious tenant 221 or 222 attempts to access key 228 or 229 in an attempt to obtain PII data of another tenant 221 or 222 stored on the non-volatile memory device 210, then when the memory controller 202 detects an attack on the cache 214, the key 228 or 229 used to access the target data stored on the non-volatile memory device 210 will be erased from the cache 214 of the memory controller 202; thereby making it difficult for malicious tenant 221 or 222 to access the data stored on the non-volatile memory device 210. Although PII has been provided as an example of data that may require security, any data may be protected according to the examples described herein, including proprietary data, sensitive data, or confidential data.

[0032] Additionally or alternatively, as described with respect to memory controller 104, memory controller 202 may be an NVDIMM memory controller that is coupled to the host computing device 204 via the host bus 220. The host bus 220 may operate according to an NVDIMM protocol, such as NVDIMM-F, NVDIMM-N, NVDIMM-P, or NVDIMM-X. For example, in such embodiments, the non-volatile memory device 210 may include a NAND memory device or a 3DXPoint memory device, or a Compute Express Link (CXL) device configured to communicate via a CXL bus. Thus, in such embodiments, the non-volatile memory device 210 may also operate as a persistent storage device for the cache 214, which may be a volatile memory device, and / or as a persistent storage device for any volatile memory on the memory controller 202 or the host computing device 204. In various embodiments, memory controller 202 may be used to implement memory controller 104, including any of the methods described herein that may be executed in memory controller 202.

[0033] Figure 3 Schematic illustration of method 300 according to an example described herein. For example, Figure 1 memory controller 104 and / or Figure 2 processor 206 may be used to execute example method 300, where the processor executes executable instructions (e.g., stored in memory, not necessarily shown) to interact with non-volatile memory device 210 via corresponding memory bus 218. In some examples, method 300 may be implemented in whole or in part by Figure 1 encryption logic 106 and / or Figure 2 encryption logic 208. For example, the operations described in steps 302 to 306 may be stored as computer-executable instructions in a computer-readable medium accessible by Figure 1 memory controller 104 and / or Figure 2 processor 206. In an implementation, the computer-readable medium accessible by processor 206 may include Figure 1 one of non-volatile memory device 108 or cache memory 110 coupled to the volatile memory device, or Figure 2 one of non-volatile memory device 210 or cache memory 214 coupled to the volatile memory device. For example, the executable instructions may be stored on one of non-volatile memory devices 210 and retrieved by memory controller 202 for processor 206 to execute the executable instructions to perform method 300. Additionally or alternatively, the executable instructions may be stored in memory coupled to host computing device 204 and retrieved by processor 206 to execute the executable instructions to perform method 300.

[0034] Method 300 includes writing a first encryption key associated with a first tenant of a non-volatile memory device coupled to a volatile memory device to a cache memory coupled to the volatile memory device at 302. Method 300 further includes writing a second encryption key associated with a second tenant of a non-volatile memory device coupled to the volatile memory device to the cache memory coupled to the volatile memory device at 304. For example, key 116 (e.g., the first key) associated with tenant 120 (e.g., the first tenant) of non-volatile memory device 108 and key 118 (e.g., the second key) associated with tenant 122 (e.g., the second tenant) of non-volatile memory device 108 may be written to Figure 1a cache memory 110, which may be included on a volatile memory device. In another example, a key 228 (e.g., a first key) associated with a tenant 221 (e.g., a first tenant) of the non-volatile memory device 210 and a key 229 (e.g., a second key) associated with a tenant 222 (e.g., a second tenant) of the non-volatile memory device 210 may be written to Figure 2 a cache memory 214, which may be included on a volatile memory device. In some examples, method 300 further includes generating a first encryption key based in part on a first pseudo-random value from a pseudo-random number generator. In some examples, method 300 further includes generating a second encryption key based in part on a second pseudo-random value from a pseudo-random number generator. In some examples, method 300 further includes using an authenticated stream cipher to generate the first encryption key. In some examples, both the first tenant and the second tenant are hosted on a host computing device. In some examples, the non-volatile memory device includes at least one of a NAND memory device or a 3D XPoint memory device.

[0035] Method 300 further includes, at 306, in response to detecting an attack by the first tenant on a portion of the cache memory storing the second encryption key, erasing the stored second encryption key from the cache memory. In some examples, method 300 includes detecting an attack on the cache memory by repeatedly accessing a portion of the cache memory physically adjacent to the portion storing the second encryption key. In some examples, method 300 further includes, further in response to detecting an attack by the first tenant on a portion of the cache memory storing the second encryption key, blocking all accesses by the second tenant to the non-volatile memory.

[0036] In some examples, method 300 includes, in response to receiving a memory access request from the second tenant, storing data to or retrieving data from the non-volatile memory device using the second encryption key. In some examples, method 300 includes, in response to receiving a memory access request from the first tenant, storing data to or retrieving data from the non-volatile memory device using the first encryption key.

[0037] The steps included in the described example method 300 are for illustrative purposes. In some embodiments, these steps may be performed in a different order. In some other embodiments, various steps may be eliminated. In still other embodiments, each step may be divided into additional steps, supplemented with other steps, or combined together into fewer steps. Other variations of these specific steps are expected, including variations in the order of the steps, variations in the content of the steps that are split or combined into other steps, etc.

[0038] Certain details are set forth above to provide an adequate understanding of the described examples. However, one of ordinary skill in the art will understand that the described examples may be practiced without these specific details. The description herein of example configurations with reference to the figures does not represent all examples that may be implemented or that are within the scope of the claims. The terms "exemplary" and "example" as used herein are intended to mean "serving as an example, instance, or illustration" and not "preferred over" or "better than" other examples. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the technology may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0039] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0040] Various illustrative blocks and modules described herein in connection with the present disclosure may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0041] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both non-transitory computer-readable storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. The non-transitory storage media can be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor.

[0042] Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. Combinations of the above are also included within the scope of computer-readable media.

[0043] Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations.

[0044] In addition, as used herein, including in the claims, the term "or" as used in a list of items (e.g., a list of items prefaced by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Further, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0045] From the foregoing, it should be understood that although specific examples have been described herein for purposes of illustration, various modifications may be made while still remaining within the scope of the claimed art. The description provided herein enables those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Accordingly, the present disclosure is not limited to the examples and designs described herein, but is accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, comprising: Writing a first encryption key associated with a first tenant of a non - volatile memory device coupled to a volatile memory device into a cache memory coupled to the volatile memory device; Writing a second encryption key associated with a second tenant of the non - volatile memory device coupled to the volatile memory device into the cache memory coupled to the volatile memory device; And In response to detecting an attack by the first tenant on a portion of the cache memory storing the second encryption key, erasing the stored second encryption key from the cache memory.

2. The method according to claim 1, further comprising detecting the attack on the cache memory by repeatedly accessing a portion of the cache memory physically adjacent to the portion storing the second encryption key.

3. The method according to claim 1, further comprising, in further response to detecting the attack by the first tenant on a portion of the cache memory storing the second encryption key, blocking all accesses by the second tenant to the non - volatile memory.

4. The method according to claim 1, further comprising, in response to receiving a memory access request from the second tenant, using the second encryption key to store data into or retrieve data from the non - volatile memory device.

5. The method according to claim 4, further comprising, in response to receiving a memory access request from the first tenant, using the first encryption key to store data into or retrieve data from the non - volatile memory device.

6. The method according to claim 1, wherein both the first tenant and the second tenant are hosted on a host computing device.

7. The method according to claim 1, wherein the non - volatile memory device includes at least one of a NAND memory device or a 3D XPoint memory device.

8. The method according to claim 1, further comprising generating the first encryption key at least in part based on a pseudo - random value from a pseudo - random number generator.

9. The method according to claim 8, further comprising using an authenticated stream cipher to generate the first encryption key.

10. An apparatus, comprising: A cache memory of a volatile memory, configured to store a first encryption key associated with a first tenant for accessing a non - volatile memory and a second encryption key associated with a second tenant for accessing the non - volatile memory; And A processor having encryption logic configured to detect an attack by the first tenant on a portion of the cache memory storing the second encryption key and, in response to detecting the attack, erase the stored second encryption key from the cache memory.

11. The apparatus according to claim 10, wherein the encryption logic is configured to detect an attack on the cache memory based on repeated access to a portion of the cache memory that is physically adjacent to the portion storing the second encryption key of the cache memory.

12. The apparatus according to claim 10, wherein the encryption logic is further configured to block all accesses by the second tenant to the non-volatile memory in response to detecting an attack by the first tenant on a portion of the cache memory storing the second encryption key.

13. The apparatus according to claim 10, wherein the processor is configured to: store data in or retrieve data from the non-volatile memory device using the second encryption key in response to receiving a memory access request from the second tenant; and store data in or retrieve data from the non-volatile memory device using the first encryption key in response to receiving a memory access request from the first tenant.

14. The apparatus according to claim 10, wherein both the first tenant and the second tenant are hosted on a host computing device.

15. The apparatus according to claim 10, wherein the encryption logic is further configured to generate the first encryption key based in part on a pseudo-random value from a pseudo-random number generator.

16. The apparatus according to claim 15, wherein the encryption logic is further configured to use an authenticated stream cipher to generate the first encryption key.

17. A system, comprising: a host computing device configured to host a first tenant and a second tenant; a non-volatile memory configured to store data of the first tenant and data of the second tenant; and a memory controller comprising: a cache memory of volatile memory configured to store a first encryption key associated with the first tenant for accessing the data stored at the non-volatile memory and a second encryption key associated with the second tenant for accessing the data stored at the non-volatile memory; and a processor having encryption logic configured to detect an attack by the first tenant on a portion of the cache memory storing the second encryption key and, in response to detecting the attack, erase the stored second encryption key from the cache memory.

18. The system according to claim 17, wherein the encryption logic is configured to detect the attack on the cache memory based on repeated access to a portion of the cache memory that is physically adjacent to the portion storing the second encryption key of the cache memory.

19. The system according to claim 17, wherein the encryption logic is further configured to block all accesses by the second tenant to the non-volatile memory in response to detecting an attack by the first tenant on a portion of the cache memory storing the second encryption key.

20. The system according to claim 17, wherein the processor is configured to: in response to receiving a memory access request from the second tenant, store data to or retrieve data from the non-volatile memory device using the second encryption key; and in response to receiving a memory access request from the first tenant, store data to or retrieve data from the non-volatile memory device using the first encryption key.

21. The system according to claim 17, wherein the encryption logic is further configured to generate the first encryption key based in part on a pseudo-random value from a pseudo-random number generator.

22. The system according to claim 21, wherein the memory controller further includes the pseudo-random number generator configured to generate the pseudo-random value.

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