Matrix parallel computing device and method

Abstract

The present application relates to the technical field of data parallel operation optimization, and relates to a matrix parallel operation device and method. The device includes: a DDR memory for storing input matrix data blocks and output matrix data blocks; an L1 cache unit, including an input ring buffer and an output ring buffer; a calculation control unit, including control logic and a DMA controller; the control logic is used to receive information synchronization information and a calculation start signal from the host, and schedule data transmission based on the idle data block status of the input ring buffer and the idle channel status of the DMA controller; a parallel calculation unit, for reading input data blocks from the input ring buffer for calculation, and writing the calculation results into the output ring buffer. The present invention combines an efficient DMA data transmission mechanism with double buffering technology to achieve efficient scheduling of computing tasks and high-speed data transmission, significantly improving the efficiency of matrix operations.

Description

Technical Field

[0001] The present application relates to the technical field of data parallel operation optimization, and in particular to a matrix parallel operation device and method. Background Art

[0002] With the rapid development of artificial intelligence, deep learning, and big data technologies, matrix operations, as core computing tasks in these fields, are experiencing explosive growth in scale and complexity. Traditional serial computing methods are no longer able to meet the high throughput and low latency requirements of modern applications. This is especially true during neural network training and inference, where large-scale matrix multiplications, convolutions, and other operations place extremely high demands on computational efficiency. Therefore, efficiently implementing matrix parallel operations has become a hot research topic.

[0003] Existing matrix parallel computing solutions typically rely on general-purpose processors (CPUs) or graphics processing units (GPUs). However, CPUs have limited parallel computing capabilities, making it difficult to fully exploit data-level parallelism. While GPUs offer strong parallel computing capabilities, their architecture is more oriented towards general-purpose graphics computing, and they may not deliver optimal performance in specific scenarios (such as small-scale matrix operations or those requiring low latency). Furthermore, traditional solutions often incur high overhead in data transmission and computing task scheduling, resulting in insufficient utilization of computing resources.

[0004] To address these challenges, researchers have conducted in-depth exploration and optimization of matrix parallel operations across multiple technical areas. In terms of hardware architecture, the emergence of dedicated accelerator chips has provided new solutions for matrix operations. These chips utilize innovative architectures such as systolic arrays to achieve efficient data reuse and optimized memory access, significantly improving the throughput of matrix multiplication. Furthermore, by increasing on-chip storage and utilizing technologies such as high-bandwidth memory (HBM), the limitations imposed by the memory barrier on computing performance have been further reduced. Furthermore, the application of techniques such as pruning and weight coefficient compression has effectively reduced the number of parameters in neural networks, accelerating the computational process.

[0005] With the increasing prevalence of multi-core processors and GPUs, as well as the rise of large-scale clusters and distributed computing systems, parallel computing has become the mainstream approach for handling large-scale matrix operations. By optimizing parallel algorithms and software architectures, researchers are able to more fully utilize computing resources and improve computational efficiency. However, parallel computing also faces challenges such as resource scheduling and load balancing, which require continuous research and innovation.

[0006] Storage optimization is also crucial for improving the efficiency of matrix parallel computing. The emergence of distributed storage systems provides a reliable solution for storing and accessing large-scale matrix data. Technologies such as data compression and deduplication can effectively reduce storage space requirements and improve storage efficiency. Furthermore, the application of caching strategies and load balancing technologies further optimizes data access speed and avoids single-point overload issues.

[0007] In addition to the optimizations in the aforementioned technical fields, the application of matrix operations themselves has also been widely expanded in fields such as image processing, machine learning, and deep learning. In image processing, matrix operations are used to implement tasks such as image transformation, filtering, compression, and feature extraction, improving the efficiency and accuracy of image processing. In machine learning and deep learning, matrix operations accelerate data preprocessing, model training, and inference, supporting large-scale data processing and high-dimensional feature learning.

[0008] With the continuous advancement of technology and the expansion of application scenarios, matrix parallel computing will play an important role in more fields. In the future, researchers will continue to explore new hardware architectures, parallel strategies, and storage optimization techniques to further improve the efficiency and performance of matrix parallel computing and promote the continued development of artificial intelligence, deep learning, and big data technologies.

[0009] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention

[0010] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0011] The embodiments of the present disclosure provide a matrix parallel operation device and method, which realizes efficient scheduling of computing tasks and high-speed transmission of data, significantly improves the efficiency of matrix operations, and is particularly suitable for operator acceleration in neural network models.

[0012] In some embodiments, the apparatus comprises:

[0013] DDR memory, used for storing input matrix data blocks and output matrix data blocks;

[0014] An L1 cache unit includes an input ring buffer and an output ring buffer, wherein the input ring buffer is used to cache input data blocks transmitted from the DDR, and the output ring buffer is used to cache calculation results of the parallel computing unit;

[0015] A computing control unit, comprising control logic and a DMA controller, wherein the DMA controller is configured with multiple transmission channels for transmitting input data blocks from the DDR to the input ring buffer and output data blocks from the output ring buffer to the DDR; the control logic is configured to receive information synchronization information and a computing start signal from the host, and schedule data transmission based on the idle data block status of the input ring buffer and the idle channel status of the DMA controller;

[0016] A parallel computing unit is used to read input data blocks from an input ring buffer for computing and write computing results to an output ring buffer;

[0017] The calculation control unit and the parallel computing unit share an L1 cache unit.

[0018] Preferably, the DMA controller includes at least 16 transmission channels.

[0019] Preferably, each channel of the DMA controller is configured as follows:

[0020] In the input transmission phase, the input data blocks at the specified base address in the storage unit are incrementally transmitted according to the block size based on the idle channel status and input buffer space availability;

[0021] In the output transmission phase, the calculation results are incrementally transmitted back according to the block size based on the idle channel status and the data ready status of the output buffer.

[0022] Preferably, the input transmission stage is specifically as follows:

[0023] The control logic receives a data base address parameter and a calculation start signal sent by the host, wherein the base address parameter includes an input data first address and an output data first address;

[0024] The control logic sends a start calculation instruction to the parallel computing unit to start data transmission: set the input DMA controller source address equal to the input data starting address, and determine whether there is an idle transmission channel in the DMA controller and whether there is an idle data block in the input buffer; if both are met, set the destination address of the idle transmission channel to the starting address of the idle data block, and update the input DMA controller source address and input data block index according to the transmission length.

[0025] Preferably, the output transmission stage is specifically as follows:

[0026] Set the output DMA controller destination address equal to the output data starting address, determine whether there is an idle transmission channel in the DMA controller and whether there is a calculated data block in the input buffer; if both are met, set the source address of the idle transmission channel to the starting address of the calculated data block, and update the source address of the idle transmission channel and the output data block index according to the transmission length.

[0027] Preferably, the input ring buffer and the output ring buffer use double buffering technology to achieve pipeline operation of data transmission and computing tasks.

[0028] Preferably, the parallel computing unit calculation process is as follows:

[0029] After receiving the start calculation instruction issued by the calculation control unit, it is determined whether the calculation unit is idle. If the calculation unit is idle, it is determined whether there is a memory block in the input ring buffer that has been transferred, and whether there is an idle memory block in the output ring buffer. If the above conditions are met, the memory block is read out for calculation and the calculation result is stored in the output ring buffer. Otherwise, the loop waits for the conditions to be met before performing the calculation operation.

[0030] In some embodiments, the matrix parallel operation method includes the following steps:

[0031] Divide the input matrix into blocks according to the size of the blocks and pre-store the block data into the DDR memory;

[0032] Send input / output data base address, block size parameters and calculation start instructions to the device end through the communication synchronization interface;

[0033] The DMA controller performs data transfer from the DDR memory to the input ring buffer in block index order according to the current idle channel status and input buffer space status;

[0034] The parallel computing unit reads data blocks from the input ring buffer for calculation and writes the results to the output ring buffer;

[0035] The calculation control unit determines the calculation completion data block of the output buffer and the DMA idle channel. If the conditions are met, the output data is transferred from the output ring buffer to the DDR memory in blocks;

[0036] Repeat the data transmission and calculation steps until all blocks are calculated and transmitted.

[0037] Preferably, the block size of the DMA transfer is dynamically adjusted according to the maximum computing capability of the parallel computing unit.

[0038] In some embodiments, the storage medium stores a computer program, which implements the matrix parallel operation method when executed by a processor.

[0039] The embodiments of the present disclosure provide a matrix parallel computing device and method, which can achieve the following technical effects:

[0040] This invention achieves efficient scheduling of computing tasks and high-speed data transmission by designing a dedicated computation control unit and parallel computing unit, combined with an efficient DMA data transfer mechanism and double buffering technology (input / output ring buffer). Furthermore, this architecture supports flexible block computing strategies and can dynamically adjust the scale of parallel computing based on hardware resources, significantly improving the efficiency of matrix operations. It is particularly suitable for accelerating operators in neural network models.

[0041] By decoupling computational control from data transmission, and through hardware-level parallelization and intelligent scheduling, we maximize computing resource utilization while reducing data transmission latency. This technology not only meets the demands of modern high-performance computing but also provides a scalable solution for future larger-scale and more complex matrix operations.

[0042] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,

[0044] Figure 1 This is a system structure diagram of the present invention.

[0045] Figure 2 It is a control logic flow chart of the calculation control unit.

[0046] Figure 3 This is the control logic flow chart of the parallel computing unit.

[0047] Figure 4 It is a schematic flow chart of the method of the present invention. DETAILED DESCRIPTION

[0048] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0049] In the description and claims of the embodiments of the present disclosure, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to describe the embodiments of the present disclosure herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0050] Unless otherwise stated, the term "plurality" means two or more.

[0051] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.

[0052] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0053] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0054] Example 1

[0055] like Figure 1 As shown, a matrix parallel computing device, DDR memory, computing control unit, parallel computing unit and L1 cache unit are used to accelerate the computing process of neural network model operators.

[0056] The device comprises:

[0057] DDR memory, used for storing input matrix data blocks and output matrix data blocks;

[0058] An L1 cache unit includes an input ring buffer and an output ring buffer, wherein the input ring buffer is used to cache input data blocks transmitted from the DDR, and the output ring buffer is used to cache calculation results of the parallel computing unit;

[0059] A computing control unit, comprising control logic and a DMA controller, wherein the DMA controller is configured with multiple transmission channels for transmitting input data blocks from the DDR to the input ring buffer and output data blocks from the output ring buffer to the DDR; the control logic is configured to receive information synchronization information and a computing start signal from the host, and schedule data transmission based on the idle data block status of the input ring buffer and the idle channel status of the DMA controller;

[0060] A parallel computing unit is used to read input data blocks from an input ring buffer for computing and write computing results to an output ring buffer;

[0061] The calculation control unit and the parallel computing unit share an L1 cache unit.

[0062] As a refinement of the above embodiment, Figure 2 As shown, the control logic design of the calculation control unit is as follows:

[0063] The control logic is mainly used to synchronize the data transmission process and the operator calculation process. Assuming that the maximum amount of data that the parallel computing unit can calculate at one time is N, before starting the calculation, the host first divides the input matrix data into small blocks of size N and transfers them to the DDR. The input and output data first addresses base_addr_in and base_addr_out in the DDR are transmitted to the device-side L1-Cache through the calculation start information, and then the communication synchronization information in the L1-Cache sends a signal to start the calculation to the device side. After receiving the calculation start signal, the control logic sends a start calculation instruction to the parallel computing unit through the communication synchronization information, and then starts the data transmission process as follows:

[0064] Let the input DMA source address src_addr_in:=base_addr_in. For each input data matrix, the control logic determines whether the following conditions are met:

[0065] There is an idle transmission channel ch_idle_in in the DMA controller;

[0066] There is an idle data block db_idle in the input buffer.

[0067] If both of the above conditions are met, set the destination address dst_addr_in of channel ch_idle_in to the first address of db_idle, set src_addr_in:=src_addr_in+N, set the transfer length to N, set the input data block index tile_idx_in:=tile_idx_in+1, and start data transmission.

[0068] After that, the output DMA destination address dst_addr_out:=base_addr_out is set. For each output data matrix, the control logic determines whether the following conditions are met:

[0069] There is an idle transmission channel ch_idle_out in the DMA controller;

[0070] The output buffer contains the data block db_ready for which calculation has been completed.

[0071] If both of the above conditions are met, set the source address src_addr_out of channel ch_idle_out to the first address of db_ready, set src_addr_out:=src_addr_out+N, set the transfer length to N, set the output data block index tile_idx_out:=tile_idx_out+1, and start data transmission.

[0072] The above steps are executed repeatedly until all input and output data blocks are transmitted.

[0073] As a refinement of the above embodiment, Figure 3 As shown, the parallel computing unit control logic is designed as follows:

[0074] After receiving the calculation start message from the calculation control unit, the parallel computing unit first determines whether the computing unit is idle. If so, it then checks whether there are any transferred memory blocks in the input ring buffer and whether there are any free memory blocks in the output ring buffer. If these conditions are met, it reads the memory block for calculation and stores the calculation result in the output ring buffer. Otherwise, it loops and waits until the conditions are met before continuing the calculation operation.

[0075] It should be noted that this invention achieves efficient scheduling of computing tasks and high-speed data transmission by designing a dedicated computation control unit and parallel computing unit, combined with an efficient DMA data transmission mechanism and double buffering technology (input / output ring buffer). Furthermore, this architecture supports flexible block computing strategies and can dynamically adjust the scale of parallel computing based on hardware resources, significantly improving the efficiency of matrix operations. This makes it particularly suitable for accelerating operators in neural network models.

[0076] By decoupling computational control from data transmission, and through hardware-level parallelization and intelligent scheduling, we maximize computing resource utilization while reducing data transmission latency. This technology not only meets the demands of modern high-performance computing but also provides a scalable solution for future larger-scale and more complex matrix operations.

[0077] Example 2

[0078] like Figure 4 As shown, a matrix parallel operation method includes the following steps:

[0079] S1: Divide the input matrix into block sizes and pre-store the block data into DDR memory;

[0080] S2: Send the input / output data base address, block size parameters and calculation start instructions to the device end through the communication synchronization interface;

[0081] S3: The DMA controller performs data transfer from the DDR memory to the input ring buffer in block index order according to the current idle channel status and input buffer space status;

[0082] S4: The parallel computing unit reads data blocks from the input ring buffer for calculation and writes the results to the output ring buffer;

[0083] S5: The calculation control unit determines the calculation completion data block in the output buffer and the DMA idle channel. If the conditions are met, the output data blocks are transferred from the output ring buffer to the DDR memory.

[0084] S6: Repeat steps S4-S5 until all blocks are calculated and transmitted.

[0085] As a refinement of the above embodiment, the block size of the DMA transfer is dynamically adjusted according to the maximum computing capability of the parallel computing unit.

[0086] This example describes a matrix parallel operation method using a matrix multiplication task. This task requires computing the product of matrix A (4x4) and matrix B (4x4), storing the result in matrix C (4x4). The parallel computing unit can compute a maximum of 4 data items at a time (N = 4), meaning it can compute one 2x2 block at a time. Data in host memory is already divided into blocks and transferred to the device's DDR via DMA.

[0087] S1. Data Blocking

[0088] The input matrices A and B are divided into four 2x2 blocks:

[0089] Blocks of A: A1, A2, A3, A4

[0090] Blocks of B: B1, B2, B3, B4

[0091] Output matrix C blocks: C1, C2, C3, C4 (initially empty, waiting for calculation results to be written)

[0092] Control unit operation flow

[0093] S2. Initialization:

[0094] The host transfers the blocks of A and B into DDR.

[0095] The host sends the first address of the input / output data (base_addr_in_A, base_addr_in_B, base_addr_out_C) to the L1-Cache on the device side through communication synchronization information.

[0096] The host sends a signal to start the calculation. After receiving the start signal, the control unit starts data transmission and calculation scheduling.

[0097] S3. Input data transmission (blocks of A and B):

[0098] S3-1, first round of transmission:

[0099] Check if there is an idle DMA channel (ch_idle_in) and input buffer (db_idle).

[0100] Set DMA parameters:

[0101] src_addr_in_A = base_addr_in_A (transmission A1), dst_addr_in = db_idle (input buffer address).

[0102] src_addr_in_B = base_addr_in_B (transmission B1), dst_addr_in = db_idle (input buffer address).

[0103] Start a DMA transfer to transfer A1 and B1 to the input buffer.

[0104] Update addresses and indexes:

[0105] src_addr_in_A:=src_addr_in_A+4 (pointing to A2).

[0106] src_addr_in_B:=src_addr_in_B+4 (pointing to B2).

[0107] tile_idx_in:=tile_idx_in+1.

[0108] S3-2, second round of transmission:

[0109] Checks for free channels and buffers.

[0110] Transfer A2 and B2 to the input buffer.

[0111] Update the address and index (pointing to A3 and B3).

[0112] Repeat the above process until all input blocks (A1-A4 and B1-B4) are transferred.

[0113] S4, parallel computing unit operation:

[0114] The compute unit continuously checks the input and output buffers:

[0115] If there is data in the input buffer (such as A1 and B1) and there is a free block in the output buffer, the calculation starts.

[0116] S4-1. Calculate C1:

[0117] Read A1 and B1 from the input buffer and calculate C1 = A1 * B1.

[0118] Write C1 to the output buffer.

[0119] S4-2. Calculate C2:

[0120] Read A1 and B2, and calculate C2=A1*B2.

[0121] Write to the output buffer.

[0122] Repeat the above process until all blocks are calculated (C1-C4).

[0123] S5. Output data transmission (blocking of C):

[0124] S5-1, first round of transmission:

[0125] Check whether there is an idle DMA channel (ch_idle_out) and whether there is a calculated data block in the output buffer (db_ready, such as C1).

[0126] Set DMA parameters:

[0127] src_addr_out = db_ready (the address of C1), dst_addr_out = base_addr_out_C (the address of C1 in the host memory).

[0128] Initiate a DMA transfer to transfer C1 back to host memory.

[0129] Update addresses and indexes:

[0130] dst_addr_out:=dst_addr_out+4 (pointing to C2).

[0131] tile_idx_out:=tile_idx_out+1.

[0132] S5-2, Second round of transmission:

[0133] Transfer C2 to host memory.

[0134] Update the address (pointing to C3).

[0135] Repeat the above process until all output blocks (C1-C4) are transferred.

[0136] S6. After all input blocks are transferred, calculated, and output blocks are transferred, the task ends.

[0137] Preferably, the block size of the DMA transfer is dynamically adjusted according to the maximum computing capability of the parallel computing unit.

[0138] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned matrix parallel operation method.

[0139] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0140] The technical solutions of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk, and other media that can store program code, or a transient storage medium.

[0141] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible variations. Unless expressly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. Moreover, the terms used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and claims, the singular forms "a", "an" and "the" are intended to also include the plural forms unless the context clearly indicates otherwise. Similarly, the term "and / or" as used in this application means any and all possible combinations of one or more of the associated listings. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, an element defined by the sentence "comprising a..." does not exclude the presence of other identical elements in the process, method or device that includes the element. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments can be referenced to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can be referred to the description of the method part.

[0142] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0143] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices and equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units may be merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or omitting or disabling some features. In addition, the coupling or direct coupling or communication connection shown or discussed between each other may be through some interface, or the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to implement the present embodiments according to actual needs. In addition, the functional units in the embodiments of the present disclosure may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0144] The flowcharts and block diagrams in the accompanying drawings show the possible implementation architectures, functions and operations of the systems, methods and computer program products according to the embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in an order different from that disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A matrix parallel computing device, characterized in that: include: DDR memory, used for storing input matrix data blocks and output matrix data blocks; An L1 cache unit includes an input ring buffer and an output ring buffer, wherein the input ring buffer is used to cache input data blocks transmitted from the DDR, and the output ring buffer is used to cache calculation results of the parallel computing unit; A computing control unit, comprising control logic and a DMA controller, wherein the DMA controller is configured with multiple transmission channels for transmitting input data blocks from the DDR to the input ring buffer and transmitting output data blocks from the output ring buffer to the DDR; The control logic is used to receive information synchronization information and a calculation start signal from the host, and schedule data transmission based on the idle data block status of the input ring buffer and the idle channel status of the DMA controller; A parallel computing unit is used to read input data blocks from an input ring buffer for computing and write computing results to an output ring buffer; The calculation control unit and the parallel computing unit share an L1 cache unit.

2. The matrix parallel operation device according to claim 1, wherein: The DMA controller includes at least 16 transmission channels.

3. The matrix parallel operation device according to claim 1 or 2, characterized in that: The channels of the DMA controller are configured as follows; In the input transmission phase, the input data blocks at the specified base address in the storage unit are incrementally transmitted according to the block size based on the idle channel status and input buffer space availability; In the output transmission phase, the calculation results are incrementally transmitted back according to the block size based on the idle channel status and the data ready status of the output buffer.

4. The matrix parallel operation device according to claim 3, characterized in that: The input transmission stage is specifically as follows: The control logic receives a data base address parameter and a calculation start signal sent by the host, wherein the base address parameter includes an input data first address and an output data first address; The control logic sends a start calculation instruction to the parallel computing unit to start data transmission: set the input DMA controller source address equal to the input data starting address, and determine whether there is an idle transmission channel in the DMA controller and whether there is an idle data block in the input buffer; if both are met, set the destination address of the idle transmission channel to the starting address of the idle data block, and update the input DMA controller source address and input data block index according to the transmission length.

5. The matrix parallel operation device according to claim 3, characterized in that: The output transmission stage is specifically as follows: Set the output DMA controller destination address equal to the output data starting address, determine whether there is an idle transmission channel in the DMA controller and whether there is a calculated data block in the input buffer; if both are met, set the source address of the idle transmission channel to the starting address of the calculated data block, and update the source address of the idle transmission channel and the output data block index according to the transmission length.

6. The matrix parallel operation device according to claim 1, characterized in that: The input ring buffer and the output ring buffer use double buffering technology to achieve pipeline operation of data transmission and computing tasks.

7. The matrix parallel operation device according to claim 1, wherein: The parallel computing unit calculation process is as follows: After receiving the start calculation instruction issued by the calculation control unit, it is determined whether the calculation unit is idle. If the calculation unit is idle, it is determined whether there is a memory block in the input ring buffer that has been transferred, and whether there is an idle memory block in the output ring buffer. If the above conditions are met, the memory block is read out for calculation and the calculation result is stored in the output ring buffer. Otherwise, the loop waits for the conditions to be met before performing the calculation operation.

8. A matrix parallel operation method, applied to the matrix parallel operation device according to any one of claims 1 to 7, characterized in that: The following steps are involved: Divide the input matrix into blocks according to the size of the blocks and pre-store the block data into the DDR memory; Send input / output data base address, block size parameters and calculation start instructions to the device end through the communication synchronization interface; The DMA controller performs data transfer from the DDR memory to the input ring buffer in block index order according to the current idle channel status and input buffer space status; The parallel computing unit reads data blocks from the input ring buffer for calculation and writes the results to the output ring buffer; The calculation control unit determines the calculation completion data block of the output buffer and the DMA idle channel. If the conditions are met, the output data is transferred from the output ring buffer to the DDR memory in blocks; Repeat the data transmission and calculation steps until all blocks are calculated and transmitted.

9. The matrix parallel operation method according to claim 8, characterized in that: The block size of the DMA transfer is dynamically adjusted according to the maximum computing capability of the parallel computing unit.

10. A computer-readable storage medium, characterized in that A computer program is stored thereon, and when the program is executed by a processor, the matrix parallel operation method as described in any one of claims 8 or 9 is implemented.

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