Configuration method and device of instruction set operation unit in multi-core processor

Abstract

The embodiment of the application provides a configuration method and device of an instruction set operation unit in a multi-core processor, the method comprising: obtaining a chip area requirement of a multi-core processor to be configured and a vector instruction set extension requirement of each core in the multi-core processor; selecting a configuration scheme corresponding to the current multi-core processor to be configured from preset instruction set operation unit configuration schemes according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor; and configuring the instruction set operation unit in the current multi-core processor based on the configuration scheme, which is flexible in actual application and can flexibly control the support of each processor core to the V extension operation unit in the multi-core processor, greatly improving the operation utilization rate of each core in the multi-core processor and avoiding resource waste.

Description

Technical Field

[0001] The present application relates to the technical field of multi-core processors, and in particular to a configuration method, apparatus, computer equipment, and storage medium for an instruction set operation unit in a multi-core processor. Background Art

[0002] In the RISC-V architecture (RISC-V is an open-source instruction set architecture that defines a base set of opcodes and registers, as well as some optional extended instructions), the "V" extensions are available for standard server and application processor platform profiles. Other platforms, including embedded platforms, may choose to implement a subset of these extensions. The base vector extension, intended to serve as the foundation for other vector extensions in various fields, including cryptography and machine learning, consumes significant hardware resources, such as instruction set arithmetic units (ISAs).

[0003] like Figure 1 As shown in , in the related art, an instruction set operation unit is configured for each core in a multi-core processor. Under this configuration, the multi-core processor is provided with maximum instruction set processing performance. Although the instruction set processing performance is strong, each core in the multi-core processor is configured with an instruction set operation unit. The chip area of ​​the multi-core processor is particularly large, which will cause performance waste in many scenarios and has a very low cost performance. Summary of the Invention

[0004] Embodiments of the present application provide a method, apparatus, computer device, and storage medium for configuring an instruction set operation unit in a multi-core processor.

[0005] A first aspect of an embodiment of the present application provides a method for configuring an instruction set operation unit in a multi-core processor, comprising:

[0006] Obtain the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor;

[0007] Selecting a configuration scheme corresponding to the multi-core processor to be configured from preset instruction set operation unit configuration schemes according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor;

[0008] Based on the configuration scheme, the instruction set operation unit is configured in the current multi-core processor.

[0009] The preset instruction set operation unit configuration scheme is one of the following four configuration schemes:

[0010] For some cores in a multi-core processor, each core is configured with an instruction set operation unit;

[0011] grouping all the cores of the multi-core processor, each group of cores sharing one instruction set operation unit;

[0012] all the cores of the multi-core processor freely sharing a plurality of instruction set operation units, wherein the number of instruction set operation units is less than the number of cores of the multi-core processor;

[0013] all the cores of the multi-core processor sharing one instruction set operation unit.

[0014] In an optional embodiment of the present application, the chip area requirement of the multi-core processor to be configured includes a first-level chip area requirement and a second-level chip area requirement, wherein the first-level chip area requirement is less than the second-level chip area requirement, and the vector instruction set extension requirement of each core of the multi-core processor includes a first-level vector instruction set extension requirement and a second-level vector instruction set extension requirement, wherein the first-level vector instruction set extension requirement is less than the second-level vector instruction set extension requirement.

[0015] In an optional embodiment of the present application, according to the chip area requirement and the vector instruction set extension requirement of each core of the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured is selected from the preset instruction set operation unit configuration schemes, comprising:

[0016] in the case that the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core of the multi-core processor are both first-level, the configuration scheme of the current multi-core processor to be configured is that all the cores of the multi-core processor share one instruction set operation unit;

[0017] in the case that the chip area requirement of the multi-core processor to be configured is second-level and the vector instruction set extension requirement of at least part of the cores of the multi-core processor is second-level, according to the different vector instruction set extension requirements of each core of the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured is selected from the configuration schemes other than that all the cores share one instruction set operation unit.

[0018] In an optional embodiment of the present application, in the case that the chip area requirement of the multi-core processor to be configured is second-level and the vector instruction set extension requirement of at least part of the cores of the multi-core processor is second-level, according to the different vector instruction set extension requirements of each core of the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured is selected from the configuration schemes other than that all the cores share one instruction set operation unit, comprising:

[0019] In a case where the chip area requirement of the to-be-configured multi-core processor is two levels and the vector instruction set extension requirement of a part of the cores in the multi-core processor is two levels, the configuration scheme corresponding to the current to-be-configured multi-core processor is that, for the part of the cores in the multi-core processor, each core is configured with an instruction set operation unit, and the vector instruction set extension requirement of each core configured with the instruction set operation unit is two levels, and the vector instruction set extension requirement of each core not configured with the instruction set operation unit is one level.

[0020] In an optional embodiment of the present application, in a case where the chip area requirement of the to-be-configured multi-core processor is two levels and the vector instruction set extension requirement of at least a part of the cores in the multi-core processor is two levels, the configuration scheme corresponding to the current to-be-configured multi-core processor is selected from the configuration schemes other than sharing one instruction set operation unit by all the cores according to the different vector instruction set extension requirements of each core in the multi-core processor, and the configuration scheme includes:

[0021] In a case where the chip area requirement of the to-be-configured multi-core processor is two levels and the vector instruction set extension requirement of all the cores in the multi-core processor is two levels, if the instruction set processing time of all the cores is dispersed in multiple time periods and the instruction set processing time of each group of cores is not conflicted after grouping all the cores according to the instruction set processing time, the configuration scheme of the current multi-core processor is that all the cores of the multi-core processor are grouped, and each group of cores shares one instruction set operation unit.

[0022] In an optional embodiment of the present application, in a case where the chip area requirement of the to-be-configured multi-core processor is two levels and the vector instruction set extension requirement of at least a part of the cores in the multi-core processor is two levels, the configuration scheme corresponding to the current to-be-configured multi-core processor is selected from the configuration schemes other than sharing one instruction set operation unit by all the cores according to the different vector instruction set extension requirements of each core in the multi-core processor, and the configuration scheme includes:

[0023] In a case where the chip area requirement of the to-be-configured multi-core processor is two levels and the vector instruction set extension requirement of all the cores in the multi-core processor is two levels, if the instruction set processing time of all the cores is concentrated in a preset time period, the configuration scheme of the current multi-core processor is that all the cores of the multi-core processor freely share multiple instruction set operation units, and the number of the instruction set operation units is less than the number of the cores of the multi-core processor.

[0024] In an optional embodiment of the present application, the method further includes:

[0025] For multiple cores sharing one instruction set operation unit, in the case that at least two cores simultaneously issue instruction set processing requests to the shared one instruction set operation unit, the multiple cores simultaneously issued instruction set processing requests are arbitrated according to a preset arbitration mechanism to determine the processing order of the multiple instruction set processing requests by the shared one instruction set operation unit.

[0026] A second aspect of the embodiment of the application provides a configuration device of an instruction set operation unit in a multi-core processor, comprising:

[0027] The obtaining module is configured to obtain a chip area requirement of a multi-core processor to be configured and a vector instruction set extension requirement of each core in the multi-core processor;

[0028] The selecting module is configured to select, according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured from preset instruction set operation unit configuration schemes;

[0029] The configuration module is configured to configure the instruction set operation unit in the current multi-core processor based on the configuration scheme,

[0030] The preset instruction set operation unit configuration scheme is one of the following four configuration schemes:

[0031] For some cores in the multi-core processor, one instruction set operation unit is configured for each core;

[0032] All cores of the multi-core processor are grouped, and one instruction set operation unit is shared by cores in each group;

[0033] All cores of the multi-core processor are free to share multiple instruction set operation units, and the number of instruction set operation units is less than the number of cores of the multi-core processor;

[0034] All cores in the multi-core processor share one instruction set operation unit.

[0035] A third aspect of the embodiment of the application provides a computer device, comprising a memory and a processor, the memory stores a computer program, and the processor implements the steps of the configuration method of the instruction set operation unit in the multi-core processor according to any one of the above when executing the computer program.

[0036] A fourth aspect of the embodiment of the application provides a computer readable storage medium, which stores a computer program, and the computer program implements the steps of the configuration method of the instruction set operation unit in the multi-core processor according to any one of the above when executed by a processor.

[0037] The above technical solutions provided by the embodiments of the application have at least some or all of the following advantages compared with the prior art:

[0038] The configuration method of the instruction set operation unit in the multi-core processor provided by the embodiment of the present application comprises the following steps: obtaining the chip area requirement of a multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor; selecting a configuration scheme corresponding to the current multi-core processor to be configured from preset instruction set operation unit configuration schemes according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor; and configuring the instruction set operation unit in the current multi-core processor based on the configuration scheme. The preset instruction set operation unit configuration schemes are one of the following four configuration schemes: one instruction set operation unit is configured for each core in the multi-core processor; all cores of the multi-core processor are grouped, and one instruction set operation unit is shared by each group of cores; all cores of the multi-core processor share multiple instruction set operation units, wherein the number of instruction set operation units is less than the number of cores of the multi-core processor; and all cores in the multi-core processor share one instruction set operation unit, which is flexibly configured according to the actual application scenario in the actual application process, especially in the scenario of using the multi-core processor. In the multi-core processor, the support of each processor core for the "V" extension operation unit can be flexibly controlled, which greatly improves the operation utilization rate of each core in the multi-core processor and avoids the waste of resources. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the present application. In the drawings:

[0040] Figure 1 The configuration diagram of the instruction set operation unit in the multi-core processor provided by the related art is shown;

[0041] Figure 2 The flowchart of the configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application is shown;

[0042] Figure 3 The configuration diagram of the configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application is applied to the scenario of configuring one instruction set operation unit for each core in the multi-core processor is shown;

[0043] Figure 4 The configuration diagram of the configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application is applied to the scenario of grouping all cores of the multi-core processor, and one instruction set operation unit is shared by each group of cores is shown;

[0044] Figure 5The configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application is applied to a scenario in which all the cores in the multi-core processor share one instruction set operation unit;

[0045] Figure 6 The configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application is applied to a scenario in which all the cores in the multi-core processor share one instruction set operation unit;

[0046] Figure 7 The configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application is applied to a scenario in which all the cores in the multi-core processor share one instruction set operation unit;

[0047] Figure 8 The configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application is applied to a scenario in which all the cores in the multi-core processor share one instruction set operation unit; DETAILED DESCRIPTION

[0048] In order to make the technical solutions and advantages in the embodiments of the present application clearer, the following further describes exemplary embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0049] Please refer to Figure 2 The configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application includes the following steps S100-S300:

[0050] S100, obtaining a chip area requirement of a multi-core processor to be configured and a vector instruction set extension requirement of each core in the multi-core processor;

[0051] S200, selecting, according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured from preset instruction set operation unit configuration schemes;

[0052] S300, configuring an instruction set operation unit in the current multi-core processor based on the configuration scheme,

[0053] The preset instruction set operation unit configuration scheme is one of the following four configuration schemes:

[0054] For some cores in the multi-core processor, one instruction set operation unit is configured for each core;

[0055] All the cores in the multi-core processor are grouped, and one instruction set operation unit is shared by each group of cores;

[0056] All cores of the multi-core processor freely share multiple instruction set operation units, wherein the number of instruction set operation units is less than the number of cores of the multi-core processor;

[0057] All cores in a multi-core processor share one instruction set arithmetic unit.

[0058] In an optional embodiment of the present application, the chip area requirements of the multi-core processor to be configured include a first-level chip area and a second-level chip area, wherein the first-level chip area is smaller than the second-level chip area, and the vector instruction set extension requirements of each core in the multi-core processor include a first-level vector instruction set extension requirement and a second-level vector instruction set extension requirement, wherein the first-level vector instruction set extension requirement is smaller than the second-level vector instruction set extension requirement.

[0059] In an optional embodiment of the present application, the first-level chip area is within a first preset area range, and the second-level chip area is within a second preset area range, wherein the maximum value of the first preset area range is less than the minimum value of the second preset area range, the first-level vector instruction set extension requirement is that instruction set processing performance is not required, and the second-level vector instruction set extension requirement is that instruction set processing performance is required.

[0060] In an optional embodiment of the present application, based on the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor, a configuration scheme corresponding to the multi-core processor to be configured is selected from preset instruction set operation unit configuration schemes, including:

[0061] When the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor are both level 1, the current configuration scheme of the multi-core processor to be configured is that all cores in the multi-core processor share one instruction set operation unit;

[0062] When the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirement of at least some cores in the multi-core processor is level 2, based on the different vector instruction set extension requirements of each core in the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured is selected from configuration schemes other than configuration schemes in which all cores share one instruction set operation unit.

[0063] See also Figure 3 While minimizing the first-level chip area in a multi-core processor system requires that each core utilize an instruction set arithmetic unit (ISA). This allows each processor core to be configured with a shared ISA. This configuration provides the multi-core processor system with the best area and cost-performance while also ensuring that each core can utilize an ISA.

[0064] In an optional embodiment of the present application, when the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirement of at least some cores in the multi-core processor is level 2, a configuration scheme corresponding to the multi-core processor to be configured is selected from configuration schemes other than a configuration scheme in which all cores share one instruction set operation unit based on the different vector instruction set extension requirements of each core in the multi-core processor, including:

[0065] When the chip area requirement of the multi-core processor to be configured is level 2 and some of the cores in all the cores in the multi-core processor have level 2 requirements for vector instruction set extension, the current configuration scheme corresponding to the multi-core processor to be configured is to configure an instruction set operation unit for each of the cores in the multi-core processor, wherein each core configured with an instruction set operation unit has level 2 requirements for vector instruction set extension, and each core not configured with an instruction set operation unit has level 1 requirements for vector instruction set extension.

[0066] See also Figure 4 In a multi-core processor system, when balancing area and ISA performance, ISAs can be allocated to some cores. Specifically, an ISA is allocated to each core that requires ISA performance, while cores that do not require ISA performance are left without one. This configuration optimizes the distribution of ISAs in the multi-core processor system, enabling deep coupling of diverse application requirements.

[0067] In an optional embodiment of the present application, when the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirement of at least some cores in the multi-core processor is level 2, a configuration scheme corresponding to the multi-core processor to be configured is selected from configuration schemes other than a configuration scheme in which all cores share one instruction set operation unit based on the different vector instruction set extension requirements of each core in the multi-core processor, including:

[0068] When the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirements of all cores in the multi-core processor are all level 2, if the instruction set processing time of all cores is dispersed in multiple time periods, and after all cores are grouped according to the instruction set processing time, the instruction set processing time of each group of cores does not conflict, then the current configuration scheme of the multi-core processor is to group all the cores of the multi-core processor, and each group of cores shares one instruction set operation unit.

[0069] See also Figure 5When the multi-core processor system needs to consider both area and computing performance, the cores in the multi-core processor system are sequentially or randomly grouped, and a shared instruction set operation unit is provided for each group of cores. In this way, the multi-core processor system can reduce the area and consider the computing performance.

[0070] In an optional embodiment of the present application, when the chip area requirement of the multi-core processor to be configured is two levels and the vector instruction set extension requirement of at least part of the cores in the multi-core processor is two levels, a configuration scheme corresponding to the current multi-core processor to be configured is selected from the configuration schemes other than sharing one instruction set operation unit by all cores according to the different vector instruction set extension requirements of each core in the multi-core processor, including:

[0071] When the chip area requirement of the multi-core processor to be configured is two levels and the vector instruction set extension requirement of all cores in the multi-core processor is two levels, if the instruction set processing time of all cores is concentrated in a preset period, the configuration scheme of the current multi-core processor is that all cores of the multi-core processor freely share multiple instruction set operation units, and the number of instruction set operation units is less than the number of cores of the multi-core processor.

[0072] Referring to Figure 6 When the multi-core processor system needs to consider both area and instruction set processing performance, and efficiently utilizes the instruction request of each core, the multi-core processor system is configured with freely shared instruction set operation units, which can maximize the utilization rate of each instruction set operation unit, and each core can schedule all instruction set operation units. In this way, the multi-core processor system can reduce the area while not losing the instruction set processing performance of full configuration, and fully utilizes the resources of the instruction set operation units.

[0073] In an optional embodiment of the present application, Figure 6 The cores and instruction set operation units in the multi-core processor system are connected as master devices and slave devices through a configurable bus interconnection network to generate a bus interconnection system. The workflow of the bus interconnection system includes the following steps:

[0074] The permission information is configured on each master device, and the permission information includes security information and access device identification information;

[0075] The permission information of each master device is sent to the corresponding slave device port through the user command bit field of the bus;

[0076] The slave device port verifies the received permission information, and executes subsequent business logic in the case of passing the verification, and terminates the request and returns a response error in the case of passing the verification.

[0077] In an optional embodiment of the present application, the permission information of the master device is obtained through bus bundling or programming. In the case that the permission information of the master device is obtained through bus bundling, the address of the slave device port corresponding to the current master device is unique. In the case that the permission information of the master device is obtained through programming, the slave device port corresponding to the current master device includes multiple address intervals.

[0078] In an optional embodiment of the present application, for the slave device port with a unique address, the port security information, the read-write-execute permission information and the vector logic module information are configured.

[0079] For the slave device port with multiple address intervals, multiple address regions and the region enable information, the region base address, the region address mask, the region security information, the read-write-execute permission information and the vector logic module information corresponding to each address region are configured.

[0080] In an optional embodiment of the present application, in the case that the address of the slave device port is unique, the slave device port verifies the received permission information, including:

[0081] If the received permission information is security information and the slave device port is not secure, it is determined that the verification is passed. If the received permission information is security information and the slave device port is secure, it is determined that the verification is passed if the received permission information meets the requirements of the read-write-execute permission information and the vector logic module information at the same time. If the received permission information is not security information and the slave device port is secure, it is determined that the verification is not passed. If the received permission information is not security information and the slave device port is not secure, it is determined that the verification is passed if the received permission information meets the requirements of the read-write-execute permission information and the vector logic module information at the same time.

[0082] In an optional embodiment of the present application, in the case that the slave device port includes multiple address intervals, the slave device port verifies the received permission information, including:

[0083] The transmission address in the received permission information is compared with the multiple address intervals. If the transmission address matches the base address and the address mask of the target region, and the region enable of the target region has been opened, the received permission information is verified according to the region security information, the read-write-execute permission information and the vector logic module information of the target region.

[0084] In an optional embodiment of the present application, the received permission information is verified according to the region security information, the read-write-execute permission information and the vector logic module information of the target region, including:

[0085] If the received permission information is security information and the region of the target region is not safe, it is determined that the test passes; if the received permission information is security information and the region of the target region is safe, it is determined that the test passes if the received permission information meets the requirements of the read-write-execute permission information and the vector logic module information at the same time; if the received permission information is not security information and the region of the target region is safe, it is determined that the test does not pass; if the received permission information is not security information and the region of the target region is not safe, it is determined that the test passes if the received permission information meets the requirements of the read-write-execute permission information and the vector logic module information at the same time.

[0086] In an optional embodiment of the present application, the plurality of address intervals includes a specified address interval and a non-specified address interval, and the comparison of the transmission address in the received permission information with the plurality of address intervals includes:

[0087] Comparing the transmission address in the received permission information with the non-specified address interval;

[0088] In a case where the transmission address does not match the base address and the address mask of each address interval in the non-specified address interval, it is determined that the transmission address matches the base address and the address mask of the specified address interval.

[0089] In an optional embodiment of the present application, in the three application scenarios of sharing one instruction set operation unit within each group of cores, all cores of the multi-core processor freely sharing a plurality of instruction set operation units, and all cores of the multi-core processor sharing one instruction set operation unit, the method further includes:

[0090] For a plurality of cores sharing one instruction set operation unit, in a case where at least two cores simultaneously issue instruction set processing requests to the shared one instruction set operation unit, the plurality of cores simultaneously issuing instruction set processing requests are arbitrated according to a preset arbitration mechanism to determine the processing order of the plurality of instruction set processing requests by the shared one instruction set operation unit.

[0091] In an optional embodiment of the present application, the preset arbitration mechanism can be an instruction set processing priority of the core, and the plurality of cores simultaneously issuing instruction set processing requests are ordered according to the instruction set processing priority to obtain an instruction set processing order of the core.

[0092] Based on the flexibility and modularity of the RSIC-V instruction architecture, the present application provides a variety of schemes for configuring instruction set operation units to cope with different application scenarios of multi-core processor chips, so that the multi-core processor system is more flexible and efficient in using instruction set operation units.

[0093] It should be understood that although the steps in the flowchart are shown in a sequential order, the steps are not necessarily performed in the order shown by the arrows. Unless explicitly stated otherwise, the steps can be performed in other orders. Also, at least some of the steps can include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but can be performed at different times, and the order of the sub-steps or stages can not be sequential, but can be interleaved or alternated with at least some of the other steps or sub-steps or stages of other steps.

[0094] Referring to Figure 7 An embodiment of the present application provides a configuration device 700 of an instruction set operation unit in a multi-core processor, comprising:

[0095] An obtaining module 710 is configured to obtain a chip area requirement of a multi-core processor to be configured and a vector instruction set extension requirement of each core in the multi-core processor;

[0096] A selecting module 720 is configured to select, from preset instruction set operation unit configuration schemes, a configuration scheme corresponding to a current multi-core processor to be configured according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor;

[0097] A configuring module 730 is configured to configure, based on the configuration scheme, an instruction set operation unit in the current multi-core processor,

[0098] The preset instruction set operation unit configuration scheme is one of the following four configuration schemes:

[0099] For some cores in the multi-core processor, one instruction set operation unit is configured for each core;

[0100] All cores of the multi-core processor are grouped, and each group of cores shares one instruction set operation unit;

[0101] All cores of the multi-core processor share multiple instruction set operation units, and the number of instruction set operation units is less than the number of cores of the multi-core processor;

[0102] All cores of the multi-core processor share one instruction set operation unit.

[0103] The configuration device of the instruction set operation unit in the multi-core processor of the present application provides a configuration of the instruction set operation unit different from that of a conventional multi-core processor system, and provides four unique schemes to meet the compromise requirements of the area and instruction set processing performance of the multi-core processor system in different application scenarios.

[0104] The specific definitions of the apparatus 700 can refer to the above definitions of the configuration method of the instruction set operation unit in the multi-core processor, and will not be repeated here. Each module in the apparatus 700 can be implemented by software, hardware, and a combination thereof. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0105] In one embodiment, a computer device is provided, and an internal structure diagram of the computer device can be as shown in Figure 8 The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The database of the computer device is configured to store data. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement the above method for configuring an instruction set operation unit in a multi-core processor. The method includes: including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement any step in the method for configuring an instruction set operation unit in a multi-core processor.

[0106] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement any step in the above method for configuring an instruction set operation unit in a multi-core processor.

[0107] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0108] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0109] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0110] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0111] While the preferred embodiments of the application have been described, additional variations and modifications can be employed by those skilled in the art. Therefore, the appended claims intend to cover all such modifications and variations as fall within the true spirit and scope of the application.

[0112] It is apparent that a person skilled in the art can make various changes and modifications to the application without departing from the spirit and scope thereof. Therefore, if these modifications and changes fall within the scope of the claims and their equivalents, it is intended to include them in the application.

Claims

1. A method for configuring an instruction set operation unit in a multi-core processor, characterized in that: include: Obtain the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor; Selecting a configuration scheme corresponding to the multi-core processor to be configured from preset instruction set operation unit configuration schemes according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor; Based on the configuration scheme, the instruction set operation unit is configured in the current multi-core processor. The preset instruction set operation unit configuration scheme is one of the following four configuration schemes: For some cores in a multi-core processor, each core is configured with an instruction set operation unit; All cores of a multi-core processor are grouped, and each group of cores shares an instruction set operation unit; All cores of the multi-core processor freely share multiple instruction set operation units, wherein the number of instruction set operation units is less than the number of cores of the multi-core processor; All cores in a multi-core processor share an instruction set operation unit. The core and the instruction set operation unit are respectively used as a master device and a slave device connected through a configurable bus interconnection network to form a bus interconnection system. The workflow of the bus interconnection system includes the following steps: Each master device is configured with permission information, wherein the permission information includes security information and access device identification information; Sending the permission information of each master device to the corresponding slave device port via the user command bit field of the bus; The received permission information is checked from the device port. If the check passes, the subsequent business logic is executed. If the check fails, the request is terminated and a response error is returned.

2. The method according to claim 1, characterized in that The chip area requirements of the multi-core processor to be configured include a first-level chip area and a second-level chip area, wherein the first-level chip area is smaller than the second-level chip area, and the vector instruction set extension requirements of each core in the multi-core processor include a first-level vector instruction set extension requirement and a second-level vector instruction set extension requirement, wherein the first-level vector instruction set extension requirement is smaller than the second-level vector instruction set extension requirement.

3. The method according to claim 2, characterized in that Based on the chip area requirements and the vector instruction set extension requirements of each core in the multi-core processor, a configuration scheme corresponding to the multi-core processor to be configured is selected from the preset instruction set operation unit configuration schemes, including: When the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor are both level 1, the current configuration scheme of the multi-core processor to be configured is that all cores in the multi-core processor share one instruction set operation unit; When the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirement of at least some cores in the multi-core processor is level 2, based on the different vector instruction set extension requirements of each core in the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured is selected from configuration schemes other than configuration schemes in which all cores share one instruction set operation unit.

4. The method according to claim 3, characterized in that When the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirement of at least some cores in the multi-core processor is level 2, a configuration scheme corresponding to the multi-core processor to be configured is selected from configuration schemes other than a configuration scheme in which all cores share one instruction set operation unit based on different vector instruction set extension requirements of each core in the multi-core processor, including: When the chip area requirement of the multi-core processor to be configured is level 2 and some of the cores in all the cores in the multi-core processor have level 2 requirements for vector instruction set extension, the current configuration scheme corresponding to the multi-core processor to be configured is to configure an instruction set operation unit for each of the cores in the multi-core processor, wherein each core configured with an instruction set operation unit has level 2 requirements for vector instruction set extension, and each core not configured with an instruction set operation unit has level 1 requirements for vector instruction set extension.

5. The method according to claim 3, characterized in that When the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirement of at least some cores in the multi-core processor is level 2, a configuration scheme corresponding to the multi-core processor to be configured is selected from configuration schemes other than a configuration scheme in which all cores share one instruction set operation unit based on different vector instruction set extension requirements of each core in the multi-core processor, including: When the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirements of all cores in the multi-core processor are all level 2, if the instruction set processing time of all cores is dispersed in multiple time periods, and after all cores are grouped according to the instruction set processing time, the instruction set processing time of each group of cores does not conflict, then the current configuration scheme of the multi-core processor is to group all the cores of the multi-core processor, and each group of cores shares one instruction set operation unit.

6. The method according to claim 3, characterized in that When the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirement of at least some cores in the multi-core processor is level 2, a configuration scheme corresponding to the multi-core processor to be configured is selected from configuration schemes other than a configuration scheme in which all cores share one instruction set operation unit based on different vector instruction set extension requirements of each core in the multi-core processor, including: When the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirements of all cores in the multi-core processor are all level 2, if the instruction set processing time of all cores is concentrated within a preset time period, the current configuration scheme of the multi-core processor is that all cores of the multi-core processor freely share multiple instruction set operation units, where the number of instruction set operation units is less than the number of cores of the multi-core processor.

7. The method according to claim 1, characterized in that The method further comprises: For multiple cores sharing an instruction set operation unit, when at least two cores simultaneously issue instruction set processing requests to the shared instruction set operation unit, the instruction set processing requests simultaneously issued by the multiple cores are arbitrated according to a preset arbitration mechanism to determine the processing order of the multiple instruction set processing requests by the shared instruction set operation unit.

8. A configuration device for an instruction set operation unit in a multi-core processor, characterized in that: include: An acquisition module, used to obtain the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor; A selection module is used to select a configuration scheme corresponding to the multi-core processor to be configured from preset instruction set operation unit configuration schemes based on chip area requirements and vector instruction set extension requirements of each core in the multi-core processor; A configuration module, configured to configure the instruction set operation unit in the current multi-core processor based on the configuration scheme, The preset instruction set operation unit configuration scheme is one of the following four configuration schemes: For some cores in a multi-core processor, each core is configured with an instruction set operation unit; All cores of a multi-core processor are grouped, and each group of cores shares an instruction set operation unit; All cores of the multi-core processor freely share multiple instruction set operation units, wherein the number of instruction set operation units is less than the number of cores of the multi-core processor; All cores in a multi-core processor share an instruction set operation unit. The core and the instruction set operation unit are respectively used as a master device and a slave device connected through a configurable bus interconnection network to form a bus interconnection system. The workflow of the bus interconnection system includes the following steps: Each master device is configured with permission information, wherein the permission information includes security information and access device identification information; Sending the permission information of each master device to the corresponding slave device port via the user command bit field of the bus; The received permission information is checked from the device port. If the check passes, the subsequent business logic is executed. If the check fails, the request is terminated and a response error is returned.

9. A computer device comprising: It includes a memory and a processor, the memory stores a computer program, and is characterized in that when the processor executes the computer program, it implements the steps of the configuration method of the instruction set operation unit in the multi-core processor according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for configuring the instruction set operation unit in the multi-core processor according to any one of claims 1 to 7 are implemented.

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