A circuit for entering chip debugging mode after power-on

Abstract

The present application relates to a circuit for entering a chip debugging mode after power-on, comprising a power-on detection module, an input state latch module, an input module, a data clock separation module, a shift register, and an efuse module; the power-on detection module is used to detect the access status of the power supply, and its output end is electrically connected to the first input end of the input state latch module through a delay module; a chip pin PIN1 is electrically connected to the input end of the data clock separation module and the input module; the first output end and the second output end of the data clock separation module are both electrically connected to the input state latch module and the shift register; the input state latch module is electrically connected to the shift register, and the output end of the shift register is electrically connected to the input end of the efuse module, and the efuse module is electrically connected to the input state latch module and the internal circuit module. The present application has the effect of operating the internal register of the chip by only sharing one pin of the chip itself.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a circuit that enters a chip debugging mode after power-on. Background Art

[0002] Chip manufacturing is a complex process with many uncontrollable factors, so the actual chips produced will generally deviate from the ideal design parameters. To debug the packaged chip, debugging circuits are usually designed into the chip to receive external data and adjust circuit parameters.

[0003] The industry often uses I2C communication to operate internal chip registers, then reads and program register values ​​through the efuse module. However, I2C communication requires at least one additional clock pin, CLK, and data pin, SDA, to operate on the chip. In some special cases, chip port resources are limited, and adding two additional pins for I2C communication is not feasible, making this solution unusable. Summary of the Invention

[0004] In order to be able to operate the internal registers of the chip and complete the chip debugging mode function by sharing only one pin of the chip itself when adding pins, the present application provides a circuit for entering the chip debugging mode after power-on.

[0005] The present application provides a circuit for entering chip debugging mode after power-on, which adopts the following technical solution:

[0006] A circuit for entering a chip debugging mode after power-on, comprising a power-on detection module, a delay module, an input state latch module, an input module, a data clock separation module, a shift register, and an efuse module; the power-on detection module is used to detect the connection status of the power supply, and the output end of the power-on detection module is electrically connected to the first input end of the input state latch module through the delay module; a chip pin Pin1 is electrically connected to the input end of the data clock separation module and the input end of the input module; the first output end of the data clock separation module is electrically connected to the second input end of the input state latch module and the first input end of the shift register; the second output end of the data clock separation module is electrically connected to the third input end of the input state latch module and the second input end of the shift register; the output end of the input state latch module is electrically connected to the third input end of the shift register, and the output end of the shift register is electrically connected to the input end of the efuse module, the first output end of the efuse module is electrically connected to the fourth input end of the input state latch module, and the second output end of the efuse module is electrically connected to an internal circuit module.

[0007] By adopting the above technical solution, the power-on detection module detects power connection and provides a trigger signal for subsequent operations. The input module and data-clock separation module process the input signal from the chip's Pin 1, separating it into different data and clock signals. The shift register shifts the input serial data and stores it as parallel data for subsequent processing. The efuse module stores key information, and its output is connected to the input status latch module and the internal circuit module, respectively, to achieve data feedback and control of the internal circuit. Through the interconnection between these modules, power connection detection is achieved. The input signal is processed, latched, shifted and stored, and data exchanged with the efuse module is completed through a single pin of the chip, providing a complete circuit foundation for the chip to enter debug mode.

[0008] Preferably, the data clock separation module includes a first comparator comp1 and a second comparator comp2, a voltage output end of a power supply VDD is grounded in sequence through resistors R1, R2, R3, and R4, and the resistance values ​​of the resistors R1, R2, R3, and R4 are the same; the pin Pin1 is electrically connected to the non-inverting input end of the first comparator comp1, the connection point between the resistors R1 and R2 is electrically connected to the inverting input end of the first comparator comp1, and the output end of the first comparator comp1 is set as the first output end sda of the data clock separation module; the pin Pin1 is electrically connected to the non-inverting input end of the second comparator comp2, the connection point between the resistors R3 and R4 is electrically connected to the inverting input end of the second comparator comp2, and the output end of the second comparator comp2 is set as the second output end sd1 of the data clock separation module.

[0009] By adopting the above technical solution, multiple resistors and two comparators are used to compare the voltage signal of pin Pin1 with the reference voltage set by the voltage divider, and the input signal is separated into a signal output from the first output terminal SDA and a signal output from the second output terminal SDL.

[0010] Preferably, the power-on detection module includes a first NMOS transistor N1, a second NMOS transistor N2 and an inverter inv1; the voltage output end of the power supply VDD is electrically connected to the drain of the second NMOS transistor N2 through a resistor R5, the source of the second NMOS transistor N2 is electrically connected to the drain of the first NMOS transistor N1, and the source of the first NMOS transistor N1 is grounded; the gate of the second NMOS transistor N2 is electrically connected to the gate of the first NMOS transistor N1, and the gate of the first NMOS transistor N1 is electrically connected to the voltage output end of the power supply VDD; the drain of the second NMOS transistor N2 is electrically connected to the input end of the inverter inv1, and the output end of the inverter inv1 is set as the output end Pwr_on of the power-on detection module.

[0011] By adopting the above technical solution, the power supply VDD is connected to the drain of the second NMOS transistor N2 through the resistor R5, and the connection between the NMOS transistors and the inverter inv1 is used to detect the power-on status of the power supply VDD, and the detection result is output through the inverter inv1 to form a power-on detection signal.

[0012] Preferably, the power-on detection module also includes an inverter inv2 and an inverter inv3, the output end of the inverter inv1 is electrically connected to the input end of the inverter inv2, the output end of the inverter inv2 is electrically connected to the input end of the inverter inv3, and the output end of the inverter inv3 is set as the output end Pwr_on of the power-on detection module.

[0013] By adopting the above technical solution, by passing the output of inverter inv1 through inv2 and inv3 in sequence, the output power-on detection signal can be buffered and shaped, thereby ensuring the quality of the output signal, avoiding signal jitter and glitches, improving the stability and reliability of the signal, and enabling subsequent circuits to receive a more stable power-on trigger signal.

[0014] Preferably, the delay module includes a plurality of buffers electrically connected in sequence, the output end of the power-on detection module passes through the plurality of buffers in sequence, and the output end of the last buffer is set as the output end Pwr_on1 of the delay module.

[0015] By adopting the above technical solution and utilizing the delay characteristics of the buffer to delay the signal, after receiving the output signal of the power-on detection module, the signal can be output after a certain time delay, thereby achieving time coordination between different operations in the circuit, ensuring that each module operates in a predetermined time sequence, and avoiding conflicts between signals.

[0016] Preferably, the input state latch module includes a first D flip-flop FF1, a second D flip-flop FF2, an inverter inv4 and a NOR gate; the first output end of the data clock separation module is electrically connected to pin D of the first D flip-flop FF1, and the second output end sd1 of the data clock separation module is electrically connected to pin D of the second D flip-flop FF2; the output end of the delay module is electrically connected to pin CLK of the first D flip-flop FF1 and pin CLK of the second D flip-flop FF2, and the second output end Efuse_ready of the efuse module is electrically connected to pin Reset of the first D flip-flop FF1 and pin Reset of the second D flip-flop FF2; pin Q of the first D flip-flop FF1 is electrically connected to the first input end of the NOR gate, pin Q of the second D flip-flop FF2 is electrically connected to the input end of the inverter inv4, the output end of the inverter inv4 is electrically connected to the second input end of the NOR gate, and the output end of the NOR gate is set to the output end Testmode_on of the input state latch module.

[0017] By adopting this technical solution, the output signal of the data-clock separation module serves as the input of a D-type flip-flop, the output of the delay module serves as the clock signal, and the output of the efuse module serves as the reset signal. The D-type flip-flop latches the input state, processes it through an inverter and a NOR gate, and ultimately outputs the test mode-on signal, Testmode_on. This module can latch the input state under appropriate clock and reset signals, providing a stable test mode control signal for subsequent circuit operations.

[0018] Preferably, the shift register includes a D flip-flop FF3, a D flip-flop FF4, a D flip-flop FF5, a D flip-flop FF6 and an inverter Inv5; the output terminal Testmode_en of the input state latch module is electrically connected to the input terminal of the inverter Inv5, and the output terminal of the inverter Inv5 is electrically connected to the pin Reset of the D flip-flops FF3, D flip-flops FF4, D flip-flops FF5 and D flip-flops FF6; the output terminal scl of the data clock separation module is electrically connected to the pin clk of the flip-flops FF3, D flip-flops FF4, D flip-flops FF5 and D flip-flops FF6; the output terminal sda of the data clock separation module is electrically connected to the pin D of the D flip-flop FF3, the pin Q of the D flip-flop FF3 is electrically connected to the pin D of the D flip-flop FF4, the pin Q of the D flip-flop FF4 is electrically connected to the pin D of the D flip-flop FF5, and the pin Q of the D flip-flop FF5 is electrically connected to the D of the D flip-flop FF6; the pins Q of the D flip-flops FF3, D flip-flops FF4, D flip-flops FF5 and D flip-flops FF6 are all electrically connected to the input terminal of the efuse module.

[0019] By adopting this technical solution, the output of the input state latch module resets the flip-flop through inverter Inv5. The output of the data-clock separation module serves as the clock signal and data signal, and data shift storage is implemented through multiple D flip-flops. The input serial data is sequentially shifted and stored in multiple D flip-flops, ultimately forming parallel data output to the efuse module, completing the conversion from serial data to parallel data and facilitating data storage and processing in the efuse module.

[0020] Preferably, when power is applied at time t0, the output voltage of the power supply VDD begins to rise, and the output voltage of the power supply VDD stabilizes at a high level after t1; the pin Pin1 outputs a voltage of VDD / 2 at time t0; the power-on detection module detects that the VDD power supply is successfully powered on at time t1, and the output terminal of the power-on detection module outputs a high level at this time. At the same time, the data clock separation module detects the output voltage of pin Pin1, and the first output terminal of the data clock separation module outputs a high level and the second output terminal outputs a low level at this time; at time t1, the delay module receives the output signal of the power-on detection module and starts timing, and at time t2, the delay module outputs a high level; at time t2, the input state latch module receives the rising edge of the output of the delay module, internally records the states of the first output terminal and the second output terminal of the data clock separation module at this time, and outputs a high level at the same time, at which time the input module is closed, the shift register module is opened, and the efuse module is opened; after time t2, the shift register module receives the output signals of the first output terminal and the second output terminal of the data clock separation module, shifts the serial data into the register to form parallel data.

[0021] By adopting the above technical solution, the voltage changes of the power supply and Pin 1 at power-on at time t0, and the subsequent signal changes and operation sequences of each module at times t1 and t2, etc., are clearly defined. For example, at time t1, the power-on detection is successful and the data clock separation module begins operation; at time t2, the delay module outputs a high level, the input status latch module records the status, and the shift register begins receiving data. This provides a clear time sequence basis for circuit debugging and performance analysis, helping to understand the circuit workflow and troubleshooting.

[0022] In summary, the present application includes at least one of the following beneficial technical effects: by using only one pin Pin1 to realize the operation and debugging of the internal register of the chip, the problem of port resource shortage caused by adding additional pins in the prior art is effectively solved; by utilizing the power-on detection module and the delay module to work together, precise timing control is achieved, ensuring that the chip can reliably enter the debugging mode after power-on, thereby improving the success rate and stability of debugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a principle block diagram of an embodiment of the present application;

[0024] Figure 2 This is a simulation diagram of an embodiment of the present application;

[0025] Figure 3 1 is a circuit diagram of a data clock separation module in an embodiment of the present application;

[0026] Figure 4 1 is a circuit diagram of a power-on detection module in an embodiment of the present application;

[0027] Figure 5 1 is a circuit diagram of a delay module in an embodiment of the present application;

[0028] Figure 6 1 is a circuit diagram of an input state latch module in an embodiment of the present application;

[0029] Figure 7 1 is a circuit diagram of a shift register module in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following is combined with Figure 1-7 This application is described in further detail.

[0031] An embodiment of the present application discloses a circuit for entering a chip debugging mode after power-on.

[0032] Reference Figure 1 A circuit for entering chip debugging mode after power-on includes a power-on detection module, a delay module, an input state latch module, an input module, a data clock separation module, and a shift register. The power-on detection module is used to detect the connection status of the power supply, and the output terminal Pwr_on of the power-on detection module is electrically connected to the first input terminal of the input state latch module through the delay module. The chip pin Pin1 is electrically connected to the input terminal of the data clock separation module and the input terminal of the input module. The first output terminal sda of the data clock separation module is electrically connected to the second input terminal of the input state latch module and the first input terminal of the shift register; the second output terminal sdl of the data clock separation module is electrically connected to the third input terminal of the input state latch module and the second input terminal of the shift register. The output terminal Testmode_on of the input state latch module is electrically connected to the third input terminal of the shift register, and the output terminal of the shift register is electrically connected to the input terminal of the efuse module, the first output terminal of the efuse module is electrically connected to the fourth input terminal of the input state latch module, and the second output terminal of the efuse module is electrically connected to the internal circuit module.

[0033] Reference Figure 2The embodiment of the present application includes two working modes. t0-t2 is a post-power-on adjustment test mode, and after t2 is a register data write mode. Power is turned on at time t0, and the output voltage value of the power supply VDD begins to rise, and after t1, it outputs a stable high level. Pin Pin1 outputs a voltage value of VDD / 2 at time t0. The power-on detection module detects that the VDD power supply is successfully powered on at time t1. At this time, the output terminal Pwr_on of the power-on detection module outputs a high level; at the same time, the data clock separation module detects the output voltage of pin Pin1, and the first output terminal sda outputs a high level, and the second output terminal sdl outputs a low level.

[0034] Reference Figure 3 The data clock separation module includes a first comparator comp1 and a second comparator comp2. The voltage output terminal of the power supply VDD is connected to ground in sequence through resistors R1, R2, R3, and R4. In this embodiment, the resistance values ​​of resistors R1, R2, R3, and R4 are the same. Pin Pin1 is electrically connected to the non-inverting input terminal of the first comparator comp1, and the connection point between resistors R1 and R2 is electrically connected to the inverting input terminal of the first comparator comp1. The output terminal of the first comparator comp1 is set as the first output terminal sda of the data clock separation module. Pin Pin1 is electrically connected to the non-inverting input terminal of the second comparator comp2, and the connection point between resistors R3 and R4 is electrically connected to the inverting input terminal of the second comparator comp2. The output terminal of the second comparator comp2 is set as the second output terminal sdl of the data clock separation module.

[0035] The voltage at the inverting input of the first comparator comp1 is VDD / 4, and the voltage at the inverting input of the second comparator comp2 is 3*VDD / 4. When the output voltage of pin Pin1 reaches VDD / 2, the output terminal sda of the first comparator comp1 outputs a high level, and the output terminal sdl of the second comparator comp2 outputs a low level. By controlling the output voltage of pin Pin1, the output terminal sda can be controlled to output a high / low level, and the output terminal sdl can be controlled to output a low / high level.

[0036] refer to Figure 4The power-on detection module includes a first NMOS transistor N1, a second NMOS transistor N2, an inverter inv1, an inverter inv2, and an inverter inv3. The voltage output terminal of the power supply VDD is electrically connected to the drain of the second NMOS transistor N2 through a resistor R5. The source of the second NMOS transistor N2 is electrically connected to the drain of the first NMOS transistor N1. The source of the first NMOS transistor N1 is grounded. The gate of the second NMOS transistor N2 is electrically connected to the gate of the first NMOS transistor N1, and the gate of the first NMOS transistor N1 is electrically connected to the voltage output terminal of the power supply VDD. The drain of the second NMOS transistor N2 is electrically connected to the input terminal of the inverter inv1, the output terminal of the inverter inv1 is electrically connected to the input terminal of the inverter inv2, the output terminal of the inverter inv2 is electrically connected to the input terminal of the inverter inv3, and the output terminal of the inverter inv3 is set as the output terminal Pwr_on of the power-on detection module.

[0037] When the power supply VDD is powered on, the gate voltages of the first NMOS transistor N1 and the second NMOS transistor N2 are pulled high, thereby turning on the first NMOS transistor N1 and the second NMOS transistor N2. This causes the voltage at the input of the inverter inv1 to be pulled low via the first NMOS transistor N1 and the second NMOS transistor N2, thereby causing the output of the inverter inv1 to output a high level, the output of the inverter inv2 to output a level, and the output of the inverter inv3 to output a high level. That is, when the power supply VDD is powered on, the output terminal Pwr_on of the power-on detection module outputs a high level.

[0038] refer to Figure 5 The delay module includes multiple buffers electrically connected in series. The power-on detection module's output, Pwr_on, passes through each buffer in sequence, with the output of the last buffer set as the delay module's output, Pwr_on1. When multiple buffers are connected in series, the signal must pass through each buffer in turn, inducing a certain propagation delay in each buffer. These delays accumulate, thus delaying the signal.

[0039] At time t1, the delay module starts timing when it receives a high level output from the output terminal Pwr_on of the power-on detection module. At time t2, the output terminal Pwr_on1 of the delay module outputs a high level.

[0040] refer to Figure 6The input state latch module includes a first D flip-flop FF1, a second D flip-flop FF2, an inverter inv4, and a NOR gate. The first output terminal sda of the data clock separation module is electrically connected to pin D of the first D flip-flop FF1, and the second output terminal sdl of the data clock separation module is electrically connected to pin D of the second D flip-flop FF2. The output terminal Pwr_on1 of the delay module is electrically connected to pins CLK of the first D flip-flop FF1 and CLK of the second D flip-flop FF2. The second output terminal Efuse_ready of the fuse module is electrically connected to pins Reset of the first D flip-flop FF1 and Reset of the second D flip-flop FF2. Pin Q of the first D flip-flop FF1 is electrically connected to the first input terminal of the NOR gate, pin Q of the second D flip-flop FF2 is electrically connected to the input terminal of inverter inv4, and the output terminal of inverter inv4 is electrically connected to the second input terminal of the NOR gate. The output terminal of the NOR gate is set to the output terminal Testmode_on of the input state latch module.

[0041] At time t2, the output voltage value of the output terminal Pwr_on of the delay module is on the rising edge, and the pin D of the first D flip-flop FF1 receives a low level, and the pin D of the second D flip-flop FF2 receives a high level; at this time, the pin Q of the first D flip-flop FF1 outputs a low level, and the pin Q of the second D flip-flop FF2 outputs a high level, so that the first input terminal of the NOR gate receives a low level, the second input terminal of the NOR gate receives a low level, and the NOR gate outputs a high level.

[0042] When the output terminal Testmode_en of the input state latch module outputs a high level, the input module is turned off, the shift register module is turned on, and the efuse module is turned on.

[0043] refer to Figure 7The shift register includes D flip-flops FF3, FF4, FF5, FF6, and an inverter Inv5. The output terminal Testmode_en of the input state latch module is electrically connected to the input terminal of inverter Inv5, and the output terminal of inverter Inv5 is electrically connected to the Reset pin of the D flip-flops FF3, FF4, FF5, and FF6. The output terminal scl of the data clock separation module is electrically connected to the clk pin of the flip-flops FF3, FF4, FF5, and FF6. The output terminal sda of the data clock separation module is electrically connected to pin D of the D flip-flop FF3, pin Q of the D flip-flop FF3 is electrically connected to pin D of the D flip-flop FF4, pin Q of the D flip-flop FF4 is electrically connected to pin D of the D flip-flop FF5, and pin Q of the D flip-flop FF5 is electrically connected to pin D of the D flip-flop FF6. Pin Q of the D flip-flops FF3, FF4, FF5, and FF6 are all electrically connected to the input terminal of the efuse module. When the output terminal Testmode_en outputs a high level, the shift register starts working and shifts the serial data into the register to form parallel data.

[0044] The implementation principle of a circuit for entering chip debugging mode after power-on in an embodiment of the present application is as follows: when power is applied at time t0, the output voltage value of the power supply VDD begins to rise, and the output voltage value of pin Pin1 at time t0 is VDD / 2; the power-on detection module detects that the VDD power supply is successfully powered on at time t1, and at this time the output terminal Pwr_on of the power-on detection module outputs a high level, and at the same time the data clock separation module detects the output voltage of pin Pin1, and at this time the first output terminal sda of the data clock separation module outputs a high level, and the second output terminal scl outputs a low level; at time t1, the delay module receives The power-on detection module receives the output signal and begins timing. At time t2, the output terminal Pwr_on1 of the delay module outputs a high level. At time t2, the input state latch module receives the rising edge of the delay module's output and internally records the output status of the data clock separation module's first output terminal SDA and second output terminal SCL at that time, while simultaneously outputting a high level. At this point, the input module is closed, the shift register module is opened, and the efuse module is opened. After time t2, the shift register module receives the output signal of the data clock separation module and shifts the serial data into the register to form parallel data. By using only one pin, Pin1, to operate and debug the chip's internal registers, the port resource shortage problem caused by the addition of additional pins in the prior art is effectively resolved.

[0045] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A circuit for entering a chip debugging mode after power-on, characterized in that: It includes a power-on detection module, a delay module, an input state latch module, an input module, a data clock separation module, a shift register and an efuse module; the power-on detection module is used to detect the access status of the power supply, and the output end of the power-on detection module is electrically connected to the first input end of the input state latch module through the delay module; the chip pin Pin1 is electrically connected to the input end of the data clock separation module and the input end of the input module; the first output end of the data clock separation module is electrically connected to the second input end of the input state latch module and the first input end of the shift register; the second output end of the data clock separation module is electrically connected to the third input end of the input state latch module and the second input end of the shift register; the output end of the input state latch module is electrically connected to the third input end of the shift register, and the output end of the shift register is electrically connected to the input end of the efuse module, the first output end of the efuse module is electrically connected to the fourth input end of the input state latch module, and the second output end of the efuse module is electrically connected to the internal circuit module; At time t0, power is applied, and the output voltage of the power supply VDD begins to rise. After time t1, the output voltage of the power supply VDD stabilizes and outputs a high level. At time t0, the pin Pin1 outputs a voltage of VDD / 2. At time t1, the power-on detection module detects that the VDD power supply is successfully powered on, and the output terminal of the power-on detection module outputs a high level. At the same time, the data clock separation module detects the output voltage of pin Pin1, and the first output terminal of the data clock separation module outputs a high level and the second output terminal outputs a low level. At time t1, the delay module receives the output signal of the power-on detection module and starts timing. At time t2, the delay module outputs a high level. At time t2, the input state latch module receives the rising edge of the delay module output, internally records the states of the first and second output terminals of the data clock separation module at this time, and outputs a high level. At this time, the input module is closed, the shift register module is opened, and the efuse module is opened. After time t2, the shift register module receives the output signals of the first and second output terminals of the data clock separation module and shifts the serial data into the register to form parallel data.

2. The circuit for entering a chip debugging mode after power-on according to claim 1, characterized in that: The data clock separation module includes a first comparator comp1 and a second comparator comp2. A voltage output terminal of a power supply VDD is grounded in sequence through resistors R1, R2, R3, and R4, and the resistance values ​​of the resistors R1, R2, R3, and R4 are the same. The pin Pin1 is electrically connected to the non-inverting input terminal of the first comparator comp1, and the connection point between the resistors R1 and R2 is electrically connected to the inverting input terminal of the first comparator comp1. The output terminal of the first comparator comp1 is set as the first output terminal sda of the data clock separation module. The pin Pin1 is electrically connected to the non-inverting input terminal of the second comparator comp2, and the connection point between the resistors R3 and R4 is electrically connected to the inverting input terminal of the second comparator comp2. The output terminal of the second comparator comp2 is set as the second output terminal sd1 of the data clock separation module.

3. The circuit for entering a chip debugging mode after power-on according to claim 1, wherein: The power-on detection module includes a first NMOS transistor N1, a second NMOS transistor N2, and an inverter inv1; a voltage output terminal of a power supply VDD is electrically connected to the drain of the second NMOS transistor N2 through a resistor R5, a source of the second NMOS transistor N2 is electrically connected to the drain of the first NMOS transistor N1, and the source of the first NMOS transistor N1 is grounded; a gate of the second NMOS transistor N2 is electrically connected to the gate of the first NMOS transistor N1, and the gate of the first NMOS transistor N1 is electrically connected to the voltage output terminal of the power supply VDD; a drain of the second NMOS transistor N2 is electrically connected to the input terminal of the inverter inv1, and an output terminal of the inverter inv1 is set as an output terminal Pwr_on of the power-on detection module.

4. The circuit for entering chip debugging mode after power-on according to claim 3, characterized in that: The power-on detection module also includes an inverter inv2 and an inverter inv3. The output end of the inverter inv1 is electrically connected to the input end of the inverter inv2, the output end of the inverter inv2 is electrically connected to the input end of the inverter inv3, and the output end of the inverter inv3 is set as the output end Pwr_on of the power-on detection module.

5. The circuit for entering a chip debugging mode after power-on according to claim 1, wherein: The delay module includes a plurality of buffers electrically connected in sequence. The output end of the power-on detection module passes through the plurality of buffers in sequence, and the output end of the last buffer is set as the output end Pwr_on1 of the delay module.

6. The circuit for entering a chip debugging mode after power-on according to claim 1, characterized in that: The input state latch module includes a first D flip-flop FF1, a second D flip-flop FF2, an inverter inv4 and a NOR gate; the first output end of the data clock separation module is electrically connected to pin D of the first D flip-flop FF1, and the second output end sd1 of the data clock separation module is electrically connected to pin D of the second D flip-flop FF2; the output end of the delay module is electrically connected to pin CLK of the first D flip-flop FF1 and pin CLK of the second D flip-flop FF2, and the second output end Efuse_ready of the efuse module is electrically connected to pin Reset of the first D flip-flop FF1 and pin Reset of the second D flip-flop FF2; pin Q of the first D flip-flop FF1 is electrically connected to the first input end of the NOR gate, pin Q of the second D flip-flop FF2 is electrically connected to the input end of the inverter inv4, the output end of the inverter inv4 is electrically connected to the second input end of the NOR gate, and the output end of the NOR gate is set to the output end Testmode_on of the input state latch module.

7. The circuit for entering a chip debugging mode after power-on according to claim 1, characterized in that: The shift register includes a D flip-flop FF3, a D flip-flop FF4, a D flip-flop FF5, a D flip-flop FF6 and an inverter Inv5; the output terminal Testmode_en of the input state latch module is electrically connected to the input terminal of the inverter Inv5, and the output terminal of the inverter Inv5 is electrically connected to the pin Reset of the D flip-flops FF3, D flip-flops FF4, D flip-flops FF5 and D flip-flops FF6; the output terminal scl of the data clock separation module is electrically connected to the pin CLK of the flip-flops FF3, D flip-flops FF4, D flip-flops FF5 and D flip-flops FF6; the output terminal sda of the data clock separation module is electrically connected to the pin D of the D flip-flop FF3, the pin Q of the D flip-flop FF3 is electrically connected to the pin D of the D flip-flop FF4, the pin Q of the D flip-flop FF4 is electrically connected to the pin D of the D flip-flop FF5, and the pin Q of the D flip-flop FF5 is electrically connected to the D pin of the D flip-flop FF6; the pins Q of the D flip-flops FF3, D flip-flops FF4, D flip-flops FF5 and D flip-flops FF6 are all electrically connected to the input terminal of the efuse module.

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