Wafer test data processing method and device, electronic equipment and medium

Abstract

The invention provides a wafer test data processing method and device, electronic equipment and a medium, and relates to the technical field of wafer testing, and the method comprises the steps: obtaining a test sequence composed of test data of a plurality of DIEs on a target wafer; dividing a plurality of test data in the test sequence to obtain a plurality of subsequences; converting the test data in each sub-sequence to obtain a target sub-sequence; and deleting the target subsequences meeting the deletion conditions in the corresponding processing threads. Through the BS architecture and the memory optimization technology, the problem of memory overflow when a traditional CS architecture processes large-scale wafer test data is effectively solved. The processing efficiency and the response speed of the system are improved through the technologies of data block processing, streaming processing, asynchronous generation and the like. The stability and the reliability of the system are enhanced by optimizing the memory use and the data processing flow.

Description

Technical Field

[0001] This application relates to the technical field of wafer testing, and in particular, to a method, apparatus, electronic device, and medium for processing wafer test data. Background Art

[0002] Traditional wafer test systems usually adopt a CS (Client-Server) architecture for processing test data and generating Map diagrams. However, with the increase in the number of Dies on a wafer, the traditional CS architecture is prone to memory overflow problems when processing large-scale data, resulting in system crashes or performance degradation. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide a method, apparatus, electronic device, and medium for processing wafer test data, which solves the above problems existing in the prior art and can optimally solve the problem of memory overflow when the traditional CS architecture processes test data of large-scale wafers.

[0004] In a first aspect, a method for processing wafer test data is provided, which is applied to a data processing system. The data processing system includes: a scheduling center and a thread pool; the thread pool includes multiple processing threads; the method may include:

[0005] Obtain a test sequence composed of test data of multiple DIEs on a target wafer;

[0006] Divide the multiple test data in the test sequence to obtain multiple subsequences;

[0007] Convert the test data in each subsequence to obtain target subsequences;

[0008] Delete the target subsequences that meet the deletion conditions in the corresponding processing threads.

[0009] In a possible implementation, dividing the multiple test data in the test sequence to obtain multiple subsequences includes:

[0010] Based on multiple pre-configured regions on the target wafer, divide the multiple test data in the test sequence to obtain multiple subsequences.

[0011] In a possible implementation, before processing each subsequence, the method further includes:

[0012] Process the multiple subsequences in the order of arrangement of multiple pre-configured regions on the target wafer to obtain multiple subsequences arranged in order.

[0013] In a possible implementation, dividing the multiple test data in the test sequence to obtain multiple subsequences includes:

[0014] Cluster the parameters in the test data based on the configured performance level to obtain multiple subsequences.

[0015] In a possible implementation, transform the test data in each subsequence to obtain a target subsequence, including:

[0016] After outputting the test data in XML format, convert it to the target result in EXCEL format for storage.

[0017] In a possible implementation, delete the target subsequences that meet the deletion conditions in the corresponding processing threads, including:

[0018] Determine the target level of each subsequence based on the configured weight value, weight decay factor, and last access time;

[0019] For the target level of any subsequence, if the target level meets the configured elimination level, delete the subsequence corresponding to the target level.

[0020] In a possible implementation, the configured weight value can be a base weight or a dynamic weight.

[0021] In a second aspect, a processing device for wafer test data is provided, which is applied to a data processing system. The data processing system includes: a scheduling center and a thread pool; the thread pool includes multiple processing threads; the device may include:

[0022] An acquisition unit, configured to acquire a test sequence composed of test data of multiple DIEs on a target wafer;

[0023] A partitioning unit, configured to partition the multiple test data in the test sequence to obtain multiple subsequences;

[0024] A conversion unit, configured to transform the test data in each subsequence to obtain a target subsequence;

[0025] A deletion unit, configured to delete the target subsequences that meet the deletion conditions in the corresponding processing threads.

[0026] In a third aspect, an electronic device is provided. The electronic device includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus;

[0027] The memory is used to store a computer program;

[0028] The processor, when executing the program stored in the memory, implements any of the method steps in the first aspect described above.

[0029] In a fourth aspect, a computer-readable storage medium is provided, in which a computer program is stored, and when the computer program is executed by a processor, the method steps described in any one of the above first aspects are implemented.

[0030] This application provides a method for processing wafer test data. The method includes: obtaining a test sequence composed of test data of multiple DIEs on a target wafer; dividing the multiple test data in the test sequence to obtain multiple subsequences; converting the test data in each subsequence to obtain target subsequences; and deleting the target subsequences that meet the deletion conditions in the corresponding processing threads. This application effectively solves the problem of memory overflow in traditional CS architectures when processing large-scale wafer test data through BS architecture and memory optimization techniques. Through technologies such as data block processing, streaming processing, and asynchronous generation, the processing efficiency and response speed of the system are improved. By optimizing memory usage and data processing flow, the stability and reliability of the system are enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the following will briefly introduce the drawings required to be used in the embodiments of this application. It should be understood that the following drawings only show some embodiments of this application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0032] Figure 1 It is a system architecture diagram of a data processing system provided by an embodiment of this application;

[0033] Figure 2 It is a flowchart of a method for processing wafer test data provided by an embodiment of this application;

[0034] Figure 3 It is a structural diagram of a device for processing wafer test data provided by an embodiment of this application;

[0035] Figure 4 It is a structural diagram of an electronic device provided by an embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the drawings in the embodiments of this application. Obviously, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this application.

[0037] A method for processing wafer test data provided by an embodiment of the present application can be applied in Figure 1 the system architecture shown in Figure 1 As shown, the data processing system may include: a scheduling center and a thread pool; the thread pool includes a plurality of processing threads; each processing thread further includes a plurality of sub-threads; each sub-thread can be divided according to the type of test data. The data processing system is designed based on the BS architecture.

[0038] A dedicated thread group can also be created according to the data processing stage (such as cleaning, feature extraction, defect analysis) or data type (electrical parameters, optical detection data).

[0039] Since traditional wafer test systems usually adopt the CS (Client-Server) architecture, for the processing of test data and the generation of Map diagrams; however, with the increase in the number of Dies on the wafer, the traditional CS architecture is prone to memory overflow problems when processing large-scale data, resulting in system crashes or performance degradation.

[0040] Therefore, the present application provides a method for processing wafer test data to solve the above problems existing in the prior art, and can optimally solve the memory overflow problem of the traditional CS architecture when processing test data of large-scale wafers.

[0041] The following describes the preferred embodiments of the present application with reference to the accompanying drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. And without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0042] Figure 2 It is a schematic flowchart of a method for processing wafer test data provided by an embodiment of the present application. As Figure 2 shown, the method may include:

[0043] Step S210, obtaining a test sequence composed of test data of multiple Dies on the target wafer.

[0044] Specifically, the original test data is collected and stored in the cloud database for subsequent analysis. Usually, these original test data will include identification information (such as coordinate position), test item name, test value, pass / fail status, etc. of each Die.

[0045] In some embodiments, the detailed data in the original test data is processed. For example: calculating the average value and standard deviation of the test values of the same test item among multiple Dies on the target wafer for statistical data to understand the performance distribution of Dies in the entire wafer or a partial area. This helps to identify Dies or areas with abnormal performance.

[0046] In another embodiment, for the physical layout of each DIE on the target wafer, spatial statistical methods can be applied to analyze the spatial distribution characteristics of performance and identify factors that may affect product quality (such as uniformity issues in the manufacturing process).

[0047] Step S220: Divide multiple test data in the test sequence to obtain multiple subsequences.

[0048] There can be multiple ways of division:

[0049] A. Based on multiple pre-configured regions on the target wafer, divide multiple test data in the test sequence to obtain multiple subsequences.

[0050] Specifically, based on the physical location, the configuration process of multiple regions on the target wafer can include:

[0051] Concentric circles: Divide the target wafer into multiple concentric circles expanding outward from the center. This method helps analyze radial differences caused by process steps such as etching and deposition.

[0052] Sector segments: Divide the target wafer into several equal-angle sector segments along the diameter direction. This division method is suitable for identifying process problems related to wafer rotation.

[0053] After that, the multiple subsequences can also be processed according to the arrangement order of multiple pre-configured regions on the target wafer to obtain multiple ordered subsequences.

[0054] B. Cluster the parameters in the test data based on the configured performance levels to obtain multiple subsequences.

[0055] That is, based on the analysis results of the original data, dynamically adjust the region division scheme. For example, if it is found that defects in certain specific patterns are concentrated in a certain region, the division of that region can be refined accordingly for in-depth research. Specifically, the regions can be ranked based on the analysis results.

[0056] After that, based on the levels of each region, the subsequences can be processed to obtain multiple ordered subsequences.

[0057] Step S230: Convert the test data in each subsequence to obtain target subsequences.

[0058] Specifically, for any test data, after outputting the test data in XML format, it is converted into the target result in EXCEL format for storage. Among them, this method is executed under the BS architecture, and the target result in EXCEL format after output is stored locally.

[0059] In some embodiments, the generated EXCEL file is compatible with different operating systems and software versions. The implementation method can be as follows: First, import the test data in XML format into the database. Use SQL queries to extract the required test data from the database. Utilize the database export function to save the test data in CSV or Excel format.

[0060] In this method, the test data is output to an XML file: To reduce memory consumption and prevent the CPU usage from reaching 100%, by writing the test data to an XML file, the data processing pressure in memory can be reduced, and at the same time, the storage capacity of the file system can be utilized to avoid memory overflow problems.

[0061] Step S240: Delete the target subsequence that meets the deletion condition in the corresponding processing thread.

[0062] Specifically, the following method is implemented by combining the preset cache algorithm with JVM memory management:

[0063] Determine the target level of each subsequence based on the configured weight value, weight decay factor, and last access time;

[0064] Target level = last access time + weight decay factor × weight value;

[0065] Among them, the last access time: the core indicator of the traditional LRU (the smaller the value, the longer it has not been accessed).

[0066] Weight decay factor: a parameter used to balance time and weight (for example, 0.5).

[0067] Weight value: a predefined or dynamically calculated priority value.

[0068] Among them, the dynamic calculation method can train a weight prediction model (such as a random forest) based on historical data and output the dynamic weight; the features include: DIE location, test parameter variance, associated batch yield, etc.

[0069] In this method, even if the high-weight data has not been accessed for a long time, its elimination priority may still be lower than that of the low-weight data.

[0070] Use a priority queue (Priority Queue) to replace the traditional linked list and sort the target priorities.

[0071] For the target level of any subsequence, if the target level meets the configured elimination level, delete the subsequence corresponding to the target level.

[0072] If the target level does not meet the configured elimination level, there is no need to delete the subsequence corresponding to the target level.

[0073] In Java, by implementing preset caching algorithms such as using LinkedHashMap and combining with the garbage collection mechanism of the JVM, invalid memory can be cleared in a timely manner. In the specific implementation, the LRU caching algorithm will give priority to retaining frequently used data, while less frequently used data will be released in a timely manner, thereby optimizing the memory usage efficiency. In the scenario of wafer DIE testing, the traditional LRU algorithm only eliminates the least recently used entries according to the time order of data access. However, in actual business, there may be a need to retain critical data for a long time (such as DIEs with high failure risks, data in the wafer edge area). At this time, a weight enhancement mechanism needs to be introduced. On the basis of retaining the core logic of LRU, by dynamically adjusting the elimination priority, key data can be prevented from being removed prematurely.

[0074] In another embodiment, first, the entire configured cache space is divided into several different regions, and each region corresponds to different storage rules or elimination strategies.

[0075] Protection area: Specifically used to store those critical data that must be retained for a long time, such as data of DIEs with high failure risks, data in the wafer edge area, etc. This part of the data will not be easily replaced unless they themselves also meet certain preset conditions (such as having reached the maximum retention period).

[0076] Normal area: Follows the standard LRU or other elimination strategies and is used to store general data.

[0077] A weight-based mechanism is introduced within each partition to further refine data management. Each entry has an associated weight value, which is dynamically adjusted according to its importance. For example:

[0078] For critical data, a higher initial weight can be given when it is placed in the protection area, and if this data is accessed again during the subsequent process, its weight is increased to ensure that it can also obtain a higher priority within the protection area.

[0079] In the normal area, in addition to using the usage time as the basis for elimination, the weight of the entry can also be considered. Even if an entry has not been accessed recently, but if its weight is high (indicating that it is of great significance to the business), then the time of its elimination can be appropriately postponed.

[0080] Under this hybrid strategy, when the system needs to decide whether to replace a piece of data, it will first check the region where this data is located. If it is in the protection area, replacement will only be considered when its weight is lower than a certain threshold or other specific conditions are met; if it is in the normal area, both time and weight factors will be comprehensively considered for decision-making.

[0081] In addition, certain rules can be set to allow data to migrate between different regions. For example, as the business develops, some entries that were originally not within the scope of critical data may become very important. At this time, their weights can be increased and ultimately migrated to the protected area to ensure that they are not easily lost. In this way, not only can critical data be properly preserved, but also cache resources can be effectively utilized to improve the performance and reliability of the overall system.

[0082] In some embodiments, the DIEs at the edge of the target wafer are retained;

[0083] The DIEs at the edge are prone to failure due to process fluctuations, but the test data after testing may no longer be actively accessed. Solution: Mark the weight of the edge DIEs as 3 (the weight of the central DIEs = 1) during initialization. Even if they have not been accessed for 7 days, their priority is still higher than that of the central DIEs that have not been accessed for 3 days.

[0084] In another embodiment, the monitoring of DIEs with high failure risk;

[0085] A new type of defect pattern appears in a certain batch of DIEs and needs to be tracked for a long time. Solution: When the number of defects exceeds the configured quantity threshold, automatically increase the weights of all DIEs in this batch. Manually mark the critical DIEs as "permanently retained" (weight = ∞, which needs to be managed independently).

[0086] After deleting the corresponding target subsequence in the corresponding processing thread, the processing thread is in an idle state. To improve the overall efficiency and resource utilization rate of the system, the task allocation of these processing threads can be managed through a scheduling center. When a processing thread finishes processing a specified type of subsequence, it reports its current status (for example, by sending a heartbeat message) to the scheduling center, indicating that it has become "idle". After receiving the status update from the processing thread, the scheduling center makes a decision based on the workload of all processing threads in the current system. Specifically, the scheduling center checks whether there are other processing threads of the same type that are running but have a high load. If it is found that the same type of test data is waiting to be processed and the corresponding processing thread is busy, the scheduling center can take out a part of the unprocessed data subsequences from the task queue of the busy thread. Then, these subsequences are reallocated to the processing thread that has just become idle for processing.

[0087] In this way, not only can certain processing threads be prevented from being idle for a long time, but also the pressure on those overburdened processing threads can be reduced, thereby achieving a more uniform workload distribution. This helps to improve the throughput and response speed of the entire system.

[0088] By adopting asynchronous generation technology, the process of generating Excel tables is carried out in a background thread. Through multi-threaded concurrent processing, the system can continue to process other tasks while generating Excel tables, thereby improving the overall generation efficiency.

[0089] This application provides a method for processing wafer test data, which includes: obtaining a test sequence composed of test data of multiple DIEs on a target wafer; dividing the multiple test data in the test sequence to obtain multiple subsequences; converting the test data in each subsequence to obtain target subsequences; and deleting the target subsequences that meet the deletion conditions in corresponding processing threads. This application can solve:

[0090] Memory overflow problem: Through the BS architecture and memory optimization technology, the problem of memory overflow in the traditional CS architecture when processing large-scale wafer test data is effectively solved.

[0091] Improve system performance: Through technologies such as data chunking processing, streaming processing, and asynchronous generation, the processing efficiency and response speed of the system are improved.

[0092] Reduce costs: Reduce the dependence on hardware resources and lower the overall cost of the system.

[0093] Enhance system stability: By optimizing memory usage and data processing flow, the stability and reliability of the system are enhanced.

[0094] Corresponding to the above method, an embodiment of this application also provides a device for processing wafer test data, as Figure 3 shown, the device includes:

[0095] An acquisition unit 310, configured to acquire a test sequence composed of test data of multiple DIEs on a target wafer;

[0096] A division unit 320, configured to divide the multiple test data in the test sequence to obtain multiple subsequences;

[0097] A conversion unit 330, configured to convert the test data in each subsequence to obtain target subsequences;

[0098] A deletion unit 340, configured to delete the target subsequences that meet the deletion conditions in corresponding processing threads.

[0099] The functions of each functional unit of a device for processing wafer test data provided by the above embodiment of this application can be implemented by the above method steps. Therefore, the specific working processes and beneficial effects of each unit in a device for processing wafer test data provided by an embodiment of this application will not be elaborated here.

[0100] An embodiment of the present application also provides an electronic device, such as Figure 4 shown, which includes a processor 410, a communication interface 420, a memory 430, and a communication bus 440. Among them, the processor 410, the communication interface 420, and the memory 430 communicate with each other through the communication bus 440.

[0101] The memory 430 is used to store a computer program;

[0102] When the processor 410 executes the program stored on the memory 430, the following steps are implemented:

[0103] Obtain a test sequence composed of test data of multiple DIEs on a target wafer;

[0104] Divide the multiple test data in the test sequence to obtain multiple subsequences;

[0105] Convert the test data in each subsequence to obtain a target subsequence;

[0106] Delete the target subsequence that meets the deletion condition in the corresponding processing thread.

[0107] The above-mentioned communication bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity, only a thick line is used in the figure to represent it, but it does not mean that there is only one bus or one type of bus.

[0108] The communication interface is used for communication between the above-mentioned electronic device and other devices.

[0109] The memory may include a Random Access Memory (RAM), or may also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.

[0110] The above-mentioned processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0111] Since the implementation manners and beneficial effects of the devices of the electronic device in the above embodiments for solving problems can be realized by referring to the steps in the embodiments shown in Figure 2 the specific working process and beneficial effects of the electronic device provided in the embodiments of the present application will not be described in detail here.

[0112] In another embodiment provided by the present application, a computer-readable storage medium is further provided. Instructions are stored in the computer-readable storage medium, and when it runs on a computer, it causes the computer to execute the method for processing wafer test data described in any one of the above embodiments.

[0113] In another embodiment provided by the present application, a computer program product containing instructions is further provided. When it runs on a computer, it causes the computer to execute the method for processing wafer test data described in any one of the above embodiments.

[0114] Those skilled in the art should understand that the embodiments in the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the embodiments in the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments in the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0115] Embodiments of the present application are described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments in the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0116] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means implement the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0117] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0118] Unless otherwise defined, the technical terms or scientific terms used in the present application should have the ordinary meaning understood by those of ordinary skill in the field to which the present invention belongs. The "first", "second", and similar terms used in the present application do not indicate any order, quantity, or importance, but are only used to distinguish different components. Words such as "including" or "comprising" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected", "coupled", or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0119] Although the preferred embodiments in the embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the embodiments of the present application are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0120] Obviously, those skilled in the art can make various changes and modifications to the embodiments in the embodiments of the present application without departing from the spirit and scope of the embodiments in the embodiments of the present application. Thus, if these modifications and variations of the embodiments in the embodiments of the present application fall within the scope of the embodiments of the present application and their equivalent technologies, the embodiments of the present application are also intended to include these changes and modifications.

Claims

1. A method for processing wafer test data, characterized in that, Applied to a data processing system, the data processing system includes: a scheduling center and a thread pool; the thread pool includes a plurality of processing threads; the method includes: Obtain a test sequence composed of test data of multiple DIEs on a target wafer; Divide the multiple test data in the test sequence to obtain multiple subsequences; Convert the test data in each subsequence to obtain a target subsequence; Delete the target subsequence that meets the deletion condition in the corresponding processing thread.

2. The method according to claim 1, wherein Dividing the multiple test data in the test sequence to obtain multiple subsequences includes: Based on multiple pre-configured regions on the target wafer, divide the multiple test data in the test sequence to obtain multiple subsequences.

3. The method according to claim 2, characterized in that, Before processing each subsequence, the method further includes: Process the multiple subsequences in the order of arrangement of multiple pre-configured regions on the target wafer to obtain multiple subsequences arranged in order.

4. The method according to claim 1, characterized in that, Dividing the multiple test data in the test sequence to obtain multiple subsequences includes: Cluster the parameters in the test data based on the configured performance level to obtain multiple subsequences.

5. The method according to claim 1, characterized in that, Converting the test data in each subsequence to obtain a target subsequence includes: Output the test data in XML format and then convert it to the target result in EXCEL format for storage.

6. The method according to claim 1, wherein Deleting the target subsequence that meets the deletion condition in the corresponding processing thread includes: Determine the target level of each subsequence based on the configured weight value, weight decay factor, and last access time; For the target level of any subsequence, if the target level meets the configured elimination level, delete the subsequence corresponding to the target level.

7. The method according to claim 6, characterized in that, The configured weight value is a basic weight or a dynamic weight.

8. A processing device for wafer test data, characterized in that, Applied to a data processing system, the data processing system includes: a scheduling center and a thread pool; the thread pool includes a plurality of processing threads; the device includes: An acquisition unit for acquiring a test sequence composed of test data of multiple DIEs on a target wafer; A division unit for dividing the multiple test data in the test sequence to obtain multiple subsequences; A conversion unit for converting the test data in each subsequence to obtain a target subsequence; A deletion unit for deleting the target subsequence that meets the deletion condition in the corresponding processing thread.

9. An electronic device, characterized in that, The electronic device includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus; The memory is used to store a computer program; When the processor executes the program stored on the memory, it implements the method steps described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, it implements the method steps described in any one of claims 1-7.

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