A digital radar signal simulation system based on RFSoC

Abstract

The application discloses a kind of digital radar signal simulation systems based on RFSoC, mainly solve the problem of the integration of existing discrete architecture composition analog system is not high, software and hardware design is complex, configuration flexibility is limited, volume, weight is relatively high, power consumption is also relatively high.The simulation system includes display control terminal, intermediate frequency signal generation unit, micro cell unit, antenna unit and power supply unit;Unlike existing radar signal simulation system, the digital radar signal simulation system based on RFSoC adopts RFSoC series digital chip, the high-performance DAC module, ARM module and FPGA module are closely integrated on a single chip in the series chip, wherein FPGA has abundant programmable DDS resources inside, i.e.single RFSoC chip can realize the core signal generation function in radar signal simulation, therefore has the characteristics of high integration, simple hardware design, flexible software configuration, small size, light weight and low power consumption.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of radar communication, and particularly relates to a digital radar signal simulation system based on RFSoC. BACKGROUND

[0002] In the face of increasingly complex battlefield environment, it is of great significance to provide complex, realistic and dynamic electromagnetic signal scenes by using signal simulation technology for evaluating the performance of radar or reconnaissance equipment and optimizing system design, and radar signal simulation plays a very important role in constructing such complex electromagnetic environment. The existing radar signal simulation system usually adopts the architecture combined by FPGA chips and DDS chips. The integration degree of the simulation system composed of the discrete architecture is not high, the software and hardware design is complex, the volume and weight are relatively large, and the power consumption is also relatively high. The radar signal types that can be simulated are less, the types are fixed, the software configuration flexibility is not high, free combination signals cannot be generated, the antenna scanning characteristics cannot be simulated in real time and in detail, and the expandability of the simulated radar number is limited due to the constraints of discrete DDS chips and other hardware resources. SUMMARY

[0003] The application aims to provide a digital radar signal simulation system based on RFSoC, and mainly solves the problems of low integration degree, complex software and hardware design, limited configuration flexibility, relatively large volume and weight, and relatively high power consumption of the simulation system composed of the existing discrete architecture.

[0004] To achieve the above-mentioned purpose, the technical scheme adopted by the application is as follows:

[0005] A digital radar signal simulation system based on RFSoC, comprising a display control terminal, a middle frequency signal generation unit, a micro pump unit, an antenna unit and a power supply unit.

[0006] The display control terminal and the middle frequency signal generation unit are in communication connection through a network interface. The configuration method of the display control terminal is as follows:

[0007] a. Configure system start and stop control instructions;

[0008] b. Configure and issue radar signal parameters, including system parameters, signal characteristic parameters and antenna scanning characteristic parameters;

[0009] c. Configure network connection state display, middle frequency signal generation unit state display and micro pump unit state display;

[0010] d. Configure record printing and storage system operation log;

[0011] The intermediate frequency signal generation unit is configured to receive, analyze, convert and store radar signal parameters issued by a display control terminal, and generate analog intermediate frequency signals of various radar systems in real time by using a DDS inside an RFSoC chip under the control of a start instruction;

[0012] The micro-pulse unit is configured to up-convert the analog intermediate frequency signals generated by the intermediate frequency signal generation unit into radio frequency signals according to carrier frequency parameters issued by the display control terminal, and output or not output the radio frequency signals under the control of a start / stop instruction, and modulate the power of the output radio frequency signals according to power control parameters issued by the display control terminal;

[0013] The antenna unit is configured to radiate the up-converted radio frequency signals.

[0014] The power supply unit is configured to convert commercial power into direct current required for the operation of the intermediate frequency signal generation unit and the micro-pulse unit.

[0015] Further, in the present application, the intermediate frequency signal generation unit is a signal processing board comprising an RFSoC series digital chip, and the RFSoC chip internally integrates an ARM module, an FPGA module and a DAC module; wherein,

[0016] The ARM module is configured to receive and analyze radar signal parameters and control instructions issued by a display control terminal through a network interface, and convert the radar signal parameters and control instructions into parameters and instructions directly available for the FPGA module, and send the parameters and instructions to the FPGA module through an AXI bus inside the chip;

[0017] The FPGA module is configured to receive, analyze and store the radar signal parameters and control instructions sent by the ARM module through the AXI bus, control the chip internal DDS to generate digital intermediate frequency signals in real time according to the analyzed parameters and instructions, and send the digital intermediate frequency signals to the DAC module through a digital interface inside the chip, and feed back the state information of the FPGA module to the ARM module through the AXI bus;

[0018] The DAC module is configured to convert the digital intermediate frequency signals generated by the FPGA module into analog intermediate frequency signals in real time, and output the analog intermediate frequency signals to the micro-pulse unit.

[0019] Further, in the present application, the micro-pulse unit comprises a frequency synthesizer unit and an up-conversion unit; wherein,

[0020] The frequency synthesizer unit is configured to generate clock signals for the operation of the intermediate frequency signal generation unit and the micro-pulse unit itself, and generate local oscillator signals required for up-conversion;

[0021] The up-conversion unit is configured to convert the generated analog intermediate frequency signals into radio frequency signals.

[0022] Further, in the present application, the system parameters comprise analog radar parameters and power control parameters.

[0023] The signal characteristic parameters include signal type, signal modulation type, carrier frequency variation law, repetition frequency variation law, frequency point number, carrier frequency, pulse number in group, frequency modulation bandwidth, pulse width, subcode time width, sub-pulse width, repetition frequency number, repetition period, repetition period jitter range, continuous wave frequency modulation period, continuous wave phase modulation period, and Doppler velocity.

[0024] The antenna scanning characteristic parameters include scanning mode, scanning speed, scanning acceleration, scanning center, scanning range, and antenna directional diagram data.

[0025] Further, in the application, the digital intermediate frequency signal generation step in the FPGA module is as follows:

[0026] S1, parameter analysis and storage: used for receiving and analyzing the radar signal parameters and control instructions sent by the ARM module through the AXI bus, and storing the antenna directional diagram data locally;

[0027] S2, pulse envelope generation: used for simulating the repetition frequency variation law of the signal, and generating an envelope signal according to the signal type, pulse width, repetition frequency variation law, repetition frequency number, and repetition period;

[0028] S3, intra-pulse signal generation: used for simulating the modulation characteristics of the signal, calculating a frequency control word according to the signal modulation type and frequency modulation bandwidth parameter, and controlling a group of DDS inside the chip to generate a baseband point frequency, linear frequency modulation or nonlinear frequency modulation signal under the action of the envelope signal; and generating a baseband phase encoding signal according to the phase encoding mode and subcode time width parameter;

[0029] S4, frequency modulation: according to the carrier frequency variation law, frequency point number, carrier frequency, pulse number in group, and sub-pulse width parameters, controlling another group of DDS inside the chip to generate a local oscillator signal under the action of the envelope signal, and mixing the local oscillator signal with the baseband signal output by the intra-pulse signal generation module, so as to simulate the carrier frequency variation law of the signal and generate an intermediate frequency signal with fixed frequency, inter-pulse agility, intra-pulse agility, or frequency diversity;

[0030] S5, directional diagram simulation: according to the scanning mode, scanning speed, scanning center, and scanning range parameters of the antenna, calculating a current scanning azimuth in real time, querying the corresponding value in the locally stored antenna directional diagram data according to the azimuth information, and using the value to perform real-time amplitude modulation on the signal output by the frequency modulation module, so as to simulate the scanning characteristics of the antenna, such as circular scanning, sector scanning, and tracking;

[0031] S6, power adjustment: used for adjusting the amplitude of the finally generated digital intermediate frequency signal to a set range, so as to adapt to the intermediate frequency input power requirement of the backend microwave unit.

[0032] Furthermore, in the present invention, the simulation method of the simulation system is:

[0033] (1) Setting and issuing radar signal parameters through the display and control terminal, including system parameters, signal characteristic parameters, and antenna scanning characteristic parameters;

[0034] (2) Issue the system startup command and the control system starts working;

[0035] (3) The intermediate frequency signal generation unit receives, analyzes, converts and stores radar signal parameters. Under the control of the startup command, it uses the internal DDS of the chip to generate intermediate frequency signals of various radar systems in real time. The microwave unit up-converts the intermediate frequency signals into radio frequency signals, and finally radiates them through the antenna unit.

[0036] (4) Issue a system stop command to stop the control system.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] (1) The present invention adopts the RFSoC series digital chip, which makes the digital radar signal simulation system based on RFSoC have multiple advantages: high integration, simple hardware design, flexible software configuration, small size, light weight and low power consumption;

[0039] (2) The present invention can flexibly simulate various radar signals: conventional pulse, stepped frequency, frequency agility (inter-pulse, pulse group, intra-pulse), frequency diversity (simultaneous, time-sharing), intra-pulse modulation (linear frequency modulation, nonlinear frequency modulation, Barker code, M-sequence code), repetition frequency stagger, repetition frequency jitter, repetition frequency sliding, pulse Doppler, ordinary continuous wave, continuous wave frequency modulation (linear, nonlinear), continuous wave phase modulation (Barker code, M-sequence code) signals, and can also generate various combination signals through software configuration, such as frequency agility + repetition frequency jitter signal, etc.

[0040] (3) The present invention can load antenna pattern data online and simulate antenna scanning characteristics in real time and precision: the antenna pattern data file can be selected on the display and control terminal and sent to the intermediate frequency signal generation unit, where the FPGA operating clock rate is as high as 300MHz, and amplitude modulation is performed in each clock cycle, so that circular scanning, sector scanning and tracking antenna scanning characteristics can be simulated in real time and precision;

[0041] (4) The present invention adopts a digital and software-based design concept, which can flexibly expand the number of analog radars: a single-system radar signal can be generated through software configuration, and multiple independent signal generation channels can be implemented using software to simultaneously generate radar signals of multiple different systems, thereby constructing a more complex electromagnetic environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1A composition block diagram of a digital radar signal simulation system based on RFSoC;

[0043] Figure 2 A working principle schematic diagram of the digital radar signal simulation system based on RFSoC;

[0044] Figure 3 A flow block diagram of a digital intermediate frequency signal generation process in the FPGA module;

[0045] Figure 4 A simulation method flow chart of the digital radar signal simulation system based on RFSoC. DETAILED DESCRIPTION

[0046] The application will be further described in the following description and examples in conjunction with the accompanying drawings, and the modes of the application include but are not limited to the following examples.

[0047] The disclosed digital radar signal simulation system based on RFSoC mainly comprises a display control terminal, an intermediate frequency signal generation unit, a microwave unit, an antenna unit and a power supply unit, and a system composition block diagram is shown in Figure 1 A working principle schematic diagram of the system is shown in Figure 2 The display control terminal issues radar signal parameters and control instructions, the intermediate frequency signal generation unit generates intermediate frequency signals of various radar systems in real time according to the received parameter information under the control of the start instruction, the microwave unit up-converts the intermediate frequency signals into radio frequency signals, and finally the radio frequency signals are radiated through the antenna unit.

[0048] The computer is used as the display control terminal of the simulation system in this embodiment, and is used for realizing friendly human-computer interaction. The display control terminal and the intermediate frequency signal generation unit are connected and communicated through a network interface.

[0049] In this embodiment, the display control terminal is configured in the following method:

[0050] a. Configure system start and stop control instructions;

[0051] b. Configure and issue radar signal parameters, including system parameters, signal characteristic parameters and antenna scanning characteristic parameters; wherein,

[0052] The system parameters include: the number of simulated radars, power control parameters;

[0053] The signal characteristic parameters include: signal type (pulse signal, continuous wave signal), signal modulation type (point frequency, linear frequency modulation, nonlinear frequency modulation, Barker code, M sequence code), carrier frequency variation law (fixed frequency, inter-pulse change, pulse group change, intra-pulse change, frequency diversity), pulse repetition frequency variation law (fixed, staggered, jitter, sliding), frequency point number, carrier frequency, pulse number in group, frequency modulation bandwidth, pulse width, sub-code time width, sub-pulse width, pulse repetition frequency number, repetition period, repetition period jitter range, continuous wave frequency modulation period, continuous wave phase modulation period, and Doppler velocity.

[0054] The antenna scanning characteristic parameters include: scanning mode (circular scanning, fan scanning, tracking), scanning speed, scanning acceleration, scanning center, scanning range, and antenna directional diagram data.

[0055] c, configure network connection state display, intermediate frequency signal generation unit state display and micro cell state display; including intermediate frequency signal generation unit state and micro cell state information.

[0056] d, configure record and storage system operation log.

[0057] The intermediate frequency signal generation unit is the core unit of the digital radar signal simulation system based on RFSoC, which is a signal processing board containing Xilinx's RFSoC series of digital chips. The RFSoC series of chips tightly integrate high-performance DAC modules, ARM modules and FPGA modules on a single chip, and the FPGA has rich programmable DDS resources inside, that is, a single RFSoC chip can realize the core signal generation function in radar signal simulation. The intermediate frequency signal generation unit function is realized by ARM module, FPGA module and DAC module; wherein,

[0058] The ARM module is used to receive and analyze the radar signal parameters and control instructions issued by the display control terminal through the network interface, and convert the radar signal parameters and control instructions into parameters and instructions directly available to the FPGA module, and send them to the FPGA module through the internal AXI bus of the chip;

[0059] The FPGA module is used to receive, analyze and store the radar signal parameters and control instructions sent by the ARM module through the AXI bus; according to the analyzed parameters and instructions, the chip internally DDS generates digital intermediate frequency signals in real time, and sends the digital intermediate frequency signals to the DAC module through the internal digital interface of the chip; through the AXI bus, the state information of the FPGA module is fed back to the ARM module; as Figure 3 As shown in the figure, the steps of generating digital intermediate frequency signals in the FPGA module are as follows:

[0060] S1, parameter analysis and storage: used for receiving and analyzing radar signal parameters and control instructions sent by the ARM module through the AXI bus, and storing the antenna pattern data locally;

[0061] S2, pulse envelope generation: used for simulating the repetition frequency variation law of the signal, generating an envelope signal according to the signal type, pulse width, repetition frequency variation law, number of repetition frequencies and repetition period;

[0062] S3, intra-pulse signal generation: used for simulating the modulation characteristics of the signal, calculating a frequency control word according to the signal modulation type and frequency modulation bandwidth parameters, and controlling a group of DDS inside the chip to generate a baseband point frequency, linear frequency modulation or nonlinear frequency modulation signal under the action of the envelope signal; and generating a baseband phase encoding signal according to the phase encoding mode and subcode time width parameters;

[0063] S4, frequency modulation: according to the carrier frequency variation law, frequency point number, carrier frequency, number of pulses in a group and sub-pulse width parameters, another group of DDS inside the chip is controlled to generate a local oscillator signal under the action of the envelope signal, and the baseband signal output by the intra-pulse signal generation module is mixed, so as to simulate the carrier frequency variation law of the signal, and generate an intermediate frequency signal with fixed frequency, inter-pulse agility, intra-pulse agility or frequency diversity;

[0064] S5, pattern simulation: according to the scanning mode, scanning speed, scanning center and scanning range parameters of the antenna, the current scanning azimuth is calculated in real time, the corresponding value in the locally stored antenna pattern data is queried according to the azimuth information, and the signal output by the frequency modulation module is modulated in real time according to the value, so as to simulate the scanning characteristics of the antenna, such as circular scanning, fan scanning and tracking;

[0065] S6, power adjustment: used for adjusting the amplitude of the finally generated digital intermediate frequency signal to a set range, so as to adapt to the intermediate frequency input power requirement of the backend micro cell unit.

[0066] The DAC module is used for converting the digital intermediate frequency signal generated by the FPGA module into an analog intermediate frequency signal in real time, and outputting the analog intermediate frequency signal to the micro cell unit.

[0067] The micro cell unit up-converts the analog intermediate frequency signal generated by the intermediate frequency signal generation unit into a radio frequency signal according to the carrier frequency parameter issued by the display control terminal, and outputs or does not output the radio frequency signal under the control of the start / stop instruction, and modulates the power of the output radio frequency signal according to the power control parameter issued by the display control terminal; the micro cell unit includes a frequency synthesizer unit and an up-conversion unit; wherein,

[0068] The frequency synthesizer unit is used for generating a clock signal for the intermediate frequency signal generation unit and the micro cell unit itself, and generating a local oscillator signal required for up-conversion;

[0069] The up-conversion unit is used for converting the generated analog intermediate frequency signal into a radio frequency signal.

[0070] The antenna unit is used for radiating the up-converted radio frequency signal.

[0071] The power supply unit is used for converting commercial power into direct current required for the operation of the intermediate frequency signal generation unit and the micro-unit.

[0072] As shown in Figure 4 the analog method of the analog system is as follows:

[0073] (1) The radar signal parameters are set and issued through the display control terminal, including the system parameters, the signal characteristic parameters and the antenna scanning characteristic parameters;

[0074] (2) The system start instruction is issued to control the system to start working;

[0075] (3) The intermediate frequency signal generation unit receives, analyzes, converts and stores the radar signal parameters, and generates the intermediate frequency signals of various radar systems in real time under the control of the start instruction by using the internal DDS of the chip, and the intermediate frequency signals are up-converted into radio frequency signals by the micro-unit, and finally radiated out through the antenna unit;

[0076] (4) The system stop instruction is issued to control the system to stop working.

[0077] Different from the existing radar signal simulation system, the digital radar signal simulation system based on RFSoC adopts the RFSoC series digital chip, which integrates the high-performance DAC module, the ARM module and the FPGA module in a single chip, and the FPGA has rich programmable DDS resources, that is, the single RFSoC chip can realize the core signal generation function of the radar signal simulation, so it has the characteristics of high integration, simple hardware design, flexible software configuration, small size, light weight and low power consumption; the types of the simulated signals are more diverse and can be freely combined, and have high flexibility; the antenna pattern data can be loaded online to simulate the antenna scanning characteristics in real time and in detail; the digital and software design idea is adopted to flexibly expand the number of simulated radars to achieve the purpose of simultaneously simulating multiple radars of different systems.

[0078] The above embodiment is only one of the preferred embodiments of the present application and should not be used to limit the protection scope of the present application, but any modification or polishing without substantial meaning made within the main design idea and spirit of the present application, which still solves the technical problems consistent with the present application, should be included in the protection scope of the present application.

Claims

1. A digital radar signal simulation system based on RFSoC, characterized in that: It includes a display and control terminal, an intermediate frequency signal generating unit, a microwave unit, an antenna unit and a power supply unit; The display and control terminal is connected to the intermediate frequency signal generating unit via a network interface; the method for configuring the display and control terminal is as follows: a. Configure system start and stop control instructions; b. Configure and distribute radar signal parameters, including system parameters, signal characteristic parameters, and antenna scanning characteristic parameters; c. Configure the network connection status display, intermediate frequency signal generation unit status display and microwave unit status display; d. Configure records and store system operation logs; The intermediate frequency signal generation unit is used to receive, analyze, convert and store radar signal parameters sent by the display and control terminal, and use the internal DDS of the RFSoC chip to generate analog intermediate frequency signals of various radar systems in real time under the control of the startup command; wherein, the intermediate frequency signal generation unit is a signal processing board including the RFSoC series digital chip, the ARM module, FPGA module and DAC module integrated in the RFSoC series digital chip; wherein, The ARM module is used to receive and analyze radar signal parameters and control instructions sent by the display and control terminal through the network interface, convert the radar signal parameters and control instructions into parameters and instructions that can be directly used by the FPGA module, and send them to the FPGA module through the chip's internal AXI bus; The FPGA module is used to receive, parse, and store radar signal parameters and control instructions sent by the ARM module via the AXI bus. Based on the parsed parameters and instructions, it controls the DDS inside the chip to generate a digital intermediate frequency signal in real time, and sends the digital intermediate frequency signal to the DAC module via the chip's internal digital interface. Furthermore, it feeds back its own status information to the ARM module via the AXI bus. The DAC module is used to convert the digital intermediate frequency signal generated by the FPGA module into an analog intermediate frequency signal in real time and output it to the microwave unit; The microwave unit up-converts the analog intermediate frequency signal generated by the intermediate frequency signal generation unit into a radio frequency signal according to the carrier frequency parameters sent by the display and control terminal, and outputs or does not output the radio frequency signal under the control of the start / stop command, and modulates the power of the output radio frequency signal according to the power control parameters sent by the display and control terminal; The antenna unit is used to radiate the radio frequency signal output by the up-conversion; The power supply unit is used to convert the mains electricity into direct current required for the operation of the intermediate frequency signal generating unit and the microwave unit; The simulation method of the simulation system is: (1) Set and send radar signal parameters through the display and control terminal, including system parameters, signal characteristic parameters, and antenna scanning characteristic parameters; (2) Issue the system startup command and the control system starts working; (3) The intermediate frequency signal generation unit receives, analyzes, converts and stores radar signal parameters. Under the control of the startup command, it uses the internal DDS of the chip to generate intermediate frequency signals of various radar systems in real time. The microwave unit up-converts the intermediate frequency signals into radio frequency signals, and finally radiates them through the antenna unit. (4) Issue a system stop command to stop the control system.

2. The digital radar signal simulation system based on RFSoC according to claim 1, characterized in that: The microwave unit includes a frequency synthesizer unit and an up-conversion unit; wherein, The frequency synthesizer unit is used to generate clock signals for the intermediate frequency signal generation unit and the microwave unit itself, and also generates the local oscillator signal required for up-conversion; The up-conversion unit is used to convert the generated analog intermediate frequency signal into a radio frequency signal.

3. The digital radar signal simulation system based on RFSoC according to claim 2, characterized in that: The system parameters include the number of simulated radar units and power control parameters; The signal characteristic parameters include signal type, signal modulation type, carrier frequency variation law, repetition frequency variation law, number of frequency points, carrier frequency, number of pulses in a group, frequency modulation bandwidth, pulse width, subcode time width, sub-pulse width, number of repetition frequencies, repetition period, repetition period jitter range, continuous wave frequency modulation period, continuous wave phase modulation period and Doppler velocity; The antenna scanning characteristic parameters include: scanning mode, scanning speed, scanning acceleration, scanning center, scanning range and antenna pattern data.

4. The RFSoC-based digital radar signal simulation system according to claim 3, characterized in that: The steps for generating a digital intermediate frequency signal in the FPGA module are as follows: S1, parameter parsing and storage: used to receive and parse radar signal parameters and control instructions sent by the ARM module through the AXI bus, and store antenna pattern data locally; S2, pulse envelope generation: used to simulate the repetition rate variation of the signal and generate the envelope signal according to the signal type, pulse width, repetition rate variation, number of repetition rates and repetition period; S3, intra-pulse signal generation: This simulates the modulation characteristics of the signal and calculates the frequency control word based on the signal modulation type and FM bandwidth parameters. Under the action of the envelope signal, it controls a set of DDS inside the chip to generate baseband dot frequency, linear FM, or nonlinear FM signals. It also generates baseband phase-coded signals based on the phase encoding method and subcode time width parameters. S4, frequency modulation: Based on the carrier frequency variation pattern, number of frequency points, carrier frequency, number of pulses within a group, and sub-pulse width parameters, under the action of the envelope signal, another set of DDS inside the chip is controlled to generate a local oscillator signal. This is mixed with the baseband signal output by the intra-pulse signal generation module to simulate the carrier frequency variation pattern of the signal and generate an intermediate frequency signal with fixed frequency, pulse-to-pulse agility, pulse-group agility, intra-pulse agility, or frequency diversity; S5, Pattern Simulation: Calculates the current scanning azimuth in real time based on the antenna's scanning mode, scanning speed, scanning center, and scanning range parameters. Query the corresponding value in the locally stored antenna pattern data based on the azimuth angle information. Use this value to perform real-time amplitude modulation on the signal output by the frequency modulation module to simulate the antenna's scanning characteristics, such as circular scanning, sector scanning, and tracking. S6, power adjustment: used to adjust the amplitude of the final generated digital intermediate frequency signal to a set range to adapt to the intermediate frequency input power requirement of the back-end microwave unit.

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