Method and apparatus with tile-based image rendering

Abstract

Methods and apparatus with tile-based image rendering are disclosed. The method includes: determining a first color value of a partial pixel included in a plurality of pixels by performing shading on the partial pixel by using a shader module, the partial pixel being in a tile frame corresponding to a partial region of an input frame; determining a second color value of other pixels by performing a neural network-based oversampling process on the other pixels, the other pixels being pixels of the plurality of pixels that are not included in the partial pixels of the tile frame; and determining a rendered tile frame comprising a first color value of the portion of pixels and a second color value of the other pixels, the step of determining the first color value of the portion of pixels comprising: performing shading on pixels in an edge region of the tile frame by using a shader module, and determining the edge color value of the pixel in the edge area.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0000278, filed on Jan. 2, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] The following description relates to a method and apparatus having tile-based image rendering. Background Art

[0003] A graphics processing system may include multiple processing units (such as, a graphics processing unit (GPU)) to obtain performance gains through parallel processing of graphics tasks. Multiple GPUs may be used for rendering an image. Rendering is a technique for obtaining a final result of one or more objects in an image that takes into account an external environment of one or more objects (such as, a position of an object or illumination within an image), and is also referred to as image synthesis. Summary of the Invention

[0004] The present invention content is provided in a simplified form to introduce a selection of concepts that are further described below in the detailed description. The present invention content is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0005] In one general aspect, there is provided a processor-implemented method, the method including: determining a first color value of partial pixels by performing shading on the partial pixels included in a plurality of pixels using a shader module, the partial pixels being in a tile frame corresponding to a partial region of an input frame; determining a second color value of other pixels by performing neural-network-based supersampling processing on the other pixels, the other pixels being pixels among the plurality of pixels that are not included in the partial pixels of the tile frame; and determining a rendered tile frame including the first color value of the partial pixels and the second color value of the other pixels, the step of determining the first color value of the partial pixels includes: determining an edge color value of pixels in an edge region of the tile frame by performing shading on the pixels in the edge region of the tile frame using the shader module.

[0006] The step of determining the first color value may include: determining a non-edge color value of non-edge partial pixels by performing shading on the non-edge partial pixels included in a non-edge region, the non-edge partial pixels being included in the non-edge region, and the non-edge region being a region of the tile frame other than the edge region.

[0007] The step of determining the second color value may include: performing the supersampling processing based on the edge color value and the non-edge color value.

[0008] The step of determining the second color value may include performing the supersampling process without using a third color value of pixels included in additional tile frames located around the tile frame.

[0009] The step of determining the edge color value may include determining all edge color values of all pixels in the edge region by performing shading on all pixels included in the edge region using a shader module.

[0010] Based on one of an image magnification ratio, a frame rate, or an estimated resource consumption amount, determine the number of non-edge partial pixels to be shaded using the shader module.

[0011] The method may include, after determining the second color value, sending the rendered tile frame including the first color value and the second color value to the system memory.

[0012] The step of determining the first color value may be performed by a shader module included in a graphics processing unit (GPU), and the step of determining the second color value may be performed by a supersampler module configured to perform the supersampling process.

[0013] The supersampler module may be included in the GPU.

[0014] In one general aspect, there is provided a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method.

[0015] In one general aspect, there is provided an electronic device including: a control processor; and a graphics processing unit (GPU) configured to perform image rendering based on control by the control processor, the GPU including: a processor configured to execute instructions; and a memory storing the instructions, wherein executing the instructions configures the processor to: determine a first color value of a first partial pixel by performing shading on the first partial pixel, the first partial pixel being a pixel among a plurality of pixels in a tile frame corresponding to a partial region of an input frame; and determine a second color value of a second pixel by performing a neural network-based supersampling process on a second partial pixel, the second partial pixel being a pixel among the plurality of pixels not included in the first part; and a graphics memory configured to store a rendered tile frame including the first color value of the first partial pixel and the second color value of the second partial pixel, and the step of determining the first color value includes: determining an edge color value of a pixel in the edge region by performing shading on the pixel in the edge region of the tile frame.

[0016] The step of determining the first color value may include: determining the non-edge color value of a third portion of pixels in the non-edge region by performing shading on the third portion of pixels in the non-edge region, where the non-edge region is the region of the tile frame other than the edge region.

[0017] The step of determining the second color value may include: determining the second color value by performing the supersampling process based on the edge color value and the non-edge color value.

[0018] The step of determining the second color value may include: performing the supersampling process without using the third color value of pixels included in additional tile frames located around the tile frame.

[0019] The step of determining the second color value may include: determining the all-edge color value of all pixels in the edge region by performing shading on all pixels included in the edge region.

[0020] The electronic device may include: a system configured to: receive the tile frame rendered by the electronic device from a graphics memory and store an output frame obtained by combining the rendered tile frames.

[0021] In one general aspect, there is provided an electronic device including: a graphics processing unit (GPU) including: a processor configured to execute instructions; and a memory storing the instructions, wherein executing the instructions configures the processor to: determine a first color value of a first portion of pixels by performing shading on the first portion of pixels, where the first portion of pixels are pixels among a plurality of pixels included in a tile frame corresponding to a partial region of an input frame; and determine a second color value of a second portion of pixels by performing a neural network-based supersampling process on the second portion of pixels, where the second portion of pixels are pixels among the plurality of pixels not included in the first portion; and a first graphics memory configured to store the determined color values of the partial pixels; a second graphics memory configured to store the determined color values of the second portion of pixels; and a system memory connected to the first graphics memory and the second graphics memory, and the step of determining the first color value includes: determining the edge color value of pixels in the edge region of the tile frame by performing shading on the pixels in the edge region.

[0022] The step of determining the first color value may include: determining the non-edge color value of a third portion of pixels among the pixels in the non-edge region by performing shading on the third portion of pixels, where the non-edge region is the region of the tile frame other than the edge region.

[0023] The step of determining the second color value may include: determining the second color value by performing the supersampling process based on the edge color value and the non-edge color value.

[0024] The system memory may be configured to store a rendered tile frame including a first color value and a second color value. Description of the Drawings

[0025] Figure 1 An example image rendering device that performs tile-based image processing according to one or more embodiments is shown.

[0026] Figure 2 An example tile-based image rendering method according to one or more embodiments is shown.

[0027] Figure 3 An example of a tile frame shaded by a shader module according to one or more embodiments is shown.

[0028] Figure 4 An example of a tile frame supersampled by a supersampler module according to one or more embodiments is shown.

[0029] Figure 5 An example neural network for supersampling processing according to one or more embodiments is shown.

[0030] Figure 6 An example of an output frame generated by image processing of an image rendering device according to one or more embodiments is shown.

[0031] Figure 7 An example configuration of an image rendering device according to one or more embodiments is shown.

[0032] Figure 8 An example configuration of an image rendering device according to one or more embodiments is shown.

[0033] Throughout the drawings and the detailed description, unless otherwise described or provided, the same reference numerals may be understood to represent the same or similar elements, features, and structures. The drawings may not be to scale, and for clarity, illustration, and convenience, the relative dimensions, proportions, and depictions of the elements in the drawings may be exaggerated. Detailed Description

[0034] When a convolutional neural network (CNN) is used for neural network-based super-sampling processing, due to the characteristics of the convolutional operation in the CNN, the size of the output can be reduced compared to the size of the input. When the size of the output is reduced, the number of pixels included in the output is reduced compared to the number of pixels included in the input. The CNN may include a plurality of convolutional layers in which the convolutional operation is performed, and when more convolutional layers are included, an input of a size larger than the size of the output is required. A typical method of setting the size of the input to be the same as the output of the CNN is to make the size of the input larger than the size of the original input by adding a padding area to the input. However, since the padding area does not include any meaningful values, the typical method of adding the padding area may cause a degradation in the quality at the boundary portion of the output. In order to perform super-sampling processing on a single tile (or block) frame using the CNN, due to the above reasons, an input larger than the tile frame may be required. Another typical method may include selecting some of the tile frames corresponding to the tile frame that is the target of the image processing and the tile frames around the corresponding tile frame as the input of the CNN. In this typical method, there is the following limitation: in order to perform super-sampling processing on the corresponding tile frame, it is necessary to wait until the coloring of all the surrounding tile frames is completed, resulting in a long processing time.

[0035] Figure 1 An example image rendering device that performs tile-based image processing according to one or more embodiments is shown.

[0036] Referring to Figure 1 , in one non-limiting embodiment, for the image rendering device 100, when the input frame 110 is given, the input frame 110 may be divided into a plurality of tile frames 122, 124, 126, and 128. The input frame 110 may include an image to be rendered. Each of the tile frames 122, 124, 126, and 128 may correspond to a part or a partial region of the input frame 110. Here, the "tile frame" may also be referred to as a "tile" or a "tile region". The number of tile frames generated by dividing the input frame 110 is more than one. For ease of description, Figure 1An example is shown in which the input frame 110 is divided into four tile frames 122, 124, 126, and 128. However, the number of tile frames generated by dividing the input frame 110 is not limited to any specific number. The shapes of the tile frames 122, 124, 126, and 128 may be rectangles having a predetermined size (e.g., 16×16 pixels or 32×32 pixels). The sizes and shapes of the tile frames 122, 124, 126, and 128 may be the same as each other, but are not limited thereto. In one example, the tile frames 122, 124, 126, and 128 may not be the same in size and / or shape. Dividing the input frame 110 into the tile frames 122, 124, 126, and 128 may be performed by the image rendering device 100, or may be performed by a processor not included in the image rendering device 100.

[0037] In one example, the tile frames 122, 124, 126, and 128 may be transmitted to the image rendering device 100. The image rendering device 100 may perform image processing (e.g., rendering) on the tile frames 122, 124, 126, and 128, and generate an output frame 130 as a result of performing the image processing. By performing image processing on a tile frame-by-tile frame basis without processing the entire input frame 110 at the same time, the amount of memory required for image processing can be reduced. The image processing to be performed on each of the tile frames 122, 124, 126, and 128 may be performed sequentially or in parallel. The image rendering device 100 may include a graphics processing unit (GPU) for performing image processing on the tile frames. The GPU may be a dedicated electronic circuit designed to accelerate the processing of images. When the image rendering device 100 includes multiple GPUs, the GPUs may perform image processing on the tile frames in parallel. Parallel processing can improve the speed of image processing.

[0038] The image rendering device 100 may perform rendering on a tile frame-by-tile frame basis. In one example, when the image rendering device 100 performs rendering on the tile frame 122, the tile frame 122 may be allocated to a graphics memory included in the image rendering device 100 (e.g., Figure 7 the graphics memory 729, Figure 8 the first graphics memory 828, or the second graphics memory 838), and the image rendering device 100 may determine the color values of the pixels included in the tile frame 122 by performing shading and neural network-based supersampling processing on the tile frame 122 by a shader module of the GPU (e.g., Figure 7 the shader module 723, or Figure 8 the shader module 824). Here, the color values may be determined by performing rendering.

[0039] In one example, the shader module may include a vertex shader, a geometry shader, and / or a pixel shader that perform shading. In rendering in the field of computer graphics, shading may represent an operation of determining a shading value (or luminance value) of an object surface based on position, direction, and / or color of luminance when calculating the color of the object surface shown in an image. Through shading, the color value of pixels included in the object surface can be determined.

[0040] In one example, the supersampling process may represent a process of converting a low-resolution image into a high-resolution image. Through the supersampling process, the image can be upscaled to a higher resolution. Instead of the color values of all pixels included in a tile frame being determined by the shader module of the GPU, the color values of some pixels included in the tile frame may be determined by the shader module, and the color values of the remaining pixels can be determined through the supersampling process. The neural network-based supersampling process may represent an operation of performing the supersampling process using a trained neural network (e.g., a convolutional neural network (CNN)). Compared with the case of performing shading using the GPU, through the neural network-based supersampling process, the color values of pixels included in the object surface can be determined at a higher speed with lower power consumption.

[0041] In one example, the rendered tiles may be combined to generate an output frame 130, and the generated output frame 130 may be output through a display. The next input frame of the input frame 110 may be divided into tile frames as described above, and undergo image processing through the image rendering device 100 to generate the next output frame, and the generated next output frame may be output through the display. These processes may be sequentially performed on all input frames. The next input frame represents an input frame processed after the input frame 110 in time, and the next output frame represents an output frame generated after the output frame 130 in time.

[0042] In an example described in more detail below, the image rendering device 100 may divide the entire area of the tile frame into an edge area and a non-edge area. In one example, the image rendering device 100 may perform shading on all pixels included in the edge area and some pixels included in the non-edge area through a shader module, and perform supersampling processing on the remaining pixels included in the non-edge area. The size of the non-edge area is smaller than the size of the entire area of the tile frame. As described above, the output of the neural network performing supersampling processing becomes smaller than the input size. However, in the case where the entire area of the tile frame is input to the neural network, the output of the neural network may have the same size as the size of the non-edge area, or may have a size smaller than the size of the entire area of the tile frame but larger than the size of the non-edge area. Through the above method, it is feasible to perform supersampling processing on the tile frame without using the surrounding tile frames. In one example, when the surrounding tile frames are not used, the processing flow of image rendering can be simplified, the processing speed can be increased, and the amount of resources (such as memory or power) required for processing can be reduced.

[0043] Figure 2 Shows an example of operations of a tile-based image rendering method according to one or more embodiments. In one example, Figure 2 The operations may be performed simultaneously or in parallel with each other, and the order of the operations may be changed. In addition, some of the operations may be omitted, or additional operations may be additionally performed. The image rendering method may be performed by an image rendering device (such as, Figure 1 the image rendering device 100) as described in more detail above.

[0044] Referring to Figure 2 , in a non-limiting example, in operation 210, the image rendering device may load a tile frame. The tile frame to be rendered may be allocated to the graphics memory, and the image rendering device may load the tile frame from the graphics memory. The image rendering device may schedule the rendering of multiple tile frames configuring a single input frame, and allocate the tile frames to be rendered to the graphics memory according to the scheduling result.

[0045] In one example, in operation 220, the image rendering device may determine the color values of some pixels by performing shading on some pixels included in the tile frame corresponding to a partial area of the input frame through a shader module. The operation of determining the color values of some pixels may be performed by a shader module included in the GPU (such as, Figure 7 the shader module 723 as described in more detail below or Figure 8 the shader module 824). The preprocessed tile frame may be generated by performing shading.

[0046] The image rendering device can perform shading on the pixels in the edge region of the tile frame through a shader module to determine the color values of the pixels in the edge region. In one example, the image rendering device can perform shading on all the pixels included in the edge region to determine the color values of all the pixels in the edge region. The image rendering device can perform shading on some of the pixels included in the non-edge region other than the edge region in the tile frame to determine the color values of some of the pixels in the non-edge region.

[0047] In one example, based on at least one of the image magnification ratio, the frame rate, and the estimated resource consumption (e.g., the estimated power consumption), the number of some pixels in the non-edge region to be shaded by the shader module can be determined. In one example, as the image magnification ratio, the frame rate, or the estimated resource consumption increases, the number of a part of the pixels in the non-edge region to be shaded by the shader module can decrease. As the image magnification ratio, the frame rate, or the estimated resource consumption decreases, the number of a part of the pixels in the non-edge region to be shaded by the shader module can increase.

[0048] As described above, the image rendering device can generate preprocessed tile frames with different resolutions for each region by performing shading on each region (edge region and non-edge region) of the tile frame at different resolutions.

[0049] In one example, in operation 230, the image rendering device can perform neural network-based supersampling processing on the other pixels in the non-edge region other than the shaded pixels among all the pixels included in the tile frame to determine the color values of the other pixels. The operation of determining the color values of the other pixels can be performed by a supersampler module (e.g., Figure 7 supersampler module 727 or Figure 8 supersampler module 834) that performs the supersampling processing. In one example, the supersampler module can operate in the GPU or can operate in a separate device other than the GPU.

[0050] The image rendering device can perform supersampling processing based on the color values of the pixels in the edge region and the color values of some of the pixels in the non-edge region to determine the color values of the other pixels (pixels with color values not determined by shading through the shader module) in the non-edge region. The image rendering device can perform supersampling processing without using the color values of the pixels included in other tile frames located around the tile frame.

[0051] For example, the neural network performing supersampling processing can be a CNN. The CNN can use the preprocessed tile frame colored in operation 220 as input, perform neural network-based supersampling processing on non-edge regions corresponding to low-resolution regions in the preprocessed tile frame to output a tile frame including non-edge regions with high resolution. The CNN can perform supersampling processing to determine the rendered color values of pixels in the non-edge regions with color values not determined by coloring.

[0052] If needed, in one example, in operation 240, the image rendering device can perform post-processing (e.g., post-rendering processing). When post-rendering processing is not selected or needed, operation 240 can be omitted. Post-rendering processing can include, for example, rearranging pixels in the tile frame, limiting the color values of the rendered pixels within a specific image range, adding text to the pixel frame, filtering, adjusting brightness, and / or adjusting chroma.

[0053] In one example, in operation 250, the image rendering device can determine a rendered tile frame including the color values of some pixels determined by performing coloring and the color values of other pixels determined by performing supersampling processing. After all the color values in the other pixels are determined by supersampling processing, the rendered tile frame including the color values of some pixels determined by performing coloring and the color values of other pixels determined by performing supersampling processing can be transmitted to the system memory (e.g., system memory 730 as discussed in more detail below Figure 7 or Figure 8 system memory 840).

[0054] In operation 260, in one example, the image rendering device can determine whether all in the tile frame have been rendered. When not all of the tile frames configuring the input frame have been completed in rendering (in the case of "No" in operation 260), the image rendering device can perform operations 210 to 260 for the next tile frame.

[0055] According to the above example, coloring, supersampling processing, and post-rendering processing by the shader module can be continuously performed on a single tile frame without relying on other tile frames. There is no need to obtain data from neighboring tile frames to render the tile frame, so the power consumed by memory access can be reduced.

[0056] Figure 3 An example of a tile frame colored by a shader module according to one or more embodiments is shown. Referring to Figure 3 , in one non-limiting example, the tile frame 310 can be colored. The tile frame 310 can correspond to, for example, Figure 1One of the tile frames 122, 124, 126, and 128 shaded by the shader module of the GPU. The tile frame 310 may include a plurality of pixels that are basic units for forming a digital image. In the tile frame 310, each grid region may correspond to a single pixel region. The illustrated tile frame 310 has a size of 32×32 and includes 1024 pixels.

[0057] The shading process by the shader module may be performed differently for each region in the tile frame 310. In one example, the shader module may perform a shading process on all pixels 322 in an edge region corresponding to a region between the outer boundary 320 and the inner boundary 330 of the tile frame 310. The shader module may perform a shading process on some of the pixels 332 included within the inner boundary 330, and may not perform a shading process using the shader module on the remaining pixels 334 other than the some pixels 332. Among the pixels included in the illustrated tile frame 310, the pixels 322 and 332 represented as "O" may represent the pixels shaded by the shader module to determine their color values.

[0058] In one example, the edge region may have a horizontal thickness (or depth) 342 and a vertical thickness (or depth) 344, and the horizontal thickness 342 and the vertical thickness 344 may be determined based on a neural network for supersampling processing. In one example, the horizontal thickness 342 and the vertical thickness 344 may be determined in consideration of the number of convolution processes performed during the operation of the neural network. The convolution process may be performed by a convolution layer included in the neural network. As the number of convolution processes performed increases, the horizontal thickness 342 and the vertical thickness 344 may gradually become thicker. The horizontal thickness 342 and the vertical thickness 344 need to have such a thickness that does not cause problems even when the size of the tile frame input to the neural network during the supersampling process is gradually reduced by the convolution process when determining the pixel values of the pixels 334. In one example, assuming that a convolution process with a kernel size of 3×3 is performed four times during the supersampling process, the horizontal thickness 342 and the vertical thickness 344 each need to have a thickness of at least four or more pixels. The horizontal thickness 342 and the vertical thickness 344 may be defined such that the color values of all the shaded pixels required for the supersampling process are present in the tile frame 310.

[0059] Figure 4 An example of a tile frame supersampled by a supersampler module according to one or more embodiments is shown.

[0060] Refer to Figure 4, in a non-limiting embodiment, the pre-processed tile frame 310 shaded by the shader module can be input into a neural network that performs supersampling processing, and the tile frame 410 can be generated through the neural network-based supersampling processing. The neural network-based supersampling processing can be performed on other unshaded pixels 334 in the non-edge regions except for the shaded pixels (pixels 322 in the edge region and pixels 332 in the non-edge region) among all the pixels included in the pre-processed tile frame 310. The color values of the other pixels 334 in the non-edge regions can be determined through the supersampling processing. Among the pixels included in the shown tile frame 410, the pixels 352 of the circles with shadows represent the pixels that undergo the neural network-based supersampling processing to determine their color values.

[0061] In one example, the supersampling processing can be performed independently for each tile frame, and the shading using the shader module and the neural network-based supersampling processing can be continuously performed on the tile frames. The color values of all the pixels included in the tile frames can be determined through the shading using the shader module and the neural network-based supersampling processing. In one example, compared with rendering the entire region of the tile frame only through shading, the rendering performed by combining shading and supersampling processing can reduce power consumption. In addition, since no data of other tile frames is required to perform the supersampling processing, the scheduling for the tile frames becomes simple, and since no memory for storing data of surrounding tile frames is required, the amount of memory required can be reduced.

[0062] Figure 5 An example neural network for supersampling processing according to one or more embodiments is shown.

[0063] Referring to Figure 5 , in a non-limiting example, the tile frame 310 shaded by the shader module can be input into the neural network 510. The neural network 510 can be a CNN including convolutional layers 512, 514, and 516. Convolution operations can be performed in the convolutional layers. In addition to the convolutional layers 512, 514, and 516, the neural network 510 can also include a depth-to-space layer. In the depth-to-space layer, the data in the depth dimension can be replaced with blocks of two-dimensional (2D) spatial data. The depth-to-space layer can be placed after the convolutional layers 512, 514, and 516, and direct resolution conversion can occur in the depth-to-space layer. In the neural network 510, the number of output channels in each layer can be increased or decreased by adjusting the number of filters included in the neural network 510. The supersampling processing can be performed by increasing the number of output channels required in the magnification for supersampling and changing the data output from the output channels to the width and height of the frame in the depth-to-space layer.

[0064] The neural network 510 can determine the color values of the uncolored pixels in the tile frame 310 through supersampling processing. Pixels with color values determined by coloring can be combined with pixels with color values determined by supersampling processing to determine the rendered tile frame 410.

[0065] Supersampling processing is a graphics processing technique for generating a high-resolution image (or frame) from a low-resolution image (or frame). In neural network-based supersampling processing, instead of using a predetermined formula for interpolation for supersampling, the neural network 510 is used. In one example, the neural network 510 for supersampling processing may have been trained through a training process. In the training process, the weights of the neural network 510 can be updated by inputting a low-resolution image (or frame) for training into the neural network 510 to obtain a high-resolution output image from the neural network 510 and minimizing the difference between the obtained high-resolution output image and a reference high-resolution image. These training processes can be performed for a large number of low-resolution images for training, and the trained neural network can be used to generate a high-resolution output image based on the low-resolution image given during the inference process.

[0066] In an example of the training process, a training tile frame in which only a part of the pixels in the edge region and the non-edge region are colored as in the tile frame 310 can be input into the neural network 510, and the neural network 510 can generate a rendered tile frame by performing supersampling processing on the input training tile frame. The quality difference between the rendered tile frame generated by the supersampling processing based on the neural network 510 and the rendered tile frame derived by performing coloring on all the pixels of the tile frame using a shader module can be measured, and the parameters of the neural network 510 (e.g., the connection weights between neurons and the biases of neurons) can be updated to reduce the measured quality difference. The update of the parameters can be performed using the error backpropagation algorithm. In the error backpropagation algorithm, the parameters of the neural network 510 can be updated such that the loss calculated using a loss function is reduced.

[0067] Figure 6 Shows an example output frame generated by image processing of an image rendering device according to one or more embodiments.

[0068] Refer to Figure 6 , in a non-limiting example, the output frame 600 may have a structure in which rendered tile frames are combined. In one example, each of Figure 1 the tile frames 122, 124, 126, and 128 may be performed as described above with reference to Figure 2The operations of the more detailed image rendering method are performed to generate the rendered tile frames 610, 620, 630, and 640, and the rendered tile frames 610, 620, 630, and 640 can be combined with each other again in the arrangement order of the tile frames 122, 124, 126, and 128 to generate the output frame 600.

[0069] Each of the edge regions 612, 622, 632, and 642 of the rendered tile frames 610, 620, 630, and 640 corresponds to a region that is colored using a shader module for high resolution. Each of the non-edge regions 614, 624, 634, and 644 of the rendered tile frames 610, 620, 630, and 640 corresponds to a region in which a part of the pixels is colored by the shader module and the remaining pixels are supersampled based on a neural network.

[0070] Figure 7 An example configuration of an image rendering device according to one or more embodiments is shown.

[0071] Referring Figure 7 , in a non-limiting example, an electronic device 700 (e.g., an image rendering device (such as Figure 1 the image rendering device 100)) may include a control processor 710 and a GPU 720, and the GPU 720 is configured to perform image rendering based on the control of the control processor 710. The shading and supersampling processes in the image rendering device may be performed in the same GPU 720. The image rendering device may include one or more GPUs 720. In one example, some of the components may be omitted from the image rendering device, or additional components may be added to the image rendering device.

[0072] In one example, the control processor 710 may control the GPU 720. The control processor 710 may send rendering-related commands to the GPU 720. The rendering-related commands may include commands for performing specific graphics processing tasks (e.g., commands for instructing the GPU 720 to render a specific input frame). The commands may include information about the resolution, image content, and / or color of the output frame. The control processor 710 may also be referred to as a host processor.

[0073] In one example, the control processor 710 may include a central processing unit (CPU). The control processor 710 may execute software (e.g., a program) for controlling the components (e.g., hardware components or software components) connected to the control processor 710 of the image rendering device, and may perform various data processing or operations. The control processor 710 may also be implemented as a system-on-chip (SoC) or an integrated circuit (IC) that performs processing.

[0074] The GPU 720 can render the input frame in units of tile frames. In one example, the GPU 720 can perform a series of processing tasks in a "graphics pipeline" to convert the input frame including an image into an output frame that can be rendered on a display. The graphics pipeline can include performing rendering operations on objects in image space, transforming and rasterizing objects in the image scene, and generating a 2D rendered image suitable for reproduction by display pixels.

[0075] The GPU 720 may include a command processor 721, a shader module 723, a scheduler module 725, a supersampler module 727, and a graphics memory 729. In one example, the graphics memory 729 may not be provided in the GPU 720, and the graphics memory 729 may include a first graphics memory that stores color values determined by the shader module 723 and a second graphics memory that stores color values determined by the supersampler module 727.

[0076] The command processor 721 can process commands received from the control processor 710 and control the execution of commands in the GPU 720. The command processor 721 can analyze the received commands and distribute rendering-related tasks to the shader module 723, the scheduler module 725, and / or the supersampler module 727 based on the analysis results.

[0077] The shader module 723 can perform shading on the tile frame to generate a preprocessed tile frame (e.g., Figure 3 and Figure 4 the tile frame 310). The shader module 723 can determine the color values of pixels by performing shading on the tile frame selected by the scheduler module 725. In one example, the shader module 723 can perform rendering tasks according to the graphics pipeline. The shader module 723 can include a vertex shader and a pixel shader. The vertex shader adjusts the characteristics of primitives for each vertex, and the pixel shader adjusts the pixel values of each pixel or adjusts the application of textures to primitives before sending the pixel data to the display. The shader module 723 can also include a geometry shader that generates a new set of primitives using the output of the vertex shader, and a compute shader that performs computational tasks.

[0078] The shader module 723 can determine the color values of a portion of pixels by performing shading on a portion of the pixels included in a tile frame corresponding to a partial area of an input frame. The shader module 723 can perform shading on the pixels in the edge area of the tile frame to determine the color values of the pixels in the edge area. In one example, the shader module 723 can perform shading on all the pixels included in the edge area through the shader module 723 to determine the color values of all the pixels in the edge area. The shader module 723 can perform shading on a portion of the pixels included in the non-edge area (other than the edge area) in the tile frame to determine the color values of a portion of the pixels in the non-edge area. As described above, the shader module 723 can perform shading on the edge area and the non-edge area in the tile frame at different resolutions to generate a preprocessed tile frame with different resolutions in the edge area and the non-edge area.

[0079] The scheduler module 725 can schedule the tile frames to be shaded by the shader module 723 and the tile frames to be supersampled by the supersampler module 727. The scheduler module 725 can control the processing order of the tile frames. The scheduler module 725 can select the tile frames that can be processed by the shader module 723 and / or the supersampler module 727 by checking the status of the tile frames to be rendered, and send information about the selected tile frames to the shader module 723 and the supersampler module 727.

[0080] In one example, the supersampler module 727 can perform a supersampling process on the preprocessed tile frame shaded by the shader module 723. The supersampler module 727 can generate a supersampled tile frame (e.g., Figure 4 tile frame 410) by using the preprocessed tile frame as an input. The supersampler module 727 can perform a neural network-based supersampling process on other pixels in the non-edge area among all the pixels included in the tile frame except the shaded pixels to determine the color values of the other pixels. The supersampler module 727 can perform a supersampling process based on the color values of the pixels in the edge area and the color values of a portion of the pixels in the non-edge area to determine the color values of other pixels in the non-edge area (pixels with color values not determined by shading through the shader module). The supersampler module 727 can perform a supersampling process without using the color values of the pixels included in other tile frames located around the tile frame.

[0081] The graphics memory 729 can store the data of the tile frames. The graphics memory 729 can be used as, for example, a buffer, and can include volatile memory and / or non-volatile memory. In an example where the shader module 723 and the supersampler module 727 are included in the same GPU 720 as shown in the example, the shader module 723 and the supersampler module 727 can share the same scheduler module 725 and the same graphics memory 729.

[0082] The graphics memory 729 can obtain the tile frames (the tile frames to be rendered) to be input to the shader module 723 from the system memory 730, store the tile frames, and store the rendered tile frames. The graphics memory 729 can store the tile frames input to the shader module 723 and the supersampler module 727, and the rendered tile frames output from the shader module 723 and the supersampler module 727, respectively. When the graphics memory 729 is provided, the memory access to the system memory 730 can be reduced during the shading and supersampling processes.

[0083] The graphics memory 729 can store the rendered tile frames, and the rendered tile frames include the color values of a part of the pixels colored by the shader module 723 among the pixels and the color values of the other pixels determined by the supersampling process of the supersampler module 727. In one example, the rendered tile frame can be a tile frame in which the color values of all the pixels are determined, similar to the tile frame 410 discussed in more detail above. In one example, when the supersampling process is completed by the supersampler module 727, the supersampler module 727 can send a signal notifying the graphics memory 729 of the completion of the supersampling process, and the graphics memory 729 can send the rendered tile frame to the system memory 730 in response to receiving the signal. Figure 4 The graphics memory 729 can store the rendered tile frames, and the rendered tile frames include the color values of a part of the pixels colored by the shader module 723 among the pixels and the color values of the other pixels determined by the supersampling process of the supersampler module 727. In one example, the rendered tile frame can be a tile frame in which the color values of all the pixels are determined, similar to the tile frame 410 discussed in more detail above. In one example, when the supersampling process is completed by the supersampler module 727, the supersampler module 727 can send a signal notifying the graphics memory 729 of the completion of the supersampling process, and the graphics memory 729 can send the rendered tile frame to the system memory 730 in response to receiving the signal.

[0084] The system memory 730 can store the commands and data transmitted between the control processor 710 and the GPU 720. After the tile frames are processed by the GPU 720, the processed tile frames can be stored in the system memory 730. The system memory 730 can receive the tile frames rendered by the image rendering device from the graphics memory 729 and store the received tile frames. The system memory 730 can store the output frames (e.g., Figure 1 the output frame 130) in which the rendered tile frames are combined.

[0085] Figure 8 An example configuration of an image rendering device according to one or more embodiments is shown.

[0086] Referring to Figure 8 In a non-limiting example, the electronic device 800 (e.g., an image rendering device (such as, Figure 1The image rendering device 100 may include a control processor 810, a GPU 820, and a supersampling processing unit 830. The GPU 820 is configured to perform image rendering based on the control of the control processor 810. The image rendering device may include one or more GPUs 820 and supersampling processing units 830. In one example, shading and supersampling processing may be performed on different devices (or components). In one example, some of the components may be omitted from the image rendering device, or additional components may be added to the image rendering device.

[0087] In one example, the control processor 810 may control the GPU 820 and the supersampling processing unit 830. The control processor 810 may send rendering-related commands to the GPU 820. In one example, the control processor 810 may include a CPU. The control processor 810 may execute software for controlling components connected to the control processor 810 of the image rendering device and may perform various data processing or operations. The control processor 810 may execute the operations performed by Figure 7 the control processor 710.

[0088] The GPU 820 may perform shading on the tile frames. In one example, the GPU 820 may include a command processor 822, a shader module 824, a scheduler module 826, and a first graphics memory 828.

[0089] The command processor 822 may process commands received from the control processor 810 and control the execution of commands in the GPU 820. The command processor 822 may analyze the received commands and distribute rendering-related tasks to the shader module 824 and the scheduler module 826 based on the analysis results.

[0090] The scheduler module 826 may schedule the tile frames to be shaded by the shader module 824. The scheduler module 826 may control the processing order of the tile frames processed by the shader module 824. The scheduler module 826 may select tile frames that can be processed by the shader module 824 by checking the status of the tile frames to be rendered and send information about the selected tile frames to the shader module 824.

[0091] The shader module 824 may perform shading on the tile frames to generate preprocessed tile frames (e.g., Figure 3 and Figure 4of the tile frame 310). The shader module 824 can determine the color value of a part of the pixels by performing shading on a part of the pixels included in the tile frame corresponding to a partial area of the input frame. In one example, the shader module 824 can perform shading on the pixels in the edge area of the tile frame to determine the color values of the pixels in the edge area. In one example, the shader module 824 can perform shading on all the pixels included in the edge area to determine the color values of all the pixels in the edge area. The shader module 824 can perform shading on some of the pixels included in the non-edge area other than the edge area in the tile frame to determine the color values of some of the pixels in the non-edge area.

[0092] The first graphics memory 828 can store the data of the tile frame. In one example, the first graphics memory 828 can be used as a buffer and can include volatile memory and / or non-volatile memory. The first graphics memory 828 can store the color values of a part of the pixels (e.g., all the pixels in the edge area and a part of the pixels in the non-edge area) determined by the shading of the shader module 824. The first graphics memory 828 can store the preprocessed tile frame shaded by the shader module 824 and send the preprocessed tile frame to the system memory 840. When the shading of the tile frame is completed by the shader module 824, the shader module 824 can send a signal indicating the completion of the shading to the first graphics memory 828. In response to receiving the signal, the first graphics memory 828 can send the preprocessed tile frame received from the shader module 824 to the system memory 840.

[0093] The preprocessed tile frame stored in the system memory 840 can be shared with the supersampling processing unit 830 and assigned to the second graphics memory 838 of the supersampling processing unit 830. The supersampling processing unit 830 can perform supersampling processing on the preprocessed tile frame shaded by the shader module 824. In one example, the supersampling processing unit 830 can include a command processor 832, a supersampler module 834, a scheduler module 836, and a second graphics memory 838.

[0094] The command processor 832 can process the commands received from the control processor 810 and control the execution of the commands in the supersampling processing unit 830. The command processor 832 can analyze the received commands and distribute the rendering-related tasks to the supersampler module 834 and the scheduler module 836 based on the analysis results.

[0095] The scheduler module 836 can schedule the tile frames super-sampled by the super-sampler module 834. The scheduler module 836 can control the processing order of the tile frames processed by the super-sampler module 834. The scheduler module 836 can select the tile frames that can be processed by the super-sampler module 834 by checking the status of the tile frames to be rendered, and send information about the selected tile frames to the super-sampler module 834.

[0096] The super-sampler module 834 can perform super-sampling processing on the pre-processed tile frames shaded by the shader module 824. The super-sampler module 834 can generate super-sampled tile frames (e.g., Figure 4 tile frame 410) by using the pre-processed tile frames as inputs. The super-sampler module 834 can perform neural network-based super-sampling processing on other pixels in the non-edge regions among all the pixels included in the tile frames except for the shaded pixels to determine the color values of the other pixels. The super-sampler module 834 can perform super-sampling processing based on the color values of the pixels in the edge regions and the color values of a part of the pixels in the non-edge regions to determine the color values of the other pixels (pixels with color values not determined by shading through the shader module) in the non-edge regions.

[0097] The second graphics memory 838 can store the data of the tile frames. In one example, the second graphics memory 838 can be used as a buffer and can include volatile memory and / or non-volatile memory. The second graphics memory 838 can store the color values of the other pixels (pixels with color values not determined by shading through the shader module) in the non-edge regions determined by the super-sampling processing of the super-sampler module 834. The second graphics memory 838 can store the tile frames super-sampled by the super-sampler module 834 and send the super-sampled tile frames to the system memory 840. When the super-sampling processing of the tile frames is completed by the super-sampler module 834, the super-sampler module 834 can send a signal notifying the completion of the super-sampling processing to the second graphics memory 838. In response to receiving the signal, the second graphics memory 838 can send the super-sampled tile frames from the super-sampler module 834 to the system memory 840.

[0098] The system memory 840 can be connected to the first graphics memory 828 of the GPU 820 and the second graphics memory 838 of the supersampling processing unit 830. The data of the tile frame can be shared between the first graphics memory 828 and the second graphics memory 838 via the system memory 840. In one example, the data can be moved between the first graphics memory 828 and the second graphics memory 838 in units of tile frames (or multiple tile frames) via the system memory 840. The system memory 840 can store the rendered tile frames, and the rendered tile frames include the color values of a part of the pixels colored by the shader module 824 among the pixels and the color values of other pixels determined by the supersampling process of the supersampler module 834.

[0099] The various examples described herein can be implemented in the form of a chip including circuits or software, and installed on an electronic device. The electronic device can be, for example, a mobile communication terminal, a smart phone, a tablet personal computer (PC), a notebook, a personal digital assistant (PDA), a wearable device (e.g., a virtual reality (VR) device or an augmented reality (AR) device), a server, a television, a monitor, a digital camera, or a PC.

[0100] For Figures 1 to 8The electronic devices, processors, memories, neural networks, CPUs, GPUs, image rendering device 100, neural network 510, electronic device 700, control processor 710, GPU 720, command processor 721, shader module 723, scheduler module 725, supersampler module 727, graphics memory 729, system memory 730, electronic device 800, control processor 810, GPU 820, supersampling processing unit 830, command processor 822, shader module 824, scheduler module 826, first graphics memory 828, command processor 832, supersampler module 834, scheduler module 836, second graphics memory 838, and system memory described herein are implemented by or represent hardware components. As described above, or in addition to the above description, examples of hardware components that can be used to perform the operations described in this application include, where appropriate: controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). The processor or computer can be implemented by one or more processing elements (such as, logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond and execute instructions in a defined manner to achieve the desired result). In one example, the processor or computer includes or is connected to one or more memories that store instructions or software executed by the processor or computer. The hardware components implemented by the processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) to perform the operations described in this application. The hardware components can also access, manipulate, process, create, and store data in response to the execution of the instructions or software. For the sake of brevity, the singular terms "processor" or "computer" can be used in the description of the examples described in this application, but in other examples, multiple processors or computers can be used, or the processor or computer can include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component, or two or more hardware components, can be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or additional processors and additional controllers.One or more processors, or a processor and a controller, can implement a single hardware component, or two or more hardware components. As described above, or in addition to the above description, example hardware components can have any one or more of different processing configurations. Examples of different processing configurations include: a single processor, a stand-alone processor, a parallel processor, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0101] Figures 1 to 8 The method of performing the operations described in this application, shown in ,

[0101] , and Figures 1 to 8 , is performed by computing hardware (e.g., by one or more processors or a computer) that is implemented to execute instructions or software as described above to perform the operations performed by the method described in this application. For example, a single operation, or two or more operations, can be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations can be performed by one or more processors, or a processor and a controller, and one or more other operations can be performed by one or more other processors, or additional processors and additional controllers. One or more processors, or a processor and a controller, can perform a single operation, or two or more operations.

[0102] Instructions or software for controlling computing hardware (e.g., one or more processors or a computer) to implement the hardware components and perform the method as described above can be written as a computer program, code segment, instruction, or any combination thereof to individually or jointly direct or configure one or more processors or a computer to operate as a machine or a special-purpose computer to perform the operations performed by the hardware components and the method as described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) that is directly executed by one or more processors or a computer. In another example, the instructions or software include high-level code that is executed by one or more processors or a computer using an interpreter. The instructions or software can be written in any programming language based on the block diagrams and flowcharts shown in the figures and the corresponding descriptions herein, and the block diagrams and flowcharts shown in the figures and the corresponding descriptions herein disclose algorithms for performing the operations performed by the hardware components and the method as described above.

[0103] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement the hardware components and execute the methods as described above, along with any associated data, data files, and data structures, can be recorded, stored, or fixed in one or more non-transitory computer-readable storage media, or on one or more non-transitory computer-readable storage media. As described above, or in addition to the above description, examples of non-transitory computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage devices, hard disk drives (HDDs), solid state drives (SSDs), cartridge memories (such as multimedia cards or micro-cards (e.g., Secure Digital (SD) or Extreme Digital (XD))), magnetic tapes, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid state disks, and / or any one or more of any other devices configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and to provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers such that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed across a networked computer system such that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0104] Although the present disclosure includes specific examples, it will be apparent after understanding the disclosure of this application that various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered illustrative only and not for purposes of limitation. The description of a feature or aspect in each example should be considered applicable to similar features or aspects in other examples. Suitable results can be achieved if the described techniques are performed in a different order, and / or if the components in the described systems, architectures, devices, or circuits are combined in a different manner, and / or are replaced or supplemented by other components or their equivalents.

[0105] Accordingly, in addition to what has been described above and what is disclosed in all of the accompanying drawings, the scope of the disclosure also includes the claims and their equivalents, that is, all variations within the scope of the claims and their equivalents will be construed as being included in the disclosure.

Claims

1. A processor-implemented method for tile-based image rendering, the method comprising: Determining a first color value for a portion of pixels among a plurality of pixels by performing shading on the portion of pixels using a shader module, the plurality of pixels being in a tile frame corresponding to a partial region of an input frame; Determining a second color value for other pixels by performing neural network-based supersampling processing on the other pixels, the other pixels being pixels among the plurality of pixels that are not included in the portion of pixels of the tile frame; And Determining a rendered tile frame including the first color value of the portion of pixels and the second color value of the other pixels, Wherein the step of determining the first color value for the portion of pixels includes: determining an edge color value for pixels in an edge region of the tile frame by performing shading on the pixels in the edge region using a shader module.

2. The method according to claim 1, wherein The step of determining the first color value further includes: determining a non-edge color value for non-edge partial pixels by performing shading on the non-edge partial pixels in a non-edge region using a shader module, the non-edge partial pixels being included in the non-edge region, and the non-edge region being the region of the tile frame other than the edge region.

3. The method according to claim 2, wherein, The step of determining the second color value includes: performing the supersampling processing based on the edge color value and the non-edge color value.

4. The method according to claim 1, wherein, The step of determining the second color value includes: performing the supersampling processing without using a third color value of pixels included in additional tile frames located around the tile frame.

5. The method according to claim 1, wherein, The step of determining the edge color value includes: determining an overall edge color value for all pixels in the edge region by performing shading on all pixels included in the edge region using a shader module.

6. The method according to claim 2, wherein, Determining the number of non-edge partial pixels to be shaded using the shader module based on at least one of an image magnification ratio, a frame rate, and an estimated resource consumption.

7. The method according to any one of claims 1 to 6, further comprising: After determining the second color value, sending the rendered tile frame including the first color value and the second color value to a system memory.

8. The method according to any one of claims 1 to 6, wherein, The step of determining the first color value is performed by a shader module included in a graphics processor, and Wherein the step of determining the second color value is performed by a supersampler module configured to perform the supersampling processing.

9. The method according to claim 8, wherein, The supersampler module is included in the graphics processor.

10. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 9.

11. An electronic device, comprising: A control processor; And A graphics processor configured to perform image rendering based on control by the control processor, Wherein the graphics processor includes: A processor configured to execute instructions; and A memory storing the instructions, wherein executing the instructions configures the processor to: Determine a first color value for a first portion of pixels by performing shading on the first portion of pixels, the first portion of pixels being pixels among a plurality of pixels in a tile frame corresponding to a partial region of an input frame; and Determining a second color value for a second portion of pixels by performing neural network-based supersampling processing on the second portion of pixels, where the second portion of pixels are pixels among the plurality of pixels that are not included in a first portion of pixels; and A graphics memory configured to store a rendered tile frame including a first color value of the first portion of pixels and a second color value of the second portion of pixels, and wherein the step of determining the first color value includes: determining an edge color value of pixels in an edge region of the tile frame by performing shading on the pixels in the edge region of the tile frame.

12. The electronic device according to claim 11, wherein, The step of determining the first color value further includes: determining a non-edge color value of a third portion of pixels by performing shading on the third portion of pixels in a non-edge region, where the non-edge region is a region of the tile frame other than the edge region.

13. The electronic device according to claim 12, wherein, The step of determining the second color value includes: determining the second color value by performing the supersampling processing based on the edge color value and the non-edge color value.

14. The electronic device according to claim 11, wherein, The step of determining the second color value includes: performing the supersampling processing without using a third color value of pixels included in additional tile frames located around the tile frame.

15. The electronic device according to claim 11, wherein, The step of determining the edge color value includes: determining all edge color values of all pixels in the edge region by performing shading on all pixels included in the edge region.

16. The electronic device according to any one of claims 11 to 15, further comprising: A system memory configured to: receive the tile frame rendered by the electronic device from the graphics memory and store an output frame obtained by combining the rendered tile frames.

17. An electronic device, comprising: A graphics processor, comprising: A processor configured to execute instructions; and A memory storing the instructions, wherein executing the instructions configures the processor to: Determine a first color value of a first portion of pixels by performing shading on the first portion of pixels, where the first portion of pixels are pixels among a plurality of pixels included in a tile frame corresponding to a partial region of an input frame; and Determine a second color value of a second portion of pixels by performing neural network-based supersampling processing on the second portion of pixels, where the second portion of pixels are pixels among the plurality of pixels that are not included in the first portion of pixels; A first graphics memory configured to store the determined first color value of the first portion of pixels; A second graphics memory configured to store the determined second color value of the second portion of pixels; and A system memory connected to the first graphics memory and the second graphics memory, wherein the step of determining the first color value includes: determining an edge color value of pixels in an edge region of the tile frame by performing shading on the pixels in the edge region of the tile frame.

18. The electronic device according to claim 17, wherein, The step of determining the first color value further includes: determining a non-edge color value of a third portion of pixels by performing shading on the third portion of pixels in a non-edge region, where the non-edge region is a region of the tile frame other than the edge region.

19. The electronic device according to claim 18, wherein, The step of determining the second color value includes: determining the second color value by performing the supersampling processing based on the edge color value and the non-edge color value.

20. The electronic device according to any one of claims 17 to 19, wherein, The system memory is configured to store a rendered tile frame including a first color value and a second color value.

Images