Memory testing method, device, equipment and medium

Abstract

The memory testing method, apparatus, device and medium provided by the embodiments of the present disclosure include: obtaining write data and read data of multiple storage cells, wherein the write data of different storage cells are the same, and the read data of different storage cells are read write data; determining a first test result of the target storage cell group based on the read data of the storage cells included in the target storage cell group, wherein any storage cell group includes a first storage cell and a second storage cell; determining a second test result of the storage cells included in the target storage cell group based on the write data and read data of the storage cells included in the target storage cell group; determining the read and write status of the storage cells included in the target storage cell group based on the first test result of the target storage cell group and the second test result of the storage cells included in the target storage cell group, and determining the status of the write operation and read operation of the two storage cells included in each storage cell group.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of memory technology and related technologies, and in particular, to a memory testing method, apparatus, device, and medium. Background Art

[0002] With the rapid development of integrated circuits, chip functions are becoming increasingly complex. Testing and verification in chip design has become the most time-consuming task in the chip R&D process, occupying an increasingly larger proportion of the R&D cycle. The verification workload has accounted for 65% to 70% of the entire chip R&D. In the verification process, building the verification platform, debugging the verification platform, and waveform checking work account for a large workload. Therefore, how to improve the efficiency of verification becomes crucial.

[0003] In the existing technology, most of them use a simple UVM verification platform to complete the construction of the scene, generate simulation waveforms, and manually open the waveforms to check the read and write operations of the asynchronous memory chip to determine whether the read and write are correct. However, this method cannot realize the write and read check of the full address data of the asynchronous memory chip, and can only randomly check whether the write and read data of some addresses in some scenarios are correct. In addition, waveform checking consumes a lot of time and may cause manual inspection errors. Summary of the Invention

[0004] The embodiments described herein provide a memory testing method, apparatus, device, and medium that solve the problems existing in the prior art.

[0005] In a first aspect, according to the present disclosure, a memory testing method is provided, comprising:

[0006] Acquire write data and read data of a plurality of storage units, wherein the write data of different storage units are the same, and the read data of different storage units are the read write data;

[0007] determining a first test result of the target storage cell group according to read data of storage cells included in the target storage cell group, wherein any storage cell group includes a first storage cell and a second storage cell;

[0008] determining a second test result of the storage cells included in the target storage cell group according to the write data and the read data of the storage cells included in the target storage cell group;

[0009] The read and write states of the storage cells included in the target storage cell group are determined according to the first test result of the target storage cell group and the second test results of the storage cells included in the target storage cell group.

[0010] In some embodiments of the present disclosure, the method further includes:

[0011] The read / write status of the memory is determined according to the read / write status of the storage units included in different target storage unit groups.

[0012] In some embodiments of the present disclosure, before determining the first test result of the target storage unit group based on the read data of the storage units included in the target storage unit group, the method further includes:

[0013] According to the storage units included in the memory, the storage units are combined in pairs to obtain multiple groups of storage unit groups.

[0014] In some embodiments of the present disclosure, determining a first test result of the target storage cell group based on read data of storage cells included in the target storage cell group includes:

[0015] Acquire first read data of a first storage cell included in the target storage cell group, and second read data of a second storage cell included in the target storage cell group;

[0016] The first read data and the second read data are sequentially compared for the same number of bits, and a first test result of the target memory cell group is determined according to the comparison result of the first read data and the second read data for the same number of bits.

[0017] In some embodiments of the present disclosure, determining the second test results of the storage cells included in the target storage cell group according to the write data and the read data of the storage cells included in the target storage cell group includes:

[0018] Acquire first read data and first write data of a first storage cell included in the target storage cell group, and second read data and second write data of a second storage cell included in the target storage cell group;

[0019] sequentially comparing data of the same number of bits in the first read data and the first write data, and determining a third test result of the first storage unit according to the comparison result of the data of the same number of bits in the first read data and the first write data;

[0020] The data of the same number of bits in the second read data and the second write data are sequentially compared, and a fourth test result of the second storage unit is determined according to the comparison result of the data of the same number of bits in the second read data and the second write data.

[0021] In some embodiments of the present disclosure, determining the read / write status of the storage cells included in the target storage cell group according to the first test result of the target storage cell group and the second test result of the storage cells included in the target storage cell group includes:

[0022] When the second test results of the storage cells included in the target storage cell group are all low levels, and the first test results of the target storage cell group are low levels, the read states and write states of the storage cells included in the target storage cell group are normal;

[0023] When the first test result of the target storage cell group is a high level, there is a storage cell in the storage cells included in the target storage cell group whose read state or write state is abnormal.

[0024] In some embodiments of the present disclosure, when the first test result of the target storage cell group is a high level, there is a storage cell in the storage cells included in the target storage cell group with an abnormal read state or an abnormal write state, including:

[0025] When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all low levels, and the fourth test results of the second storage cells included in the target storage cell group are all high levels, then the read state of the second storage cells included in the target storage cell group is abnormal;

[0026] When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all high levels and the fourth test results of the second storage cells included in the target storage cell group are all low levels, then the read state of the first storage cells included in the target storage cell group is abnormal;

[0027] When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all low levels, and the fourth test results of the second storage cells included in the target storage cell group are all low levels, then the write state of the first storage cells included in the target storage cell group is abnormal, or the write state of the second storage cells is abnormal.

[0028] In a second aspect, according to the present disclosure, a memory testing device is provided, comprising:

[0029] A data acquisition module is used to acquire write data and read data of multiple storage units, wherein the write data of different storage units are the same, and the read data of different storage units are the read write data;

[0030] a first test result determination module, configured to determine a first test result of the target storage cell group based on read data of storage cells included in the target storage cell group, wherein any storage cell group includes a first storage cell and a second storage cell;

[0031] a second test result determining module, configured to determine a second test result of the storage cells included in the target storage cell group according to the write data and the read data of the storage cells included in the target storage cell group;

[0032] The read / write status determination module is configured to determine the read / write status of the storage cells included in the target storage cell group according to the first test result of the target storage cell group and the second test result of the storage cells included in the target storage cell group.

[0033] In a third aspect, according to the present disclosure, a computer device is provided, comprising:

[0034] one or more processors;

[0035] a storage device for storing one or more programs,

[0036] When the one or more programs are executed by the one or more processors, the one or more processors implement any method as described in the first aspect.

[0037] In a fourth aspect, according to the content of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, it implements any method as described in the first aspect.

[0038] The memory testing method, apparatus, device, and medium provided by the embodiments of the present disclosure first obtain write data and read data of multiple memory cells, wherein the write data of different memory cells are the same and the read data of different memory cells are read write data; then, based on the read data of the memory cells included in the target memory cell group, a first test result of the target memory cell group is determined; and based on the write data and read data of the memory cells included in the target memory cell group, a second test result of the memory cells included in the target memory cell group is determined; finally, based on the first test result of the target memory cell group and the second test result of the memory cells included in the target memory cell group, the read and write status of the memory cells included in the target memory cell group is determined. Compared with the prior art that only compares the write data and read data of the memory cells to determine whether there is an abnormality in the read operation of the memory cells, the embodiments of the present disclosure write test data stored in a register into different memory cells, compares the read data of the memory cell group consisting of any two memory cells to obtain a first test result, and compares the write data and read data of two memory cells included in the memory cell group to obtain two second test results. The first test result and the second test result can be used to determine the status of the write and read operations of the two memory cells included in the memory cell group. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0040] Figure 1 is a flowchart of a memory testing method provided by an embodiment of the present disclosure;

[0041] Figure 2 is a structural diagram of a memory testing device provided by an embodiment of the present disclosure;

[0042] Figure 3 It is a structural diagram of a computer device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0045] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0046] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0047] Based on the problems existing in the prior art, the present invention provides a memory testing method. Figure 1 FIG. 1 is a flow chart of a memory testing method provided by an embodiment of the present disclosure, such as Figure 1 As shown, the memory testing method includes:

[0048] S110 , obtaining write data and read data of a plurality of storage units.

[0049] The written data of different storage units are the same, and the read data of different storage units are the read written data.

[0050] In a specific embodiment, when the memory is in the test mode, each storage unit performs a write operation to write the test data stored in the register to obtain the write data, and then each storage unit performs a read operation to read the write data to obtain the read data.

[0051] In the prior art, only by comparing the written data and read data of each storage unit to determine whether the read data is consistent with the written data, but it is impossible to determine whether the data is written correctly. To address the problems existing in the prior art, the memory test method provided in the embodiment of the present disclosure first writes the test data stored in the register into each storage unit. When the read operation of each storage unit is normal, it is possible to determine whether the write operation of each storage unit is abnormal by comparing the read data of any two storage units.

[0052] Therefore, in the memory testing method provided by the embodiment of the present disclosure, the write data and read data of multiple memory cells are first obtained, wherein the write data is based on the write operation of each memory cell, and is the data obtained by writing the test data stored in the register into each memory cell; the read data is based on the read operation of each memory cell, and is the data obtained by reading the write data of each memory cell.

[0053] S120 : Determine a first test result of the target storage cell group according to the read data of the storage cells included in the target storage cell group.

[0054] Wherein, any storage unit group includes a first storage unit and a second storage unit.

[0055] In order to determine whether there is an abnormality in the process of writing data to the memory, the memory testing method provided in the embodiment of the present disclosure further includes, before executing step S120, combining the storage cells included in the memory into two groups to obtain multiple groups of storage cells.

[0056] In a specific embodiment, according to the storage units included in the memory, the storage units are combined in pairs to obtain multiple groups of storage units.

[0057] In a specific example, if the number of storage units included in the memory is 8, namely storage unit 01, storage unit 02, storage unit 03, storage unit 04, storage unit 05, storage unit 06, storage unit 07 and storage unit 08, then storage unit 01 and storage unit 02 are combined into a first storage unit group 001, storage unit 03 and storage unit 04 are combined into a second storage unit group 002, storage unit 05 and storage unit 06 are combined into a third storage unit group 003, and storage unit 07 and storage unit 08 are combined into a fourth storage unit group. Group 004, at this time, a first test result is obtained by comparing the read data of storage cell 01 and storage cell 02 in the first storage cell group 001, a first test result is obtained by comparing the read data of storage cell 03 and storage cell 04 in the second storage cell group 002, a first test result is obtained by comparing the read data of storage cell 05 and storage cell 06 in the third storage cell group 003, and a first test result is obtained by comparing the read data of storage cell 07 and storage cell 08 in the fourth storage cell group 004.

[0058] It should be noted that, in the above embodiment, an example of a combination of storage unit groups is shown. Storage unit 01 and storage unit 08 may form a storage unit group, storage unit 02 and storage unit 07 may form a storage unit group, storage unit 03 and storage unit 06 may form a storage unit group, and storage unit 04 and storage unit 05 may form a storage unit group. The embodiment of the present disclosure does not limit the specific combination of storage unit groups.

[0059] As a specific implementable method, determining a first test result of the target storage cell group based on the read data of the storage cells included in the target storage cell group includes: obtaining first read data of the first storage cell included in the target storage cell group, and second read data of the second storage cell included in the target storage cell group; comparing the data of the same number of bits in the first read data and the second read data in sequence, and determining the first test result of the target storage cell group based on the comparison result of the data of the same number of bits in the first read data and the second read data.

[0060] The following embodiment will be specifically described by taking as an example that the first storage unit included in the target storage unit group is storage unit 01 and the second storage unit included in the target storage unit group is storage unit 02.

[0061] First, obtain the first read data of the storage cell 01 included in the target storage cell group and the second read data of the storage cell 02 included in the target storage cell group. Specifically, for example, if the test data stored in the register is Testcode<7:0>, the first write data of the storage cell 01 is Write1<7:0>, the first read data of the storage cell 01 is Read1<7:0>, the second write data of the storage cell 02 is Write2<7:0>, and the second read data of the storage cell 02 is Read2<7:0>. If there is no abnormality in the process of the storage cell 01 performing a read operation to read the first write data Write1<7:0> and the process of the storage cell 02 performing a read operation to read the second write data Write2<7:0> is normal, then according to the first test result determined by the first read data Read1<7:0> and the second read data Read2<7:0>, it can be determined whether the process of the storage cell 01 performing a write operation to write the test data stored in the register into the storage cell 01 and the process of the storage cell 02 performing a write operation to write the test data stored in the register into the storage cell 02 are abnormal.

[0062] In the above embodiment, whether the process of the storage unit 01 performing the read operation to read the first write data Write1<7:0> is abnormal and whether the process of the storage unit 02 performing the read operation to read the second write data Write2<7:0> is abnormal can be determined based on step S130.

[0063] In a specific embodiment, the first read data Read1<7:0> and the second read data Read2<7:0> are both 8 bits. <0> and the second read data first bit data Read2 <0> , compare the first read data with the second data Read1 <1> and the second read data second bit data Read2 <1> , ...., compare the eighth bit of the first read data Read1 <7> and the eighth bit of the second read data Read2 <7> , in the first read data first bit data Read1 <0> and the second read data first bit data Read2 <0> Same, the first read data second data Read1 <1> and the second read data second bit data Read2 <1> Same, ...., the first read data eighth data Read1 <7> and the eighth bit of the second read data Read2 <7> If they are the same, then the write and read operations of storage unit 01 and storage unit 02 are normal, and the first bit of data Read1 is read. <0> and the second read data first bit data Read2 <0> , the first read data second bit data Read1 <1> and the second read data second bit data Read2 <1> , ...., the first read data eighth bit data Read1 <7> and the eighth bit of the second read data Read2 <7> If there is at least one set of first read data and second read data that are different in a certain bit, it may be that there is an abnormality in the read operation or write operation of the storage unit 01, or it may be that there is an abnormality in the read operation or write operation of the storage unit 02.

[0064] It should be noted that, in the above embodiment, when the first read data Read1<7:0> of the storage cell 01 and the second read data Read2<7:0> of the storage cell 02 are the same, the first test result of the storage cell group 001 where the storage cell 01 and the storage cell 02 are located is a low level; when there is at least one group of the first read data Read1<7:0> of the storage cell 01 and the second read data Read2<7:0> of the storage cell 02 in which a certain bit of the first read data and the second read data are different, the first test result of the storage cell group 001 where the storage cell 01 and the storage cell 02 are located is a high level.

[0065] S130 : Determine a second test result of the memory cells included in the target memory cell group according to the write data and the read data of the memory cells included in the target memory cell group.

[0066] In a specific embodiment, determining the second test results of the storage cells included in the target storage cell group based on the write data and the read data of the storage cells included in the target storage cell group includes: obtaining the first read data and the first write data of the first storage cell included in the target storage cell group, and the second read data and the second write data of the second storage cell included in the target storage cell group; comparing the data of the same number of bits in the first read data and the first write data in sequence, and determining the third test result of the first storage cell based on the comparison result of the data of the same number of bits in the first read data and the first write data; comparing the data of the same number of bits in the second read data and the second write data in sequence, and determining the fourth test result of the second storage cell based on the comparison result of the data of the same number of bits in the second read data and the second write data.

[0067] In a specific embodiment, the first read data Read1<7:0> and the first write data Write1<7:0> are both 8 bits. <0> And the first write data first bit data Write1 <0> , compare the first read data with the second data Read1 <1> and the first write data second bit data Write1 <1> , ...., compare the eighth bit of the first read data Read1 <7> And the first write data eighth bit data Write1 <7> , if the first data is the first bit of the read data Read1 <0> And the first write data first bit data Write1 <0> Same, the first read data second data Read1 <1> and the first write data second bit data Write1 <1> Same, ...., the first read data eighth data Read1 <7> And the first write data eighth bit data Write1 <7> If the first data is the same as Read1, then the read operation of the storage unit 01 is normal. <0> And the first write data first bit data Write1 <0> , the first read data second bit data Read1 <1> And the first write data second data Write1 <1> , ...., the first read data eighth bit data Read1 <7> And the first write data eighth bit data Write1 <7> If there is at least one set of first read data and first write data that are different in a certain bit, then the read operation of the storage unit 01 is abnormal.

[0068] Similarly, the second read data Read2<7:0> and the second write data Write2<7:0> are both 8 bits. Compare the first bit data Read2 of the second read data <0> And the second write data first bit data Write2 <0> , compare the second read data second bit data Read2 <1> The second bit of the second write data is Write2 <1> , ...., compare the eighth bit of the second read data Read2 <7> And the eighth bit of the second write data Write2 <7> , if the first bit of the second read data is Read2 <0> And the second write data first bit data Write2 <0> Same, the second read data second bit data Read2 <1> and the second write data second bit data Write2 <1> Same, ...., the eighth bit of the second read data Read2 <7> And the eighth bit of the second write data Write2 <7> If the first bit of the second read data is Read2, then the read operation of the storage unit 01 is normal. <0> And the second write data first bit data Write2 <0> , the second read data second bit data Read2 <1> and the second write data second bit data Write2 <1> , ...., the second read data eighth bit data Read2 <7> And the eighth bit of the second write data Write2 <7> If there is at least one set of a certain bit of the second read data and the second write data that are different, then the read operation of the storage unit 02 is abnormal.

[0069] It should be noted that, in the above embodiment, when the first read data Read1<7:0> of the storage cell 01 and the first write data Write1<7:0> of the storage cell 01 are the same, the third test result of the storage cell 01 is a low level, and when the second read data Read2<7:0> of the storage cell 02 and the second write data Write2<7:0> of the storage cell 02 are the same, the fourth test result of the storage cell 02 is a low level.

[0070] When there is at least one group of a certain bit of the first read data Read1<7:0> of the storage cell 01 and the first write data Write1<7:0> of the storage cell 01, in which the read data and the first write data are different, the third test result of the storage cell 01 is a high level; when there is at least one group of a certain bit of the second read data and the second write data different in the second read data Read2<7:0> of the storage cell 02 and the second write data Write2<7:0> of the storage cell 02, in which the fourth test result of the storage cell 02 is a high level.

[0071] By judging the write data and read data of the same storage unit, it can be determined whether the write data and the read data are consistent. If the write data and the read data are inconsistent, there is an abnormality in the read operation of the storage unit. If the write data and the read data are consistent, there is no abnormality in the read operation of the storage unit.

[0072] S140 , determining the read and write states of the memory cells included in the target memory cell group according to the first test result of the target memory cell group and the second test results of the memory cells included in the target memory cell group.

[0073] In a specific implementation method, the read and write states of the storage cells included in the target storage cell group are determined based on the first test result of the target storage cell group and the second test result of the storage cells included in the target storage cell group, including: when the second test results of the storage cells included in the target storage cell group are all low levels, and the first test result of the target storage cell group is low level, then the read state and write state of the storage cells included in the target storage cell group are normal; when the first test result of the target storage cell group is high level, then there is a storage cell in the storage cells included in the target storage cell group whose read state or write state is abnormal.

[0074] Since comparing the write data and read data of a storage cell can only determine whether there is an abnormality in the read operation of the storage cell, when there is an abnormality in the write operation of the storage cell, simply comparing the write data and read data of the storage cell cannot determine it. Therefore, the embodiment of the present disclosure writes the test data stored in the register into different storage cells, compares the read data of two storage cells in the same storage cell group to obtain a first test result, and compares the write data and read data of the two storage cells included in the storage cell group to obtain two second test results. Finally, based on the first test result and the second test result, the status of the read operation and the write operation of the two storage cells included in the storage cell group can be determined.

[0075] In an exemplary embodiment, the first storage cell included in the target storage cell group is storage cell 01, and the second storage cell included in the target storage cell group is storage cell 02. If the third test result based on the first write data and the first read data of storage cell 01 is a low level, the fourth test result based on the second write data and the second read data of storage cell 02 is a low level, and the first test result based on the first read data of storage cell 01 and the second read data of storage cell 02 of the target storage cell group is a low level, then the read operation and the write operation of storage cell 01 are both normal, and the read operation and the write operation of storage cell 02 are both normal; if the first test result based on the first read data of storage cell 01 and the second read data of storage cell 02 of the target storage cell group is a high level, the third test result based on the first write data and the first read data of storage cell 01 is a high level, the first test result based on the second write data of storage cell 02 is a high level. If the fourth test result of the first read data and the second read data of the storage cell 01 based on the target storage cell group is a high level, the third test result based on the first write data and the first read data of the storage cell 01 is a low level, and the fourth test result based on the second write data and the second read data of the storage cell 02 is a high level, then the read operation of the storage cell 02 is abnormal. If the first test result of the first read data of the storage cell 01 based on the target storage cell group and the second read data of the storage cell 02 is a high level, the third test result based on the first write data and the first read data of the storage cell 01 is a low level, and the fourth test result based on the second write data and the second read data of the storage cell 02 is a low level, then the write operation of the storage cell 01 or the storage cell 02 is abnormal.

[0076] The memory test method provided by the embodiment of the present disclosure first obtains write data and read data of multiple memory cells, wherein the write data of different memory cells are the same and the read data of different memory cells are read write data; then, based on the read data of the memory cells included in the target memory cell group, a first test result of the target memory cell group is determined; and based on the write data and read data of the memory cells included in the target memory cell group, a second test result of the memory cells included in the target memory cell group is determined; finally, based on the first test result of the target memory cell group and the second test result of the memory cells included in the target memory cell group, the read and write status of the memory cells included in the target memory cell group is determined. Compared with the prior art that only compares the write data and read data of the memory cells to determine whether there is an abnormality in the read operation of the memory cells, the embodiment of the present disclosure writes test data stored in a register into different memory cells, compares the read data of the memory cell group consisting of any two memory cells to obtain a first test result, and compares the write data and read data of two memory cells included in the memory cell group to obtain two second test results. The first test result and the second test result can be used to determine the status of the write operation and the read operation of the two memory cells included in the memory cell group.

[0077] Based on the above embodiments, the present disclosure further provides a memory testing device. Figure 2 FIG. 1 is a structural diagram of a memory testing device provided by an embodiment of the present disclosure. Figure 2 As shown, the memory test device includes:

[0078] A data acquisition module 210 is configured to acquire write data and read data of a plurality of storage units, wherein the write data of different storage units are the same, and the read data of different storage units are the read write data;

[0079] A first test result determination module 220 is configured to determine a first test result of a target storage cell group based on read data of storage cells included in the target storage cell group, wherein any storage cell group includes a first storage cell and a second storage cell;

[0080] A second test result determination module 230 is configured to determine a second test result of the storage cells included in the target storage cell group based on the write data and the read data of the storage cells included in the target storage cell group;

[0081] The read / write status determination module 240 is configured to determine the read / write status of the storage cells included in the target storage cell group according to the first test result of the target storage cell group and the second test results of the storage cells included in the target storage cell group.

[0082] The memory testing device provided by the embodiment of the present disclosure first obtains write data and read data of multiple memory cells, wherein the write data of different memory cells are the same and the read data of different memory cells are read write data; then, based on the read data of the memory cells included in the target memory cell group, a first test result of the target memory cell group is determined; and based on the write data and read data of the memory cells included in the target memory cell group, a second test result of the memory cells included in the target memory cell group is determined; finally, based on the first test result of the target memory cell group and the second test result of the memory cells included in the target memory cell group, the read and write status of the memory cells included in the target memory cell group is determined. Compared with the prior art that only compares the write data and read data of the memory cells to determine whether there is an abnormality in the read operation of the memory cells, the embodiment of the present disclosure writes test data stored in a register into different memory cells, compares the read data of the memory cell group consisting of any two memory cells to obtain a first test result, and compares the write data and read data of two memory cells included in the memory cell group to obtain two second test results. The first test result and the second test result can be used to determine the status of the write and read operations of the two memory cells included in the memory cell group.

[0083] In a specific embodiment, the method further comprises:

[0084] The read / write status of the memory is determined according to the read / write status of the storage units included in different target storage unit groups.

[0085] In a specific embodiment, before determining the first test result of the target storage unit group based on the read data of the storage units included in the target storage unit group, the method further includes:

[0086] According to the storage units included in the memory, the storage units are combined in pairs to obtain multiple groups of storage unit groups.

[0087] In a specific embodiment, determining the first test result of the target storage unit group according to the read data of the storage units included in the target storage unit group includes:

[0088] Acquire first read data of a first storage cell included in the target storage cell group, and second read data of a second storage cell included in the target storage cell group;

[0089] The first read data and the second read data are sequentially compared for the same number of bits, and a first test result of the target memory cell group is determined according to the comparison result of the first read data and the second read data for the same number of bits.

[0090] In a specific embodiment, determining the second test results of the storage cells included in the target storage cell group based on the write data and the read data of the storage cells included in the target storage cell group includes:

[0091] Acquire first read data and first write data of a first storage cell included in the target storage cell group, and second read data and second write data of a second storage cell included in the target storage cell group;

[0092] sequentially comparing data of the same number of bits in the first read data and the first write data, and determining a third test result of the first storage unit according to the comparison result of the data of the same number of bits in the first read data and the first write data;

[0093] The data of the same number of bits in the second read data and the second write data are sequentially compared, and a fourth test result of the second storage unit is determined according to the comparison result of the data of the same number of bits in the second read data and the second write data.

[0094] In a specific embodiment, determining the read / write status of the storage cells included in the target storage cell group according to the first test result of the target storage cell group and the second test result of the storage cells included in the target storage cell group includes:

[0095] When the second test results of the storage cells included in the target storage cell group are all low levels, and the first test results of the target storage cell group are low levels, the read states and write states of the storage cells included in the target storage cell group are normal;

[0096] When the first test result of the target storage cell group is a high level, there is a storage cell in the storage cells included in the target storage cell group whose read state or write state is abnormal.

[0097] In a specific embodiment, when the first test result of the target storage cell group is a high level, there is a storage cell in the storage cells included in the target storage cell group with an abnormal read state or an abnormal write state, including:

[0098] When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all low levels, and the fourth test results of the second storage cells included in the target storage cell group are all high levels, then the read state of the second storage cells included in the target storage cell group is abnormal;

[0099] When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all high levels and the fourth test results of the second storage cells included in the target storage cell group are all low levels, then the read state of the first storage cells included in the target storage cell group is abnormal;

[0100] When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all low levels, and the fourth test results of the second storage cells included in the target storage cell group are all low levels, then the write state of the first storage cells included in the target storage cell group is abnormal, or the write state of the second storage cells is abnormal.

[0101] The present application also provides a computer device. Figure 3 , Figure 3 This is a basic structural block diagram of the computer device in this embodiment.

[0102] The computer device includes a memory 510 and a processor 520 that are interconnected and communicate with each other via a system bus. It should be noted that the figure only shows a computer device with components 510-520, but it should be understood that it is not required to implement all the components shown, and more or fewer components can be implemented instead. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0103] Computer devices can be desktop computers, laptops, PDAs, cloud servers, etc. Computer devices can interact with users through keyboards, mice, remote controls, touchpads, or voice-activated devices.

[0104] The memory 510 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, such as flash memory, a hard disk, a multimedia card, card-type memory (such as SD or DX memory), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic storage, a magnetic disk, an optical disk, etc. RAM may include static RAM or dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of the computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of the computer device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, or a flash card equipped with the computer device. Of course, the memory 510 may also include both an internal storage unit of the computer device and an external storage device thereof. In this embodiment, the memory 510 is generally used to store an operating system and various application software installed on the computer device, such as the program code of the above-mentioned method. In addition, the memory 510 may also be used to temporarily store various types of data that have been output or are about to be output.

[0105] The processor 520 is generally used to perform the overall operation of the computer device. In this embodiment, the memory 510 is used to store program code or instructions, which include computer operating instructions. The processor 520 is used to execute the program code or instructions stored in the memory 510 or process data, such as the program code for running the above method.

[0106] In this article, a bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. This bus system can be divided into address buses, data buses, and control buses. For ease of illustration, the diagram uses only a single thick line, but this does not imply that there is only one bus or only one type of bus.

[0107] Another embodiment of the present application further provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads the computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or combination of steps in the above method, and to generate a device that implements the functional actions specified in each block or combination of blocks in the block diagram.

[0108] Computer-readable media include but are not limited to electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any appropriate combination of the foregoing, the memory is used to store program codes or instructions, the program codes include computer operating instructions, and the processor is used to execute the program codes or instructions of the above-mentioned methods stored in the memory.

[0109] For the definitions of memory and processor, please refer to the description of the aforementioned computer device embodiment and will not be repeated here.

[0110] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0111] Each functional unit or module in each embodiment of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or software functional units.

[0112] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0113] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0114] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0115] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A memory testing method, characterized in that: include: Acquire write data and read data of a plurality of storage units, wherein the write data of different storage units are the same, and the read data of different storage units are the read write data; determining a first test result of the target storage cell group according to read data of storage cells included in the target storage cell group, wherein any storage cell group includes a first storage cell and a second storage cell; determining a second test result of the storage cells included in the target storage cell group according to the write data and the read data of the storage cells included in the target storage cell group; determining the read / write status of the storage cells included in the target storage cell group according to the first test result of the target storage cell group and the second test results of the storage cells included in the target storage cell group; Before determining the first test result of the target storage unit group based on the read data of the storage units included in the target storage unit group, the method further includes: According to the storage units included in the memory, the storage units are combined in pairs to obtain multiple groups of storage unit groups; The step of determining a first test result of the target storage cell group based on read data of storage cells included in the target storage cell group includes: Acquire first read data of a first storage cell included in the target storage cell group, and second read data of a second storage cell included in the target storage cell group; sequentially comparing data of the same number of bits in the first read data and the second read data, and determining a first test result of the target memory cell group according to a comparison result of the data of the same number of bits in the first read data and the second read data; The determining, based on the write data and the read data of the storage cells included in the target storage cell group, a second test result of the storage cells included in the target storage cell group comprises: Acquire first read data and first write data of a first storage cell included in the target storage cell group, and second read data and second write data of a second storage cell included in the target storage cell group; sequentially comparing data of the same number of bits in the first read data and the first write data, and determining a third test result of the first storage unit according to the comparison result of the data of the same number of bits in the first read data and the first write data; sequentially comparing data of the same number of bits in the second read data and the second write data, and determining a fourth test result of the second storage unit according to the comparison result of the data of the same number of bits in the second read data and the second write data; The determining, based on the first test result of the target storage cell group and the second test result of the storage cells included in the target storage cell group, the read / write status of the storage cells included in the target storage cell group comprises: When the second test results of the storage cells included in the target storage cell group are all low levels, and the first test results of the target storage cell group are low levels, the read states and write states of the storage cells included in the target storage cell group are normal; When the first test result of the target storage cell group is a high level, there is a storage cell in the storage cells included in the target storage cell group whose read state or write state is abnormal; When the first test result of the target storage cell group is a high level, there is a storage cell in the storage cells included in the target storage cell group with an abnormal read state or an abnormal write state, including: When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all low levels, and the fourth test results of the second storage cells included in the target storage cell group are all high levels, then the read state of the second storage cells included in the target storage cell group is abnormal; When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all high levels and the fourth test results of the second storage cells included in the target storage cell group are all low levels, then the read state of the first storage cells included in the target storage cell group is abnormal; When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all low levels, and the fourth test results of the second storage cells included in the target storage cell group are all low levels, then the write state of the first storage cells included in the target storage cell group is abnormal, or the write state of the second storage cells is abnormal.

2. The method according to claim 1, characterized in that The method further comprises: The read / write status of the memory is determined according to the read / write status of the storage units included in different target storage unit groups.

3. A memory testing device, characterized in that: include: A data acquisition module is used to acquire write data and read data of multiple storage units, wherein the write data of different storage units are the same, and the read data of different storage units are the read write data; a first test result determination module, configured to determine a first test result of the target storage cell group based on read data of storage cells included in the target storage cell group, wherein any storage cell group includes a first storage cell and a second storage cell; a second test result determining module, configured to determine a second test result of the storage cells included in the target storage cell group according to the write data and the read data of the storage cells included in the target storage cell group; a read / write status determining module, configured to determine the read / write status of the storage cells included in the target storage cell group according to the first test result of the target storage cell group and the second test result of the storage cells included in the target storage cell group; Before determining the first test result of the target storage unit group based on the read data of the storage units included in the target storage unit group, the method further includes: According to the storage units included in the memory, the storage units are combined in pairs to obtain multiple groups of storage unit groups; The step of determining a first test result of the target storage cell group based on read data of storage cells included in the target storage cell group includes: Acquire first read data of a first storage cell included in the target storage cell group, and second read data of a second storage cell included in the target storage cell group; sequentially comparing data of the same number of bits in the first read data and the second read data, and determining a first test result of the target memory cell group according to a comparison result of the data of the same number of bits in the first read data and the second read data; The determining, based on the write data and the read data of the storage cells included in the target storage cell group, a second test result of the storage cells included in the target storage cell group comprises: Acquire first read data and first write data of a first storage cell included in the target storage cell group, and second read data and second write data of a second storage cell included in the target storage cell group; sequentially comparing data of the same number of bits in the first read data and the first write data, and determining a third test result of the first storage unit according to the comparison result of the data of the same number of bits in the first read data and the first write data; sequentially comparing data of the same number of bits in the second read data and the second write data, and determining a fourth test result of the second storage unit according to the comparison result of the data of the same number of bits in the second read data and the second write data; The determining, based on the first test result of the target storage cell group and the second test result of the storage cells included in the target storage cell group, the read / write status of the storage cells included in the target storage cell group comprises: When the second test results of the storage cells included in the target storage cell group are all low levels, and the first test results of the target storage cell group are low levels, the read states and write states of the storage cells included in the target storage cell group are normal; When the first test result of the target storage cell group is a high level, there is a storage cell in the storage cells included in the target storage cell group whose read state or write state is abnormal; When the first test result of the target storage cell group is a high level, there is a storage cell in the storage cells included in the target storage cell group with an abnormal read state or an abnormal write state, including: When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all low levels, and the fourth test results of the second storage cells included in the target storage cell group are all high levels, then the read state of the second storage cells included in the target storage cell group is abnormal; When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all high levels and the fourth test results of the second storage cells included in the target storage cell group are all low levels, then the read state of the first storage cells included in the target storage cell group is abnormal; When the first test result of the target storage cell group is a high level, if the third test results of the first storage cells included in the target storage cell group are all low levels, and the fourth test results of the second storage cells included in the target storage cell group are all low levels, then the write state of the first storage cells included in the target storage cell group is abnormal, or the write state of the second storage cells is abnormal.

4. A computer device, characterized in that: include: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 2.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 2 is implemented.

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