Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a substrate is provided, the substrate is provided with a first face and a second face which are opposite, a plurality of interconnection structures are arranged in the substrate, and the interconnection structures are exposed out of the second face; forming a cooling groove on the second surface of the substrate; forming a filling layer in the cooling groove, wherein the second surface exposes the surface of the filling layer; forming an initial first protection layer on the second surface and the surface of the filling layer; after the initial first protection layer is formed, part of the initial first protection layer on the surface of the cooling groove is removed until part of the surface of the filling layer is exposed, and a first protection layer is formed; and after the first protection layer is formed, the filling layer is removed. On one hand, the first protection layer is made of a material with high fracture toughness, so that the first protection layer cannot be broken in the wafer cutting process to damage the substrate, and the process stability is improved; and on the other hand, the filling layer only plays a role in occupying, and the cooling groove after the filling layer is removed is of a cavity structure, so that a structural basis is provided for subsequent liquid cooling, and the heat dissipation requirement of the semiconductor structure is met.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a method for forming a semiconductor structure. Background Art

[0002] Currently, Moore's Law is slowing down. 2.5D packaging is an on-chip stacking technology that can expand a variety of complex chips, enabling the industry to embark on a new path that can transcend Moore's Law, quickly provide large-scale complex chip integration, and at the same time reduce power consumption and costs. To solve the problem of insufficient wiring density of organic substrates, a silicon substrate technology with vertical through-silicon vias (TSVs) and high-density metal wiring has emerged.

[0003] With the maturity and wide application of multi-chip package interposer technologies, the number of integrated chips on the interposer is increasing continuously, resulting in an increasing unit thermal density on the substrate; and due to the different chip heating powers, the thermal distribution of the substrate carrying the chips is uneven. If this local heat cannot be dissipated in a targeted manner in time, it is very likely to reduce the performance of the entire system or even cause the entire system to fail. Although the external cooling structure is mature in structure, its dissipation efficiency is low and it cannot meet the problem of the large increase in thermal density brought about by the continuous improvement of integration. Therefore, a cooling device with strong heat dissipation ability needs to be provided in a specific area of the silicon substrate.

[0004] However, there are still many problems in the current substrate heat dissipation and cooling structure. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the substrate heat dissipation and cooling structure.

[0006] To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate having opposite first and second surfaces, the substrate having a plurality of interconnect structures therein, and the second surface exposing the interconnect structures; forming cooling grooves on the second surface of the substrate; forming a filling layer in the cooling grooves, the second surface exposing the surface of the filling layer; forming an initial first protective layer on the second surface and the surface of the filling layer; after forming the initial first protective layer, removing a part of the initial first protective layer on the surface of the cooling grooves until a part of the surface of the filling layer is exposed to form a first protective layer; and after forming the first protective layer, removing the filling layer.

[0007] Optionally, the fracture toughness range of the initial first protective layer material is: 20 MPa to 50 MPa; the method for forming the initial first protective layer includes: chemical vapor deposition.

[0008] Optionally, the thickness of the initial first protective layer is greater than 2 μm; the material of the initial first protective layer includes silicon nitride.

[0009] Optionally, before forming the cooling trench, it further includes: forming a dielectric layer on the first surface and a conductive layer located within the dielectric layer.

[0010] Optionally, before forming the cooling trench, after forming the dielectric layer, it further includes: providing a carrier wafer; forming a plurality of first bumps on the dielectric layer; bonding the first bumps to the carrier wafer.

[0011] Optionally, before forming the cooling trench, after bonding the first bumps to the carrier wafer, it further includes: forming a second protective layer on the surface of the second side.

[0012] Optionally, the material of the second protective layer includes silicon oxide.

[0013] Optionally, the method for forming the cooling trench includes: forming a first mask layer on the surface of the second protective layer, the first mask layer exposing a partial surface of the second protective layer; using the first mask layer as a mask to etch the second protective layer and the substrate to form a cooling trench located within the substrate.

[0014] Optionally, the etching method includes dry etching.

[0015] Optionally, the method for forming the cooling trench further includes: performing laser patterning on the second protective layer and the substrate to form a cooling trench located within the substrate; the parameters of the laser patterning include: the time range of the laser patterning is: 100 milliseconds to 5 seconds.

[0016] Optionally, the method for forming the filling layer includes: forming an initial filling layer within the cooling trench; performing planarization on the initial filling layer to form the filling layer.

[0017] Optionally, the method for forming the initial filling layer includes electroplating; the parameters of the electroplating include: the crystal grain size is less than 0.1 μm; the material of the filling layer includes copper.

[0018] Optionally, after forming the initial first protective layer and before forming the first protective layer, it further includes: forming a plurality of openings within the initial first protective layer and the second protective layer, the openings exposing the surface of the interconnect structure; forming a plurality of second bumps within the openings, the second bumps being electrically connected to the interconnect structure.

[0019] Optionally, after forming the second bumps, it further includes: forming an initial third protective layer on the surface of the initial first protective layer and the second bumps.

[0020] Optionally, the thickness of the initial third protective layer is greater than 5 μm; the material of the initial third protective layer includes a polymer.

[0021] Optionally, the method for forming the first protective layer includes: removing a part of the initial first protective layer on the surface of the cooling trench and the initial third protective layer on the surface of the initial first protective layer until a part of the surface of the filling layer is exposed, to form the first protective layer and the third protective layer on the surface of the first protective layer.

[0022] Optionally, the method for removing the initial third protective layer includes: forming a second mask layer on the surface of the initial third protective layer, and the second mask layer exposes a part of the surface of the initial third protective layer; using the second mask layer as a mask to etch the initial third protective layer until the surface of the initial first protective layer is exposed.

[0023] Optionally, the etching method includes dry etching.

[0024] Optionally, the method for removing the initial third protective layer further includes: photolithography or laser removal.

[0025] Optionally, the method for removing the initial first protective layer includes: forming a third mask layer on the surface of the initial first protective layer, and the third mask layer exposes a part of the surface of the initial first protective layer; using the third mask layer as a mask to etch the initial first protective layer until a part of the surface of the filling layer is exposed.

[0026] Optionally, the method for removing the initial first protective layer includes wet etching.

[0027] Optionally, the method for removing the filling layer includes: reverse electroplating; the parameters of the reverse electroplating method include: bias current range: 100 mA to 2 A.

[0028] Optionally, after removing the filling layer, it further includes: removing the third protective layer.

[0029] Optionally, the method for removing the third protective layer includes wet etching.

[0030] Optionally, several passive devices are further included in the dielectric layer.

[0031] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0032] In the method for forming a semiconductor structure according to the technical solution of the present invention, on the one hand, the first protective layer is made of a material with high fracture toughness, which can prevent the first protective layer from damaging the substrate due to breakage during the wafer dicing process, improving the process stability; on the other hand, the filling layer only serves as a placeholder. After removing the filling layer, the cooling trench is a cavity structure, which provides a structural basis for subsequent liquid cooling and meets the heat dissipation requirements of the semiconductor structure.

[0033] Furthermore, the fracture toughness range of the initial first protective layer material is: 20 MPa to 50 MPa. Due to the high fracture toughness of the initial first protective layer material, during the subsequent wafer dicing process, the substrate will not be damaged due to the breakage of the initial first protective layer, improving the performance stability of the semiconductor structure.

[0034] Furthermore, the material of the filling layer includes copper. The method for removing the filling layer includes: reverse electroplating. On the one hand, the price of copper material is low, reducing the process cost; on the other hand, the effect of removing copper by reverse electroplating is very good, which is beneficial to removing the filling layer and forming a cavity-structured cooling trench, meeting the heat dissipation requirements of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 14 is a schematic cross-sectional structure diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] As described in the background art, there are still many problems in the prior art. In an embodiment of a semiconductor structure, a glass sheet is used to seal the cooling channel, and during the subsequent wafer dicing, the entire silicon substrate chip is easily scrapped due to the breakage of the glass sheet.

[0037] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure. On the one hand, the first protective layer is made of a material with high fracture toughness, which can prevent the first protective layer from damaging the substrate due to breakage during the wafer dicing process, improving the process stability; on the other hand, the filling layer only serves as a placeholder. After removing the filling layer, the cooling trench is a cavity structure, which provides a structural basis for subsequent liquid cooling and meets the heat dissipation requirements of the semiconductor structure.

[0038] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0039] Figures 1 to 14 is a schematic cross-sectional structure diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 1, a substrate 100 is provided, the substrate 100 has opposite first and second surfaces, and a plurality of interconnect structures 101 are provided within the substrate 100, and the second surface exposes the interconnect structures 101.

[0041] The material of the substrate 100 includes: silicon or glass.

[0042] Specifically, in this embodiment, the material of the substrate 100 is silicon.

[0043] The thickness range of the substrate 100 is: 50 μm to 100 μm.

[0044] The material of the interconnect structure 101 includes: copper.

[0045] The substrate 100 has interconnect structures 101 therein, and a conductive layer 102 and passive devices 104 are subsequently formed on the substrate 100, and the interconnect structures 101, conductive layer 102, and passive devices 104 have high heat dissipation requirements.

[0046] Please refer to Figure 2 , a dielectric layer 102 and a conductive layer 103 located within the dielectric layer 102 are formed on the first surface.

[0047] The material of the dielectric layer 102 includes: silicon oxide.

[0048] The material of the conductive layer 103 includes: copper.

[0049] The conductive layer 103 has high heat dissipation requirements.

[0050] The dielectric layer 102 also includes a plurality of passive devices 104.

[0051] The passive devices 104 include: one or more of a capacitor, an inductor, and a resistor.

[0052] The passive devices 104 have high heat dissipation requirements.

[0053] Please refer to Figure 3 , a carrier wafer 105 is provided; a plurality of first bumps 106 are formed on the dielectric layer 102; and the first bumps 106 are bonded to the carrier wafer 105.

[0054] The material of the carrier wafer 105 includes: glass.

[0055] The material of the first bumps 106 includes: tin-silver.

[0056] The function of the first bumps 106 is to connect a plurality of devices on the substrate 100.

[0057] The first bump 106 is also electrically connected to the conductive layer 103.

[0058] Please refer to Figure 4 , and a second protective layer 107 is formed on the surface of the second side.

[0059] The material of the second protective layer 107 includes silicon oxide.

[0060] The thickness range of the second protective layer 107 is:

[0061] The function of the second protective layer 107 is as follows: When forming a photoresist layer is required for subsequent formation of the cooling trench 108, the presence of the second protective layer 107 prevents the photoresist layer from being directly formed on the substrate 100, avoiding the residue of the photoresist layer on the substrate 100.

[0062] Please refer to Figure 5 , and a cooling trench 108 is formed on the second side of the substrate 100.

[0063] The depth range of the cooling trench 108 is: 200 μm to 2000 μm.

[0064] The cooling trench 108 meets the heat dissipation requirements of the semiconductor structure.

[0065] The cooling trench 108 provides a structural basis for subsequent formation of the filling layer 110.

[0066] In this embodiment, the method for forming the cooling trench 108 includes: forming a first mask layer (not shown) on the surface of the second protective layer 107, and the first mask layer exposes a part of the surface of the second protective layer 107; using the first mask layer as a mask, etching the second protective layer 107 and the substrate 100 to form the cooling trench 108 located in the substrate 100.

[0067] The etching method includes dry etching.

[0068] In another embodiment, the method for forming the cooling trench further includes: performing laser patterning on the second protective layer and the substrate to form the cooling trench located in the substrate; the parameters of the laser patterning include: the time range of the laser patterning is: 100 milliseconds to 5 seconds.

[0069] After forming the cooling trench 108, a filling layer 110 is formed in the cooling trench 108, and the surface of the filling layer 110 is exposed on the second side. The method for forming the filling layer 110 includes: forming an initial filling layer 109 in the cooling trench 108; performing planarization processing on the initial filling layer 109 to form the filling layer 110. For details, please refer to Figures 6 to 7 .

[0070] Please refer to Figure 6 , and an initial filling layer 109 is formed in the cooling groove 108.

[0071] The method for forming the initial filling layer 109 includes electroplating; the parameters of the electroplating method include: the crystal grain size is less than 0.1 μm.

[0072] The material of the initial filling layer 109 includes copper.

[0073] On the one hand, the price of copper material is low, reducing the process cost; on the other hand, the effect of removing copper by the reverse electroplating method is very good, which is beneficial to the subsequent removal of the filling layer to form a cooling groove with a cavity structure, meeting the heat dissipation requirements of the semiconductor structure.

[0074] The initial filling layer 109 provides a structural basis for the subsequent formation of the filling layer 110. The filling layer 110 only plays a placeholder role. The cooling groove after the subsequent removal of the filling layer 110 is a cavity structure, and the cavity structure provides a structural basis for subsequent liquid cooling, meeting the heat dissipation requirements of the semiconductor structure.

[0075] Please refer to Figure 7 , and the initial filling layer 109 is planarized to form the filling layer 110.

[0076] The planarization method includes: mechanical polishing method, chemical polishing method, fluid polishing method, and chemical mechanical polishing method, etc. Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing methods, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the disadvantages of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high-planarity polishing of nanoscale of various materials.

[0077] On the one hand, the price of copper material is low, reducing the process cost; on the other hand, the effect of removing copper by the reverse electroplating method is very good, which is beneficial to the subsequent removal of the filling layer to form a cooling groove with a cavity structure, meeting the heat dissipation requirements of the semiconductor structure.

[0078] The filling layer 110 only plays a placeholder role. The cooling groove after the subsequent removal of the filling layer 110 is a cavity structure, and the cavity structure provides a structural basis for subsequent liquid cooling, meeting the heat dissipation requirements of the semiconductor structure.

[0079] Please refer to Figure 8 , and an initial first protective layer 111 is formed on the second surface and the surface of the filling layer 110.

[0080] The fracture toughness range of the material of the initial first protective layer 111 is: 20 MPa to 50 MPa; the forming method of the initial first protective layer 111 includes: chemical vapor deposition.

[0081] The thickness of the initial first protective layer 111 is greater than 2 μm; the material of the initial first protective layer 111 includes silicon nitride.

[0082] The initial first protective layer 111 provides a structural basis for the subsequent formation of the first protective layer 115. Selecting a material with high fracture toughness for the initial first protective layer 111 can prevent the subsequent first protective layer 115 from damaging the substrate due to breakage during the wafer cutting process, improving the stability of the process.

[0083] Please refer to Figure 9 , a plurality of openings (not shown) are formed in the initial first protective layer 111 and the second protective layer 107, and the openings expose the surface of the interconnect structure 101; a plurality of second bumps 112 are formed in the openings, and the second bumps 112 are electrically connected to the interconnect structure 101.

[0084] The forming method of the openings includes: forming a fourth mask layer (not shown) on the surface of the initial first protective layer 111, and the fourth mask layer exposes a part of the surface of the initial first protective layer 111; using the fourth mask layer as a mask, etching the initial first protective layer 111 and the second protective layer 107 until the surface of the interconnect structure 101 is exposed to form the openings.

[0085] The forming method of the second bumps 112 includes: vacuum evaporation process.

[0086] The material of the second bumps 112 includes: tin-silver.

[0087] The function of the second bumps 112 is to connect the substrate 100 and the PCB carrier.

[0088] Please refer to Figure 10 , after forming the second bumps 112, it further includes: forming an initial third protective layer 113 on the surfaces of the initial first protective layer 111 and the second bumps 112.

[0089] The thickness of the initial third protective layer 113 is greater than 5 μm; the material of the initial third protective layer 113 includes polymer.

[0090] The function of the initial third protective layer 113 is to protect the second bumps 112. The material of the second bumps 112 is metal, which can avoid the influence on the second bumps 112 caused by removing the copper of the filling layer 110 by electroplating method when removing the filling layer 110 subsequently.

[0091] After forming the initial first protective layer 111 and the initial third protective layer 113 on the surface of the initial first protective layer 111 (as shown in Figure 10 ), a part of the initial first protective layer 111 on the surface of the cooling trench 108 is removed until a part of the surface of the filling layer 110 is exposed, thereby forming the first protective layer 115. The method for forming the first protective layer 115 includes: removing a part of the initial first protective layer 111 on the surface of the cooling trench 108 and the initial third protective layer 113 on the surface of the initial first protective layer 111 until a part of the surface of the filling layer 110 is exposed, thereby forming the first protective layer 115 and the third protective layer 114 on the surface of the first protective layer 115. The method for removing the initial third protective layer 113 includes: forming a second mask layer (not shown) on the surface of the initial third protective layer 113, and the second mask layer exposes a part of the surface of the initial third protective layer 113; using the second mask layer as a mask, etching the initial third protective layer 113 until the surface of the initial first protective layer 111 is exposed. The method for removing the initial first protective layer 111 includes: forming a third mask layer (not shown) on the surface of the initial first protective layer 111, and the third mask layer exposes a part of the surface of the initial first protective layer 111; using the third mask layer as a mask, etching the initial first protective layer 111 until a part of the surface of the filling layer 110 is exposed. For details, please refer to Figures 11 to 12 .

[0092] Please refer to Figure 11 , a second mask layer (not shown) is formed on the surface of the initial third protective layer 113, and the second mask layer exposes a part of the surface of the initial third protective layer 113; using the second mask layer as a mask, etching the initial third protective layer 113 until the surface of the initial first protective layer 111 is exposed, thereby forming the third protective layer 114.

[0093] The thickness range of the third protective layer 114 is: greater than 5 μm.

[0094] The material of the third protective layer 114 includes: polymer.

[0095] Specifically, in this embodiment, the method for removing the initial third protective layer 113 includes dry etching.

[0096] In this embodiment, the advantages of dry etching over wet etching are as follows: on the one hand, when etching the initial third protective layer 113 to form the third protective layer 114, it is necessary to remove the initial third protective layer 113 on the surface of the filling layer 110, which requires a high etching precision; on the other hand, when etching the initial third protective layer 113 to form the third protective layer 114, the filling layer 110 has not been removed yet. If wet etching is used, the problem of cross - contamination will occur.

[0097] In other embodiments, the method for removing the initial third protective layer further includes: photolithography or laser removal.

[0098] Please refer to Figure 12 , a third mask layer (not shown) is formed on the surface of the initial first protective layer 111, and the third mask layer exposes a part of the surface of the initial first protective layer 111; using the third mask layer as a mask, the initial first protective layer 111 is etched until a part of the surface of the filling layer 110 is exposed to form the first protective layer 115.

[0099] The method for removing the initial first protective layer 111 includes: wet etching.

[0100] The material of the first protective layer 115 includes: silicon nitride.

[0101] The thickness range of the first protective layer 115 is: greater than 2μm.

[0102] The function of the first protective layer 115 is to seal the surface of the cooling trench and only retain the water inlet and outlet ports. On the one hand, it improves the heat dissipation performance of the semiconductor structure; on the other hand, it ensures the normal operation of the device.

[0103] The fracture toughness range of the material of the first protective layer 115 is: 20MPa - 50MPa.

[0104] Selecting a material with a large fracture toughness for the first protective layer 115 can prevent the first protective layer 115 from damaging the substrate due to breakage during the wafer dicing process, thus improving the process stability.

[0105] Please refer to Figure 13 , after forming the first protective layer 115, the filling layer 110 is removed (as Figure 12 shown).

[0106] The method for removing the filling layer 110 includes: reverse electroplating; the parameters of the reverse electroplating method include: the bias current range: 100mA - 2A.

[0107] The filling layer 110 only serves as a placeholder. After removing the filling layer 110, the cooling trench is a cavity structure, and the cavity structure provides a structural basis for subsequent liquid cooling, meeting the heat dissipation requirements of the semiconductor structure.

[0108] On the one hand, the price of copper material is low, reducing the process cost; on the other hand, the effect of removing copper by the reverse electroplating method is very good, which is conducive to removing the filling layer 110 to form a cooling trench with a cavity structure, meeting the heat dissipation requirements of the semiconductor structure.

[0109] Please refer to Figure 14 , after removing the filling layer 110, it further includes: removing the third protective layer 114.

[0110] The method for removing the third protective layer 114 includes wet etching.

[0111] On the one hand, when removing the third protective layer 114, the filling layer 110 has been removed, and at this time, wet etching will not affect the metal of the filling layer 110; on the other hand, for large-area etching, the efficiency of wet etching is relatively high.

[0112] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate having opposite first and second surfaces, with a plurality of interconnect structures therein, and the second surface exposing the interconnect structures; Forming cooling grooves on the second surface of the substrate; Forming a filling layer in the cooling grooves, with the second surface exposing the surface of the filling layer; Forming an initial first protective layer on the second surface and the surface of the filling layer; After forming the initial first protective layer, removing a part of the initial first protective layer on the surface of the cooling grooves until a part of the surface of the filling layer is exposed to form a first protective layer; After forming the first protective layer, removing the filling layer.

2. The method for forming a semiconductor structure according to claim 1, wherein The fracture toughness range of the material of the initial first protective layer is: 20 MPa to 50 MPa; the forming method of the initial first protective layer includes: chemical vapor deposition.

3. The method for forming the semiconductor structure according to claim 2, wherein The thickness of the initial first protective layer is greater than 2 μm; the material of the initial first protective layer includes silicon nitride.

4. The method for forming a semiconductor structure according to claim 1, wherein, Before forming the cooling grooves, it further includes: forming a dielectric layer on the first surface and a conductive layer within the dielectric layer.

5. The method for forming a semiconductor structure according to claim 4, wherein, Before forming the cooling grooves, after forming the dielectric layer, it further includes: providing a carrier wafer; forming a plurality of first bumps on the dielectric layer; bonding the first bumps to the carrier wafer.

6. The method for forming a semiconductor structure according to claim 5, wherein, Before forming the cooling grooves, after bonding the first bumps to the carrier wafer, it further includes: forming a second protective layer on the surface of the second surface.

7. The method for forming a semiconductor structure according to claim 6, wherein, The material of the second protective layer includes silicon oxide.

8. The method for forming a semiconductor structure according to claim 6, wherein, The forming method of the cooling grooves includes: forming a first mask layer on the surface of the second protective layer, with the first mask layer exposing a part of the surface of the second protective layer; using the first mask layer as a mask to etch the second protective layer and the substrate to form cooling grooves within the substrate.

9. The method for forming a semiconductor structure according to claim 8, wherein The etching method includes dry etching.

10. The method for forming a semiconductor structure as described in claim 6, wherein, The forming method of the cooling grooves further includes: performing laser patterning on the second protective layer and the substrate to form cooling grooves within the substrate; the parameters of the laser patterning include: the time range of the laser patterning is: 100 milliseconds to 5 seconds.

11. The method for forming a semiconductor structure according to claim 1, wherein, The forming method of the filling layer includes: forming an initial filling layer in the cooling grooves; performing planarization on the initial filling layer to form the filling layer.

12. The method for forming a semiconductor structure as claimed in claim 11, wherein, The method of forming the initial filling layer includes electroplating; the parameters of the electroplating include: the crystal grain size is less than 0.1 μm; The material of the filling layer includes copper.

13. The method for forming a semiconductor structure according to claim 6, wherein After forming the initial first protective layer and before forming the first protective layer, it further includes: forming a plurality of openings in the initial first protective layer and the second protective layer, with the openings exposing the surface of the interconnect structures; forming a plurality of second bumps in the openings, with the second bumps electrically connected to the interconnect structures.

14. The method for forming a semiconductor structure as described in claim 13, wherein, After forming the second bumps, it further includes: forming an initial third protective layer on the surface of the initial first protective layer and the second bumps.

15. The method for forming the semiconductor structure according to claim 14, wherein, The thickness of the initial third protective layer is greater than 5 μm; the material of the initial third protective layer includes polymer.

16. The method for forming a semiconductor structure according to claim 14, wherein The method for forming the first protective layer includes: removing a part of the initial first protective layer on the surface of the cooling trench and the initial third protective layer on the surface of the initial first protective layer until a part of the surface of the filling layer is exposed, forming the first protective layer and the third protective layer on the surface of the first protective layer.

17. The method for forming a semiconductor structure as claimed in claim 16, wherein, The method for removing the initial third protective layer includes: forming a second mask layer on the surface of the initial third protective layer, and the second mask layer exposes a part of the surface of the initial third protective layer; using the second mask layer as a mask to etch the initial third protective layer until the surface of the initial first protective layer is exposed.

18. The method for forming a semiconductor structure as described in claim 17, wherein, The etching method includes dry etching.

19. The method for forming the semiconductor structure as described in claim 17, wherein, The method for removing the initial third protective layer further includes: photolithography or laser removal.

20. The method for forming a semiconductor structure as claimed in claim 16, wherein, The method for removing the initial first protective layer includes: forming a third mask layer on the surface of the initial first protective layer, and the third mask layer exposes a part of the surface of the initial first protective layer; using the third mask layer as a mask to etch the initial first protective layer until a part of the surface of the filling layer is exposed.

21. The method for forming a semiconductor structure according to claim 20, wherein The method for removing the initial first protective layer includes: wet etching.

22. The method for forming a semiconductor structure according to claim 1, wherein, The method for removing the filling layer includes: reverse electroplating; the parameters of the reverse electroplating method include: bias current range: 100 mA to 2 A.

23. The method for forming a semiconductor structure according to claim 16, wherein, After removing the filling layer, it further includes: removing the third protective layer.

24. The method for forming the semiconductor structure according to claim 23, wherein, The method for removing the third protective layer includes wet etching.

25. The method for forming a semiconductor structure according to claim 4, wherein The dielectric layer further includes a number of passive devices.

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