Wafer patterning processing method, wafer and light-emitting device
Through innovative processing methods of forming barrier patterns and mask patterns on the wafer, the problem of insufficient spacing of epitaxial structures is solved, and the reduction of epitaxial structures and resolution improvement is achieved, which is suitable for high integrated circuit design of light emitting devices.
Patent Information
- Application Number
- CN202410006554.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-02
- Publication Date
- 2025-07-04
AI Technical Summary
In the prior art, the distance between the epitaxial structures of the light emitting devices cannot reach less than 4 μm to 6 μm, and cannot meet the high resolution requirements.
By forming a first barrier pattern on the wafer to be patterned, and making a first mask layer thereon, the first mask pattern is formed after the etching process, so that the spacing between the two adjacent first mask sub-patterns is smaller than the spacing between the two adjacent barrier layers, the barrier pattern is then removed, and the etching process is performed using the first mask pattern as a mask to form an epitaxial structure.
The spacing of the epitaxial structure is reduced, the overall resolution is improved, allowing the tight integration of multiple devices and circuits on the wafer surface to achieve a highly integrated circuit design.
Smart Images
Figure CN120261284A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of light-emitting devices, and particularly to a method for patterning a wafer, a wafer, and a light-emitting device. Background Art
[0002] In addition to a substrate, a light-emitting device also includes a plurality of epitaxial structures arranged in an array on the surface of the substrate. The pitch value between two adjacent epitaxial structures determines the overall resolution height of the light-emitting device to which the light-emitting device belongs; the smaller the pitch, the higher the resolution, and vice versa, the larger the pitch, the lower the resolution.
[0003] In the prior art, a light-emitting device is often realized through the following steps: spin coating, exposure, and development are performed on the surface of a wafer, and then SiO2 is deposited, so as to prepare a barrier pattern composed of a plurality of barrier layers on the surface of the wafer, and the wafer is etched using the barrier pattern as a mask, so as to form epitaxial structures corresponding to the barrier pattern on the outer surface of the wafer.
[0004] In the above steps, due to the limitations of the existing process technology, the minimum limit of the pitch between two adjacent barrier layers can only reach 4 μm to 6 μm, and thus the minimum limit of the pitch between two adjacent epitaxial structures in the prepared wafer can also only reach 4 μm to 6 μm, which cannot meet the high-resolution requirements. Summary of the Invention
[0005] In view of the above defects in the related art, a method for patterning a wafer, a wafer, and a light-emitting device are provided, aiming to improve the overall resolution.
[0006] The technical solutions adopted by the present application to solve the technical problems are as follows:
[0007] In a first aspect, the present application provides a method for patterning a wafer, which includes:
[0008] providing a wafer to be patterned, and forming a first barrier pattern on the wafer to be patterned; wherein, the first barrier pattern includes a plurality of first barrier layers extending along a first direction;
[0009] fabricating a first mask layer on the first barrier pattern;
[0010] etching the first mask layer to obtain a first mask pattern; wherein, the first mask pattern includes a plurality of first mask sub-patterns, and each of the first mask sub-patterns is arranged at least on both sides of the first barrier layer;
[0011] removing the first barrier pattern;
[0012] etching the wafer to be patterned using the first mask pattern as a mask.
[0013] Through the above solution, the minimum distance between two adjacent first barrier layers can reach 4 μm to 6 μm. After the first mask pattern is prepared on the first barrier pattern, each of the first mask sub-patterns is arranged at least along both sides of the first barrier layer, so that the distance between two adjacent first mask sub-patterns is reduced compared to the distance between two adjacent first barrier layers. Therefore, after the epitaxial structure obtained by etching the wafer to be patterned using the first mask pattern as a mask, the distance of the epitaxial structure is reduced compared to the distance of the first barrier pattern, thereby achieving the purpose of reducing the overall resolution.
[0014] Optionally, before the step of etching the wafer to be patterned using the first mask pattern as a mask, it further includes:
[0015] Forming a second barrier pattern on the first mask pattern; wherein, the second barrier pattern includes a plurality of second barrier layers extending along a second direction, and the first direction is perpendicular to the second direction;
[0016] Fabricating a second mask layer on the second barrier pattern;
[0017] Etching the second mask layer to obtain a second mask pattern; wherein, the second mask pattern includes a plurality of second mask sub-patterns, and each of the second mask sub-patterns is arranged at least along both sides of the second barrier layer;
[0018] Removing the second barrier layer and the non-overlapping portions of the first mask pattern and the second mask pattern to obtain a final mask pattern;
[0019] Etching the wafer to be patterned using the final mask pattern as a mask.
[0020] Through the above solution, after etching the wafer to be patterned using the final mask pattern as a mask, a square-shaped epitaxial structure arranged in an array can be obtained, making it easier to modularize the design of the wafer, so that the functions of the modules can be combined and adjusted more flexibly during the design and manufacturing of the wafer; and, the square-shaped epitaxial array structure allows multiple devices and circuits to be closely integrated on the wafer surface, thereby realizing a highly integrated circuit and achieving the purpose of improving the resolution.
[0021] Optionally, the forming step of the first barrier pattern includes:
[0022] Coating a photoresist layer on the surface of the wafer to be patterned;
[0023] Patternizing the photoresist layer to form a first photoresist pattern; wherein the first photoresist pattern includes a plurality of first photoresist layers extending along a first direction;
[0024] Form a barrier layer on the surface of the first photoresist pattern;
[0025] Remove the first photoresist layer and the barrier layer on the surface of the first photoresist layer to obtain the first barrier pattern.
[0026] Through the above solution, a plurality of first barrier layers extending in the first direction can be formed on the wafer to be patterned, thereby forming the first barrier pattern.
[0027] Optionally, the first barrier layer includes a metal material; the step of removing the first photoresist layer and the barrier layer on the surface of the first photoresist layer to obtain the first barrier pattern includes:
[0028] Adopt a gold stripping process to remove the first photoresist layer and the barrier layer on the surface of the first photoresist layer to obtain the first barrier pattern.
[0029] Through the above solution, the barrier layer includes a metal material, and it is easier to strip the barrier layer on the surface of the first photoresist layer by using the gold stripping process; after stripping the barrier layer on the surface of the first photoresist layer, the first photoresist layer is removed at the same time, and only the barrier layer located between the first photoresist patterns can be retained, thereby forming the first barrier pattern.
[0030] Optionally, the distance between adjacent first barrier layers ranges from 4 μm to 6 μm.
[0031] Through the above solution, the distance between adjacent two first mask sub-patterns is smaller than the distance between adjacent two first barrier layers. Then, when the distance between adjacent first barrier layers reaches the minimum limit value of 4 μm, the distance between adjacent two first mask sub-patterns must be less than 4 μm.
[0032] Optionally, the cross-sectional width of any side of the first mask sub-pattern is less than or equal to 2 μm; and there is a gap between adjacent two first mask sub-patterns, and the width of the gap is greater than or equal to the cross-sectional width.
[0033] Through the above solution, the distance of the first mask pattern can be less than or equal to 2 μm; at the same time, an equal-width first mask sub-pattern is respectively arranged on both sides of a first barrier layer. After removing the first barrier layer, an equally spaced first mask pattern can be obtained, thereby realizing the reduction of the distance in the first direction.
[0034] Optionally, the wafer to be patterned includes a growth substrate and an epitaxial layer grown on the growth substrate; or the wafer to be patterned includes a CMOS substrate and an epitaxial layer bonded to the CMOS substrate.
[0035] Optionally, the first mask sub-pattern is arranged around the first barrier layer.
[0036] A wafer is prepared by a patterning method of the wafer according to any one of the above.
[0037] In a second aspect, the present application provides a light-emitting device, and the light-emitting device is made based on the wafer described above.
[0038] In the present application, the distance between two adjacent first barrier layers can reach at least 4 μm to 6 μm at minimum. After the first mask pattern is prepared on the first barrier pattern, each of the first mask sub-patterns is arranged at least on both sides of the first barrier layer, so that the distance between two adjacent first mask sub-patterns is reduced compared with the distance between two adjacent first barrier layers; therefore, after the wafer to be patterned is etched using the first mask pattern as a mask, the distance of the obtained epitaxial structure is reduced compared with the distance of the first barrier pattern, thereby achieving the purpose of reducing the overall resolution. Description of the Drawings
[0039] Figure 1 is a schematic structural diagram of the wafer to be patterned in the present application;
[0040] Figure 2 is a schematic structural diagram of the first photoresist pattern in the present application;
[0041] Figure 3 is Figure 2 a cross-sectional view taken along line A-A in
[0042] Figure 4 is a reference view of the usage state after the barrier layer is prepared on the first photoresist pattern in the present application;
[0043] Figure 5 is a schematic structural diagram of the first barrier pattern in the present application;
[0044] Figure 6 is a reference view of the usage state after the first mask layer is prepared on the first barrier pattern in the present application;
[0045] Figure 7 is a schematic distribution structure diagram of the first mask pattern and the first barrier pattern in the present application;
[0046] Figure 8 is Figure 7 a cross-sectional view taken along line B-B in
[0047] Figure 9 is a schematic structural diagram of the first mask pattern described in the present application;
[0048] Figure 10 is a reference view of the usage state after preparing the second barrier pattern on the first mask pattern in the present application;
[0049] Figure 11 is Figure 10 a cross-sectional view taken along the C-C direction in
[0050] Figure 12 is a reference view of the usage state after preparing the second mask layer on the second barrier pattern in the present application;
[0051] Figure 13 is a schematic distribution structure diagram of the second barrier layer, the second mask sub-pattern and the first mask sub-pattern in the present application;
[0052] Figure 14 is a schematic distribution diagram of the overlapping area and non-overlapping area between the second mask pattern and the first mask pattern in the present application;
[0053] Figure 15 is Figure 14 a cross-sectional view taken along the D-D direction in
[0054] Figure 16 is a schematic structural diagram of the final mask pattern obtained after removing the non-overlapping area between the first mask pattern and the second mask pattern in the present application;
[0055] Figure 17 is a first view of the distribution of the final mask pattern on the wafer to be patterned after removing the final mask sub-patterns on the periphery of the final mask pattern in the present application;
[0056] Figure 18 is a second view of the distribution of the final mask pattern on the wafer to be patterned after removing the final mask sub-patterns on the periphery of the final mask pattern in the present application;
[0057] Figure 19 is a schematic structural diagram of the wafer in the present application;
[0058] Figure 20 is a flowchart of the patterning method of the wafer in the present application.
[0059] Explanation of reference numerals:
[0060] 1 - Wafer to be patterned; 11 - Substrate; 12 - Epitaxial layer; 121 - Epitaxial structure; 13 - Bonding metal layer; 2 - First barrier pattern; 21 - First barrier layer; 3 - First photoresist pattern; 31 - First photoresist layer; 4 - Barrier layer; 5 - First mask layer; 6 - First mask pattern; 61 - First mask sub - pattern; 7 - Second barrier pattern; 71 - Second barrier layer; 8 - Second mask layer; 9 - Second mask pattern; 91 - Second mask sub - pattern; 10 - Final mask pattern; 101 - Final mask sub - pattern; 14 - Overlap region; 15 - Non - overlap region. Detailed implementation mode
[0061] To make the purpose, technical solution and advantages of the present application clearer and more definite, the following further elaborates on the present application with reference to the attached drawings and by way of examples. It should be understood that the specific examples described herein are only used to explain the present application and are not used to limit the present application.
[0062] The present application provides a method for patterning a wafer, as Figure 20 shown, the method for patterning the wafer includes the following steps:
[0063] S100. Provide a wafer 1 to be patterned, and form a first barrier pattern 2 on the wafer 1 to be patterned; wherein, the first barrier pattern 2 includes a plurality of first barrier layers 21 extending along a first direction;
[0064] The step of forming the first barrier pattern 2 includes:
[0065] S101. Coat a photoresist layer on the surface of the wafer 1 to be patterned;
[0066] Specifically, the photoresist is coated on the surface of the wafer 1 to be patterned by spin - coating, so that the photoresist covers the surface of the wafer 1 to be patterned, thereby forming a photoresist layer on the surface of the wafer 1 to be patterned.
[0067] S102. Pattern the photoresist layer to form a first photoresist pattern 3; wherein the first photoresist pattern 3 includes a plurality of first photoresist layers 31 extending along a first direction;
[0068] Specifically, in the present application, the production of the first photoresist pattern 3 is the same as the method of making a photolithography pattern on the wafer 1 to be patterned in the prior art, so that the minimum pitch d1 of the first photoresist pattern 3 in the present application can reach 4 μm (as Figure 2 shown).
[0069] As Figure 2 and Figure 3As shown, patterning the photoresist layer means fabricating a photolithography pattern on the surface of the wafer 1 to be patterned, thereby forming the first photoresist pattern 3 on the surface of the wafer 1 to be patterned; wherein, the first photoresist pattern 3 envelopes a plurality of first photoresist layers 31, the first photoresist layers 31 are arranged to extend along the first direction, and a plurality of the first photoresist layers 31 are arranged along the second direction, and the first direction and the second direction are perpendicular to each other.
[0070] The patterning process of the photoresist layer specifically includes:
[0071] A mask plate is arranged above the photoresist layer corresponding to the area of the first photoresist layer 31, and the photoresist layer is exposed.
[0072] The photoresist layer is developed to remove the photoresist in the area outside the first photoresist layer 31 and form the first photoresist pattern 3.
[0073] It should be noted that the photoresist layer has photosensitive properties and can undergo chemical changes after exposure; therefore, when exposing the photoresist layer, a mask plate needs to be arranged above the photoresist layer to block the positions on the photoresist layer that do not need to be exposed, while the positions that need to be exposed are exposed. Among them, the positions on the photoresist layer that need to be exposed are the positions of the first barrier layer 21; a hollowing process is performed on the mask plate corresponding to the position of the first barrier layer 21, then after exposing the photoresist layer, the positions on the photoresist layer corresponding to the first barrier layer 21 are irradiated by light and undergo chemical reactions, while the remaining positions remain unchanged.
[0074] The exposed photoresist layer is developed, so that the photoresist in the exposed area is dissolved, while the unexposed area remains unchanged, thereby retaining a plurality of the first photoresist layers 31 to form the first photoresist pattern 3; the part of the wafer 1 to be patterned corresponding to the first barrier layer 21 is exposed, and other areas are blocked by the first photoresist pattern 3.
[0075] S103. Fabricate a barrier layer 4 on the surface of the first photoresist pattern 3;
[0076] Specifically, the barrier layer 4 is made of a metal material; metal film formation is performed on the surface of the first photoresist pattern 3 to fabricate the barrier layer 4 (as Figure 4 shown). A part of the barrier layer 4 covers the first photoresist layer 31, and a part covers the wafer 1 to be patterned.
[0077] S104. Remove the first photoresist layer 31 and the barrier layer 4 on the surface of the first photoresist layer 31 to obtain the first barrier pattern 2 (as Figure 5 shown).
[0078] Specifically, the first barrier layer 21 is prepared from the barrier layer 4. Therefore, the material of the first barrier layer 21 is the same as that of the barrier layer 4, that is, the first barrier layer 21 includes a metal material.
[0079] The step of removing the first photoresist layer 31 and the barrier layer 4 on the surface of the first photoresist layer 31 to obtain the first barrier pattern 2 includes:
[0080] Adopt a gold stripping process to remove the first photoresist layer 31 and the barrier layer 4 on the surface of the first photoresist layer 31 to obtain the first barrier pattern 2.
[0081] In the first barrier pattern 2, the first barrier layer 21 has a strip structure, the first barrier layer 21 extends along the first direction, and a plurality of the first barrier layers 21 are arranged along the second direction.
[0082] S200. Fabricate a first mask layer 5 on the first barrier pattern 2 (as Figure 6 shown);
[0083] Specifically, the first mask layer 5 includes SiO2. Fabricating the first mask layer 5 on the first barrier pattern 2 specifically means: depositing a layer of SiO2 on the surface of the first barrier pattern 2 by using an ALD device and chemical vapor deposition technology. Since the first barrier pattern 2 blocks a part of the area of the wafer 1 to be patterned, and the areas on the wafer 1 to be patterned other than the first barrier pattern 2 are exposed, after depositing SiO2 on the first barrier pattern 2, the SiO2 can cover the first barrier pattern 2 and the areas on the wafer 1 to be patterned other than the first barrier pattern 2 (as Figure 6 shown).
[0084] S300. Etch the first mask layer 5 to obtain a first mask pattern 6 (as Figure 7 shown); wherein, the first mask pattern 6 includes a plurality of first mask sub-patterns 61, and each of the first mask sub-patterns 61 is arranged at least on both sides of the first barrier layer 21;
[0085] As Figure 7 and Figure 8As shown, for each of the first barrier layers 21, at least the SiO2 on both sides of the first barrier layer 21 is retained to form the first mask sub-pattern 61; then the remaining SiO2 is removed, thereby forming the first mask pattern 6. At this time, in addition to the first mask sub-pattern 61 being retained on the surface of the wafer 1 to be patterned, the first barrier layer 21 is also retained.
[0086] The distance between two adjacent first barrier layers 21 ranges from 4 μm to 6 μm; since at least two first mask sub-patterns 61 are retained between every two adjacent first barrier layers 21, the distance between adjacent first mask sub-patterns 61 is smaller than the distance between two adjacent first barrier layers 21; when the distance between two adjacent first barrier layers 21 reaches the minimum limit value of 4 μm, the distance d2 between two adjacent first mask sub-patterns 61 arranged along the second direction (as Figure 3 shown) is less than 4 μm.
[0087] Specifically, after the first mask layer 5 is prepared, as Figure 7 、 Figure 8 and Figure 9 shown, the SiO2 outside the first barrier layer 21 is retained, and the SiO2 in the area that does not need to be retained and the SiO2 higher than the first barrier layer 21 are selectively dry-etched, thereby forming the first mask pattern 6 on the surface of the wafer 1 to be patterned.
[0088] It should be noted that among all the first mask sub-patterns 61 between two adjacent first barrier layers 21, there is a gap between any two adjacent first mask sub-patterns 61.
[0089] S400. Remove the first barrier pattern 2;
[0090] Specifically, the first barrier layer 21 is wet-etched to remove all the first barrier layers 21 on the surface of the wafer 1 to be patterned, and only the first mask sub-patterns 61 (as Figure 9 shown) are retained, thereby achieving the purpose of removing the first barrier pattern 2.
[0091] S500. Etch the wafer 1 to be patterned using the first mask pattern 6 as a mask.
[0092] Before etching the wafer 1 to be patterned using the first mask pattern 6 as a mask, it further includes:
[0093] As Figure 10 and Figure 11As shown, a second barrier pattern 7 is formed on the first mask pattern 6; wherein, the second barrier pattern 7 includes a plurality of second barrier layers 71 extending in a second direction, and the first direction is perpendicular to the second direction;
[0094] A second mask layer 8 is fabricated on the second barrier pattern 7 (as Figure 12 shown);
[0095] The second mask layer 8 is etched to obtain a second mask pattern 9 (as Figure 13 shown); wherein, the second mask pattern 9 includes a plurality of second mask sub-patterns 91, and each of the second mask sub-patterns 91 is arranged at least on both sides of the second barrier layer 71;
[0096] The second barrier layer 71 and the non-overlapping portions of the first mask pattern 6 and the second mask pattern 9 are removed to obtain a final mask pattern 10;
[0097] Using the final mask pattern 10 as a mask, the wafer 1 to be patterned is etched.
[0098] According to the above steps, when the second mask pattern 9 is prepared on the first mask pattern 6, then: as Figure 13 shown, along the second direction, the spacing between two adjacent first mask sub-patterns 61 is less than the spacing between two adjacent first barrier layers 21; along the first direction, the spacing between two adjacent second mask sub-patterns 91 is less than the spacing between two adjacent first barrier layers 21; and, a part of the second mask sub-pattern 91 overlaps and covers the corresponding first mask sub-pattern 61 (this region is the height of the two-layer structure of the second mask sub-pattern 91 and the first mask sub-pattern 61), and a part directly covers the surface of the wafer 1 to be patterned (this region is only the height of the single-layer structure of the second mask sub-pattern 91).
[0099] The preparation process of the second barrier pattern 7 is the same as that of the first barrier pattern 2, and the number, size, and shape of the second barrier layers 71 are equal to those of the first barrier layers 21, and the spacing between two adjacent second barrier layers 71 is equal to the spacing between two adjacent first barrier layers 21 (i.e., 4 μm to 6 μm).
[0100] After the second barrier pattern 7 is prepared, as Figure 12 shown, an ALD device is used and chemical vapor deposition technology is employed to deposit SiO2 on the second barrier pattern 7; this layer of SiO2 will cover the surfaces of the first mask pattern 6 and the second barrier pattern 7 to form a second mask layer 8.
[0101] After the deposition of the second mask layer 8 is completed, as Figure 13 shown, at least the SiO2 on both sides of the second barrier layer 71 is retained, and the SiO2 in the areas that do not need to be retained is selectively dry-etched, so as to form a pattern on the surface of the wafer 1 to be patterned, which is composed of a plurality of the first mask sub-patterns 61, a plurality of the second barrier layers 71, and the SiO2 on both sides of the second barrier layer 71. The SiO2 distributed on both sides of the second barrier layer 71 forms the second mask sub-pattern 91; a plurality of the second mask sub-patterns 91 constitute the second mask pattern 9. Among them, for all the second mask sub-patterns 91 located between two adjacent second barrier layers 71, there is a gap between any two adjacent second mask sub-patterns 91.
[0102] Then, the second barrier layer 71 is wet-etched to remove the second barrier pattern 7 on the surface of the wafer 1 to be patterned, and only the first mask pattern 6 and the second mask pattern 9 are retained; at this time, a part of the surface of the wafer 1 to be patterned is directly attached to the first mask pattern 6, and a part is directly attached to the second mask pattern 9; the part of the second mask pattern 9 that is not attached to the wafer 1 to be patterned overlaps on the surface of the first mask pattern 6.
[0103] It should be noted that, as Figure 13 shown, whether along the first direction or the second direction, the edges of the first mask pattern 6 are flush with the edges of the second mask pattern 9, so as to ensure that for each of the first mask sub-patterns 61, all the second mask sub-patterns 91 arranged along the second direction overlap with it and are perpendicular and cross; similarly, for each of the second mask sub-patterns 91, all the first mask sub-patterns 61 arranged along the first direction overlap with it and are perpendicular and cross.
[0104] Finally, the non-overlapping areas 15 of the first mask pattern 6 and the second mask pattern 9 (as Figure 14 shown) are removed, and only the overlapping area 14 of the two (as Figure 14 shown) is retained, so as to obtain the final mask pattern 10.
[0105] It can be understood that, as Figure 15As shown, the thickness of each final mask sub-pattern 101 in the final mask pattern 10 is the thickness of two layers of SiO2 deposition, and each final mask sub-pattern 101 includes overlapping first mask sub-pattern 61 and second mask sub-pattern 91; wherein, in the final mask sub-pattern 101, the first mask sub-pattern 61 is attached to the chip 1 to be patterned, and the second mask sub-pattern 91 is located above the first mask sub-pattern 61 (that is, the first mask sub-pattern 61 is away from the side of the chip 1 to be patterned).
[0106] In one embodiment of the present application, after removing the non-overlapping area 15 of the first mask pattern 6 and the second mask pattern 9, the method further includes:
[0107] Corresponding to the overlapping area 14 between the first mask pattern 6 and the second mask pattern 9 , the second mask pattern 9 higher than the first mask pattern 6 is removed.
[0108] Specifically, after the non-overlapping area 15 of the first mask pattern 6 and the second mask pattern 9 is removed and only the overlapping area 14 of the two is retained, thereby obtaining the final mask pattern 10, the second mask sub-pattern 91 arranged on the outer surface of each final mask sub-pattern 101 is removed, thereby only retaining a layer of the first mask sub-pattern 61 with a thickness of 100 mm (e.g., 100 mm). Figure 18 As shown), it is convenient to remove the final mask sub-pattern 101 from the wafer 1 to be patterned later.
[0109] In one embodiment of the present application, the first mask sub-pattern 61 is arranged around the first barrier layer 21, that is, the periphery of the first barrier layer 21 is surrounded by the first mask sub-pattern 61; after the first barrier layer 21 is etched away, the first mask sub-pattern 61 forms a hollow closed-loop structure. Similarly, the second mask sub-pattern 91 can also be arranged around the second barrier layer 71, and after the second barrier layer 71 is etched away, the second mask sub-pattern 91 forms a hollow closed-loop structure; then, in the final mask pattern 10, in addition to the multiple final mask sub-patterns 101 arranged in an array, a circle of final mask sub-patterns 101 arranged at intervals is formed on the periphery of the final mask sub-pattern 101 array. It should be noted that in actual use, the final mask pattern 10 (such as Figure 16 The outer circle of the final mask sub-pattern 101 is removed, and only the multiple final mask sub-patterns 101 arranged in an array in the central area are retained (as shown in FIG. Figure 17 and Figure 18as shown); each final mask sub-pattern 101 in the central region is in a square shape, enabling the patterned wafer to be more easily modularly designed, so that the functions of the modules can be more flexibly combined and adjusted during wafer design and manufacturing; moreover, the square-shaped epitaxial array structure allows multiple devices and circuits to be closely integrated on the wafer surface, thereby realizing a highly integrated circuit and achieving the purpose of improving the resolution.
[0110] The wafer 1 to be patterned includes a growth substrate and an epitaxial layer grown on the growth substrate; or as Figure 1 shown, the wafer 1 to be patterned includes a CMOS substrate 11 and an epitaxial layer 12 bonded to the CMOS substrate 11. Using an etching technique, the regions on the epitaxial layer 12 that are not protected by the final mask pattern 10 are etched, thereby removing the unnecessary epitaxial layer material and leaving the required patterned structure; wherein the patterned structure is multiple epitaxial structures 121 (as Figure 19 shown), and the multiple epitaxial structures 121 are arranged in an array.
[0111] After obtaining the epitaxial structure 121, since the epitaxial structure 121 is still covered by the final mask pattern 10, therefore, the final mask sub-pattern 101 covering the surface of the epitaxial structure 121 also needs to be removed to expose the epitaxial structure 121.
[0112] The epitaxial structure 121 is used to be connected to a driving circuit; specifically, the multiple epitaxial structures 121 are connected in parallel to the driving circuit to independently control the lighting of each epitaxial structure 121 through the driving circuit.
[0113] In an embodiment of the present application, when the wafer 1 to be patterned includes a CMOS substrate 11 and an epitaxial layer 12 bonded to the CMOS substrate 11, a bonding metal layer 13 (as Figure 19 shown) is further arranged between the CMOS substrate 11 and the epitaxial structure 121 to bond the epitaxial structure 121 and the CMOS substrate 11 through the bonding metal layer 13.
[0114] In an embodiment of the present application, the cross-sectional width d3 of any side of the first mask sub-pattern 61 is less than or equal to 2 μm; and there is a gap between two adjacent first mask sub-patterns 61, and the width d4 of the gap is greater than or equal to the cross-sectional width d3. Then, the width of the remaining first mask sub-pattern 61 is the same as the width of the first barrier layer 21. After removing the first barrier layer 21, the first mask pattern 6 with equal spacing can be obtained, thereby realizing the reduction of the spacing in the first direction.
[0115] Since the cross-sectional width d3 of any side of the first mask sub-pattern 61 is larger, the corresponding gap is smaller, and the spacing of the finally etched epitaxial layer 12 is smaller. Therefore, in this embodiment, the cross-sectional width d3 of any side of the first mask sub-pattern 61 is less than or equal to 2 μm, so that the spacing between adjacent epitaxial structures 121 in the epitaxial layer 12 can be reduced to 2 μm or even less than 2 μm.
[0116] The present application also provides a wafer prepared based on the patterning method of the wafer described in any one of the above.
[0117] The present application also provides a light-emitting device made based on the wafer described above.
[0118] In summary, the present application provides a patterning method of a wafer, a wafer, and a light-emitting device, including: providing a wafer to be patterned, and forming a first barrier pattern on the wafer to be patterned; wherein, the first barrier pattern includes a plurality of first barrier layers extending in a first direction; making a first mask layer on the first barrier pattern; performing an etching process on the first mask layer to obtain a first mask pattern; wherein, the first mask pattern includes a plurality of first mask sub-patterns, and each of the first mask sub-patterns is arranged at least on both sides of the first barrier layer; removing the first barrier pattern; and performing an etching process on the wafer to be patterned with the first mask pattern as a mask. In the present application, the minimum spacing between two adjacent first barrier layers can reach 4 μm to 6 μm. After the first mask pattern is prepared on the first barrier pattern, each of the first mask sub-patterns is arranged at least on both sides of the first barrier layer, so that the spacing between two adjacent first mask sub-patterns is reduced compared with the spacing between two adjacent first barrier layers; therefore, after the etching process is performed on the wafer to be patterned with the first mask pattern as a mask, the spacing of the obtained epitaxial structures is reduced compared with the spacing of the first barrier pattern, thereby achieving the purpose of reducing the overall resolution.
[0119] It should be understood that the application of the present application is not limited to the above examples. For those of ordinary skill in the art, improvements or transformations can be made according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present application.
Claims
1. A patterning method for a wafer, characterized in that, It includes: Providing a wafer to be patterned, and forming a first barrier pattern on the wafer to be patterned; wherein, the first barrier pattern includes a plurality of first barrier layers extending in a first direction; Fabricating a first mask layer on the first barrier pattern; Etching the first mask layer to obtain a first mask pattern; wherein, the first mask pattern includes a plurality of first mask sub-patterns, and each of the first mask sub-patterns is arranged at least on both sides of the first barrier layer; Removing the first barrier pattern; Etching the wafer to be patterned using the first mask pattern as a mask.
2. The patterning method of the wafer according to claim 1, wherein, Before the step of etching the wafer to be patterned using the first mask pattern as a mask, it further includes: Forming a second barrier pattern on the first mask pattern; wherein, the second barrier pattern includes a plurality of second barrier layers extending in a second direction, and the first direction is perpendicular to the second direction; Fabricating a second mask layer on the second barrier pattern; Etching the second mask layer to obtain a second mask pattern; wherein, the second mask pattern includes a plurality of second mask sub-patterns, and each of the second mask sub-patterns is arranged at least on both sides of the second barrier layer; Removing the second barrier layer and the non-overlapping portions of the first mask pattern and the second mask pattern to obtain a final mask pattern; Etching the wafer to be patterned using the final mask pattern as a mask.
3. The patterning method of the wafer according to claim 1, wherein The step of forming the first barrier pattern includes: Coating a photoresist layer on the surface of the wafer to be patterned; Patterning the photoresist layer to form a first photoresist pattern; wherein the first photoresist pattern includes a plurality of first photoresist layers extending in a first direction; Fabricating a barrier layer on the surface of the first photoresist pattern; Removing the first photoresist layer and the barrier layer on the surface of the first photoresist layer to obtain the first barrier pattern.
4. The patterning method of the wafer according to claim 3, wherein The first barrier layer includes a metal material; The step of removing the first photoresist layer and the barrier layer on the surface of the first photoresist layer to obtain the first barrier pattern includes: Using a gold stripping process to remove the first photoresist layer and the barrier layer on the surface of the first photoresist layer to obtain the first barrier pattern.
5. The patterning method of the wafer according to claim 1, wherein The value range of the spacing between adjacent first barrier layers is 4μm to 6μm.
6. The patterning method of the wafer according to claim 5, wherein, The cross-sectional width of any side forming the first mask sub-pattern is less than or equal to 2μm; and there is a gap between adjacent two first mask sub-patterns, and the width of the gap is greater than or equal to the cross-sectional width.
7. The patterning method of the wafer according to any one of claims 1-6, characterized in that, The wafer to be patterned includes a growth substrate and an epitaxial layer grown on the growth substrate; or the wafer to be patterned includes a CMOS substrate and an epitaxial layer bonded to the CMOS substrate.
8. The patterning method of the wafer according to any one of claims 1-6, characterized in that, The first mask sub-pattern is arranged around the first barrier layer.
9. A wafer, characterized in that, It is prepared based on the patterning method of the wafer according to any one of claims 1-8.
10. A light-emitting device, characterized in that, The light-emitting device is fabricated based on the wafer according to claim 9.