Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; performing first ion implantation on the first surface of the substrate to form an initial first buried layer, wherein the initial first buried layer is internally provided with first buried layer ions; second ion implantation is carried out on the first surface of the substrate to form an initial second buried layer structure, second buried layer ions are arranged in the initial second buried layer structure, and the relative atomic mass of the second buried layer ions is smaller than that of the first buried layer ions; the distance between the bottom of the initial first buried layer and the first surface of the substrate is greater than that between the bottom of the initial second buried layer structure and the first surface of the substrate; forming a diffusion layer on the surface of the first surface of the substrate, wherein diffusion ions push second buried layer ions to diffuse into the initial first buried layer to form a second buried layer structure; and annealing the substrate, so that the second buried layer ions push the first buried layer ions to diffuse into the substrate to form a first buried layer, and the distance between the bottom of the first buried layer and the first surface of the substrate is greater than the distance between the bottom of the initial first buried layer and the first surface of the substrate. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] With the continuous popularity of the intelligent household appliance, network communication device, home interconnection, and electric vehicle markets, the demand for several types of chips such as AC-DC power management integrated circuits (ICs), LED driver chips, and high-voltage gate driver chips realized through the BCD process technology is increasing day by day. The BCD process technology integrates bipolar junction transistors (BJTs), complementary metal oxide semiconductors (CMOSs), and double-diffused metal oxide semiconductors (DMOSs) and has the advantages of high-voltage and high-current driving capabilities and low power consumption. However, in order to simultaneously achieve low power consumption and high-efficiency power modules, a hybrid technology is required to provide high-voltage capabilities and ultra-low leakage. And since some BCD process devices include signal processing functions and have high requirements for noise, the design of the buried layer formation process is crucial.

[0003] For devices related to the BCD process technology, the deeper the initial buried layer, the higher the upper limits of high-voltage resistance and low leakage. The buried layer is often realized through ion implantation and high-temperature driving processes. However, the depth of ion implantation is limited by the atomic size of the implanted ions and the implantation energy, and the high-temperature driving process is also limited by the high temperature that the wafer and the machine can withstand. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the quality of the buried layer.

[0005] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including opposite first and second surfaces; performing a first ion implantation on the first surface of the substrate to form an initial first buried layer in the substrate, the initial first buried layer having first buried layer ions; performing a second ion implantation on the first surface of the substrate to form an initial second buried layer structure in the substrate, the initial second buried layer structure having second buried layer ions, the relative atomic mass of the second buried layer ions being less than the relative atomic mass of the first buried layer ions, the distance from the bottom of the initial first buried layer to the first surface of the substrate being greater than the distance from the bottom of the initial second buried layer structure to the first surface of the substrate; forming a diffusion layer on the surface of the first surface of the substrate, the diffusion layer having diffusion ions, the diffusion ions pushing the second buried layer ions to diffuse into the initial first buried layer to form a second buried layer structure in the substrate; annealing the substrate to cause the second buried layer ions to push the first buried layer ions to diffuse into the substrate to form a first buried layer, the distance from the bottom of the first buried layer to the first surface of the substrate being greater than the distance from the bottom of the initial first buried layer to the first surface of the substrate.

[0006] Optionally, the first buried layer ions and the second buried layer ions have the same conduction type; the first buried layer ions include N-type ions or P-type ions, the second buried layer ions include N-type ions or P-type ions, the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions or indium ions.

[0007] Optionally, the substrate has doping ions, the conduction type of the doping ions being opposite to the conduction types of the first buried layer ions and the second buried layer ions.

[0008] Optionally, the processes of forming the diffusion layer and annealing the substrate include furnace tube processes; the temperature range for forming the diffusion layer is less than the temperature range for the annealing process.

[0009] Optionally, when the first buried layer ions and the second buried layer ions have an N-type conduction type, the material of the diffusion layer includes silicon oxide, and the diffusion ions include oxygen ions.

[0010] Optionally, the process parameters for forming the diffusion layer include: the reaction gas is oxygen, or the reaction gas is oxygen and hydrogen, or the reaction gas is oxygen and dichloroethylene; the reaction temperature range is 700 degrees Celsius to 900 degrees Celsius.

[0011] Optionally, when the first buried layer ions and the second buried layer ions have a P-type conduction type, the material of the diffusion layer includes nitrogen-doped silicon oxide, and the diffusion ions include nitrogen ions.

[0012] Optionally, the process parameters for forming the diffusion layer include: the reaction gases are oxygen and nitrous oxide, or the reaction gases are oxygen, hydrogen and nitrous oxide, or the reaction gases are oxygen, nitrous oxide and dichloroethylene; the reaction temperature ranges from 700 degrees Celsius to 900 degrees Celsius.

[0013] Optionally, the process parameters for annealing the substrate include: the gas includes nitrogen or an inert gas; the reaction temperature ranges from 1100 degrees Celsius to 1200 degrees Celsius; the reaction time is greater than 2 hours.

[0014] Optionally, the concentration of the first buried layer ions is greater than the concentration of the second buried layer ions.

[0015] The method for forming the semiconductor structure according to claim 10, wherein the initial second buried layer structure includes at least one second buried layer; when the initial second buried layer structure includes multiple second buried layers, in the direction from the initial first buried layer to the first surface of the substrate, the concentration of the second buried layer ions in several of the second buried layers gradually decreases, and the relative atomic mass of the second buried layer ions in several of the second buried layers gradually decreases.

[0016] Optionally, the initial second buried layer structure includes one second buried layer; the first buried layer ions include arsenic ions or antimony ions, and the second buried layer ions include phosphorus ions.

[0017] Optionally, the initial second buried layer structure is in contact with the initial first buried layer.

[0018] Optionally, the thickness range of the diffusion layer is greater than 100 angstroms.

[0019] Optionally, it further includes: removing the diffusion layer; forming an epitaxial layer on the surface of the first surface of the substrate.

[0020] Optionally, before performing the first ion implantation on the first surface of the substrate, it further includes: forming a protective layer on the surface of the first surface of the substrate.

[0021] Optionally, the method for performing the first ion implantation on the first surface of the substrate includes: forming a mask structure on the protective layer, the mask structure exposing a part of the surface of the protective layer; performing the first ion implantation on the first surface of the substrate with the mask structure as a mask; the method for performing the second ion implantation on the first surface of the substrate includes: performing the second ion implantation on the first surface of the substrate with the mask structure as a mask.

[0022] Optionally, before forming the diffusion layer on the surface of the first surface of the substrate, it further includes: removing the mask structure.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] The forming method of the present invention is as follows: first, an initial first buried layer is formed in the substrate, then an initial second buried layer structure is formed in the substrate, and then a diffusion layer is formed on the surface of the first side of the substrate. When forming the diffusion layer, the diffused ions in the diffusion layer can push the second buried layer ions to diffuse into the initial first buried layer. When annealing the substrate, since the relative atomic mass of the second buried layer ions is smaller than that of the first buried layer ions, the diffused ions can further diffuse into the substrate under high-temperature processes, thereby promoting the formation of emission diffusion of the second buried layer ions, enabling the second buried layer ions to further push the first buried layer ions to diffuse into the substrate, so as to form a first buried layer with a deeper depth in the substrate, improving the high-voltage resistance and low leakage of the device, and meeting the high-voltage resistance and low-leakage requirements of devices with higher high-voltage resistance requirements and smaller-size BCD devices.

[0025] Furthermore, the diffusion layer also serves to block the second buried layer ions, avoiding the situation that the second buried layer ions with a relatively small atomic mass are likely to escape from the substrate during high-temperature processes, which may lead to a decrease in the concentration of the second buried layer ions and affect the quality of the second buried layer, and cause contamination of the furnace tube machine platform, thus improving the yield during mass production.

[0026] Furthermore, the processes of forming the diffusion layer and annealing the substrate include a furnace tube process. The temperature range for forming the diffusion layer is 700 °C to 900 °C, and the temperature range for annealing the substrate is 1100 °C to 1200 °C. The temperature range for forming the diffusion layer is less than the temperature range for annealing. By using a single furnace tube process, the formation of the diffusion layer with a low-temperature process and the annealing treatment with a high-temperature process are achieved, which can save the process flow.

[0027] Furthermore, the reaction gas for forming the diffusion layer includes dichloroethylene. The dichloroethylene can act as a catalyst to increase the oxidation rate of forming the diffusion layer. The oxidation rate of forming the diffusion layer is relatively high. Under the same thermal budget, a thicker diffusion layer can be formed, and the increase in the oxidation rate can further inhibit the outward diffusion of the second buried layer ions. The diffused ions can further push the second buried layer ions to diffuse into the initial first buried layer, thereby further pushing the first buried layer ions to diffuse into the substrate, further increasing the depth of the formed first buried layer in the substrate. In addition, the dichloroethylene gas can clean the inside of the furnace tube during and after the reaction process, improve the internal environment of the furnace tube, and improve the yield.

[0028] Furthermore, the diffusion layer is removed, and an epitaxial layer is formed on the surface of the first side of the substrate. The overall thickness of the epitaxial layer and the substrate becomes thicker, so that the first buried layer and the second buried layer located in the substrate have a deeper depth, further increasing the depth of the first buried layer and the second buried layer, and improving the anti-leakage level of the substrate. Description of the Drawings

[0029] Figures 1 to 6 It is a schematic diagram of the formation process of the semiconductor structure in the embodiment of the present invention. Detailed Embodiments

[0030] As described in the background art, the formation process and quality of the buried layer still need to be improved.

[0031] Specifically, the depth can be adjusted by adjusting the ion species and implantation conditions (such as energy and doping amount) of ion implantation. However, the deeper the ion implantation depth, the higher the requirements for the ion implantation machine. Among them, when phosphorus is selected as the buried layer, since the diffusion temperature of phosphorus is lower than that of arsenic or antimony with a heavier relative atomic mass, the control requirements for the thermal budget are higher, and it is also easier to contaminate the machine in high-temperature processes, such as contaminating the machine in subsequent drive processes or epitaxial processes.

[0032] When antimony with a relatively large relative atomic mass is selected as the buried layer element, the ion implantation depth will be lower due to the large mass. Under the same ion implantation conditions, the deeper diffusion of implanted ions can also be achieved by increasing the temperature and time of the drive process, such as adjusting the temperature from 1100 °C to 1200 °C or adjusting the process time from 12 h to 48 h. However, blindly increasing the temperature and time will, on the one hand, increase the demand for furnace tube process equipment, and on the other hand, it is easier to form slip defects and silicon damage in high-temperature processes, affecting the product yield and increasing production risks. Therefore, how to form a deeper buried layer at a suitable cost and under the same thermal budget is a problem worthy of in-depth study.

[0033] To solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure. First, an initial first buried layer is formed in the substrate, then an initial second buried layer structure is formed in the substrate, and then a diffusion layer is formed on the surface of the first side of the substrate. When forming the diffusion layer, the diffusion ions in the diffusion layer can push the second buried layer ions to diffuse into the initial first buried layer. When annealing the substrate, since the relative atomic mass of the second buried layer ions is smaller than that of the first buried layer ions, the diffusion ions can further diffuse into the substrate under high-temperature processes, thereby promoting the second buried layer ions to form emission diffusion, enabling the second buried layer ions to further push the first buried layer ions to diffuse into the substrate, so as to form a first buried layer with a deeper depth in the substrate, to improve the high-voltage resistance and low leakage of the device, and meet the high-voltage resistance and low leakage requirements of devices with higher high-voltage resistance requirements and smaller-size BCD devices.

[0034] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following provides a detailed description of specific embodiments of the present invention with reference to the accompanying drawings.

[0035] Figures 1 to 6 It is a schematic diagram of the formation process of the semiconductor structure in an embodiment of the present invention.

[0036] Please refer to Figure 1 , a substrate 100 is provided, and the substrate 100 includes opposite first and second surfaces.

[0037] The substrate 100 has doped ions, and the doped ions include N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0038] In this embodiment, the conduction type of the doped ions is P-type.

[0039] In this embodiment, the material of the substrate 100 is silicon.

[0040] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0041] Please continue to refer to Figure 1 , a protective layer 101 is formed on the surface of the first surface of the substrate 100.

[0042] The protective layer 101 is used to protect the surface of the substrate 100 from being damaged during subsequent ion implantation processes.

[0043] In this embodiment, the material of the protective layer 101 includes silicon oxide. The process for forming the protective layer 101 includes an oxidation process or an in-situ steam generation process. The protective layer 101 formed by the oxidation process or the in-situ steam generation process has good quality and a dense structure, and can play a protective role without a relatively thick thickness.

[0044] Please refer to Figure 2 , a first ion implantation is performed on the first surface of the substrate 100 to form an initial first buried layer 103 in the substrate 100, and the initial first buried layer 103 has first buried layer ions.

[0045] The conduction type of the doped ions is opposite to the conduction type of the first buried layer ions.

[0046] The first buried-layer ions include N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0047] In this embodiment, the conductivity type of the first buried-layer ions is N-type.

[0048] The method for performing the first ion implantation on the first surface of the substrate 100 includes: forming a mask structure 102 on the protective layer 101, where the mask structure 102 exposes a part of the surface of the protective layer 101; using the mask structure 102 as a mask to perform the first ion implantation on the first surface of the substrate 100.

[0049] The mask structure 102 is used to define the positions in the substrate 100 where buried layers need to be formed.

[0050] In this embodiment, the material of the mask structure 102 includes photoresist.

[0051] Please refer to Figure 3 , perform a second ion implantation on the first surface of the substrate 100 to form an initial second buried-layer structure 104 in the substrate 100, and the initial second buried-layer structure 104 contains second buried-layer ions.

[0052] The conductivity types of the first buried-layer ions and the second buried-layer ions are the same; the conductivity type of the doping ions is opposite to the conductivity types of the first buried-layer ions and the second buried-layer ions.

[0053] The second buried-layer ions include N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0054] In this embodiment, the relative atomic mass of the second buried-layer ions is less than the relative atomic mass of the first buried-layer ions.

[0055] In this embodiment, the second buried-layer ions include phosphorus ions, and the first buried-layer ions include arsenic ions or antimony ions.

[0056] In this embodiment, the distance d1 from the bottom of the initial first buried layer 103 to the first surface of the substrate 100 is greater than the distance d2 from the bottom of the initial second buried-layer structure 104 to the first surface of the substrate 100. This is to facilitate the subsequent diffusion of the first buried-layer ions into the substrate 100 by the second buried-layer ions.

[0057] The method for performing the second ion implantation on the first surface of the substrate 100 includes: using the mask structure 102 as a mask to perform the second ion implantation on the first surface of the substrate 100.

[0058] In this embodiment, the concentration of the first buried layer ions is greater than that of the second buried layer ions, so that the second buried layer ions can push the first buried layer ions to diffuse into the substrate 100 subsequently.

[0059] In this embodiment, the initial second buried layer structure 104 is in contact with the initial first buried layer 103.

[0060] The initial second buried layer structure 104 includes at least one layer of second buried layer; when the initial second buried layer structure includes multiple layers of second buried layers, in the direction from the initial first buried layer to the first surface of the substrate, the concentration of the second buried layer ions in several layers of the second buried layers gradually decreases, and the relative atomic mass of the second buried layer ions in several layers of the second buried layers gradually decreases. Several layers of second buried layers are formed by ion implantation process respectively.

[0061] In this embodiment, the initial second buried layer structure 104 includes one layer of second buried layer.

[0062] Please refer to Figure 4 , remove the mask structure 102; after removing the mask structure 102, a diffusion layer 105 is formed on the surface of the first surface of the substrate 100. The diffusion layer 105 has diffusion ions, and the diffusion ions push the second buried layer ions to diffuse into the initial first buried layer 103, and a second buried layer structure 106 is formed in the substrate 100.

[0063] In this embodiment, the process of removing the mask structure 102 includes an ashing process.

[0064] In this embodiment, when the conduction types of the first buried layer ions and the second buried layer ions are N-type, the material of the diffusion layer 105 includes silicon oxide, and the diffusion ions include oxygen ions.

[0065] When forming the diffusion layer 105, the diffusion ions in the diffusion layer 105 can push the second buried layer ions to diffuse into the initial first buried layer 103; the second buried layer ions also diffuse to the first surface of the substrate 100, and the diffusion layer 105 also plays a role in blocking the second buried layer ions, so as to avoid the second buried layer ions with relatively small relative atomic mass from easily escaping from the substrate 100 during the high-temperature process, resulting in a decrease in the concentration of the second buried layer ions and affecting the quality of the subsequently formed second buried layer, and causing pollution to the furnace tube machine platform, thereby improving the yield during mass production.

[0066] In this embodiment, the process parameters for forming the diffusion layer 105 include: the reaction gases are oxygen and dichloroethylene; the reaction temperature range is 700 degrees Celsius to 900 degrees Celsius.

[0067] The reaction gas for forming the diffusion layer 105 includes dichloroethylene, which can act as a catalyst to increase the oxidation rate of forming the diffusion layer 105. The oxidation rate of forming the diffusion layer 105 is relatively high. Under the same thermal budget, a thicker diffusion layer 105 can be formed, and the increase in the oxidation rate can further inhibit the outward diffusion of the second buried layer ions. The diffused ions can further promote the diffusion of the second buried layer ions into the initial first buried layer 103, thereby further promoting the diffusion of the first buried layer ions into the substrate 100, and further increasing the depth of the formed first buried layer in the substrate. In addition, the dichloroethylene gas can clean the inside of the furnace tube during and after the reaction process, improve the internal environment of the furnace tube, and increase the yield.

[0068] In this embodiment, the thickness range of the diffusion layer 105 is greater than 100 angstroms.

[0069] In other embodiments, the process parameters for forming the diffusion layer include: the reaction gas is oxygen, or the reaction gas is oxygen and hydrogen; the reaction temperature range is 700 degrees Celsius to 900 degrees Celsius.

[0070] In this embodiment, the material of the diffusion layer 105 is the same as that of the protective layer 101. During the formation of the diffusion layer 105, the protective layer 101 and the diffusion layer 105 are combined into one layer.

[0071] In another embodiment, when the conduction types of the first buried layer ions and the second buried layer ions are P-type, the material of the diffusion layer includes silicon oxide doped with nitrogen, and the diffused ions include nitrogen ions.

[0072] The process parameters for forming the diffusion layer include: the reaction gas is oxygen and nitrous oxide, or the reaction gas is oxygen, hydrogen and nitrous oxide, or the reaction gas is oxygen, nitrous oxide and dichloroethylene; the reaction temperature range is 700 degrees Celsius to 900 degrees Celsius.

[0073] Please refer to Figure 5 , annealing the substrate 100 to cause the second buried layer ions to promote the diffusion of the first buried layer ions into the substrate 100, and forming a first buried layer 107 in the substrate 100. The distance d3 from the bottom of the first buried layer 107 to the first surface of the substrate 100 is greater than the distance d1 from the bottom of the initial first buried layer 103 to the first surface of the substrate 100 (refer to Figure 3 ).

[0074] The process parameters for annealing the substrate 100 include: the gas includes nitrogen or inert gas; the reaction temperature range is 1100 degrees Celsius to 1200 degrees Celsius; the reaction time is greater than 2 hours.

[0075] In this embodiment, the process of forming the diffusion layer 105 and annealing the substrate 100 includes a furnace tube process. The temperature range for forming the diffusion layer 105 is 700 degrees Celsius to 900 degrees Celsius, and the temperature range for annealing the substrate 100 is 1100 degrees Celsius to 1200 degrees Celsius. The temperature range for forming the diffusion layer 105 is less than the temperature range for the annealing process. By means of a single furnace tube process, the formation of the diffusion layer in a low-temperature process and the annealing treatment in a high-temperature process are achieved, which can save the process flow.

[0076] The temperature range for forming the diffusion layer 105 is less than the temperature range for the annealing process, and the annealing process has a higher temperature. When forming the diffusion layer 105, the diffused ions in the diffusion layer 105 can push the second buried layer ions to diffuse into the initial first buried layer 103. When annealing the substrate 100, since the relative atomic mass of the second buried layer ions is less than that of the first buried layer ions, the diffused ions can further diffuse into the substrate 100 under high-temperature process conditions, thereby promoting the formation of emission diffusion of the second buried layer ions, enabling the second buried layer ions to further push the first buried layer ions to diffuse into the substrate 100, so as to form a first buried layer 107 with a deeper depth in the substrate 100, improve the anti-leakage level of the substrate 100, improve the high-voltage resistance and low leakage of the device, and meet the high-voltage resistance and low-leakage requirements of devices with higher high-voltage resistance requirements and smaller-size BCD devices.

[0077] In addition, the initial first buried layer 103 and the initial second buried layer structure do not need to be implanted ultra-deep, and the high-temperature process of the furnace tube process does not need to be too high to form an ultra-deep first buried layer 107. Without increasing the thermal budget and process conditions, a deeper first buried layer 107 can be obtained.

[0078] Please refer to Figure 6 , remove the diffusion layer 105; form an epitaxial layer 108 on the surface of the first side of the substrate 100.

[0079] The process of removing the diffusion layer 105 includes a wet etching process or a dry etching process. The process of forming the epitaxial layer 108 on the surface of the first side of the substrate 100 includes an epitaxial process.

[0080] The material of the epitaxial layer 108 includes silicon, silicon germanium, silicon carbide, or phosphosilicon, etc.

[0081] The overall thickness of the epitaxial layer 108 and the substrate 100 becomes thicker, so that the first buried layer 107 and the second buried layer structure 106 located in the substrate 100 have a deeper depth, further enhancing the depth of the first buried layer 107 and the second buried layer structure 106, and improving the anti-leakage level of the substrate 100.

[0082] In other embodiments, it is possible not to form the epitaxial layer.

[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including opposite first and second surfaces; Performing a first ion implantation on the first surface of the substrate to form an initial first buried layer in the substrate, the initial first buried layer having first buried layer ions; Performing a second ion implantation on the first surface of the substrate to form an initial second buried layer structure in the substrate, the initial second buried layer structure having second buried layer ions, the relative atomic mass of the second buried layer ions being less than the relative atomic mass of the first buried layer ions, and the distance from the bottom of the initial first buried layer to the first surface of the substrate being greater than the distance from the bottom of the initial second buried layer structure to the first surface of the substrate; Forming a diffusion layer on the surface of the first surface of the substrate, the diffusion layer having diffusion ions, the diffusion ions driving the second buried layer ions to diffuse into the initial first buried layer to form a second buried layer structure in the substrate; Annealing the substrate to cause the second buried layer ions to drive the first buried layer ions to diffuse into the substrate to form a first buried layer, the distance from the bottom of the first buried layer to the first surface of the substrate being greater than the distance from the bottom of the initial first buried layer to the first surface of the substrate.

2. The method for forming a semiconductor structure according to claim 1, wherein, The first buried layer ions and the second buried layer ions have the same conduction type; the first buried layer ions include N-type ions or P-type ions, the second buried layer ions include N-type ions or P-type ions, the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions or indium ions.

3. The method for forming a semiconductor structure according to claim 2, wherein The substrate has doping ions, the conduction type of the doping ions being opposite to the conduction types of the first buried layer ions and the second buried layer ions.

4. The method for forming a semiconductor structure according to claim 2, wherein, The processes of forming the diffusion layer and annealing the substrate include furnace tube processes; the temperature range for forming the diffusion layer is less than the temperature range for the annealing treatment.

5. The method for forming a semiconductor structure according to claim 4, wherein, When the first buried layer ions and the second buried layer ions have an N-type conduction type, the material of the diffusion layer includes silicon oxide, and the diffusion ions include oxygen ions.

6. The method for forming a semiconductor structure according to claim 5, wherein, The process parameters for forming the diffusion layer include: the reaction gas is oxygen, or the reaction gas is oxygen and hydrogen, or the reaction gas is oxygen and dichloroethylene; the reaction temperature range is 700 degrees Celsius to 900 degrees Celsius.

7. The method for forming a semiconductor structure according to claim 4, wherein When the first buried layer ions and the second buried layer ions have a P-type conduction type, the material of the diffusion layer includes nitrogen-doped silicon oxide, and the diffusion ions include nitrogen ions.

8. The method for forming a semiconductor structure according to claim 7, wherein, The process parameters for forming the diffusion layer include: the reaction gas is oxygen and nitrous oxide, or the reaction gas is oxygen, hydrogen and nitrous oxide, or the reaction gas is oxygen, nitrous oxide and dichloroethylene; the reaction temperature range is 700 degrees Celsius to 900 degrees Celsius.

9. The method for forming a semiconductor structure according to claim 4, wherein, The process parameters for annealing the substrate include: the gas includes nitrogen or an inert gas; the reaction temperature range is 1100 degrees Celsius to 1200 degrees Celsius; the reaction time is greater than 2 hours.

10. The method for forming a semiconductor structure according to claim 2, wherein, The concentration of the first buried layer ions is greater than the concentration of the second buried layer ions.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The initial second buried layer structure includes at least one second buried layer; when the initial second buried layer structure includes multiple second buried layers, in the direction from the initial first buried layer to the first surface of the substrate, the concentration of the second buried layer ions in several of the second buried layers gradually decreases, and the relative atomic mass of the second buried layer ions in several of the second buried layers gradually decreases.

12. The method for forming a semiconductor structure according to claim 11, wherein, The initial second buried layer structure includes one second buried layer; the first buried layer ions include arsenic ions or antimony ions, and the second buried layer ions include phosphorus ions.

13. The method for forming a semiconductor structure according to claim 1, wherein, The initial second buried layer structure is in contact with the initial first buried layer.

14. The method for forming a semiconductor structure according to claim 1, wherein, The thickness range of the diffusion layer is greater than 100 angstroms.

15. The method for forming a semiconductor structure as claimed in claim 1, wherein, Further included are: Removing the diffusion layer; Forming an epitaxial layer on the first surface of the substrate.

16. The method for forming a semiconductor structure according to claim 1, wherein, Before performing the first ion implantation on the first surface of the substrate, further included is: forming a protective layer on the first surface of the substrate.

17. The method for forming a semiconductor structure according to claim 16, wherein, The method for performing the first ion implantation on the first surface of the substrate includes: forming a mask structure on the protective layer, the mask structure exposing a part of the surface of the protective layer; using the mask structure as a mask to perform the first ion implantation on the first surface of the substrate; the method for performing the second ion implantation on the first surface of the substrate includes: using the mask structure as a mask to perform the second ion implantation on the first surface of the substrate.

18. The method for forming a semiconductor structure according to claim 17, wherein Before forming the diffusion layer on the first surface of the substrate, further included is: removing the mask structure.

Images