Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof, and the method comprises the steps: providing a first wafer which comprises a middle region and an edge region, the edge region is located around the middle region, and a metal interconnection layer is formed on the surface of the first wafer, the part, located in the edge area, of the metal interconnection layer is provided with a cavity; forming a dielectric layer on the metal interconnection layer, wherein the dielectric layer at least fills the cavity; forming a barrier layer on the dielectric layer, wherein the barrier layer extends to cover the surface and the side wall of the metal interconnection layer; performing planarization processing to expose the surface of the metal interconnection layer; and carrying out a hybrid bonding process on the first wafer. According to the invention, the risk of metal diffusion of the metal interconnection layer is reduced or avoided, and the risk of edge breakage or crystal edge fracture of the first wafer is reduced or avoided, thereby facilitating the improvement of the yield of the wafers.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technologies, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the case where the development of very large scale integrated circuits is increasingly approaching the physical limit, three-dimensional integrated circuits, which have advantages in both physical size and cost, are an effective way to extend Moore's Law and solve advanced packaging problems. Among them, hybrid bonding technology can achieve internal interconnection of thousands of chips while bonding two wafers, greatly improving chip performance while saving production costs.

[0003] The difficulty of hybrid bonding technology lies in achieving internal interconnection of metals and maintaining a high yield after interconnection. In the case of poor edge bonding, the risk of edge cracking in subsequent processes is extremely high, seriously affecting the product yield. Therefore, a method is needed to reduce or avoid the risk of edge cracking in subsequent processes while ensuring a high yield of wafers after hybrid bonding. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof, which can reduce or avoid the risk of edge cracking in subsequent processes while ensuring a high yield of wafers.

[0005] In a first aspect, this application provides a manufacturing method of a semiconductor structure, including:

[0006] Providing a first wafer, the first wafer includes a central region and an edge region, the edge region is located around the central region, a metal interconnection layer is formed on the surface of the first wafer, and a part of the metal interconnection layer located within the edge region has voids;

[0007] Forming a dielectric layer on the metal interconnection layer, the dielectric layer at least fills the voids;

[0008] Forming a barrier layer on the dielectric layer, the barrier layer extends to cover the surface and sidewalls of the metal interconnection layer;

[0009] Performing a planarization process to expose the surface of the metal interconnection layer;

[0010] Performing a hybrid bonding process on the first wafer.

[0011] In one embodiment, the steps before forming the dielectric layer on the metal interconnection layer further include:

[0012] Removing a part of the metal interconnection layer in the edge region away from the central region;

[0013] Forming a bonding layer on the metal interconnection layer;

[0014] Remove a part of the bonding layer in the edge region that is far from the central region.

[0015] In one embodiment, along the radial direction of the first wafer, the width of the removed part of the metal interconnect layer is greater than the width of the removed part of the bonding layer.

[0016] In one embodiment, the metal interconnect layer includes an interlayer dielectric structure formed on the first wafer, and trenches and vias formed in the interlayer dielectric structure, and a metal material is electroplated in the trenches and the vias.

[0017] In one embodiment, the formation process of the interlayer dielectric structure includes:

[0018] Form a first dielectric layer on the first wafer;

[0019] Perform a planarization process on the first dielectric layer to remove at most a part of the first dielectric layer;

[0020] Form a dielectric barrier layer on the first dielectric layer;

[0021] Form a second dielectric layer on the dielectric barrier layer to form the interlayer dielectric structure including the first dielectric layer, the dielectric barrier layer, and the second dielectric layer.

[0022] In one embodiment, during the process of performing the planarization process on the first dielectric layer, the thickness range by which the first dielectric layer is thinned includes between 5 kÅ and 20 kÅ, and the remaining thickness range of the first dielectric layer after the planarization process is greater than zero and less than or equal to 3 kÅ.

[0023] In one embodiment, the hybrid bonding process includes:

[0024] Provide a second wafer, on the front surface of which a metal wiring layer is formed;

[0025] Bond the front surface of the first wafer and the front surface of the second wafer so that the projection of the metal interconnect layer along the direction perpendicular to the surface of the second wafer coincides with the projection of the metal wiring layer along the direction perpendicular to the surface of the second wafer, so that the metal wiring layer and the metal interconnect layer are connected;

[0026] Perform an annealing process;

[0027] Wherein, the first wafer and the second wafer are respectively one of a logic wafer and a pixel wafer, and the types of the first wafer and the second wafer are different.

[0028] In one embodiment, after completing the hybrid bonding process, the method for manufacturing the semiconductor structure further includes:

[0029] Performing defect detection on the semiconductor structure obtained after hybrid bonding.

[0030] In one embodiment, the thickness range of the dielectric layer is 1kÅ to 5kÅ, and the thickness range of the barrier layer is 0.5kÅ to 2kÅ.

[0031] In a second aspect, the present application also provides a semiconductor structure prepared by using the method for manufacturing the semiconductor structure described above.

[0032] An unexpected effect of the present application is that by forming a dielectric layer that fills the voids, the risk of crystal edge cracking in subsequent processes is reduced or avoided; by forming a barrier layer that covers the surface and sidewalls of the metal interconnect layer, the risk of metal diffusion in the metal interconnect layer is reduced or avoided, and at the same time, the risk of chipping or crystal edge cracking of the first wafer is reduced or avoided, thereby helping to improve the yield of the wafer. Description of the Drawings

[0033] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 It is a flowchart of the method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0035] Figure 2 It is a schematic structural diagram corresponding to the step of providing the first wafer in the method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0036] Figure 3 It is a schematic structural diagram corresponding to the step of forming a dielectric layer on the metal interconnect layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0037] Figure 4 It is a schematic structural diagram corresponding to the step of forming a barrier layer on the dielectric layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0038] Figure 5 It is a schematic structural diagram corresponding to the step of performing planarization treatment to expose the surface of the metal interconnect layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0039] Figure 6Schematic diagram corresponding to the step of performing hybrid bonding process in the manufacturing method of a semiconductor structure provided by an embodiment of the present application.

[0040] Description of reference numerals: 100 - first wafer; 110 - metal interconnect layer; 111 - bonding layer; 112 - interlayer dielectric structure; 112a - first dielectric layer; 112b - dielectric barrier layer; 112c - second dielectric layer; 113 - trench; 114 - via; 120 - dielectric layer; 130 - barrier layer; 200 - second wafer; 210 - metal wiring layer; X1 - central region; X2 - edge region; A - void. Detailed implementation manners

[0041] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0043] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be referred to as the second element, component, region, layer or part; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0044] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the attached drawings is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upper and lower orientations. In addition, the device may also have other orientations (such as rotated 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0045] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprising" or "having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0046] Figure 1 A flowchart of a method for manufacturing a semiconductor structure provided for an embodiment of the present application. Refer to Figure 1 The present application provides a method for manufacturing a semiconductor structure, including steps S01 to S05.

[0047] Step S01: Provide a first wafer. The first wafer includes a central region and an edge region. The edge region is located around the central region. A metal interconnect layer is formed on the surface of the first wafer, and a part of the metal interconnect layer located within the edge region has voids.

[0048] Refer to Figure 2 In one embodiment, void A is generally formed during the preparation process of the metal interconnect layer 110 (such as in the edge cleaning process of the metal interconnect layer 110), and the presence of void A in the metal interconnect layer 110 will greatly increase the risk of crystal edge cracking in subsequent processes, thereby affecting the yield of the first wafer 100.

[0049] Step S02: Form a dielectric layer on the metal interconnect layer. The dielectric layer fills at least the voids.

[0050] Refer to Figure 3, in one embodiment, by filling the cavity A with the dielectric layer 120, the quality of the first wafer 100 and each film layer on its surface (including the metal interconnect layer 110 and the dielectric layer 120) can be effectively improved, thereby reducing or avoiding the risk of defects or edge cracking in subsequent planarization processing and bonding processes.

[0051] In one embodiment, the material of the dielectric layer 120 is an insulating dielectric material. For example, the material of the dielectric layer 120 includes silicon oxide or other oxide materials.

[0052] Step S03, forming a barrier layer on the dielectric layer, the barrier layer extending to cover the surface and sidewalls of the metal interconnect layer.

[0053] Refer to Figure 4 , in one embodiment, the material of the barrier layer 130 includes carbon-doped silicon nitride (Nitride Doped Silicon Carbide, NDC). It should be noted that the formation of the barrier layer 130 can reduce or prevent metal diffusion on the surface of the metal interconnect layer and at the edge positions (i.e., the part of the edge region X2 far from the central region X1).

[0054] Step S04, performing planarization processing to expose the surface of the metal interconnect layer.

[0055] Refer to Figure 5 , in one embodiment, the portions of the dielectric layer 120 and the barrier layer 130 located on the surface of the metal interconnect layer 110 are both removed during the planarization process, so as to expose the surface of the metal interconnect layer 110 for subsequent hybrid bonding process. Optionally, a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP) is used for planarization processing.

[0056] It should be noted that the planarization processing in step S04 removes the dielectric layer 120 and the barrier layer 130 on the upper surface of the metal interconnect layer 110, making the remaining dielectric layer 120 and the remaining barrier layer 130 flush with the surface of the metal interconnect layer 110. At this time, the remaining dielectric layer 120 and the remaining barrier layer 130 are both located at the edge positions of the first wafer 100 (i.e., the part of the edge region X2 far from the central region X1), so as to protect the side edges of the metal interconnect layer 110 (i.e., the part of the metal interconnect layer 110 close to the edge of the first wafer 100) in the subsequent bonding process, thereby improving the product yield.

[0057] Meanwhile, it should be further explained that after the planarization process is performed to expose the surface of the metal interconnect layer, the next step of the hybrid bonding process will connect the exposed surface of the metal interconnect layer to the metal wiring layer on another wafer. Therefore, at this time, the risk of metal diffusion and contamination on the exposed surface of the metal interconnect layer is very small and can be ignored.

[0058] Step S05: Perform a Hybrid Bond (HB) process on the first wafer.

[0059] The manufacturing method of the above semiconductor structure reduces or avoids the risk of edge cracking in subsequent processes by forming a dielectric layer that fills the voids; by forming a barrier layer that covers the surface and sidewalls of the metal interconnect layer, it reduces or avoids the risk of metal diffusion in the metal interconnect layer, and at the same time reduces or avoids the risk of chipping or edge cracking of the first wafer, thereby helping to improve the yield of the wafer.

[0060] Continue to refer to Figure 2 , in one embodiment, the metal interconnect layer 110 includes an interlayer dielectric structure 112 and trenches 113 and vias 114 formed in the interlayer dielectric structure 112. The trenches 113 and vias 114 are electroplated with a metal material to ensure the normal function of the metal interconnect layer 110. Optionally, the material of the metal interconnect layer 110 includes copper (Cu).

[0061] Refer to Figure 2 , in one embodiment, the formation process of the interlayer dielectric structure 112 includes: forming a first dielectric layer 112a on the first wafer 100; performing a planarization process on the first dielectric layer 112a to remove at most a part of the first dielectric layer 112a to improve the thickness uniformity and surface flatness of the first dielectric layer 112a; forming a dielectric barrier layer 112b on the first dielectric layer 112a; forming a second dielectric layer 112c on the dielectric barrier layer 112b to form an interlayer dielectric structure 112 including the first dielectric layer 112a, the dielectric barrier layer 112b, and the second dielectric layer 112c.

[0062] In one embodiment, during the planarization process of the first dielectric layer, the thinned thickness of the first dielectric layer has a logarithmic relationship with the total thickness of the first dielectric layer. Optionally, the relationship between the total thickness D of the first dielectric layer and the thinned thickness d of the first dielectric layer is . Optionally, the total thickness range of the first dielectric layer before planarization includes 20 kÅ to 30 kÅ, the thinned thickness range of the first dielectric layer includes 5 kÅ to 20 kÅ, and the remaining thickness range of the first dielectric layer after planarization is greater than zero and less than or equal to 3 kÅ. Optionally, the thickness of the dielectric barrier layer is 1 kÅ, and the thickness of the second dielectric layer is 2.1 kÅ.

[0063] It should be noted that, during the planarization process of the first dielectric layer, by controlling the thickness of the part of the first dielectric layer removed during the planarization process, the influence of excessive thickness removed during the planarization process on subsequent lithography and etching processes can be reduced or avoided, the problem of metal residue that may occur in subsequent process steps can also be reduced or avoided, and the probability of abnormal die edge bonding can be lowered.

[0064] In one embodiment, the material of the first dielectric layer is tetraethyl orthosilicate (TEOS), the material of the dielectric barrier layer is carbon-doped silicon nitride, and the material of the second dielectric layer is silicon oxide. In other embodiments of the present application, the specific structure of the interlayer dielectric structure and the material selection of different film layers can be adjusted according to actual needs, as long as it is ensured that the interlayer dielectric structure meets the insulation performance and other process requirements of the semiconductor structure, and the present application places no restrictions thereon.

[0065] It should be noted that, during the formation process of the above interlayer dielectric structure, after forming the first dielectric layer, the first dielectric layer also needs to be etched to form trenches and vias in the first dielectric layer, and metal materials are filled in the trenches and vias through a metal electroplating process. Similarly, after forming the second dielectric layer, the second dielectric layer and the dielectric barrier layer also need to be etched to form trenches and vias in the second dielectric layer and the dielectric barrier layer, and metal materials are filled in the trenches and vias through a metal electroplating process, so as to form the interlayer dielectric structure and the metal interconnect layer.

[0066] Continue to refer to Figure 2 , in one embodiment, before forming the dielectric layer 120 on the metal interconnect layer 110, the manufacturing method of the semiconductor structure further includes: removing a part of the metal interconnect layer 110 in the edge region X2 that is far from the central region X1; forming a bonding layer 111 on the metal interconnect layer 110; removing a part of the bonding layer 111 in the edge region X2 that is far from the central region X1, so as to remove the part in the edge region X2 that is far from the central region X1, to ensure the smooth progress of subsequent processes, and reduce or avoid the formation of bubbles (Bubbles) and defects in subsequent bonding processes. Among them, along the radial direction of the first wafer 100, the width D1 of the part of the metal interconnect layer 110 removed is greater than the width D2 of the part of the bonding layer 111 removed. Exemplarily, the width D1 of the part of the metal interconnect layer 110 removed is, for example, 3.2 mm, and the width D2 of the part of the bonding layer 111 removed is, for example, 2.4 mm.

[0067] In one embodiment, electroplated copper edge bevel removal (ECP EBR) can be used to remove a portion of the metal interconnect layer 110 in the edge region X2 that is far from the central region X1. It should be noted that if voids A are generated in the removed portion of the metal interconnect layer 110 during the above-mentioned edge bevel removal process, the voids A will be filled with a dielectric layer during subsequent process steps, thereby reducing or even avoiding adverse effects of the voids A on subsequent process steps.

[0068] Continuing to refer to Figure 2 , in one embodiment, after forming the first dielectric layer 112a filled with a metal material, the method for manufacturing a semiconductor structure further includes: performing electroplated copper edge bevel removal on the first dielectric layer 112a to remove a portion of the first dielectric layer 112a in the edge region X2 that is far from the central region X1. Correspondingly, after forming the second dielectric layer 112c filled with a metal material, the method for manufacturing a semiconductor structure further includes: performing electroplated copper edge bevel removal on the second dielectric layer 112c to remove a portion of the second dielectric layer 112c in the edge region X2 that is far from the central region X1, so that the sidewall of the second dielectric layer 112c is flush with the sidewall of the first dielectric layer 112a.

[0069] In one embodiment, after forming an interlayer dielectric structure and a metal interconnect layer, the method for manufacturing a semiconductor structure further includes: performing a wafer edge trimming process on the first wafer to remove defects or structural abnormalities at the edge of the first wafer.

[0070] Refer to Figure 3 , in one embodiment, the thickness range of the dielectric layer 120 is 1 kÅ to 5 kÅ to ensure that the voids A in the metal interconnect layer 110 are filled. Optionally, the dielectric layer 120 is formed by a high-density plasma chemical vapor deposition process (HDPCVD). In other embodiments of the present application, the thickness setting and the selection of the preparation process of the dielectric layer 120 can be adjusted according to the size of the voids A in the semiconductor structure and other process requirements during actual process steps, as long as it is ensured that the dielectric layer 120 can fill the voids A, and the present application does not limit this.

[0071] Refer to Figure 4 , in one embodiment, the thickness range of the barrier layer 130 is 0.5 kÅ to 2 kÅ to ensure the effect of the barrier layer 130 in preventing metal diffusion. At the same time, the barrier layer 130 formed on the sidewall of the dielectric layer 120 can also enhance the strength of the portion of the metal interconnect layer 110 that is far from the central region X1, reducing or avoiding the risk of edge cracking during subsequent process steps.

[0072] In one embodiment, after performing a planarization process to expose the surface of the metal interconnect layer and before performing a hybrid bonding process on the first wafer, the method for manufacturing a semiconductor structure further includes: performing a planarization process on the metal interconnect layer to further improve the surface flatness of the metal interconnect layer, so as to perform a subsequent hybrid bonding process and improve the bonding effect.

[0073] Referring to Figure 6 , in one embodiment, the process of the hybrid bonding process includes: providing a second wafer 200, on the front surface of which a metal wiring layer 210 is formed; bonding the front surface of the first wafer 100 and the front surface of the second wafer 200, so that the projection of the metal interconnect layer 110 along the direction perpendicular to the surface of the second wafer 200 (i.e., the Y direction) coincides with the projection of the metal wiring layer 210 along the direction perpendicular to the surface of the second wafer 200, so that the metal wiring layer 210 and the metal interconnect layer 110 are connected; performing an annealing process (Bond Anneal) to improve the effect of the hybrid bonding.

[0074] Wherein, the first wafer 100 and the second wafer 200 are respectively one of a logic wafer and a pixel wafer, and the types of the first wafer 100 and the second wafer 200 are different. That is, the first wafer 100 is a logic wafer and the second wafer 200 is a pixel wafer, or the first wafer 100 is a pixel wafer and the second wafer 200 is a logic wafer.

[0075] In one embodiment, after performing the hybrid bonding, the method for manufacturing a semiconductor structure further includes: performing defect detection on the semiconductor structure obtained after the hybrid bonding to improve the product yield. Optionally, the defect detection includes checking whether there are bonding bubbles in the semiconductor structure after the hybrid bonding.

[0076] Correspondingly, continue to refer to Figure 6 , the present application also provides a semiconductor structure prepared by using the method for manufacturing a semiconductor structure as described above. The semiconductor structure prepared by using the method for manufacturing a semiconductor structure provided by the present application realizes the interconnection of the metal interconnect layer of the first wafer and the metal wiring layer of the second wafer, while maintaining the product yield and reducing or avoiding the problems of poor edge bonding during the preparation process and edge cracking in the subsequent process.

[0077] An unexpected effect of the present application is that by forming a dielectric layer that fills the voids, the risk of crystal edge cracking in subsequent processes is reduced or avoided; by forming a barrier layer that covers the surface and sidewalls of the metal interconnection layer, the risk of metal diffusion in the metal interconnection layer is reduced or avoided, and at the same time, the risk of chipping or crystal edge cracking of the first wafer is reduced or avoided, thereby helping to improve the yield of the wafer.

[0078] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0079] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0080] The above-described embodiments only represent several implementation manners of the present application, and the descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, Including: Providing a first wafer, the first wafer including a central region and an edge region, the edge region being located around the central region, a metal interconnect layer being formed on the surface of the first wafer, and a portion of the metal interconnect layer located within the edge region having voids; Forming a dielectric layer on the metal interconnect layer, the dielectric layer at least filling the voids; Forming a barrier layer on the dielectric layer, the barrier layer extending to cover the surface and sidewalls of the metal interconnect layer; Performing a planarization process to expose the surface of the metal interconnect layer; Performing a hybrid bonding process on the first wafer.

2. The manufacturing method of the semiconductor structure according to claim 1, wherein, The steps before forming the dielectric layer on the metal interconnect layer further include: Removing a portion of the metal interconnect layer in the edge region that is far from the central region; Forming a bonding layer on the metal interconnect layer; Removing a portion of the bonding layer in the edge region that is far from the central region.

3. The manufacturing method of the semiconductor structure according to claim 2, characterized in that, Along the radial direction of the first wafer, the width of the removed portion of the metal interconnect layer is greater than the width of the removed portion of the bonding layer.

4. The manufacturing method of the semiconductor structure according to claim 1 or 2, characterized in that, The metal interconnect layer includes an interlayer dielectric structure formed on the first wafer and trenches and vias formed in the interlayer dielectric structure, and a metal material is electroplated in the trenches and the vias.

5. The manufacturing method of the semiconductor structure according to claim 4, characterized in that, The formation process of the interlayer dielectric structure includes: Forming a first dielectric layer on the first wafer; Performing a planarization process on the first dielectric layer to remove at most a portion of the first dielectric layer; Forming a dielectric barrier layer on the first dielectric layer; Forming a second dielectric layer on the dielectric barrier layer to form the interlayer dielectric structure including the first dielectric layer, the dielectric barrier layer, and the second dielectric layer.

6. The manufacturing method of the semiconductor structure according to claim 5, characterized in that, During the process of performing the planarization process on the first dielectric layer, the thickness range of the thinned first dielectric layer includes 5 kÅ to 20 kÅ, and the remaining thickness range of the first dielectric layer after the planarization process is greater than zero and less than or equal to 3 kÅ.

7. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The hybrid bonding process includes: Providing a second wafer, a metal wiring layer being formed on the front surface of the second wafer; Bonding the front surface of the first wafer and the front surface of the second wafer, so that the projection of the metal interconnect layer in the direction perpendicular to the surface of the second wafer coincides with the projection of the metal wiring layer in the direction perpendicular to the surface of the second wafer, so that the metal wiring layer and the metal interconnect layer are connected; Performing an annealing process; Wherein, the first wafer and the second wafer are respectively one of a logic wafer and a pixel wafer, and the types of the first wafer and the second wafer are different.

8. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, After completing the hybrid bonding process, the manufacturing method of the semiconductor structure further includes: Performing defect detection on the semiconductor structure obtained after hybrid bonding.

9. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The thickness range of the dielectric layer is 1 kÅ to 5 kÅ, and the thickness range of the barrier layer is 0.5 kÅ to 2 kÅ.

10. A semiconductor structure, characterized in that, Prepared by using the manufacturing method of the semiconductor structure according to any one of claims 1 to 9.

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