Integrated circuit chip and manufacturing method thereof

Abstract

An integrated circuit chip includes a first memory cell array, a second memory cell array, a first set of bit lines, and a second set of bit lines. The first memory cell array has a first width in a first direction and a first height in a second direction. The second memory cell array has a second width in the first direction and a first height in the second direction. The first group of bit lines extends in a first direction, is connected to the first memory cell array, overlaps the first memory cell array, and is located on the first metal layer. The second group of bit lines extends in the first direction, is connected to the second memory cell array, overlaps the second memory cell array, and is on the first metal layer. At least the first width is different from the second width, or the first height is different from the second height. The embodiment of the invention further discloses a manufacturing method of the integrated circuit chip.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to integrated circuit chips and methods of manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of digital devices to solve problems in many different fields. Some of these digital devices, such as memory macros, are configured to store data. As ICs become smaller and more complex, the wire resistance within these digital devices also changes, affecting the operating voltage of these digital devices and the overall IC performance. Summary of the Invention

[0003] An embodiment of the present invention provides an integrated circuit chip, comprising: a first memory cell array having a first width in a first direction and a second height in a second direction different from the first direction; a second memory cell array having a second width in the first direction and a second height in the second direction; a first set of bit lines extending in the first direction, connected to the first memory cell array, overlapping the first memory cell array, and located on a first metal layer that is above the front side of a substrate; and a second set of bit lines extending in the first direction, connected to the second memory cell array, overlapping the second memory cell array, and located on the first metal layer, wherein at least the first width is different from the second width, or the first height is different from the second height.

[0004] Another embodiment of the present invention provides an integrated circuit chip, comprising: a first memory cell array having a first width in a first direction and a first height in a second direction different from the first direction, each memory cell in the first memory cell array comprising a first number of transistors; a second memory cell array having a second width in the first direction and a second height in the second direction, each memory cell in the second memory cell array comprising a second number of transistors greater than the first number of transistors; a first set of word lines extending in the second direction, connected to the first memory cell array, overlapping the first memory cell array, and located on a first metal layer that is above the front side of a substrate; and a second set of word lines extending in the second direction, connected to the second memory cell array, overlapping the second memory cell array, and located on the first metal layer, wherein at least the first width is different from the second width, or the first height is different from the second height.

[0005] Another embodiment of the present invention provides a method of manufacturing an integrated circuit chip, the method comprising: manufacturing a first set of memory cells in a first memory cell array, the first memory cell array having a first width in a first direction and a second height in a second direction different from the first direction, each memory cell in the first memory cell array including a first set of transistors on a front side of a substrate, wherein the first set of transistors includes a first number of transistors; manufacturing a second set of memory cells in a second memory cell array, the second memory cell array having a second width in the first direction and a second height in the second direction, each memory cell of the second memory cell array including a second set of transistors on the front side of the substrate, the second set of transistors including a second number of transistors; manufacturing a first set of vias (VD) and a second set of vias (VG) on the front side of the substrate, the first set of vias and the second set of vias being electrically connected to at least the first set of transistors or the second set of transistors; depositing a first conductive material on a first metal layer (M1) on the front side of the substrate to form a first set of word lines and a second set of word lines, the first set of word lines being electrically connected to the first set of transistors through the second set of vias and overlapping the first memory cell array and extending in the second direction, and the second set of word lines being electrically connected to the second set of transistors through the second set of vias and overlapping the second memory cell array and extending in the second direction; manufacturing a third set of vias (V1) on the front side of the substrate, the third set of vias being electrically connected to at least the first set of transistors or the second set of transistors; and depositing a second conductive material on a second metal layer (M2) on the front side of the substrate to form a first set of bit lines and a second set of bit lines, the first set of bit lines being electrically connected to the first set of transistors through the first set of vias and the third set of vias and overlapping the first memory cell array and extending in the first direction, and the second set of bit lines being electrically connected to the second set of transistors through the first set of vias and the third set of vias and overlapping the second memory cell array and extending in the first direction, the first metal layer being different from the second metal layer, wherein at least the first width is different from the second width, or the first height is different from the second height. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 is a block diagram of a memory circuit in accordance with some embodiments.

[0008] Figure 2A is a circuit diagram of a memory circuit according to some embodiments.

[0009] Figure 2B is a circuit diagram of a memory circuit according to some embodiments.

[0010] Figures 3A to 3B is according to some embodiments Figure 1 and Figures 2A to 2B corresponding circuit diagrams of the corresponding memory cells 300A and 300B available in

[0011] Figures 4A to 4C are corresponding schematic diagrams of the corresponding memory circuits 400A to 400C according to some embodiments.

[0012] Figure 5A is a corresponding schematic diagram of the corresponding memory circuit 500A according to some embodiments.

[0013] Figure 5B is a corresponding schematic diagram of the corresponding memory circuit 500B according to some embodiments.

[0014] Figure 5C is a cross-sectional view of the integrated circuit intersecting the plane A-A'.

[0015] Figure 5D is a cross-sectional view of the integrated circuit intersecting the plane B-B'.

[0016] Figure 5E is a cross-sectional view of the integrated circuit intersecting the plane C-C'.

[0017] Figure 5F is a cross-sectional view of the integrated circuit intersecting the plane D-D'.

[0018] Figure 6 is a corresponding schematic diagram of the corresponding memory circuit 600 according to some embodiments.

[0019] Figures 7A to 7B are corresponding schematic diagrams of the corresponding memory circuits 700A to 700B according to some embodiments.

[0020] Figure 8 is a corresponding schematic diagram of the corresponding memory circuit according to some embodiments.

[0021] Figure 9 is a corresponding schematic diagram of the corresponding memory circuit according to some embodiments.

[0022] Figure 10 is a schematic diagram of a memory circuit according to some embodiments.

[0023] Figure 11Schematic diagram of a memory circuit according to some embodiments.

[0024] Figure 12 Schematic diagram of a memory circuit according to some embodiments.

[0025] Figure 13 Schematic diagram of a memory circuit according to some embodiments.

[0026] Figure 14 Schematic diagram of a memory circuit according to some embodiments.

[0027] Figure 15 Functional flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0028] Figure 16 Flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0029] Figure 17 Flowchart of a method for generating a layout design of an integrated circuit according to some embodiments.

[0030] Figure 18 Schematic diagram of a system for designing an IC layout design and manufacturing an IC circuit according to some embodiments.

[0031] Figure 19 Block diagram of an IC manufacturing system and its related IC manufacturing process according to at least one embodiment of the present disclosure. Detailed Description

[0032] The present invention provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming the first component above or on the second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0033] Moreover, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component shown in the figures to another (or other) element or component. Except for the orientation shown in the figures, the spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0034] According to some embodiments, an integrated circuit chip includes a first memory cell array. In some embodiments, the first memory cell array has a first width in a first direction and a first height in a second direction. In some embodiments, the second direction is different from the first direction.

[0035] In some embodiments, the integrated circuit chip further includes a second memory cell array. In some embodiments, the second memory cell array has a second width in the first direction and a second height in the second direction.

[0036] In some embodiments, the integrated circuit chip further includes a first set of bit lines extending in the first direction. In some embodiments, the first set of bit lines is connected to the first memory cell array. In some embodiments, the first set of bit lines overlaps with the first memory cell array.

[0037] In some embodiments, the first set of bit lines is located on at least a first metal layer above the front side of the substrate.

[0038] In some embodiments, the integrated circuit chip further includes a second set of bit lines extending in the first direction. In some embodiments, the second set of bit lines is connected to the second memory cell array. In some embodiments, the second set of bit lines overlaps with the second memory cell array. In some embodiments, the second set of bit lines is on at least the first metal layer.

[0039] In some embodiments, at least the first width is different from the second width, or the first height is different from the second height.

[0040] In some embodiments, the integrated circuit chip further includes a first set of word lines extending in the second direction. In some embodiments, the first set of word lines extends in the second direction. In some embodiments, the first set of word lines is connected to the first memory cell array. In some embodiments, the first set of word lines overlaps with the first memory cell array. In some embodiments, the first set of word lines is located on at least a second metal layer. In some embodiments, the second metal layer is different from the first metal layer.

[0041] In some embodiments, the integrated circuit chip further includes a second set of word lines extending in the second direction.

[0042] In some embodiments, the second set of word lines extends in a second direction. In some embodiments, the second set of word lines is connected to the second memory cell array. In some embodiments, the second set of word lines overlaps with the second memory cell array. In some embodiments, the second set of word lines is on at least a second metal layer.

[0043] In some embodiments, at least the first width is different from the second width, or the first height is different from the second height. In some embodiments, because at least the first width is different from the second width, or the first height is different from the second height, the first memory cell array and the second memory cell array have different corresponding electrical characteristics.

[0044] In some embodiments, an integrated circuit chip including a first memory cell array and a second memory cell array having different corresponding electrical characteristics enables the integrated circuit chip to have a more flexible design than other methods with the same type of cells having the same type of electrical characteristics, thereby improving performance compared to other methods.

[0045] In some embodiments, the different corresponding electrical characteristics include one or more of the resistance / capacitance of a first set of bit lines, the resistance / capacitance of a second set of bit lines, the resistance / capacitance of a first set of word lines, and the resistance / capacitance of a second set of word lines.

[0046] Figure 1 is a block diagram of a memory circuit 100 according to some embodiments.

[0047] For ease of illustration, Figure 1 is simplified. In some embodiments, the memory circuit 100 includes various elements other than those Figure 1 shown, or is arranged to perform the operations discussed below.

[0048] The memory circuit 100 is an IC including memory partitions 102A to 102D, a global control circuit 100GC, and a global input / output (GIO) circuit 100BL.

[0049] Each of the memory partitions 102A to 102D includes banks 110U and 110L adjacent to word line (WL) driver circuits 110AC and local control circuits 110LC. Each of the banks 110U and 110L includes a memory cell array 110AR and a local input / output (LIO) circuit 110BS.

[0050] A memory partition, such as memory partitions 102A to 102D, is a portion of the memory circuit 100 that includes a subset of memory devices ( Figure 1 not shown in ) and adjacent circuits configured to selectively access the subset of memory devices during programming and read operations. In Figure 1In an embodiment, the memory circuit 100 includes a total of four partitions. In some embodiments, the memory circuit 100 includes a total number of partitions greater than or less than four.

[0051] The GIO circuit 100BL is configured to control access to one or more circuit paths (e.g., bit lines) and to each memory device of the corresponding banks 110U or 110L of each memory partition 102A to 102D, for example by generating one or more bit line signals. In some embodiments, the GIO circuit 100BL includes a global bit line driver circuit. In some embodiments, the GIO circuit 100BL is connected to each of the banks 110U and 110L via corresponding global bit lines (not shown).

[0052] The global control circuit 100GC is configured to control some or all of the programming and read operations for each of the memory partitions 102A to 102D, for example by generating and / or outputting one or more control and / or enable signals.

[0053] In some embodiments, the global control circuit 100GC includes one or more analog circuits configured to interface with the memory partitions 102A to 102D to program data in one or more memory devices and / or to use data received from one or more memory devices in one or more circuit operations. In some embodiments, the global control circuit 100GC includes one or more global address decoder or pre-decoder circuits configured to output one or more address signals to the WL driver circuits 110AC of each of the memory partitions 102A to 102D.

[0054] Each WL driver circuit 110AC is configured to generate a word line signal on a corresponding word line WL. In some embodiments, each WL driver circuit 110AC is configured to output a word line signal on the corresponding word line WL to the adjacent banks 110U and 110L of the corresponding memory partitions 102A to 102D.

[0055] Each local control circuit 110LC is an electronic circuit configured to receive one or more address signals. Each local control circuit 110LC is configured to generate signals corresponding to an adjacent subset of memory devices identified by the one or more address signals. In some embodiments, the adjacent subset of memory devices corresponds to a column of memory devices. In some embodiments, each local control circuit 110LC is configured to generate each signal as a complementary signal pair. In some embodiments, each local control circuit 110LC is configured to output the signals to corresponding word line driver circuits within the adjacent WL driver circuits 110AC of the corresponding memory partitions 102A to 102D. In some embodiments, the local control circuit 110LC includes a bank decoder circuit.

[0056] Each LIO circuit 110BS is configured to selectively access one or more bit lines of an adjacent subset of a memory device connected to a corresponding memory cell array 110AR in response to the GIO circuit 100BL, e.g., based on one or more BL control signals, as Figures 2A to 2B shown. In some embodiments, the adjacent subset of the memory device corresponds to a row of the memory device. In some embodiments, the LIO circuit 110BS includes a bit line selection circuit.

[0057] Each LIO circuit 110BS includes one or more circuits 114. For ease of illustration, the circuits 114 are not shown in the banks 110U and 110L of the memory partitions 102B, 102C, and 102D. In some embodiments, each circuit 114 includes at least a sense amplifier circuit. In some embodiments, during a read operation, the sense amplifier circuit is configured to read data from at least one memory cell 112 in a corresponding memory cell column in the corresponding memory cell array 110AR. In some embodiments, each circuit 114 in the LIO circuit 110BS is connected to a column of a corresponding memory device 112 in the memory cell array 110AR.

[0058] Each bank 110U and 110L includes a corresponding memory cell array 110AR that includes memory cells or memory devices 112 configured to be accessed by adjacent LIO circuits 110BS and adjacent WL driver circuits 110AC during programming and read operations.

[0059] Each memory cell array 110AR includes an array of memory devices 112 having N rows and M columns, where M and N are positive integers. The cell rows in the memory cell array 102 are arranged along a first direction X. The cell columns in the memory cell array 102 are arranged along a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array 110AR is divided into an upper region and a lower region (not shown). In some embodiments, each column of the memory devices 112 in the memory cell array 110AR is connected to a corresponding circuit 114 in the LIO circuit 110BS.

[0060] The memory devices 112 are shown in the banks 110U and 110L of the memory partition 102A. For ease of illustration, the memory devices 112 are not shown in the banks 110U and 110L of the memory partitions 102B, 102C, and 102D.

[0061] The storage device 112 is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by a logical state. At least one logical state of the storage device 112 can be programmed during a write operation and detected during a read operation. In some embodiments, the logical state corresponds to the voltage level of the charge stored in a given storage device 112. In some embodiments, the logical state corresponds to the physical properties of the components of a given storage device 112, such as voltage, current, resistance, or magnetic orientation.

[0062] In some embodiments, the storage device 112 includes one or more single-port (SP) static random access memory (SRAM) cells. In some embodiments, the storage device 112 includes one or more dual-port (DP) SRAM cells. In some embodiments, the storage device 112 includes one or more multi-port SRAM cells. Different types of storage cells in the storage device 112 are within the scope of this disclosure. In some embodiments, the storage device 112 includes one or more dynamic random access memory (DRAM) cells. In some embodiments, the storage device 112 includes one or more one-time programmable (OTP) storage devices, such as an electronic fuse (eFuse) or an antifuse device, a flash memory device, a random access memory (RAM) device, a resistive RAM device, a ferroelectric RAM device, a magnetoresistive RAM device, an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, etc. In some embodiments, the storage device 112 is an OTP storage device including one or more OTP storage cells.

[0063] Other configurations of the memory circuit 100 are also within the scope of this disclosure.

[0064] Figure 2A is a circuit diagram of a memory circuit 200A according to some embodiments.

[0065] The memory circuit 200A is Figure 1 an embodiment of the storage cell array 110AR of, and thus similar detailed descriptions are omitted.

[0066] Components identical or similar to those in Figures 1 to 19 one or more of are given the same reference numerals, and thus their detailed descriptions are omitted.

[0067] The memory circuit 200A includes a storage cell array 202 having M rows and N columns of storage cells MCB, where N is a positive integer corresponding to the number of columns in the storage cell array 201, and M is a positive integer corresponding to the number of rows in the storage cell array 202. The cell rows in the storage cell array 202 are arranged along a first direction X. The cell columns in the storage cell array 201 are arranged along a second direction Y.

[0068] In some embodiments, each memory cell MCB in the memory cell array 202 is configured to store bit data. In some embodiments, the memory circuit 200A is a logic-based memory.

[0069] The number of rows M in the memory cell array 202 is equal to or greater than 1. The number of columns N in the memory cell array 202 is equal to or greater than 1. Different types of memory cells MCB in the memory cell array 202 are within the scope contemplated by the present disclosure.

[0070] The memory circuit 200A further includes N bit lines BL[1],..., BL[N] (collectively referred to as "bit lines BL"). Each column 1,..., N in the memory cell array 202 overlaps and is connected to a corresponding one of the bit lines BL[1],..., BL[N]. Each bit line BL extends in the second direction Y and is above the cell columns (e.g., columns 1,..., N).

[0071] The memory circuit 200A further includes N anti-phase lines BLB[1],..., BLB[N] (collectively referred to as "anti-phase lines BLB"). Each column 1,..., N in the memory cell array 202 overlaps and is connected to a corresponding one of the anti-phase lines BLB[1],..., BLB[N]. Each anti-phase line BLB extends in the second direction Y and is above the cell columns (e.g., columns 1,..., N).

[0072] The memory circuit 200A further includes M word lines WL[1],..., WL[M] (collectively referred to as "word lines WL"). Each row 1,..., M in the memory cell array 202 overlaps and is connected to a corresponding one of the word lines WL[1],..., WL[M]. Each word line WL extends in the first direction X and is above the cell rows (e.g., rows 1,..., M).

[0073] The memory circuit 200A includes a region 201a. The region 201a includes 2 rows of memory cells MCB and 2 columns of memory cells MCB. The region 201a includes row 1 and row 2 of the memory circuit 200A, and column 1 and column 2 of the memory circuit 200A. Other numbers of rows or columns of the region 201a are also within the scope of the present disclosure. In some embodiments, the region 201a is located in other rows or columns of the memory circuit 200A.

[0074] Other configurations of the memory circuit 200A are also within the scope of the present disclosure. In some embodiments, one or more of the bit lines BL, anti-phase lines BLB, and word lines WL are not included in the memory circuit 200A. In some embodiments, one or more of the bit lines BL, anti-phase lines BLB, and word lines WL are replaced with corresponding source lines SL.

[0075] Figure 2BIt is a circuit diagram of a memory circuit 200B according to some embodiments.

[0076] The memory circuit 200B is Figure 2A a variant of the memory circuit 200A, and thus similar detailed descriptions are omitted. Compared with Figure 2A the memory circuit 200A, Figure 2A the word lines WL are Figure 2B replaced by the write word lines WWL, and thus similar detailed descriptions are omitted. Compared with Figure 2A the memory circuit 200A, Figure 2A the M word lines WL[1], … WL[M] are Figure 2B replaced by the corresponding M write word lines WWL[1], … WWL[M] (collectively referred to as “write word lines WWW”), and thus similar detailed descriptions are omitted.

[0077] Compared with Figure 2A the memory circuit 200A, the memory circuit 200B further includes N read bit lines RBL[1], … RBL[N] and M read word lines RWL[1],.. RWL[M], and thus similar detailed descriptions are omitted.

[0078] The memory circuit 200B is Figure 1 an embodiment of the memory cell array 110AR, and thus similar detailed descriptions are omitted.

[0079] The memory circuit 200A includes a memory cell array 202, bit lines BL, an inverting line BLB, and write word lines WWL.

[0080] The memory circuit 200B further includes N read bit lines RBL[1], … RBL[N] (collectively referred to as “read bit lines RBL”). Each column 1, …, N in the memory cell array 202 overlaps and is connected to the corresponding read bit lines RBL[1], …, RBL[N]. Each read bit line RBL extends in the second direction Y and is located above the cell columns (e.g., columns 1, …, N).

[0081] The memory circuit 200B further includes M read word lines read word lines RWL[1], … RWL[M] (collectively referred to as “read word lines RWL”). Each row 1, …, M in the memory cell array 202 overlaps and is connected to the corresponding read word lines RWL[1], …, RWL[M]. Each read word line RWL extends in the first direction X and is located above the cell rows (e.g., rows 1, …, M).

[0082] Memory circuit 200B includes region 201b. Region 201b includes two rows of memory cells MCB and two columns of memory cells MCB. Region 201b includes the first and second rows and the first and second columns of memory circuit 200B. Other numbers of rows or columns of region 201b are also within the scope of the present disclosure. In some embodiments, region 201b is located in other rows or columns of memory circuit 200B.

[0083] Other configurations of memory circuit 200B are also within the scope of the present disclosure. In some embodiments, one or more of bit line BL, anti-phase line BLB, read bit line RBL, write word line WWL, and read word line RWL are not included in memory circuit 200B. In some embodiments, one or more of bit line BL, anti-phase line BLB, read bit line RBL, write word line WWL, or read word line RWL are replaced with corresponding source line SL.

[0084] Figures 3A to 3B is according to some embodiments Figure 1 and Figures 2A to 2B corresponding circuit diagrams of the available corresponding memory cells 300A and 300B in

[0085] Figure 3A is according to some embodiments Figure 1 and Figures 2A to 2B circuit diagram of the available memory cell 300A in

[0086] At least one of memory cells 300A and 300B can be used as Figure 1 one or more memory cells MCB in at least one of the memory cell arrays 110AR of Figure 1 and the memory device 112 of

[0087] At least one of memory cells 300A or 300B can be used as Figure 2A one or more memory cells MCB in at least one of memory circuit 200A of Figure 2B and memory circuit 200B of

[0088] Memory cell 300A is a six-transistor (6T) single-port (SP) SRAM memory cell for illustration. In some embodiments, memory cell 300A employs more than six transistors. Other types of memories are within the scope of various embodiments.

[0089] The memory cell 300A includes two P-channel field-effect transistors (PFETs) P2-1 and P2-2, and four NFETs N2-1, N2-2, N2-3, and N2-4. The PFETs P2-1 and P2-2 and the NFETs N2-1 and N2-2 form a cross-latch or a cross-connected inverter pair. For example, the PFET P2-1 and the NFET N2-1 form a first inverter, while the PFET P21 and the NFET N2-2 form a second inverter.

[0090] The source terminal of each of the PFETs P2-1 and P2-2 is configured as a voltage supply node NODE_1. Each voltage supply node NODE_1 is connected to a first voltage supply VDDI.

[0091] The drain terminal of the PFET P2-1, the drain terminal of the NFET N2-1, the gate terminal of the PFET P21, the gate terminal of the NFET N2-2, and the source terminal of the NFET N2-3 are each connected together and configured as a storage node ND.

[0092] The drain terminal of the PFET P2-2, the drain terminal of the NFET N2-2, the gate terminal of the PFET P21, the gate terminal of the NFET N2-1, and the source terminal of the NFET N2-4 are each connected together and configured as a storage node NDB.

[0093] The source terminal of each of the NFETs N2-1 and N2-2 is configured as a power reference voltage node (not labeled) having a power reference voltage VSS. The source terminal of each of the NFETs N2-1 and N2-2 is also connected to a reference voltage source VSS.

[0094] The word line WL is connected to the gate terminal of each of the NFETs N2-3 and N2-4. The word line WL is also referred to as a write control line because the NFETs N2-3 and N2-4 are configured to be controlled by a signal on the word line WL to transfer data between the bit lines BL, BLB, and the corresponding nodes ND, NDB.

[0095] The drain terminal of the NFET N2-3 is connected to the bit line BL. The drain terminal of the NFET N2-4 is connected to the bit line BLB.

[0096] The bit line BL and the complementary bit line BLB are configured for data input and output of the memory cell 200A. In some embodiments, in a write operation, a logical value is applied to the bit line BL and an opposite logical value is applied to the complementary bit line BLB, and the logical values on the bit line and the complementary bit line can be written into the memory cell 200A. Each of the bit line BL and the complementary bit line BLB is referred to as a data line because the data carried on the bit line BL and the complementary bit line BLB is written to and read from the corresponding nodes ND and NDB.

[0097] Other configurations of the memory cell 300A are also within the scope of the present disclosure.

[0098] Figure 3B is according to some embodiments Figure 1 and Figures 2A to 2B the circuit diagram of the memory cell 300B available in

[0099] The memory cell 300B is Figure 3A a variant of the memory cell 300A, and thus similar detailed descriptions are omitted. Compared with Figure 3A the memory cell 300A, the memory cell 300B further includes NFET transistors N2-5 and N2-6, and thus similar detailed descriptions are omitted.

[0100] The memory cell 300B is an eight-transistor (8T) single read / single write (1R / 1W) dual-port (2P) SRAM memory cell for illustration. In some embodiments, the memory cell 300B employs a plurality of transistors other than eight. Other types of memory cells are within the scope of various embodiments.

[0101] Compared with Figure 3A the memory cell 300A, the complementary word line WLB replaces the word line WL, and thus similar detailed descriptions are omitted.

[0102] The memory cell 300B includes PFET transistors P2-1 and P2-2, and NFET transistors N2-1, N2-2, N2-3, N2-4, N2-5 and N2-6.

[0103] Each of the drain terminal of the PFET transistor P2-1, the drain terminal of the NFET transistor N2-1, the gate terminal of the PFET transistor P2-2, the gate terminal of the NFET transistor N2-2, the source terminal of the NFET transistor N2-4 and the gate terminal of the NFET transistor N2-5 are connected together and configured as the storage node ND.

[0104] The drain terminal of PFET transistor P2-2, the drain terminal of NFET transistor N2-2, the gate terminal of PFET transistor P21, the gate terminal of NFET transistor N2-1, and the source terminal of NFET transistor N2-3 are each connected together and configured as a storage node NDB.

[0105] The drain terminal of NFET transistor N2-3 is connected to the write bit line WBL. The drain terminal of NFET transistor N2-4 is connected to the inverted write bit line WBLB.

[0106] The source terminal of NFET transistor N2-5 is configured as a power reference voltage node (not labeled) having a power reference voltage VSS. The source terminal of NFET transistor N2-5 is also connected to the reference voltage source VSS.

[0107] Each of the drain terminal of NFET transistor N2-5 and the source terminal of NFET transistor N2-6 are connected together.

[0108] The drain terminal of NFET transistor N2-6 is connected to the read bit line RBL.

[0109] The write word line WWL is connected to the gate terminal of each of NFET transistors N2-3 and N2-4. The write word line WWL is also referred to as a write control line because NFET transistors N2-3 and N2-4 are configured to be controlled by a signal on the write word line WWL to transfer data between the write bit lines WBL, WBLB, and the corresponding nodes ND, NDB.

[0110] The read word line RWL is connected to the gate terminal of NFET transistor N2-6. The read word line RWL is also referred to as a read control line because NFET transistor N2-6 is configured to be controlled by a signal on the read word line to transfer data to the read bit line RBL.

[0111] In some embodiments, NFET transistor N2-5 is referred to as a read pull-down (RPD) transistor. In some embodiments, NFET transistor N2-6 is referred to as a read pass gate (RPG) transistor.

[0112] Other configurations of the memory cell 300B are also within the scope of the present disclosure.

[0113] Figures 4A to 4C are corresponding schematic diagrams of corresponding memory circuits 400A to 400C according to some embodiments.

[0114] Figure 4A is a schematic diagram of a memory circuit 400A according to some embodiments.

[0115] The memory circuit 400A relates to Figure 2AThe memory cell array 202. The memory circuit 400A is Figure 2A An embodiment of the region 201a of the memory circuit 200A, so similar detailed descriptions are omitted. In some embodiments, the memory circuit 400A is other than Figure 2A The region 201a of the memory circuit 200A.

[0116] The memory circuit 400A includes a memory cell array 401. The memory circuit 400A is a schematic diagram of two adjacent columns and two adjacent rows of the memory cell array 401. In some embodiments, the memory circuit 400 is Figure 2A Columns 1 and 2 of the memory cell array 202 and Figure 2A Rows 1 and 2 of the memory cell array 202, so similar detailed descriptions are omitted. In some embodiments, the memory circuit 400 is Figure 2A A schematic diagram of other columns or other rows of the memory cell array 202, rather than Figure 2A Columns 1 and 2 or rows 1 and 2 in the memory cell array 202, so similar detailed descriptions are omitted.

[0117] The memory circuits 400A to 400C are manufactured by a corresponding layout design similar to that of the memory circuits 400A to 400C. For the sake of brevity, Figure 4A 、 Figure 4B 、 Figure 4C 、 Figures 5A to 5B 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 and Figure 15 Are described as the corresponding integrated circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400 and 1500, but in some embodiments, Figure 4A 、 Figure 4B 、 Figure 4C 、Figure 5, Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 and Figure 15Each of them is also a corresponding layout design, and each structural element in integrated circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, and 1500 is a corresponding layout pattern. The structural relationships including alignment, length, and width, as well as the configuration and layers, of the corresponding layout designs of integrated circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, and 1500 are similar to the structural relationships, configuration, and layers of integrated circuits 400A, 400B, 400C, 500A to 500B, 600, 700, 700B, 800, 90, 1000, 110, 1200, 1300, 1400, and 1500. For the sake of brevity, similar detailed descriptions will not be repeated.

[0118] The memory cell array 401 is similar to Figure 2A the memory cell array 202 of, and thus similar detailed descriptions are omitted.

[0119] The memory cell array 401 includes memory cells 401a, 401b, 401c, and 401d.

[0120] The memory cell 401a is located at row 1 and column 1 of the memory cell array 401 and is identified as "r1c1" in Figure 4A . The memory cell 401b is located at row 1 and column 2 of the memory cell array 401 and is labeled as "r1c2" in the appendix Figure 4A . The memory cell 401c is located at row 2 and column 1 of the memory cell array 401 and is identified as "r2c1" in the appendix Figure 4A . The memory cell 401d is located at row 2 and column 2 of the memory cell array 401 and is identified as "r2c2" in Figure 4A .

[0121] The memory cell array 401 is shown as a 2×2 memory cell array in Figure 4A . Other numbers of rows and columns are also within the scope of the present disclosure.

[0122] The memory cell array 401 has a height H1a in the first direction X. In some embodiments, the height H1a is equal to 2CH, where CH is the scaled cell height in the first direction X of at least one of the memory cells 401a, 401b, 401c, and 401d in the memory cell array 401. In some embodiments, the cell height of the memory cells in one of the memory cell arrays 401, 411, 421, 701, or 721 or the memory circuits 500A to 500B, 600, 800, or 900 is scaled with respect to the corresponding cell height of the memory cells in another of the memory cell arrays 401, 411, 421, 701, or 721 or the memory circuits 500A to 500B, 600, 800, or 900 (e.g., the scaled cell height).

[0123] The memory cell array 401 has a width W1a in the second direction Y. In some embodiments, the width W1a is equal to 2CW, where CW is the scaled cell width in the second direction Y of at least one of the memory cells 401a, 401b, 401c, and 401d in the memory cell array 402. In some embodiments, the cell width of the memory cells in one of the memory cell arrays 401, 411, 421, 701, or 721 or the memory circuits 500A to 500B, 600, 800, or 900 is scaled with respect to the corresponding cell width of the memory cells in another of the memory cell arrays 401, 411, 421, 701, or 721 or the memory circuits 500A to 500B, 600, 800, or 900 (e.g., the scaled cell width).

[0124] In some embodiments, the width of the memory cell array 401 in the second direction Y is equal to 2 contacted polysilicon pitches (e.g., 2CPP).

[0125] In some embodiments, the memory cell array 401 has an aspect ratio AR1a equal to 1:1 (e.g., W1a / H1a).

[0126] The memory circuit 400A further includes bit lines BL[1] and BL[2] (collectively referred to as the "bit line BL group"), anti-phase lines BLB[1] and BLB[2] (collectively referred to as the anti-phase line group BLB), and word lines WL[1] and WL[2] (collectively referred to as the "word line group WL").

[0127] In some embodiments, the memory cells 401a, 401b, 401c, and 401d are similar to Figure 2A the corresponding memory cells MCB in the same corresponding rows and the same corresponding columns of the region 201a, and thus the similar detailed description is omitted. In some embodiments, each of the memory cells 401a, 401b, 401c, and 401d isFigure 3A storage cell 300A, and thus a similar detailed description is omitted.

[0128] In some embodiments, bit lines BL[1] and BL[2] are similar to Figure 2A corresponding bit lines BL[1] and BL[2], and thus a similar detailed description is omitted.

[0129] In some embodiments, anti-phase bit lines BLB[1] and BLB[2] are similar to Figure 2A corresponding anti-phase bit lines BL2[1] and BLB[2], and thus a similar detailed description is omitted.

[0130] In some embodiments, word lines WL[1] and WL[2] are similar to Figure 2A corresponding word lines WL[1] and WL[2], and thus a similar detailed description is omitted.

[0131] The group of bit lines BL and the group of anti-phase bit lines BLB extend in the second direction Y.

[0132] Bit line BL[1] and anti-phase bit line BLB[1] overlap with storage cells 401a and 401c. Bit line BL[1] is electrically connected to storage cells 401a and 401c through vias 404a. Anti-phase bit line BLB[1] is electrically connected to storage cell 401a through via 404b and to storage cell 401c through via 404e.

[0133] Bit line BL[2] and anti-phase bit line BLB[2] overlap with storage cells 401b and 401d. Bit line BL[2] is electrically connected to storage cells 401b and 401d through vias 404d. Anti-phase bit line BLB[2] is electrically connected to storage cell 401b through via 404c and to storage cell 401d through via 404f.

[0134] In some embodiments, the group of bit lines BL is in the metal 2 (M2) layer of at least one of memory circuits 400A, 400B, 400C, 700A, and 700B. In some embodiments, the group of bit lines BL is in the metal 1 (M1) layer of at least one of memory circuits 400A, 400B, 400C, 700A, or 700B. Other metal layers for the group of bit lines BL are also within the scope of the present disclosure.

[0135] In some embodiments, the anti-phase line group BLB is located in the M2 layer of at least one of the memory circuits 400A, 400B, 400C, 700A, and 700B. In some embodiments, the group of anti-phase lines BLB is located in the M1 layer of at least one of the memory circuits 400A, 400B, 400C, 700A, and 700B. Other metal layers for the group of anti-phase lines BLB are also within the scope of the present disclosure.

[0136] Other configurations of the bit line group BL, arrangements on other metal layers, or the number of bit lines are all within the scope of the present disclosure.

[0137] Other configurations of the anti-phase line group BLB, arrangements on other metal layers, or the number of anti-phase lines are all within the scope of the present disclosure.

[0138] The word line group WL extends along the first direction X.

[0139] The word line WL[1] overlaps with the memory cells 401a and 401b. The word line WL[1] is electrically connected to the memory cell 401a through vias 402a and 402b. The word line WL[1] is electrically connected to the memory cell 401b through vias 401b and 402c.

[0140] The word line WL[2] overlaps with the memory cells 401c and 401d. The word line WL[2] is electrically connected to the memory cell 401c through vias 402d and 402e. The word line WL[2] is electrically connected to the memory cell 401d through vias 402e and 402f.

[0141] In some embodiments, the word line group WL is located in the M1 layer of at least one of the memory circuits 400A, 400B, 400C, 700A, and 700B. In some embodiments, the word line group WL is located in the metal 0 (M0) layer of at least one of the memory circuits 400A, 400B, 400C, 700A, and 700B. In some embodiments, the word line group WL is located in the M2 layer of at least one of the memory circuits 400A, 400B, 400C, 700A, and 700B. Other metal layers for the word line group WL are also within the scope of the present disclosure.

[0142] In some embodiments, the word line group WL is located in the polysilicon (POLY) layer of at least one of the memory circuits 400A, 400B, 400C, 700A, and 700B.

[0143] In some embodiments, the POLY layer is located below the M0 layer and the M1 layer. In some embodiments, the M0 layer is located below the M1 layer and the M2 layer. In some embodiments, the M1 layer is located below the M2 layer. In some embodiments, the terms "layer" and "level" may be used interchangeably.

[0144] Other configurations of the word line group WL, arrangements on other metal layers, or the number of word lines are within the scope of the present disclosure.

[0145] The memory circuit 400A further includes one or more of vias 402a, 402b, 402c, 402d, 402e, and 402f (collectively referred to as "via group 402").

[0146] In some embodiments, the via group 402 is fabricated by a corresponding via pattern group (not shown) of the corresponding layout design of the memory circuits 400A to 400C or 700A to 700B. In some embodiments, the vias 402a, 402b, 402c, 402d of the via group 402 are fabricated by corresponding via patterns (not shown) of the corresponding via pattern group (not shown) of the corresponding layout design of the memory circuits 400A to 400C or 700A to 700B.

[0147] The via group 402 is located below the word line group WL and the memory cell array 401 (e.g., as shown in FIGS. 5, Figure 6 , Figure 8 or Figure 9 ). In some embodiments, the via group 402 is located between the word line group WL and at least one of the memory cells 401a, 401b, 401c, or 401d of the memory cell array 401.

[0148] In some embodiments, vias 402a and 402b are located between the word line WL[1] and the memory cell 401a. In some embodiments, vias 402b and 402c are located between the word line WL[1] and the memory cell 401b.

[0149] In some embodiments, vias 402d and 402e are located between the word line WL[2] and the memory cell 401c. In some embodiments, vias 402e and 402f are located between the word line WL[2] and the memory cell 401d.

[0150] The via group 402 is located in one or more of the diffusion upper via (VD) layer, gate upper via (VG) layer, M0 upper via (V0) layer, or M1 upper via (V1) layer of the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, or 900.

[0151] In some embodiments, the VD layer is higher than at least one of the oxide diffusion (OD) layer, the POLY layer, and the metal diffusion (MD) layer. In some embodiments, the VG layer is higher than at least one of the OD layer, the POLY layer, and the MD layer. In some embodiments, the V0 layer is higher than at least one of the OD layer, the POLY layer, the MD layer, or the M0 layer. In some embodiments, the V1 layer is higher than at least one of the OD layer, the POLY layer, the MD layer, the M0 layer, and the M1 layer.

[0152] In some embodiments, the VD layer is lower than at least one of the M0 layer, the M1 layer, and the M2 layer. In some embodiments, the VG layer is lower than at least one of the M0 layer, the M1 layer, and the M2 layer. In some embodiments, the V0 layer is lower than at least one of the M1 layer and the M2 layer. In some embodiments, the V1 layer is at least lower than the M2 layer. Other layers are also within the scope of the present disclosure.

[0153] At least other configurations of the group of vias 402, arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0154] The memory circuit 400A further includes one or more of vias 404a, 404b, 404c, 404d, 404e, and 404f (collectively referred to as "via group 404").

[0155] In some embodiments, the via group 404 is fabricated by a corresponding via pattern group (not shown) of the corresponding layout designs of the memory circuits 400A to 400C or 700A to 700B. In some embodiments, the vias 404a, 404b, 404c, 404d of the via group 404 are fabricated by corresponding via patterns (not shown) of the corresponding via pattern group (not shown) of the corresponding layout designs of the memory circuits 400A to 400C or 700A to 700B.

[0156] The via group 404 is located between at least one of the bit line group BL and the anti-phase line group BLB and the lower layer of the memory cell array 401 (e.g., as shown in FIG. 5, Figure 6 、 Figure 8 or Figure 9 ). In some embodiments, the via group 404 is located between at least one of the group of bit lines BL and the group of anti-phase lines BLB and at least one of the memory cells 401a, 401b, 401c, or 401d of the memory cell array 401.

[0157] In some embodiments, the via 404a is located between the bit line BL[1] and the memory cells 401a and 401c.

[0158] In some embodiments, via 404b is located between the anti-phase line BLB[1] and the memory cell 401a, and via 404e is located between the anti-phase line BLB[1] and the memory cell 401c.

[0159] In some embodiments, via 404d is located between the bit line BL[2] and the memory cells 401b and 401d.

[0160] In some embodiments, via 404c is located between the anti-phase line BLB[2] and the memory cell 401b, and via 404f is located between the anti-phase line BLB[2] and the memory cell 401d.

[0161] This group of vias 404 is located in one or more of the VD layer, VG layer, V0 layer, and V1 layer of the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, or 900. In some embodiments, the V1 layer is higher than at least one of the OD layer, POLY layer, MD layer, M0 layer, and M1 layer.

[0162] In some embodiments, the V1 layer is lower than the M2 layer.

[0163] The other layers of at least one of this group of vias 402 and 404 are within the scope of the present disclosure.

[0164] At least other configurations of the via group 404, the arrangement of other layers, or the number of vias are within the scope of the present disclosure.

[0165] Other configurations of the memory circuit 400A are also within the scope of the present disclosure.

[0166] Figure 4B is a schematic diagram of a memory circuit 400B according to some embodiments.

[0167] The memory circuit 400B relates to Figure 2A the memory cell array 202. The memory circuit 400B is Figure 2A an embodiment of the region 201a of the memory circuit 200A, so similar detailed descriptions are omitted. In some embodiments, the memory circuit 400B is an embodiment of a region of the memory circuit 200A other than Figure 2A the region 201a of the memory circuit 200A.

[0168] The memory circuit 400B is Figure 4A a variant of the memory circuit 400A, so similar detailed descriptions are omitted. Compared with the Figure 4A memory circuit 400A, Figure 4B the memory cell array 411 replaces the Figure 4AThe memory cell array 401 is thus omitted from a similar detailed description.

[0169] The memory circuit 400B includes a memory cell array 411. The memory cell array 411 is similar to Figure 2A the memory cell array 202 or Figure 4A the memory cell array 401, and thus a similar detailed description is omitted.

[0170] The memory cell array 411 includes memory cells 411a, 411b, 411c, and 411d. In some embodiments, at least one of the memory cells 411a, 411b, 411c, and 411d is similar to Figure 4A one of the memory cells 401a, 401b, 401c, and 401d of the memory cell array 401, and thus a similar detailed description is omitted.

[0171] The memory cell 411a is located at row 1 and column 1 of the memory cell array 411 and is identified as "r1c1" in Figure 4B . The memory cell 411b is located at row 1 and column 2 of the memory cell array 411 and is labeled as "r1c2" in FIG. 4B. The memory cell 411c is located at row 2 and column 1 of the memory cell array 411 and is identified as "r2c1" in Chart 4B. The memory cell 411d is located at row 2 and column 2 of the memory cell array 411 and is identified as "r2c2" in Figure 4B .

[0172] The memory cell array 411 is shown as a 2×2 memory cell array in Figure 4B . Other numbers of rows and columns are also within the scope of the present disclosure.

[0173] The memory cell array 411 has a height H1b in the first direction X. In some embodiments, the height H1b is equal to 1CH, where 0.5CH is the scaled cell height of at least one of the memory cells 411a, 411b, 411c, and 411d in the first direction X.

[0174] The memory cell array 411 has a width W1b in the second direction Y. In some embodiments, the width W1b is equal to 4CW, where 2CW is the scaled cell width of at least one of the memory cells 411a, 411b, 411c, and 411d in the second direction Y.

[0175] In some embodiments, the width of the memory cell array 411 in the second direction Y is equal to 4 contact polysilicon pitches (e.g., 4CPP).

[0176] In some embodiments, the memory cell array 411 has an aspect ratio AR1b (e.g., W1b / H1b) equal to 4:1.

[0177] The memory circuit 400B also includes a group of bit lines BL, a group of anti-phase lines BLB, and a group of word lines WL.

[0178] In some embodiments, the memory cells 411a, 411b, 411c, and 411d are similar to the corresponding memory cells MCB in the same corresponding rows and the same corresponding columns of the area 201a of Figure 2A , so the similar detailed description is omitted. In some embodiments, each of the memory cells 411a, 411b, 411c, and 411d is Figure 3A the memory cell 300A of , so the similar detailed description is omitted.

[0179] The group of bit lines BL and the group of anti-phase lines BLB extend in the second direction Y.

[0180] The bit line BL[1] and the anti-phase line BLB[1] overlap with the memory cells 411a and 411c. The anti-phase line BLB[1] is electrically connected to the memory cells 411a and 411c through vias 414b. The bit line BL[1] is electrically connected to the memory cell 411a through via 414b and to the memory cell 411c through via 414e.

[0181] The bit line BL[2] and the anti-phase line BLB[2] overlap with the memory cells 411b and 411d. The anti-phase line BLB[2] is electrically connected to the memory cells 411b and 411d through vias 414d. The bit line BL[2] is electrically connected to the memory cell 411b through via 414c and to the memory cell 411d through via 414f.

[0182] Other configurations of the group of bit lines BL, arrangements on other metal layers, or the number of bit lines are within the scope of the present disclosure.

[0183] Other configurations of the group of anti-phase lines BLB, arrangements on other metal layers, or the number of anti-phase lines are within the scope of the present disclosure.

[0184] The group of word lines WL extends along the first direction X.

[0185] The word line WL[1] overlaps with the memory cells 411a and 411b. The word line WL[1] is electrically connected to the memory cell 411a through via 412a. The word line WL[1] is electrically connected to the memory cell 411b through via 412b.

[0186] The word line WL[2] overlaps with the memory cells 411c and 411d. The word line WL[2] is electrically connected to the memory cell 411c through via 412c. The word line WL[2] is electrically connected to the memory cell 411d through via 412d.

[0187] Other configurations of the word line group WL, arrangements on other metal layers, or the number of word lines are within the scope of the present disclosure.

[0188] The memory circuit 400B further includes one or more of vias 412a, 412b, 412c, and 412d (collectively referred to as "via group 412").

[0189] In some embodiments, the via group 412 is similar to Figure 4A the via group 402, and thus similar detailed descriptions are omitted. In some embodiments, at least one of the vias 412a, 412b, 412c, and 412d is similar to Figure 4A at least one or more of the vias 402a, 402b, 402c, 402d, 402e, and 402f of the via group 402, and thus similar detailed descriptions are omitted.

[0190] In some embodiments, the via 412a is located between the word line WL[1] and the memory cell 411a. In some embodiments, the via 412b is located between the word line WL[1] and the memory cell 411b.

[0191] In some embodiments, the via 412c is located between the word line WL[2] and the memory cell 411c. In some embodiments, the via 412d is located between the word line WL[2] and the memory cell 411d.

[0192] Other configurations of at least the via group 412, arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0193] The memory circuit 400B further includes one or more of vias 414a, 414b, 414c, 414d, 414e, and 414f (collectively referred to as "via group 414").

[0194] In some embodiments, the via group 414 is similar to Figure 4A the via group 404, and thus similar detailed descriptions are omitted. In some embodiments, at least one of the vias 414a, 414b, 414c, 414d, 414e, and 414f is similar to Figure 4A one or more of the vias 404a, 404b, 404c, 404d, 404e, and 404f of the via group 404, and thus similar detailed descriptions are omitted.

[0195] In some embodiments, the via 414b is located between the anti-phase line BLB[1] and the memory cells 411a and 411c. In some embodiments, the via 414a is located between the bit line BL[1] and the memory cell 411a, and the via 414e is located between the bit line BL[1] and the memory cell 411c.

[0196] In some embodiments, the via 414d is located between the anti-phase line BLB[2] and the memory cells 411b and 411d. In some embodiments, the via 414c is located between the bit line BL[2] and the memory cell 411b, and the via 414 is located between the bit line BL[2] and the memory cell 411d.

[0197] At least other configurations of the group of vias 414, arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0198] Other configurations of the memory circuit 400B are also within the scope of the present disclosure.

[0199] Figure 4C is a schematic diagram of a memory circuit 400C according to some embodiments.

[0200] The memory circuit 400C relates to Figure 2A the memory cell array 202. The memory circuit 400C is Figure 2A an embodiment of the region 201a of the memory circuit 200A, and thus similar detailed descriptions are omitted. In some embodiments, the memory circuit 400C is an embodiment of a region of the memory circuit 200A other than the region 201a of the memory circuit 200A. Figure 2A the memory circuit 200A

[0201] The memory circuit 400C is Figure 4A a variant of the memory circuit 400A or Figure 4B the memory circuit 400B, and thus similar detailed descriptions are omitted. Compared with the memory circuit 400A of Figure 4A the memory circuit 400A, Figure 4B the memory cell array 421 replaces Figure 4A the memory cell array 401, and thus similar detailed descriptions are omitted.

[0202] The memory circuit 400C includes a memory cell array 421. The memory cell array 421 is similar to Figure 2A the memory cell array 202 of Figure 4A the memory cell array 401 of Figure 4B the memory cell array 411 of

[0203] The memory cell array 421 includes memory cells 421a, 421b, 421c, and 421d. In some embodiments, at least one of the memory cells 421a, 421b, 421c, and 421d is similar to Figure 4A at least one of the memory cells 401a, 401b, 401c, and 401d of the memory cell array 401 of Figure 4Bat least one of the memory cells 411a, 411b, 411c, and 411d of the memory cell array 411, and thus similar detailed descriptions are omitted.

[0204] Memory cell 421a is located at row 1 and column 1 of memory cell array 421, and is Figure 4C labeled and identified as "r1c1" therein. Memory cell 421b is located at row 2 and column 2 of memory cell array 421, and is Figure 4C labeled as "r2c1" therein. Memory cell 421c is located at row 1 and column 2 of memory cell array 421, and is Figure 4C labeled as "r1c2" therein. Memory cell 421d is located at row 2 and column 2 of memory cell array 421, and is Figure 4C labeled as "r2c2" therein.

[0205] Memory cell array 421 is shown as a 2×2 memory cell array in Figure 4C . Other numbers of rows and columns are also within the scope of the present disclosure.

[0206] Memory cell array 421 has a height H1c in the first direction X. In some embodiments, the height H1c is equal to 2CH, where CH is the scaled cell height of at least one of the memory cells 421a, 421b, 421c, and 421d in the first direction X.

[0207] Memory cell array 421 has a width W1c in the second direction Y. In some embodiments, the width W1c is equal to 2CW, where 2CW is the scaled cell width of at least one of the memory cells 421a, 421b, 421c, and 421d in the second direction Y.

[0208] In some embodiments, the width of memory cell array 421 in the second direction Y is equal to 4 contact polysilicon pitches (e.g., 4CPP).

[0209] In some embodiments, memory cell array 421 has an aspect ratio AR1c equal to 1:1 (e.g., W1c / H1c).

[0210] Memory circuit 400C further includes a set of bit lines BL, a set of anti-phase lines BLB, and a set of word lines WL.

[0211] In some embodiments, the memory cells 421a, 421b, 421c, and 421d are Figure 2A similar to the corresponding memory cells MCB in the same corresponding rows and the same corresponding columns of region 201a of Figure 3AThe storage unit 300A, so a similar detailed description is omitted.

[0212] The group of bit lines BL and the group of anti-phase lines BLB extend in the second direction Y.

[0213] The bit line BL[1] overlaps with the storage unit 421a. The bit line BL[1] is electrically connected to the storage unit 421a through the via 424a. In some embodiments, the bit line BL[1] is electrically connected to the storage unit 421a and the storage unit 421b (not shown), and the bit line BL[1] is shared between the storage unit 421a and the storage unit 421b. In other words, adjacent storage units (e.g., the storage units 421b and 421a) in the memory circuit 400C are configured to share BL with each other.

[0214] The anti-phase line BLB[1] overlaps with the storage unit 421b. The anti-phase line BLB[1] is electrically connected to the storage unit 421b through the via 424b. In some embodiments, the anti-phase line BLB[1] is electrically connected to the storage unit 421b and the storage unit 421a (not shown), and the anti-phase line BLB[1] is shared between the storage unit 421b and the storage unit 421a. In other words, adjacent storage units (e.g., the storage units 421b and 421a) in the memory circuit 400C are configured to share BLB with each other.

[0215] The anti-phase line BLB[2] overlaps with the storage unit 421c. The anti-phase line BLB[2] is electrically connected to the storage unit 421c through the via 424c. In some embodiments, the anti-phase line BLB[2] is electrically connected to the storage unit 421c and the storage unit 421d (not shown), and the anti-phase line BLB[2] is shared between the storage unit 421c and the storage unit 421d. In other words, adjacent storage units (e.g., the storage units 421d and 421c) in the memory circuit 400C are configured to share BLB with each other.

[0216] The bit line BL[2] overlaps with the storage unit 421d. The bit line BL[2] is electrically connected to the storage unit 421d through the via 424d. In some embodiments, the bit line BL[2] is electrically connected to the storage unit 421d and the storage unit 421c (not shown), and the bit line BL[2] is shared between the storage unit 421d and the storage unit 421c. In other words, adjacent storage units (e.g., the storage units 421d and 421c) in the memory circuit 400C are configured to share BL with each other.

[0217] Other configurations of the group of bit lines BL, arrangements on other metal layers, or the number of bit lines are within the scope of the present disclosure.

[0218] Other configurations of the anti-phase line BLB group, arrangements on other metal layers, or the number of anti-phase lines are within the scope of the present disclosure.

[0219] The word line group WL extends along the first direction X.

[0220] The word line WL[1] overlaps with the memory cells 421a, 421b, 421c, and 421d. The word line WL[1] is electrically connected to the memory cell 421b (also referred to as "cell 2" in Figure 4C through the via 422b. The word line WL[1] is electrically connected to the memory cell 421d (also referred to as "cell 4" in Figure 4C through the via 422d.

[0221] The word line WL[2] overlaps with the memory cells 421a, 421b, 421c, and 421d. The word line WL[2] is electrically connected to the memory cell 421a (also referred to as "cell 1" in Figure 4C through the via 422a. The word line WL[2] is electrically connected to the memory cell 421c (also referred to as "cell 3" in Figure 4C through the via 422c.

[0222] As Figure 4C shown, the word line WL[1] is electrically connected to the memory cells 421b and 421d and is shared between the memory cells 421a and 421d, and is thus referred to as an "interleaved or alternating word line". In some embodiments, by interleaving a group of WLs and sharing the BL or BLB between adjacent memory cells, the memory circuit 400C has the same aspect ratio (1:1) as the memory circuit 400A, thereby forming a more flexible cell compared to other methods.

[0223] Other configurations of the word line group WL, arrangements on other metal layers, or the number of word lines are within the scope of the present disclosure.

[0224] The memory circuit 400C further includes one or more of the vias 422a, 422b, 422c, and 422d (collectively referred to as "via group 422").

[0225] In some embodiments, the group of vias 422 is similar to Figure 4A the via group 402 of Figure 4B or Figure 4A the via group 412 of Figure 4Bat least one or more of the vias 412a, 412b, 412c, and 412d of the via group 412. Therefore, similar detailed descriptions are omitted.

[0226] In some embodiments, the via 422b is located between the word line WL[1] and the memory cell 421b. In some embodiments, the via 422d is located between the word line WL[1] and the memory cell 421d.

[0227] In some embodiments, the via 422a is located between the word line WL[2] and the memory cell 421a. In some embodiments, the via 422c is located between the word line WL[2] and the memory cell 421c.

[0228] Other configurations of at least the via group 422, arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0229] The memory circuit 400C further includes one or more of the vias 424a, 424b, 424c, and 424d (collectively referred to as "via group 424").

[0230] In some embodiments, the via group 424 is similar to Figure 4A the via group 404 of Figure 4B or the via group 414 of Figure 4A Therefore, similar detailed descriptions are omitted. In some embodiments, at least one of the vias 424a, 424b, 424c, and 424d is similar to Figure 4B at least one or more of the vias 404a, 404b, 404c, 404d, 404e, and 404f of the via group 404 of

[0231] In some embodiments, the via 424a is located between the bit line BL[1] and the memory cell 421a.

[0232] In some embodiments, the via 424b is located between the anti-phase line BLB[1] and the memory cell 421b.

[0233] In some embodiments, the via 424c is located between the anti-phase line BLB[2] and the memory cell 421c.

[0234] In some embodiments, the via 424d is located between the bit line BL[2] and the memory cell 421d.

[0235] Other configurations of at least this group of vias 424, arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0236] Other configurations of the memory circuit 400C are also within the scope of the present disclosure.

[0237] Figure 5A is a corresponding schematic diagram of a corresponding memory circuit 500A according to some embodiments.

[0238] The memory circuit 500A relates to Figure 2A the memory cell array 202. The memory circuit 500A is Figure 4A an embodiment of a memory cell (e.g., memory cell 401a, 401b, 401c, or 401d) of the memory cell array 401, and thus similar detailed descriptions are omitted.

[0239] The memory circuit 500A is manufactured by a corresponding layout design similar to that of the memory circuit 500A.

[0240] The memory circuit 500A has a height H2a in the first direction X. In some embodiments, the height H2a is equal to CH, where CH is at least the scaled unit height of the circuit 500A in the first direction X.

[0241] The memory circuit 500A has a width W2a in the second direction Y. In some embodiments, the width W2a is equal to CW, where CW is at least the scaled unit width of the memory circuit 500A in the second direction Y.

[0242] In some embodiments, the width of the memory circuit 500A in the second direction Y is equal to 2 contact polysilicon pitches (e.g., 2CPP).

[0243] In some embodiments, the memory circuit 500A can be used as Figure 4A at least one of the memory cells 401a, 401b, 401c, or 401d of the memory cell array 401, and thus similar detailed descriptions are omitted.

[0244] The memory circuit 500A includes one or more active regions 502a, 502b, 502c, or 502d (collectively referred to as "active region group 502") extending along the second direction Y. This group of active regions 502 is embedded in wells 501a, 501b, 501c, or 501d (collectively referred to as "well group 501"). The well group 501 is located in the substrate 490. In some embodiments, at least one of wells 501a and 501d is a P-well, and at least one of wells 501b and 501c is an N-well. In some embodiments, wells 501b and 501c are continuous wells. In some embodiments, at least well 501a or 501d includes a first type of dopant, and at least well 501b or 501c includes a second type of dopant different from the first type. In some embodiments, the first type is an N-type dopant and the second type is a P-type dopant. In some embodiments, the first type is a P-type dopant and the second type is an N-type dopant.

[0245] In some embodiments, this group of active regions 502 is fabricated by a corresponding set of active region patterns (not shown) of the corresponding layout designs of memory circuits 500A to 500B, 600, 800, or 900. In some embodiments, the active regions 502a, 502b, 502c, or 502d of this group of active regions 502 are fabricated by the corresponding active region patterns (not shown) in the corresponding set of active region patterns (not shown) of the corresponding layout designs of memory circuits 500A to 500B, 600, 800, or 900.

[0246] Each of the active regions 502a, 502b, 502c, and 502d in the active region group 502 is separated from each other in the first direction X.

[0247] In some embodiments, at least one of this active region group 502 is located on the front side 490a of memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500. In some embodiments, the front side 490a is a part of the substrate 490.

[0248] In some embodiments, at least one of this active region group 502 corresponds to the source and drain regions of one or more complementary FET (CFET) transistors. In some embodiments, at least one of this active region group 502 corresponds to the source and drain regions of one or more nanosheet transistors or nanowire transistors. Other transistor types are also within the scope of the present disclosure. In some embodiments, at least one of this active region group 502 corresponds to the source and drain regions of one or more finFET transistors.

[0249] In some embodiments, the active region group 502 is referred to as an oxide diffusion (OD) region that defines a source or drain diffusion region for at least one of the memory cells 300A or 300B or the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0250] In some embodiments, the active regions 502a or 502d are the source and drain regions of an NFET transistor for at least one of the memory cells 300A or the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500, and the active regions 502b or 502c are the drain and source regions of a PFET transistor for at least one of the memory cells 300A or 300B or the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0251] In some embodiments, the active regions 502a or 502d are the source and drain regions of a PFET transistor for at least one of the memory cells 300A or the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500, and the active regions 502b or 502c are the drain and source regions of an NFET transistor for at least one of the memory cells 300A or 300B or the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0252] In some embodiments, the active region group 502 is located in the first layer. In some embodiments, the first layer corresponds to the active layer or the OD layer for at least one of the memory cells 300A or 300B or the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0253] Other configurations in the active region group 502, arrangements on other layers, or the number of regions are also within the scope of the present disclosure.

[0254] The memory circuit 500A further includes one or more gates 504a, 504b, 504c, or 504d (collectively referred to as "gate group 504") extending along the first direction X.

[0255] The gate group 504 is located above the active region group 502.

[0256] The gates 504a and 504c are separated from each other in the first direction X.

[0257] The gates 504b and 504d are separated from each other in the first direction X.

[0258] The gates 504a and 504b are separated from each other in the second direction Y.

[0259] The gates 504c and 504d are separated from each other in the second direction Y.

[0260] In some embodiments, the gate group 504 is fabricated by a corresponding gate pattern group (not shown) of the corresponding layout designs of the memory circuits 500A to 500B, 600, 800, or 900. In some embodiments, the gates 504a, 504b, 504c, or 504d of the gate group 504 are fabricated by corresponding gate patterns (not shown) of a gate pattern group (not shown) of the corresponding layout designs of the memory circuits 500A to 500B, 600, 800, or 900.

[0261] In some embodiments, at least one of the gate group 504 is located on the front side of the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0262] In some embodiments, FIGS. 5, Figure 6 , Figure 8 and Figure 9 show each gate in the gate group 504, labeled "N2-1, P2-1, N2-2, P2-2, N2-3, N2-4", for identifying Figure 3A , Figure 4A , Figure 4B and Figure 4C the corresponding transistors in, and these labels are omitted for simplicity.

[0263] In some embodiments, one of the gates of the gate group 504, 604, 804, or 904 is the gate of a pseudo transistor. In some embodiments, the pseudo transistor is a non-functional transistor.

[0264] In some embodiments, the gate group 504 is located above the active region group 502.

[0265] In some embodiments, the gate group 504 encapsulates the active region pattern groups 502 and 304.

[0266] The gate group 504 is located in the second layer. In some embodiments, the second layer is different from the first layer. In some embodiments, the second layer corresponds to the POLY layer of one or more of the memory cells 300A or 300B or the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500. In some embodiments, the POLY layer is higher than the OD layer.

[0267] Other configurations of the gate group 504, arrangements on other layers, or the number of gates are within the scope of the present disclosure.

[0268] In some embodiments, at least one via in the via group 402 is electrically connected to at least one gate in the gate group 504. In some embodiments, at least one via in the via group 404 is electrically connected to at least one gate in the gate group 504.

[0269] In some embodiments, at least one via in the via group 402 is electrically connected to at least one active region in the active region group 502. In some embodiments, at least one via in the via group 404 is electrically connected to at least one active region in the active region group 502.

[0270] Other configurations of the memory circuit 500A are also within the scope of the present disclosure.

[0271] Figure 5B is a corresponding schematic diagram of the corresponding memory circuit 500B according to some embodiments.

[0272] Figure 5C is a cross-sectional view of the integrated circuit 500B taken along the plane A-A' according to some embodiments.

[0273] Figure 5D is a cross-sectional view of the integrated circuit 500B taken along the plane B-B' according to some embodiments.

[0274] Figure 5E is a cross-sectional view of the integrated circuit 500B taken along the plane C-C' according to some embodiments.

[0275] Figure 5F is a cross-sectional view of the integrated circuit 500B taken along the plane F-F' according to some embodiments.

[0276] The memory circuit 500B relates to Figure 2A the memory cell array 202. The memory circuit 500B isFigure 4A An embodiment of the memory cell 401d of the memory cell array 401, and thus similar detailed descriptions are omitted. In some embodiments, the memory circuit 500B is Figure 4A An embodiment of the memory cells 401a, 401b, or 401c of the memory cell array 401, and thus similar detailed descriptions are omitted.

[0277] The memory circuit 500B is fabricated through a corresponding layout design similar to that of the memory circuit 500B.

[0278] In some embodiments, the memory circuit 500B incorporates Figure 5A The features of the memory circuit 500A applied to Figure 4A The memory cell 401d of the memory cell array 401, and thus similar detailed descriptions are omitted. In some embodiments, the features of the memory circuit 500B are applicable to at least one of the memory circuits 400B, 400C, 600, 700A, 700B, 800, or 900, and thus similar detailed descriptions are omitted.

[0279] The memory circuit 500B is Figure 4A A variant of the memory circuit 400A and Figure 5A The memory circuit 500A, and thus similar detailed descriptions are omitted. Compared with Figure 5A The memory circuit 500A Figure 5B The memory circuit 500B further includes Figure 5A The memory circuit 500A, the contact member contact group 506, the via group 512, the via group 514, the conductor group 520, and the conductor group 530.

[0280] Compared with Figure 4A The memory circuit 400A Figure 5B The memory circuit 500B further includes Figure 5A The memory circuit 500A, the contact member contact group 506, the via group 512, the via group 514, the conductor group 520, and the conductor group 530.

[0281] The memory circuit 500B is Figure 4A An embodiment of the memory cell 401d of the memory cell array 401, and thus similar detailed descriptions are omitted.

[0282] The memory circuit 500B includes bit line BL[2], inverted bit line BLB[2], word line WL[2], vias 402e and 402f, and vias 404d and 404f, active region group 502, gate group 504, contact member contact group 506, via group 512, via group 514, conductor group 520, and conductor group 530.

[0283] In some embodiments, bit line BL[2], anti-phase bit line BLB[2], word line WL[2], vias 402e and 402f, and vias 404d and 404f are Figure 4A parts of the memory cell 401d.

[0284] The contact group 506 includes one or more of contacts 506a, 506b, 506c, and 506d. The contact group 506 extends in the first direction X. The contact group 506 is located above the active region group 502.

[0285] The contact group 506 is electrically connected to the active region group 502. In some embodiments, the contact group 506 electrically connects the active region group 502 to a higher layer (e.g., M0, M1, or M2).

[0286] Contact 506a is electrically connected to active regions 502a and 502b. Contact 506a electrically connects active regions 502a and 502b together. In some embodiments, contact 506a electrically connects the drain of NFET transistor N2-2, the drain of PFET transistor P2-2, and the source of NFET transistor N2-4 together.

[0287] Contact 506b is electrically connected to active region 502a. In some embodiments, contact 506b is electrically connected to the drain of NFET transistor N2-4.

[0288] Contact 506c is electrically connected to active regions 502c and 502d. Contact 506c electrically connects active regions 502c and 502d together. In some embodiments, contact 506c electrically connects the drain of NFET transistor N2-1, the drain of PFET transistor P2-1, and the source of NFET transistor N2-3 together.

[0289] Contact 506d is electrically connected to active region 502d. In some embodiments, contact 506d is electrically connected to the drain of NFET transistor N2-3.

[0290] The contact group 506 is located in the third layer. In some embodiments, the third layer is different from the first layer. In some embodiments, the third layer corresponds to the diffusion upper metal (MD) layer of one or more of memory cells 300A or 300B or memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500. In some embodiments, the MD layer is higher than the OD layer.

[0291] Other numbers, configurations, arrangements on other layers, or numbers of contacts in the contact group 506 are also within the scope of the present disclosure.

[0292] The via group 512 includes one or more of vias 512a, 512b, and 512c.

[0293] In some embodiments, the via group 512 is fabricated by a corresponding via pattern group (not shown) of the corresponding layout design of the memory circuit 500B. In some embodiments, the vias 512a, 512b, or 512c of the via group 512 are fabricated by corresponding via patterns (not shown) in a corresponding via pattern group (not shown) of the corresponding layout design of the memory circuit 500B.

[0294] The via group 512 is located between the gate group 504 and the conductor group 520.

[0295] In some embodiments, the via 512a is located between the gate 504b and the conductor 520a. In some embodiments, the via 512a electrically connects the gate 504b and the conductor 520a together.

[0296] In some embodiments, the via 512b is located between the gate 504d and the conductor 520d. In some embodiments, the via 512b electrically connects the gate 504d and the conductor 520d together.

[0297] In some embodiments, the via 512c is located between the gate 504c and the conductor 520d. In some embodiments, the via 512c electrically connects the gate 504c and the conductor 520d together.

[0298] The group of vias 512 is located in the VG layer of the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, or 900. Other layers are also within the scope of the present disclosure.

[0299] At least other configurations of the via group 512, arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0300] The via group 514 includes one or more of vias 514a and 514b.

[0301] In some embodiments, the via group 514 is fabricated by a corresponding via pattern group (not shown) of the corresponding layout design of the memory circuit 500B. In some embodiments, the vias 514a or 514b of the via group 514 are fabricated by corresponding via patterns (not shown) in a corresponding via group pattern (not shown) of the corresponding layout design of the memory circuit 500B.

[0302] The via group 514 is located between the contact group 506 and the conductor group 520.

[0303] In some embodiments, via 514a is located between contact 506d and conductor 520c. In some embodiments, via 514a electrically connects contact 506d and conductor 520c together.

[0304] In some embodiments, via 514b is located between contact 506b and conductor 520b. In some embodiments, via 514b electrically connects contact 506b and conductor 520b together.

[0305] The via group 514 is located in the VD layer of memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, or 900. Other layers are also within the scope of the present disclosure.

[0306] At least other configurations of the via group 514, arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0307] The conductor group 520 includes one or more of conductors 520a, 520b, 520c, and 520d.

[0308] The conductor group 520 extends in the second direction Y.

[0309] The conductor group 520 is located above the contact group 506, the gate group 504, and the active region group 502.

[0310] The conductor group 520 is located below the conductor group 530, the bit line group BL, the anti-phase line group BLB, and the word line group WL.

[0311] The conductor group 520 electrically connects the contact group 506 or the gate group 504 to an upper layer (such as M1 or M2).

[0312] Conductor 520a is electrically connected to gate 504b through via 512a.

[0313] Conductor 520b is electrically connected to contact 506b through via 514b.

[0314] Conductor 520c is electrically connected to contact 506d through via 514a.

[0315] Conductor 520d is electrically connected to gate 504d and gate 504c through corresponding vias 512b and 512c. Conductor 520d electrically connects gate 504d and gate 504c together through corresponding vias 512b and 512c.

[0316] The conductor group 520 is located in the fourth layer. The fourth layer is higher than the first layer, the second layer, and the third layer. In some embodiments, the fourth layer is referred to as the metal 0 (M0) layer. Other layers are also within the scope of the present disclosure.

[0317] Other numbers or configurations of conductor group 520 are also within the scope of the present disclosure.

[0318] Conductor group 530 includes one or more of conductors 530a and 530b.

[0319] Conductor group 530 extends along the first direction X.

[0320] Conductor group 530 is located above conductor group 530, contact group 506, gate group 504, and active region group 502.

[0321] Conductor group 530 is located below bit line group BL and anti-phase line group BLB.

[0322] Conductor group 530 electrically connects contact group 506 or gate group 504 to an upper layer (e.g., M2).

[0323] Conductor 530a is electrically connected to conductor 520c through via 522a.

[0324] Conductor 530b is electrically connected to conductor 520b through via 522b.

[0325] Conductor group 530 is located in the fifth layer. The fifth layer is higher than the first layer, the second layer, the third layer, and the fourth layer. In some embodiments, the fifth layer is referred to as the metal 1 (M1) layer. Other layers are also within the scope of the present disclosure.

[0326] In some embodiments, word line WL[2] is in the fifth layer. Word line WL[2] is electrically connected to conductor 520a through via 402e. Word line WL[2] is electrically connected to conductor 520d through via 402f.

[0327] In some embodiments, vias 402e and 402f are in the V0 layer. In some embodiments, this via group 402 is in the V0 layer. Other layers are also within the scope of the present disclosure.

[0328] Other numbers or configurations of conductor group 530 are also within the scope of the present disclosure.

[0329] This via group 522 includes one or more of vias 522a and 522b.

[0330] In some embodiments, via group 522 is fabricated by a corresponding via pattern group (not shown) of the corresponding layout design of memory circuit 500B. In some embodiments, via 522a or 522b of via group 522 is fabricated by a corresponding via pattern (not shown) in the via group pattern (not shown) of the corresponding layout design of memory circuit 500B.

[0331] Via group 522 is located between conductor group 520 and conductor group 530.

[0332] In some embodiments, via 522a is located between conductor 520c and conductor 530a. In some embodiments, via 522a electrically connects conductor 520c and conductor 530a together.

[0333] In some embodiments, via 522b is located between conductor 520b and conductor 530b. In some embodiments, via 522b electrically connects conductor 520b and conductor 530b together.

[0334] The via group 522 is located in the V1 layer of memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, or 900. Other layers are also within the scope of the present disclosure.

[0335] At least other configurations of the via group 522, arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0336] In some embodiments, the bit line group BL and the anti-phase line group BLB are located in the sixth layer. The sixth layer is higher than the first, second, third, fourth, and fifth layers. In some embodiments, the sixth layer is referred to as the metal 2 (M2) layer. Other layers are also within the scope of the present disclosure.

[0337] Bit line BL[2] is electrically connected to conductor 530a through via 404d.

[0338] Anti-phase line BLB[2] is electrically connected to conductor 530b through via 404f.

[0339] In some embodiments, vias 404d and 404f are in the V1 layer. In some embodiments, the via group 404 is in the V1 layer. Other layers are also within the scope of the present disclosure.

[0340] Other quantities or configurations of the conductor group 530 are also within the scope of the present disclosure.

[0341] Other configurations of memory circuit 500B are also within the scope of the present disclosure.

[0342] Figure 6 is a corresponding schematic diagram of the corresponding memory circuit 600 according to some embodiments.

[0343] Memory circuit 600 relates to Figure 2A the memory cell array 202 of. Memory circuit 600 is Figure 4B an embodiment of a memory cell (e.g., memory cells 411a, 411b, 411c, or 411d) of the memory cell array 411 of, and thus similar detailed descriptions are omitted.

[0344] In some embodiments, memory circuit 600 is Figure 4CAn embodiment of a memory cell (e.g., memory cell 421a, 421b, 421c, or 421d) of the memory cell array 421 is thus, and a similar detailed description is omitted.

[0345] The memory circuit 600 is fabricated by a corresponding layout design similar to the memory circuit 600.

[0346] The memory circuit 600 has a height H2b in the first direction X. In some embodiments, the height H2b is equal to 0.5CH, where CH is the scaled unit height of at least the circuit 600 in the first direction X.

[0347] The memory circuit 600 has a width W2b in the second direction Y. In some embodiments, the width W2b is equal to 2CW, where CW is the scaled unit width of at least the memory circuit 600 in the second direction Y.

[0348] In some embodiments, the width of the memory circuit 600 in the second direction Y is equal to 4 contact polysilicon pitches (e.g., 4CPP).

[0349] In some embodiments, the memory circuit 600 can be used as Figure 4B at least one of the memory cells 411a, 411b, 411c, or 411d of the memory cell array 411, and thus a similar detailed description is omitted.

[0350] In some embodiments, the memory circuit 600 can be used as Figure 4C at least one of the memory cells 421a, 421b, 421c, or 421d of the memory cell array 421, and thus a similar detailed description is omitted.

[0351] The memory circuit 600 includes one or more active regions 602a or 602b (collectively referred to as "active region group 602") extending along the second direction Y.

[0352] In some embodiments, the active region group 602 is similar to Figure 5A the active group region 502, and thus a similar detailed description is omitted. In some embodiments, one or more of the active regions 602a and 602b are similar to Figure 5A one or more of the active regions 502a, 502b, 502c, or 502d of the active region group 502, and thus a similar detailed description is omitted.

[0353] In some embodiments, the active region group 602 is fabricated from corresponding active region pattern groups (not shown) of the respective layout designs of memory circuits 500A to 500B, 600, 800, or 900. In some embodiments, the active regions 602a or 602b of the active region group 602 are fabricated from corresponding active region patterns (not shown) of the corresponding active region pattern groups (not shown) of the respective layout designs of memory circuits 500A to 500B, 600, 800, or 900.

[0354] In some embodiments, the active region 602a is the source and drain regions of a PFET transistor of a memory cell 300A or at least one of memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1600, and the active region 602b is the drain and source regions of an NFET transistor of a memory cell 300 or at least one of memory circuits 400A, 400B, and 400C.

[0355] In some embodiments, the active region 602a is the source and drain regions of an NFET transistor of a memory cell 300A or at least one of memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1600, and the active region 602b is the drain and source regions of a PFET transistor of a memory cell 300A or at least one of memory circuits 400A, 400B, 400C, 500A to 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0356] Other configurations in the active region group 602, arrangements on other layers, or the number of regions are within the scope of the present disclosure.

[0357] The memory circuit 600 further includes one or more gates 604a, 604b, 604c, or 604d (collectively referred to as "gate group 604") extending along the first direction X.

[0358] In some embodiments, the gate group 604 is similar to Figure 5A the gate group 504, and thus a similar detailed description is omitted. In some embodiments, one or more of the gates 604a, 604b, 604c, and 604d are similar to Figure 5A the gates 504a, 504b, 504c, or 504d in the gate group 504, and thus a similar detailed description is omitted.

[0359] Each gate in the gate group 604 is separated from another gate in the gate group 604 in the second direction Y.

[0360] In some embodiments, the gate group 604 is fabricated from a corresponding gate pattern group (not shown) of the corresponding layout design of the memory circuits 500A to 500B, 600, 800, or 900. In some embodiments, the gates 604a, 604b, 604c, or 604d of the gate group 604 are fabricated from corresponding gate patterns (not shown) of a corresponding gate pattern group (not shown) of the corresponding layout design of the memory circuits 500A to 500B, 600, 800, or 900.

[0361] In some embodiments, FIG. 5, Figure 6 , Figure 8 and Figure 9 show each gate in the gate group 604, labeled "N2-1, P2-1, N2-2, P2-2, N2-3, N2-4", for identifying Figure 3A , Figure 4A , Figure 4B and Figure 4C the corresponding transistors in, and these labels are omitted for simplicity.

[0362] Other configurations of the gate group 604, arrangements on other layers, or the number of gates are also within the scope of the present disclosure.

[0363] In some embodiments, at least one via in the via group 402 is electrically connected to at least one gate in the gate group 604. In some embodiments, at least one via in the via group 404 is electrically connected to at least one gate in the gate group 604.

[0364] In some embodiments, at least one via in the via group 402 is electrically connected to at least one active region in the active region group 602. In some embodiments, at least one via in the via group 404 is electrically connected to at least one active region in the active region group 602.

[0365] Other configurations of the memory circuit 600 are also within the scope of the present disclosure.

[0366] Figures 7A to 7B are corresponding schematic diagrams of the corresponding memory circuits 700A to 700B according to some embodiments.

[0367] Figure 7A is a schematic diagram of the memory circuit 700A according to some embodiments.

[0368] The memory circuit 700A relates to Figure 2B the storage cell array 202. The memory circuit 700A is Figure 2BAn embodiment of region 201b of memory circuit 200B is thus, and a similar detailed description is omitted. In some embodiments, memory circuit 700A is an embodiment of a region of memory circuit 210B other than region 201b of memory circuit 200B. Figure 2B An embodiment of a region of memory circuit 210B other than region 201b of memory circuit 200B.

[0369] Memory circuit 700A is Figure 4A A variant of memory circuit 400A is thus, and a similar detailed description is omitted. Compared with Figure 4A Memory circuit 400A, Figure 7A Memory cell array 701 of replaces Figure 4A Memory cell array 401 of, Figure 7A Read word line RWL in or Figure 7A Write word line WWL in replaces Figure 4A Word line WL in, and a similar detailed description is omitted. Compared with Figure 4A Memory circuit 400A, memory circuit 700A further includes read bit line RBL, and a similar detailed description is omitted.

[0370] Memory circuit 700A includes memory cell array 701. Memory circuit 700A is a schematic diagram of two adjacent columns and two adjacent rows of memory cell array 701. In some embodiments, memory circuit 700 is Figure 2B Columns 1 and 2 of memory cell array 202 of and Figure 2B Rows 1 and 2 of memory cell array 202 of are schematic diagrams, and a similar detailed description is omitted. In some embodiments, memory circuit 700 is Figure 2B A schematic diagram of other columns or other rows of memory cell array 202 of, rather than Figure 2B Columns 1 and 2 or rows 1 and 2 in memory cell array 202 of, and a similar detailed description is omitted.

[0371] Memory circuits 700A to 700B are manufactured by a corresponding layout design similar to that of memory circuits 700A to 700B.

[0372] Memory cell array 701 is similar to Figure 2B Memory cell array 202 of, and a similar detailed description is omitted.

[0373] Memory cell array 701 includes memory cells 701a, 701b, 701c, and 701d.

[0374] Memory cell 701a is located at row 1 and column 1 of memory cell array 701 and is labeled "r1c1" in Figure 7A Memory cell 701b is located at row 1 and column 2 of memory cell array 701 and is inFigure 7A is labeled as "r1c2" in. The storage cell 701c is located at row 2 and column 1 of the storage cell array 701, in Figure 7A is labeled "r2c1". The storage cell 701d is located at row 2 and column 2 of the storage cell array 701, in Figure 7A is labeled "r2c2".

[0375] The storage cell array 701 is shown as a 2×2 storage cell array in Figure 7A . Other numbers of rows and columns are also within the scope of the present disclosure.

[0376] The storage cell array 701 has a height H3a in the first direction X. In some embodiments, the height H3a is equal to 2CH + 2RP, where CH is the scaled cell height of at least one of the storage cell arrays 701a, 701b, 701c, and 701d in the first direction X, and RP is Figure 8 the cell height of at least one of the regions 810 in the first direction X.

[0377] The storage cell array 701 has a width W3a in the second direction Y. In some embodiments, the width W3a is equal to 2CW, where CW is the scaled cell width of at least one of the storage cell arrays 701a, 701b, 701c, and 701d in the second direction Y.

[0378] In some embodiments, the width of the storage cell array 701 in the second direction Y is equal to 2 contact polysilicon pitches (e.g., 2CPP).

[0379] In some embodiments, the aspect ratio AR1a of the storage cell array 701 is equal to ((CH + RP) / CW) (e.g., W1a / H1a).

[0380] The memory circuit 700A further includes the bit line group BL and the anti-phase line group BLB.

[0381] In some embodiments, the storage cells 701a, 701b, 701c, and 701d are similar to Figure 2B the corresponding storage cells MCB in the same corresponding rows and the same corresponding columns of the region 201b of, so the similar detailed description is omitted. In some embodiments, each of the storage cells 701a, 701b, 701c, and 701d is Figure 3B the storage cell 300B of, so the similar detailed description is omitted.

[0382] The bit line BL[1] and the complementary bit line BLB[1] overlap with the memory cells 701a and 701c. The complementary bit line BLB[1] is electrically connected to the memory cells 701a and 701c through vias 704a. The bit line BL[1] is electrically connected to the memory cell 701a through via 704b and to the memory cell 701c through via 704e.

[0383] The bit line BL[2] and the complementary bit line BLB[2] overlap with the memory cells 701b and 701d. The bit line BL[2] is electrically connected to the memory cells 701b and 701d through via 404d. The complementary bit line BLB[2] is electrically connected to the memory cell 701b through via 404c and to the memory cell 701d through via 404f.

[0384] Other configurations of the bit line group BL, arrangements on other metal layers, or the number of bit lines are within the scope of the present disclosure.

[0385] Other configurations of the complementary bit line group BLB, arrangements on other metal layers, or the number of complementary bit lines are within the scope of the present disclosure.

[0386] The memory circuit 700A further includes read word lines RWL[1] and RWL[2] (collectively referred to as "read word line group RWL") or write word lines WWL[1] and WWL[2] (collectively referred to as "write word line group WL").

[0387] The write word line group WWL or the read word line group RWL extends in the first direction X. In some embodiments, at least one of the write word line group WWL and the read word line group RWL is similar to the word line group WL, and thus the similar detailed description is omitted.

[0388] In some embodiments, the write word lines WWL[1] and WWL[2] are similar to Figure 2B the corresponding write word lines WWL[1] and WWL[2], and thus the similar detailed description is omitted. In some embodiments, the read word lines RWL[1] and RWL[2] are similar to Figure 2B the corresponding read word lines RWL[1] and RWL[2], and thus the similar detailed description is omitted.

[0389] The write word line WWL[1] or the read word line RWL[1] overlaps with the memory cells 701a and 701b. The write word line WWL[1] or the read word line RWL[1] is electrically connected to the memory cell 701a through vias 402a and 402b. The write word line WWL[1] or the read word line RWL[1] is electrically connected to the memory cell 701b through vias 402b and 402c.

[0390] The write word line WWL[2] or the read word line RWL[2] overlaps with the memory cells 701c and 701d. The write word line WWL[2] or the read word line RWL[2] is electrically connected to the memory cell 701c through the vias 402d and 402e. The write word line WWL[2] or the read word line RWL[2] is electrically connected to the memory cell 701d through the vias 402e and 402f.

[0391] In some embodiments, at least one of the write word line group WWL and the read word line group RWL is located in the M1 layer of at least one of the memory circuits 700A and 700B. In some embodiments, at least one of the write word line group WWL and the read word line group RWL is located in the M0 layer of at least one of the memory circuits 700A and 700B. Other metal layers for at least one of the write word line group WWL or the read word line group RWL are within the scope of the present disclosure.

[0392] In some embodiments, at least one of the write word line group WWL and the read word line group RWL is located in the POLY layer of at least one of the memory circuits 700A and 700B.

[0393] Other configurations of at least one of the write word line group WWL and the read word line group RWL, arrangements on other metal layers, or the number of read or write word lines are within the scope of the present disclosure.

[0394] The memory circuit 700A further includes read bit lines RBL[1] and RBL[2] (collectively referred to as "read bit line group RBL").

[0395] The read bit line group RBL extends in the second direction Y. In some embodiments, the read bit line group RBC is similar to the bit line group BL, and thus the similar detailed description is omitted.

[0396] In some embodiments, the read bit lines RBL[1] and RBL[2] are similar to Figure 2B the corresponding read bit lines RBL[1] and RBL[2], and thus the similar detailed description is omitted.

[0397] The read bit line RBL[1] overlaps with the memory cells 701a and 701c. The read bit line RBL[1] is electrically connected to the memory cell 701a through the via 704g. The read bit line RBL[1] is electrically connected to the memory cell 701c through the via 704i.

[0398] The read bit line RBL[2] overlaps with the memory cells 701b and 701d. The read bit line RBL[2] is electrically connected to the memory cell 701b through the via 704h. The read bit line RBL[2] is electrically connected to the memory cell 701d through the via 704j.

[0399] In some embodiments, the read bit line group RBL is located in the M2 layer of at least one of the memory circuits 700A and 700B. In some embodiments, the read bit line group RBL is located in the M1 layer of at least one of the memory circuits 700A and 700B. Other metal layers for the read bit line group RBL are also within the scope of the present disclosure.

[0400] Other configurations of the read bit line group RBL, arrangements on other metal layers, or the number of read bits are within the scope of the present disclosure.

[0401] The memory circuit 700A also includes one or more of vias 402a, 402b, 402c, 402d, 402e, and 402f (collectively referred to as "via group 702").

[0402] In some embodiments, the via group 702 is similar to Figure 4A the via group 402, and thus the similar detailed description is omitted.

[0403] The via group 702 is located between one of the write word line group WWL and the read word line group RWL and the lower layer of the memory cell array 701 (e.g., as shown in FIGS. 5, Figure 6 , Figure 8 or Figure 9 ). In some embodiments, the via group 702 is located between one of the write word line group WWL and the read word line group RWL and at least one of the memory cells 701a, 701b, 701c, or 701d of the memory cell array 701.

[0404] In some embodiments, vias 402a and 402b are located between the write word line WWL[1] or the read word line RWL[1] and the memory cell 701a. In some embodiments, vias 402b and 402c are located between the write word line WWL[1] or the read word line RWL[1] and the memory cell 701b.

[0405] In some embodiments, vias 402d and 402e are located between the write word line WWL[2] or the read word line RWL[2] and the memory cell 701c. In some embodiments, vias 402e and 402f are located between the write word line WWL[2] or the read word line RWL[2] and the memory cell 701d.

[0406] At least other configurations of the via group 702, arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0407] The memory circuit 700A also includes one or more of vias 704a, 704b, 404c, 404d, 704e, 704f, 704g, 704h, 704i, and 704j (collectively referred to as "via group 704").

[0408] In some embodiments, the via group 704 is similar to Figure 4A the via group 404, and thus the similar detailed description is omitted. In some embodiments, at least one of the vias 704a, 704b, 704e, 704g, 704h, 704i, and 704j is similar to Figure 4A at least one or more of the vias 404a, 404b, 404c, 404d, 404e, and 404f of the via group 404, and thus the similar detailed description is omitted.

[0409] The via group 704 is located between at least one of the bit line group BL, the anti-phase line group BLB, and the read bit line group RBL and the bottom layer of the memory cell array 701 (e.g., as shown in FIGS. 5, Figure 6 , Figure 8 or Figure 9 ). In some embodiments, the via group 704 is located between at least one of the bit line group BL, the anti-phase line group BLB, and the read bit line group RBL and at least one of the memory cells 701a, 701b, 701c, or 701d of the memory cell array 701.

[0410] In some embodiments, the via 704a is located between the anti-phase line BLB[1] and the memory cells 701a and 701c.

[0411] In some embodiments, the via 704b is located between the bit line BL[1] and the memory cell 701a, and the via 704e is located between the bit line BL[1] and the memory cell 701c.

[0412] In some embodiments, the via 704g is located between the read bit line RBL[1] and the memory cell 701a, and the via 704i is located between the upper read bit line RBL[1] and the memory cell 701c.

[0413] In some embodiments, the via 704h is located between the read bit line RBL[2] and the memory cell 701b, and the via 704j is located between the upper read bit line RBL[2] and the memory cell 701d.

[0414] In some embodiments, the via 404d is located between the bit line BL[2] and the memory cells 701b and 701d.

[0415] In some embodiments, the via 404c is located between the anti-phase line BLB[2] and the memory cell 701b, and the via 404f is located between the anti-phase line BLB[2] and the memory cell 701d.

[0416] At least other configurations of the via group 704, the arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0417] Other configurations of the memory circuit 700A are also within the scope of the present disclosure.

[0418] Figure 7B is a schematic diagram of a memory circuit 700B according to some embodiments.

[0419] The memory circuit 700B relates to Figure 2B a memory cell array 202. The memory circuit 700B is Figure 2B an embodiment of the region 201b of the memory circuit 200B of Figure 2B , and thus similar detailed descriptions are omitted. In some embodiments, the memory circuit 700B is an embodiment of a region of the memory circuit 200B other than the region 201b of the memory circuit 200B of

[0420] The memory circuit 700B is Figure 4C a variant of the memory circuit 400C of Figure 7A or the memory circuit 700A of Figure 4C , and thus similar detailed descriptions are omitted. Compared with the memory circuit 400C of Figure 7B , the memory cell array 721 of Figure 4C replaces the memory cell array 421 of

[0421] The memory circuit 700B includes a memory cell array 721. The memory cell array 721 is similar to the memory cell array 202 of Figure 2B , the memory cell array 421 of Figure 4C , or the memory cell array 701 of Figure 7A , and thus similar detailed descriptions are omitted.

[0422] The memory cell array 721 includes memory cells 721a, 721b, 721c, and 721d. In some embodiments, at least one of the memory cells 721a, 721b, 721c, and 721d is similar to at least one of the memory cells 401a, 401b, 401c, and 401d of the memory cell array 401 of Figure 4A or at least one of the memory cells 411a, 411b, 411c, and 411d of the memory cell array 411 of Figure 4B , and thus similar detailed descriptions are omitted.

[0423] The memory cell 721a (also labeled "Cell 1" in Figure 7B ) is located in row 1 and column 1 of the memory cell array 721, and is identified as "r1c1" in Figure 7B . The memory cell 721b (in Figure 7AAlso referred to as “Cell 2” in [ ], is located at row 2 and column 1 of the memory cell array 721, and is identified as “r2c1” in Table 7B. Memory cell 721c (in Figure 7B Also referred to as “Cell 3” in [ ], is located at row 1 and column 2 of the memory cell array 721, and in Figure 7B It is identified as “r1c2”. Memory cell 721d (in Figure 7B Also referred to as “Cell 4” in [ ] is located at row 2 and column 2 of the memory cell array 721, and in Figure 7B It is identified as “r2c2”. In some embodiments, a portion of memory cell 721b (e.g., memory cell portion 721b2) is located in r1c1. In some embodiments, a portion of memory cell 721d (e.g., memory cell portion 721d2) is located in r1c2.

[0424] The memory cell array 721 is shown as a 2×2 memory cell array in Figure 7B Other numbers of rows and columns are also within the scope of the present disclosure.

[0425] The memory cell array 721 has a height H3b in the first direction X. In some embodiments, the height H3b is equal to 2CH + 2RP, where 0.5CH is the scaled cell height of at least one of the memory cells 721b and 721d of the memory cell array 721 in the first direction X, and RP is Figure 9[[ The cell height of at least one of the regions 901b in the first direction X.

[0426] The memory cell array 721 has a width W3b in the second direction Y. In some embodiments, the width W3b is equal to 2CW, where 2CW is the scaled cell width of at least one of the memory cell arrays 721a, 721b, 721c, and 721d in the second direction Y.

[0427] In some embodiments, the width of the memory cell array 721 in the second direction Y is equal to 4 contact polysilicon pitches (e.g., 4CPP).

[0428] In some embodiments, the memory cell array 721 has an aspect ratio AR1a equal to ((CH + RP) / CW) (e.g., W3b / H3b).

[0429] In some embodiments, the memory cells 721a, 721b, 721c, and 721d are similar to ​ The corresponding memory cells MCB in the same corresponding rows and same corresponding columns of the region 201b, and thus similar detailed descriptions are omitted. In some embodiments, each of the memory cells 721a, 721b, 721c, and 721d is ​ The memory cell 300B of [ ], and thus similar detailed descriptions are omitted.

[0430] In some embodiments, the memory cell 721b is divided into a memory cell portion 721b1 and a memory cell portion 721b2. In some embodiments, the memory cell portion 721b2 is located at a corner of the region 750. In some embodiments, the memory cell portion 721b1 corresponds to ​ the memory circuit 600 in ​ and the region 901a in ​ In some embodiments, the memory cell portion 721b2 corresponds to

[0431] In some embodiments, the memory cell 721d is divided into a memory cell 721d1 and a memory cell 721d2. In some embodiments, the memory cell portion 721d2 is located at a corner of the region 752. In some embodiments, the memory cell portion 721d1 corresponds to ​ the memory circuit 600 in ​ and the region 901a in ​ In some embodiments, the memory cell portion 721d2 corresponds to

[0432] The memory circuit 700B further includes at least one of the bit line group BL, the anti-phase line group BLB, the read bit line group RBL, the write word line group WWL, and the read word line group RWL.

[0433] The bit line BL[1] overlaps with the memory cell 721a. The bit line BL[1] is electrically connected to the memory cell 721a through the via 724a. In some embodiments, the bit line BL[1] is electrically connected to the memory cell 721a and the memory cell 721b (not shown), and the bit line BL[1] is shared between the memory cell 721a and the memory cell 721b. In other words, adjacent memory cells (e.g., the memory cells 721b and 721a) in the memory circuit 700B are configured to share the BL with each other.

[0434] The anti-phase line BLB[1] overlaps with the memory cell 721b.

[0435] The anti-phase line BLB[1] is electrically connected to the memory cell 721b through the via 724c. In some embodiments, the anti-phase line BLB[1] is electrically connected to the memory cell 721b and the memory cell 721a (not shown), and the anti-phase line BLB[1] is shared between the memory cell 721b and the memory cell 721a. In other words, adjacent memory cells (e.g., the memory cells 721b and 721a) in the memory circuit 700B are configured to share the BLB with each other.

[0436] The anti-phase line BLB[2] overlaps with the memory cell 721d. The anti-phase line BLB[2] is electrically connected to the memory cell 721d through the via 724g. In some embodiments, the anti-phase line BLB[2] is electrically connected to the memory cell 721d and the memory cell 721c (not shown), and the anti-phase line BLB[2] is shared between the memory cell 721d and the memory cell 721c. In other words, adjacent memory cells (e.g., memory cells 721d and 721c) in the memory circuit 700B are configured to share the BLB with each other.

[0437] The bit line BL[2] overlaps with the memory cell 721c. The bit line BL[2] is electrically connected to the memory cell 721c through the via 724e. In some embodiments, the bit line BL[2] is electrically connected to the memory cell 721c and the memory cell 721d (not shown), and the bit line BL[2] is shared between the memory cell 721c and the memory cell 721d. In other words, adjacent memory cells (e.g., memory cells 721d and 721c) in the memory circuit 700B are configured to share the BL with each other.

[0438] Other configurations of the bit line group BL, arrangements on other metal layers, or the number of bit lines are within the scope of the present disclosure.

[0439] Other configurations of the anti-phase line BLB group, arrangements on other metal layers, or the number of anti-phase lines are within the scope of the present disclosure.

[0440] The read bit line RBL[1] overlaps with the memory cell 721a and the memory cell portion 721b2. The read bit line RBL[1] is electrically connected to the memory cell 721a through the via 724b. The read bit line RBL[1] is electrically connected to the memory cell portion 721b2 of the memory cell 721b through the via 724d.

[0441] In some embodiments, the read bit line RBL[1] is electrically connected to the memory cell 721a and the memory cell 721b, and the read bit line RBCL[1] is shared between the memory cell 721a and the memory cell 721b. In other words, adjacent memory cells (e.g., memory cells 721b and 721a) in the memory circuit 700B are configured to share the RBL with each other.

[0442] The read bit line RBL[2] overlaps with the memory cell 721c and the memory cell portion 721d2. The read bit line RBL[2] is electrically connected to the memory cell 721c through the via 724f. The read bit line RBL[2] is electrically connected to the memory cell portion 721d2 of the memory cell 721d through the via 724h.

[0443] In some embodiments, read bit line RBL[2] is electrically connected to memory cells 721c and 721d, and read bit line RBC[2] is shared between memory cells 721c and 721d. In other words, adjacent memory cells (e.g., memory cells 721c and 721d) in memory circuit 700B are configured to share RBL with each other.

[0444] Other configurations of the read bit line group RBL, arrangements on other metal layers, or the number of read bit lines are within the scope of the present disclosure.

[0445] Write word line WWL[1] or read word line RWL[1] overlaps with memory cells 721a, 721b, 721c, and 721d. Write word line WWL[1] or read word line RWL[1] is electrically connected to memory cell 721b through via 722b. Write word line WWL[1] or read word line RWL[1] is electrically connected to memory cell 721c through via 722d. Write word line WWL[1] or read word line RWL[1] is electrically connected to memory cell 721d through via 722f.

[0446] Write word line WWL[1] or read word line RWL[1] overlaps with memory cells 721a, 721b, 721c, and 721d. Write word line WWL[2] or read word line RWL[2] is electrically connected to memory cell 721a through via 722a. Write word line WWL[2] or read word line RWL[2] is electrically connected to memory cell 721c through via 722c. Write word line WWL[2] or read word line RWL[2] is electrically connected to memory cell 721d through via 722e.

[0447] In some embodiments, by staggering the WWL / RWL groups and sharing BL or BLB between adjacent memory cells, memory circuit 700B has the same aspect ratio ((CH+RP) / CW) as memory circuit 700A, thereby forming a more flexible cell compared to other methods.

[0448] Other configurations of the word line group WL, arrangements on other metal layers, or the number of word lines are within the scope of the present disclosure.

[0449] Memory circuit 700B further includes one or more of vias 722a, 722b, 722c, 722d, 722e, and 722f (collectively referred to as "via group 722").

[0450] In some embodiments, via group 722 is similar to ​The through - hole group 702, so a similar detailed description is omitted. In some embodiments, at least one of the through - holes 722a, 722b, 722c, 722d, 722e, and 722f is similar to one of the through - holes 402a, 402b, 402c, 402d, 402e, and 402f, so a similar detailed description is omitted.

[0451] In some embodiments, the through - hole 722b is located between the write word line WWL[1] or the read word line RWL[1] and the memory cell 721b. In some embodiments, the through - hole 722d is located between the write word line WWL[1] or the read word line RWL[1] and the memory cell 721c. In some embodiments, the through - hole 722f is located between the write word line WWL[1] or the read word line RWL[1] and the memory cell 721d.

[0452] In some embodiments, the through - hole 722a is located between the write word line WWL[2] or the read word line RWL[2] and the memory cell 721a. In some embodiments, the through - hole 722c is located between the write word line WWL[2] or the read word line RWL[2] and the memory cell 721c. In some embodiments, the through - hole 722e is located between the write word line WWL[2] or the read word line RWL[2] and the memory cell 721d.

[0453] At least other configurations of the through - hole group 722, arrangements on other layers, or the number of through - holes are within the scope of the present disclosure.

[0454] The memory circuit 700B further includes one or more of the through - holes 724a, 724b, 724c, 724d, 724e, 724f, 724g, and 724h (collectively referred to as "through - hole group 724").

[0455] In some embodiments, the through - hole group 724 is similar to ​ the through - hole group 404 or ​ the through - hole group 704, so a similar detailed description is omitted. In some embodiments, at least one of the through - holes 724a, 724b, 724c, 724d, 724e, 724f, 724g, and 724h is similar to ​ at least one or more of the through - holes 404a, 404b, 404c, 404d, 404e, and 404f of the through - hole group 404, or ​ at least one or more of the through - holes 704a, 704b, 404c, 404d, 704e, 404f, 704g, 704h, 704i, and 704j of the through - hole group 704, so a similar detailed description is omitted.

[0456] In some embodiments, via 724a is located between bit line BL[1] and memory cell 721a.

[0457] In some embodiments, via 724c is located between complementary bit line BLB[1] and memory cell 721b.

[0458] In some embodiments, via 724b is located between read bit line RBL[1] and memory cell 721a.

[0459] In some embodiments, via 724d is located between read bit line RBL[1] and memory cell portion 721b2 of memory cell 721b.

[0460] In some embodiments, via 724f is located between read bit line RBL[2] and memory cell 721c.

[0461] In some embodiments, via 724h is located between read bit line RBL[2] and memory cell portion 721d2 of memory cell 721d.

[0462] In some embodiments, via 724e is located between bit line BL[2] and memory cell 721c.

[0463] In some embodiments, via 724g is located between complementary bit line BLB[2] and memory cell 721d.

[0464] At least other configurations of via group 724, arrangements on other layers, or the number of vias are within the scope of the present disclosure.

[0465] Other configurations of memory circuit 700B are also within the scope of the present disclosure.

[0466] ​ is a corresponding schematic diagram of a corresponding memory circuit 800 according to some embodiments.

[0467] Memory circuit 800 relates to ​ memory cell array 202. Memory circuit 800 is ​ an embodiment of a memory cell (e.g., memory cell 701a, 701b, 701c, or 701d) of memory cell array 701, and thus similar detailed descriptions are omitted.

[0468] Memory circuit 800 is ​ a variant of memory circuit 500A, and thus similar detailed descriptions are omitted. Compared with ​ memory circuit 500A, memory circuit 800 further includes region 810, and thus similar detailed descriptions are omitted.

[0469] The memory circuit 800 is fabricated through a corresponding layout design similar to that of the memory circuit 800.

[0470] The memory circuit 800 has a height H4a in the first direction X. In some embodiments, the height H4a is equal to CH + RP, where CH is the scaled cell height of at least the circuit 800 in the first direction X and RP is the cell height of at least the region 810 in the first direction X.

[0471] The memory circuit 800 has a width W4a in the second direction Y. In some embodiments, the width W4a is equal to CW, where CW is the scaled cell width of at least the memory circuit 800 in the second direction Y.

[0472] In some embodiments, the width of the memory circuit 800 in the second direction Y is equal to 2 contact polysilicon pitches (e.g., 2CPP).

[0473] In some embodiments, the memory circuit 800 can be used as ​ at least one of the memory cells 701a, 701b, 701c, or 701d of the memory cell array 701, and thus similar detailed descriptions are omitted.

[0474] The memory circuit 800 includes a memory circuit 500A and a region 810. The memory circuit 500A is adjacent or directly adjacent to the region 810.

[0475] The region 810 has a height RP in the first direction X.

[0476] The region 810 includes an active region 802e.

[0477] The active region group 802 includes one or more of the active regions 502a, 502b, 502c, 502d, and 802e.

[0478] In some embodiments, the active region group 802 is similar to ​ the active region group 502, and thus similar detailed descriptions are omitted. In some embodiments, the active region 802e is similar to ​ one or more of the active regions 502a, 502b, 502c, and 502d of the active region group 502, and thus similar detailed descriptions are omitted.

[0479] In some embodiments, the active region group 802 is fabricated from corresponding active region pattern groups (not shown) of the respective layout designs of memory circuits 500A to 500B, 600, 800, or 900. In some embodiments, the active region 802e of the active region group 802 is fabricated from corresponding active region patterns in the active region patterns (not shown) of the respective layout designs of memory circuits 500A to 500B, 600, 800, or 900.

[0480] In some embodiments, the active region 802e is the source and drain of an NFET transistor of at least one of the memory cell 300B or the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0481] In some embodiments, the active region 802e is the source and drain of a PFET transistor of at least one of the memory cell 300B or the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, and 1500.

[0482] Other configurations in the active region group 802, arrangements on other layers, or the number of regions are within the scope of the present disclosure.

[0483] Region 810 further includes at least one of the gates 804e and 804f.

[0484] The gate group 804 includes one or more of the gates 504a, 504b, 504c, 504d, 804e, and 804f.

[0485] In some embodiments, the gate group 804 is similar to ​ the gate group 504, and thus the similar detailed description is omitted. In some embodiments, at least one or more of the gates 804e and 804f are similar to ​ one or more of the gates 504a, 504b, 504c, and 504d of the gate group 504, and thus the similar detailed description is omitted.

[0486] In some embodiments, the gate group 804 is fabricated from corresponding gate pattern groups (not shown) of the respective layout designs of memory circuits 500A to 500B, 600, 800, or 900. In some embodiments, the gate 804e or 804f of the gate group 804 is fabricated from corresponding gate patterns (not shown) of the corresponding gate pattern groups (not shown) of the respective layout designs of memory circuits 500A to 500B, 600, 800, or 900.

[0487] In some embodiments, each gate in gate group 804 is shown in FIGS. 5, ​ , ​ and ​ and is labeled as "N2-1, P2-1, N2-2, P2-2, N2-3, N2-4, N2-5, N2-6" for identifying ​ , ​ and ​ the corresponding transistors in , and , and these labels are omitted for brevity.

[0488] Other configurations of gate group 804, arrangements on other layers, or the number of gates are also within the scope of the present disclosure.

[0489] In some embodiments, at least one via in via group 702 is electrically connected to at least one gate in gate group 804. In some embodiments, at least one via in via group 704 is electrically connected to at least one gate in gate group 804.

[0490] In some embodiments, at least one via in via group 702 is electrically connected to at least one active region in active region group 802. In some embodiments, at least one via in via group 704 is electrically connected to at least one active region in active region group 802.

[0491] Other configurations of memory circuit 800 are also within the scope of the present disclosure.

[0492] ​ is a corresponding schematic diagram of a corresponding memory circuit 900 according to some embodiments.

[0493] Memory circuit 900 relates to ​ the storage cell array 202 of . Memory circuit 900 is ​ an embodiment of storage cells 721b and 721a of the storage cell array 721 of , and thus similar detailed descriptions are omitted.

[0494] Memory circuit 900 is ​ a variant of memory circuit 600 of , and thus similar detailed descriptions are omitted. Compared with ​ memory circuit 600 of , memory circuit 900 further includes regions 901a and 901b, and thus similar detailed descriptions are omitted.

[0495] Memory circuit 900 is manufactured through a corresponding layout design similar to that of memory circuit 900.

[0496] The memory circuit 900 has a height H4b in the first direction X. In some embodiments, the height H4b is equal to CH + RP, where CH is the scaled cell height of at least the circuit 900 in the first direction X, and RP is the cell height of at least the region 901b in the first direction X.

[0497] The memory circuit 900 has a width W4b in the second direction Y. In some embodiments, the width W4b is equal to 2CW, where CW is the scaled cell width of at least the memory circuit 900 in the second direction Y.

[0498] In some embodiments, the width of the memory circuit 900 in the second direction Y is equal to 4 contact polysilicon pitches (e.g., 4CPP).

[0499] In some embodiments, the memory circuit 900 can be used as ​ the memory cells 721a and 721b of the memory cell array 721, and thus similar detailed descriptions are omitted. In some embodiments, the memory circuit 900 can be used as ​ the memory cells 721c and 721d of the memory cell array 721, and thus similar detailed descriptions are omitted.

[0500] The memory circuit 900 includes the memory circuit 600, the region 901a, and the region 901b. The memory circuit 600 is adjacent or directly adjacent to the region 901a. The region 901a is adjacent to the region 901b. The region 901a is located between the memory circuit 600 and the region 901b.

[0501] In some embodiments, the region 901a is a mirror image of the memory circuit 600 with respect to the grid line 950 in the second direction Y, and thus similar detailed descriptions are omitted. The grid line 950 extends along the second direction Y.

[0502] The region 901b has a height RP in the first direction X.

[0503] The region 901b includes the region 910a and the region 910b.

[0504] Each of the region 910a and the region 910b has a width CW in the second direction Y.

[0505] The region 910a includes the active region 902a.

[0506] The active region group 902 includes the active region 902a.

[0507] In some embodiments, the active region group 902 is similar to ​ the active region group 602, and thus similar detailed descriptions are omitted. In some embodiments, the active region 902a is similar to ​one or more of the active regions 602a, 602b, 602c, and 602d of the active region group 602, and thus similar detailed descriptions are omitted.

[0508] In some embodiments, the active region group 902 is fabricated by corresponding active region pattern groups (not shown) of the corresponding layout designs of the memory circuits 500A to 500B, 600, 800, or 900. In some embodiments, the active region 902a of the active region group 902 is fabricated by a corresponding active region pattern in the corresponding active region pattern groups (not shown) of the corresponding layout designs of the memory circuits 500A to 500B, 600, 800, or 900.

[0509] In some embodiments, the active region 902a is the source and drain of an NFET transistor of the memory cell 300B or at least one of the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0510] In some embodiments, the active region 902a is the source and drain of a PFET transistor of the memory cell 300B or at least one of the memory circuits 400A, 400B, 400C, 500A to 500B, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300, 1400, or 1500.

[0511] Other configurations in the active region group 902, arrangements on other layers, or the number of regions are also within the scope of the present disclosure.

[0512] The region 910a also includes at least one of the gates 904a and 904b.

[0513] The gate group 904 includes one or more of the gates 904a, 904b, 904c, and 904d.

[0514] In some embodiments, the gate group 904 is similar to ​ the gate group 604, and thus similar detailed descriptions are omitted. In some embodiments, at least one or more of the gates 904a, 904b, 904c, and 904d are similar to ​ one or more of the gates 604a, 604b, 604c, and 604d of the gate group 604, and thus similar detailed descriptions are omitted.

[0515] In some embodiments, the gate group 904 is fabricated from a corresponding group of gate patterns (not shown) of the respective layout designs of the memory circuits 500A to 500B, 600, 800, or 900. In some embodiments, the gates 904a, 904b, 904c, or 904d of the gate group 904 are fabricated from corresponding gate patterns (not shown) of a corresponding group of gate patterns (not shown) of the respective layout designs of the memory circuits 500A to 500B, 600, 800, or 900.

[0516] In some embodiments, FIGS. 5, ​ , ​ and ​ each gate in the gate group 904, labeled "N2-1, P2-1, N2-2, P2-2, N2-3, N2-4, N2-5, N2-6", is shown for identifying ​ , ​ and ​ the corresponding transistors therein, and thus these labels are omitted for brevity.

[0517] Other configurations of the gate group 904, arrangements on other layers, or the number of gates are within the scope of the present disclosure.

[0518] Region 910b includes a portion of the active region 902a and at least one of the gates 904c and 904d. In some embodiments, at least one of the gates 904c and 904d is a gate of a pseudo-transistor. In some embodiments, the portion of the active region 902a located in region 910b is a portion of a pseudo-transistor.

[0519] In some embodiments, at least one via in the via group 722 is electrically connected to at least one gate in the gate group 904. In some embodiments, at least one via in the via group 724 is electrically connected to at least one gate in the gate group 904.

[0520] In some embodiments, at least one via in the via group 722 is electrically connected to at least one active region in the active region group 902. In some embodiments, at least one via in the via group 724 is electrically connected to at least one active region in the active region group 902.

[0521] Other configurations of the memory circuit 900 are also within the scope of the present disclosure.

[0522] ​ is a schematic diagram of a memory circuit 1000 according to some embodiments.

[0523] In some embodiments, the memory circuit 1000 is an integrated circuit chip. In some embodiments, the memory circuit 1000 is ​An embodiment of the memory circuit 100 is thus omitted from the similar detailed description.

[0524] The memory circuit 1000 includes a memory circuit 1002 and a memory circuit 1004.

[0525] In some embodiments, the memory circuit 1000 includes different types of memory circuits, and thus the memory circuit 1000 is referred to as a "hybrid unit".

[0526] In some embodiments, the memory circuit 1002 is ​ the memory circuit 400B, and thus the similar detailed description is omitted. In these embodiments, the memory circuit 1002 is ​ the memory circuit 400B, including ​ one or more replicas of the memory circuit 600, and thus the similar detailed description is omitted. In some embodiments, the memory circuit 1002 is ​ the memory circuit 200A, and thus the similar detailed description is omitted. In some embodiments, the memory circuit 1002 includes one or more regions similar to the region 201a of ​ the memory circuit 200A, and thus the similar detailed description is omitted.

[0527] In some embodiments, the memory circuit 1004 is ​ the memory circuit 400C, and thus the similar detailed description is omitted. In these embodiments, the memory circuit 1004 includes ​ one or more replicas of the memory circuit 600, and thus the similar detailed description is omitted. In some embodiments, the memory circuit 1004 is ​ the memory circuit 200A, and thus the similar detailed description is omitted. In some embodiments, the memory circuit 1004 includes one or more regions similar to the region 201a of ​ the memory circuit 200A, and thus the similar detailed description is omitted.

[0528] The memory circuit 1000 is shown as including one memory circuit 1002 and one memory circuit 1004. In some embodiments, the memory circuit 1000 includes at least two or more memory circuits 1002. In some embodiments, the memory circuit 1000 includes at least two or more memory circuits 1004. Other positions for at least one of the memory circuit 1002 or the memory circuit 1004 in the memory circuit 1000 are within the scope of the present disclosure.

[0529] In some embodiments, the memory circuit 1002 is generated by a first memory compiler. In some embodiments, the memory circuit 1002 is generated by an SRAM memory compiler. Other types of memory compilers are also within the scope of the present disclosure.

[0530] In some embodiments, the memory circuit 1004 is generated by a second memory compiler. In some embodiments, the memory circuit 1004 is generated by an SRAM memory compiler. Other types of memory compilers are also within the scope of the present disclosure.

[0531] The memory circuit 1002 has a height H5a in the second direction Y. In some embodiments, the height H5a is equal to ​ the height H1b of the memory circuit 400B.

[0532] The memory circuit 1002 has a width W5a in the first direction X. In some embodiments, the width W5a is equal to Figure 4B the width W1b of the memory circuit 400B.

[0533] The memory circuit 1004 has a height H5b in the second direction Y. In some embodiments, the height H5b is equal to Figure 4C the height H1c of the memory circuit 400C.

[0534] The memory circuit 1004 has a width W5b in the first direction X. In some embodiments, the width W5b is equal to Figure 4C the width W1c of the memory circuit 400C.

[0535] In some embodiments, the height H5a is different from the height H5b. In some embodiments, the height H5a is the same as the height H5b.

[0536] In some embodiments, the width W5a is different from the width W5b. In some embodiments, the width W5a is the same as the width W5b.

[0537] The memory circuit 1002 includes memory cells 1002a, 1002b, a bit line group BL1, an anti-phase line group BLB1, and a word line group WL1.

[0538] In some embodiments, the memory cell 1002a is at least one of the memory cells 411a, 411b, 411c, and 411d in one of columns 1 and 2, and the memory cell 1002b is at least one other of the memory cells 411a, 411b, 411c, and 411d in the other of columns 1 and 2. For ease of illustration, the memory circuit 1002 is shown as including 2 memory cells (memory cells 1002a and 1002b). However, other numbers of memory cells in the memory circuit 1002 are also within the scope of the present disclosure.

[0539] For ease of illustration, the memory circuit 1002 is shown as including 2 columns of memory cells and 2 rows of memory cells. However, other numbers of rows or columns of memory cells in the memory circuit 1002 are also within the scope of the present disclosure.

[0540] The memory circuit 1004 includes a memory cell 1004 a , a memory cell 1004 b , a bit line group BL2 , a bar bit line group BLB2 , and a word line group WL2 .

[0541] In some embodiments, memory cell 1004a is at least one of memory cells 421a, 421b, 421c, and 421d in one of columns 1 and 2, and memory cell 1004b is at least another of memory cells 421a, 421b, 421c, and 421d in another of columns 1 and 2. For ease of illustration, memory circuit 1004 is shown as including 2 memory cells (memory cells 1004a and 1004b). However, other numbers of memory cells in memory circuit 1004 are also within the scope of the present disclosure.

[0542] For ease of illustration, the memory circuit 1004 is shown as including 2 columns of memory cells and 2 rows of memory cells. However, other numbers of rows or columns of memory cells in the memory circuit 1004 are also within the scope of the present disclosure.

[0543] In some embodiments, Figure 10 , Figure 11 and Figure 12 One or more of the bit line groups BL1 or BL2 are similar to Figures 4A to 4C , Figure 6 , Figures 7A to 7B , Figure 8 and Figure 9 The bit line group BL is a set of bit line groups, so similar detailed description is omitted.

[0544] In some embodiments, Figure 10 , Figure 11 and Figure 12 One or more of the inverted bit line groups BLB1 or BLB2 are similar to Figures 4A to 4C , Figure 6 , Figures 7A to 7B , Figure 8 and Figure 9 The inverted bit line group BLB is provided, and thus similar detailed description is omitted.

[0545] In some embodiments, Figure 10 , Figure 11 and Figure 12 One or more word line groups WL1 or WL are similar to Figures 4A to 4C , Figure 6 ,Figures 7A to 7B , Figure 8 and Figure 9 the word line groups WL, and thus similar detailed descriptions are omitted.

[0546] The word line group WL1 has a length L1a in the second direction Y.

[0547] The bit line group BL1 and the anti-phase bit line group BLB1 have a length L1b in the first direction X.

[0548] In some embodiments, the length L1a of the word line group WL1 is greater than the length L1b of the bit line group BL1 and the length L1b of the anti-phase bit line group BLB1. In some embodiments, a memory circuit such as the memory circuit 1002 is referred to as a "tall cell" (and also has a "tall footprint") because the length L1a of the word line group WL1 is greater than the length L1b of the bit line group BL1 and the length L1b of the anti-phase bit line group BLB1. In some embodiments, since the length L1a of the word line group WL1 is greater than the length L1b of the bit line group BL1 and the length L1b of the anti-phase bit line group BLB1, the word line group WL1 is referred to as "long".

[0549] The word line group WL2 has a length L2a in the second direction Y.

[0550] The bit line group BL2 and the anti-phase bit line group BLB2 have a length L2b in the first direction X.

[0551] In some embodiments, the length L2a of the word line group WL2 is less than the length L2b of the bit line group BL2 and the length L2b of the anti-phase bit line group BLB2. In some embodiments, a memory circuit such as the memory circuit 1004 is referred to as a "long cell" (and also has a "long footprint") because the length L2a of the word line WL2 is less than the length L2b of the bit line BL2 and the length L2b of the anti-phase bit line BLB2. In some embodiments, since the length L2a of the word line group WL2 is less than the length L2b of the bit line group BL2 and the length L2b of the anti-phase bit line group BLB2, the bit line group BL2 or the anti-phase bit line group BLB2 is referred to as "long".

[0552] In some embodiments, the length L1a of the word line group WL1 is greater than the length L2a of the word line group WL2.

[0553] In some embodiments, at least one of the length L1b of the bit line group BL1 and the length L1b of the anti-phase bit line group BLB1 is less than at least one of the length L2b of the bit line group BL2 and the length L2b of the anti-phase bit line group BLB2.

[0554] In some embodiments, the memory circuit 1000 includes different memory circuits (e.g., memory circuit 1002 and memory circuit 1004) having different corresponding dimensions (e.g., tall cells and long cells) in the same direction, and thus the memory circuit 1000 is referred to as a "hybrid cell arrangement". In some embodiments, memory circuits (e.g., memory circuit 1002 and memory circuit 1004) having different corresponding dimensions in the same direction have different corresponding resistance and capacitance characteristics (e.g., as shown in Table 1 below). In some embodiments, the different characteristics of the memory circuit 1000 include one or more of the resistance of the bit line or anti-phase line, the resistance of the word line, the capacitance of the bit line or anti-phase line, and the capacitance of the word line.

[0555] In some embodiments, by using the memory circuits 1002 and 1004 with different corresponding characteristics (e.g., the resistance of the bit line or anti-phase line, the resistance of the word line, the capacitance of the bit line or anti-phase line, the capacitance of the word line), the design of the memory circuit 1000 is more flexible than other methods with the same type of cells having the same characteristics, and the performance of the memory circuit 1000 is greater than other methods. In some embodiments, compared with other methods with the same type of cells having the same characteristics, memory circuits (e.g., memory circuit 1002 and memory circuit 1004) having different corresponding dimensions in the same direction have optimized corresponding resistance and capacitance characteristics and result in better performance than other methods.

[0556] In some embodiments, Table 1 shows the word line resistance (WL-R), word line capacitance (WL-C), bit line or anti-phase line resistance (BL-R), and bit line or anti-phase line capacitance (BL-C) of each of the memory circuit 1002 (e.g., labeled "4CPP"), memory circuit 1004 (e.g., labeled "Pseudo-4CPP"), and memory circuit 1102 (e.g., labeled "2CPP", as Figure 11 shown).

[0557] Table 1 is a table of different cells and parameters of the memory circuit 1002 (e.g., labeled "4CPP"), memory circuit 1004 (e.g., labeled "Pseudo-4CPP"), and memory circuit 1102 (e.g., labeled "2CPP", as Figure 11 shown).

[0558] Table 1

[0559] Unit 2CPP 4CPP False - 4CPP Unit height (equivalent) Reference 0.5x 1x Unit width (equivalent) Reference 2x 1x BL - R Reference 1x 0.5x BL - C Reference 2x 1x WL - R Reference 0.5x 1.2x WL - C Reference 0.5x 1.2x

[0560] Table 1 includes 7 rows and 4 columns. The first row includes different cell types. The second row includes the equivalent cell height of the corresponding cells. The third row includes the equivalent cell width of the corresponding cells. The fourth row includes the bit line or anti-phase line resistance (BL-R) of the corresponding cells relative to the 2CPP cells. The fifth row includes the bit line or anti-phase line capacitance (BL-C) of the corresponding cells relative to the 2CPP cells. The sixth row includes the word line resistance (WL-R) of the corresponding cells relative to the 2CPP cells. The seventh row includes the word line capacitance (WL-C) of the corresponding cells relative to the 2CPP cells. Other numbers of columns or rows in Table 1 are also within the scope of the present disclosure.

[0561] In some embodiments, the cell entry labeled "2CPP" in Table 1 includes Figure 4A memory circuit 400A of Figure 5A memory circuit 500A of Figure 7A memory circuit 700A of Figure 8 and one or more memory circuits in memory circuit 800 of , so similar detailed descriptions are omitted.

[0562] In some embodiments, the cell entry labeled "4CPP" in Table 1 includes Figure 4B memory circuit 400B of Figure 6 and one or more memory circuits in memory circuit 600 of , so similar detailed descriptions are omitted.

[0563] In some embodiments, the cell entry labeled "fake-4CPP" in Table 1 includes Figure 4C memory circuit 400C of Figure 6 memory circuit 600 of Figure 7B memory circuit 700B of Figure 9 and one or more memory circuits in memory circuit 900 of , so similar detailed descriptions are omitted.

[0564] As shown in Table 1, compared with memory circuit 1004 (e.g., labeled "fake-4CPP"), memory circuit 1002 (e.g., labeled "4CPP") has reduced WL-R or WL-C characteristics.

[0565] As shown in Table 1, compared with memory circuit 1002 (e.g., labeled "4CPP"), memory circuit 1004 (e.g., labeled "fake-4CPP") has reduced BL-R or BL-C characteristics.

[0566] In some embodiments, the memory circuit 1002 can be used in SRAM compilers with high cells or high footprint, and the word line group WL1 of the memory circuit 1002 is also referred to as "long", as described above. For example, in some embodiments, since the memory circuit 1002 can be used in SRAM compilers with high cells or high footprint (e.g., long word line WL1), a memory circuit design with reduced WL-R or WL-C characteristics (e.g., the 4CPP cell in Table 1) is superior to a memory design with reduced BL-R characteristics (e.g., the pseudo-4CPP cell in the table). Thus, even though the memory circuit 1002 has a high footprint (e.g., long word line WL1), the reduced WL-R or WL-C characteristics of the memory circuit 1002 compensate for the longer word line WL1.

[0567] In some embodiments, the memory circuit 1004 can be used in SRAM compilers with long cells or long footprint, and as described above, the bit line group BL2 or the bit line group BLB2 of the memory circuit 1002 is also referred to as "long". For example, in some embodiments, since the memory circuit 1004 can be used in SRAM compilers with long cells or long footprint (e.g., long bit line BL2 or long complementary bit line BLB2), a memory circuit design with reduced BL-R characteristics (e.g., the pseudo-4CPP cell in Table 1) is superior to a memory design with reduced WL-R or WL-C characteristics (e.g., the 4CPP cell in Table 1) in terms of usage. Thus, even though the memory circuit 1004 has a long footprint (e.g., long bit line BL2 or long complementary bit line BLB2), the reduced BL-R characteristics of the memory circuit 1004 compensate for the longer bit line BL2 or complementary bit line BL22.

[0568] In some embodiments, to select the cell type in the memory circuit 1000, engineering trade-offs are made to balance the WL-R, WL-C, BL-R, and BL-C characteristics. In some embodiments, combining the cells of memory circuits with different corresponding characteristics allows the memory circuit 1000 to have better overall performance than a memory circuit with only a single type of storage cell having the same corresponding characteristics. For example, according to some embodiments, the memory circuit 1002 is combined with the memory circuit 1004 such that the memory circuit 1000 includes the reduced WL-R or WL-C characteristics of the memory circuit 1002 in Table 1 and the reduced BL-R characteristics of the memory circuit 1004 in Table 1. In some embodiments, combining different cells of memory circuits with different corresponding characteristics (e.g., memory circuits 1002 and 1004) into the same memory circuit such as the memory circuit 1000 results in more manufacturing steps being required in the manufacturing process of the memory circuit.

[0569] In some embodiments, by combining memory circuit 1002 and memory circuit 1004 in the same memory circuit 1000, the design of memory circuit 1000 is more flexible than other methods for the same type of units with the same type of characteristics, and memory circuit 1000 is superior in performance to other methods. In some embodiments, by combining memory circuit 1002 and memory circuit 1004 in the same memory circuit 1000, the resistance and capacitance characteristics of memory circuit 1000 are optimized compared to other methods for the same type of units with the same type of characteristics, and result in better performance than other methods.

[0570] Other configurations of memory circuit 1000 are also within the scope of the present disclosure.

[0571] Figure 11 is a schematic diagram of a memory circuit 1100 according to some embodiments.

[0572] Memory circuit 1100 is Figure 10 a variant of memory circuit 1000, and thus similar detailed descriptions are omitted. Compared with Figure 10 memory circuit 1000, Figure 10 memory circuit 1002 of Figure 11 is replaced by memory circuit 1102 of

[0573] In some embodiments, memory circuit 1100 is an integrated circuit chip.

[0574] Memory circuit 1100 includes memory circuit 1102 and memory circuit 1004.

[0575] In some embodiments, memory circuit 1100 includes different types of memory circuits, and thus memory circuit 1100 is referred to as a "hybrid unit"

[0576] In some embodiments, memory circuit 1102 is Figure 4A memory circuit 400A of Figure 4A and thus similar detailed descriptions are omitted. In these embodiments, memory circuit 1102 is Figure 5A memory circuit 400A of Figure 2A including one or more replicas of memory circuit 500A of Figure 2A and thus similar detailed descriptions are omitted. In some embodiments, memory circuit 1102 is

[0577] Memory circuit 1100 is shown as including a memory circuit 1102 and a memory circuit 1004. In some embodiments, memory circuit 1100 includes at least two or more memory circuits 1102. In some embodiments, memory circuit 1100 includes at least two or more memory circuits 1004. Other locations in memory circuit 1100 for at least one of memory circuit 1004 and memory circuit 1102 are within the scope of the present disclosure.

[0578] In some embodiments, memory circuit 1102 is generated by a third storage compiler. In some embodiments, memory circuit 1102 is generated by an SRAM storage compiler. Other types of storage compilers are also within the scope of the present disclosure.

[0579] Memory circuit 1102 has a height H5c in the second direction Y. In some embodiments, height H5c is equal to Figure 4A the height H1a of memory circuit 400A.

[0580] Memory circuit 1102 has a width W5c in the first direction X. In some embodiments, width W5c is equal to Figure 4A the width W1a of memory circuit 400A.

[0581] In some embodiments, height H5c is different from height H5b. In some embodiments, height H5c is the same as height H5b.

[0582] In some embodiments, width W5c is different from width W5b. In some embodiments, width W5c is the same as width W5b.

[0583] Memory circuit 1102 includes memory cells 1102a, 1102b, a bit line group BL3, an anti-phase line group BLB3, and a word line group WL3.

[0584] In some embodiments, memory cell 1102a is at least one of memory cells 401a, 401b, 401c, and 401d in one of column 1 and column 2, and memory cell 102b is another one of memory cells 401a, 401b, 401c, and 401d in the other of column 1 and column 2. For ease of illustration, memory circuit 1102 is shown as including 2 memory cells (memory cells 1102a and 1102b). However, other numbers of memory cells in memory circuit 1102 are also within the scope of the present disclosure.

[0585] For ease of illustration, memory circuit 1102 is shown as including 2 columns of memory cells and 2 rows of memory cells. However, other numbers of rows or columns of memory cells in memory circuit 1102 are also within the scope of the present disclosure.

[0586] In some embodiments, Figure 11 or Figure 12 the bit line group BL3 in Figures 4A to 4C 、 Figure 6 、 Figures 7A to 7B 、 Figure 8 and Figure 9 is similar to the bit line group BL, and thus the similar detailed description is omitted.

[0587] In some embodiments, Figure 11 and Figure 12 one or more of the anti-phase line groups BLB3 in Figures 4A to 4C 、 Figure 6 、 Figures 7A to 7B 、 Figure 8 and Figure 9 is similar to the anti-phase line group BLB, and thus the similar detailed description is omitted.

[0588] In some embodiments, Figure 11 and Figure 12 one or more of the word line groups WL3 in Figures 4A to 4C 、 Figure 6 、 Figures 7A to 7B 、 Figure 8 and Figure 9 is similar to the word line group WL, and thus the similar detailed description is omitted.

[0589] The word line group WL3 has a length L3a in the second direction Y.

[0590] The bit line group BL3 and the anti-phase line group BLB3 have a length L3b in the first direction X.

[0591] In some embodiments, the length L3a of the word line group WL3 is greater than the length L3 of the bit line group BL3 and the length L3b of the anti-phase line group BLB3. In some embodiments, a memory circuit such as the memory circuit 1102 is referred to as a "tall cell" (and also has a "tall footprint") because the length L3a of the word line group WL3 is greater than the length L3b of the bit line group BL3 and the length L3b of the anti-phase line group BLB3. In some embodiments, since the length L3a of the word line group WL3 is greater than the length L3b of the bit line group BL3 and the length L3b of the anti-phase line group BLB3, the word line group WL3 is referred to as "long".

[0592] In some embodiments, the length L3a of the word line group WL3 is greater than the length L2a of the word line WL2.

[0593] In some embodiments, at least one of the length L3b of bit line group BL3 and the length L3a of anti-phase line group BLB2 is less than at least one of the length L2b of bit line group BL2 and the length L2b of anti-phase line group BLB2.

[0594] In some embodiments, the memory circuit 1100 includes different memory circuits (e.g., memory circuit 1102 and memory circuit 1004) having different corresponding dimensions (e.g., tall cells and long cells) in the same direction, and thus the memory circuit 1100 is referred to as a "hybrid cell arrangement". In some embodiments, the memory circuits (e.g., memory circuit 1102 and memory circuit 1004) having different corresponding dimensions in the same direction have different corresponding resistance and capacitance characteristics (e.g., as shown in Table 1 above).

[0595] In some embodiments, by using the memory circuits 1102 and 1004 having different corresponding characteristics (e.g., resistance of bit lines or anti-phase lines, resistance of word lines, capacitance of bit lines or anti-phase lines, word line capacitance), the design of the memory circuit 1100 is more flexible than other methods with the same type of units having the same type of characteristics, and the performance of the memory circuit 1100 is greater than other methods. In some embodiments, compared with other methods with the same type of units having the same type of characteristics, the memory circuits (e.g., memory circuit 1102 and memory circuit 1004) having different corresponding dimensions in the same direction have optimized corresponding resistance and capacitance characteristics and result in better performance than other methods.

[0596] As shown in Table 1 above, the memory circuit 1102 (e.g., labeled "2CPP") has reduced WL-R or WL-C characteristics compared to the memory circuit 1004 (e.g., labeled "fake-4CPP").

[0597] As shown in Table 1, the memory circuit 1004 (e.g., labeled "fake-4CPP") has reduced BL-R characteristics compared to the memory circuit 1102 (e.g., labeled "2CPP").

[0598] As shown in Table 1, the memory circuit 1004 (e.g., labeled "fake-4CPP") has similar BL-C characteristics compared to the memory circuit 1102 (e.g., labeled "2CPP").

[0599] In some embodiments, the memory circuit 1102 can be used for SRAM compilers with high cells or high footprint, and the word line group WL3 of the memory circuit 1102 is also referred to as "long", as described above. For example, in some embodiments, since the memory circuit 1102 can be used for SRAM compilers with high cells or high footprint (e.g., long word line WL3), a memory circuit design with reduced WL-R or WL-C characteristics (e.g., the 4CPP cell in Table 1) is superior to a memory line design with reduced BL-R characteristics (e.g., the pseudo-4CPP cell in the table). Thus, even though the memory circuit 1102 has a high footprint (e.g., long word line WL3), the reduced WL-R or WL-C characteristics of the memory circuit 1102 compensate for the longer word line WL3.

[0600] In some embodiments, combining cells of memory circuits with different corresponding characteristics allows the memory circuit 1100 to have better overall performance than a memory circuit having only a single type of memory cell with the same corresponding characteristics. For example, according to some embodiments, the memory circuit 1102 is combined with the memory circuit 1004 such that the memory circuit 1100 includes the reduced WL-R or WL-C characteristics of the memory circuit 1102 in Table 1 and the reduced BL-R characteristics of the memory circuit 1004 in Table 1. In some embodiments, combining different cells of memory circuits with different corresponding characteristics (e.g., memory circuits 1102 and 1004) into the same memory circuit such as the memory circuit 1100 results in a need for more manufacturing steps in the manufacturing process of the memory circuit.

[0601] In some embodiments, by combining the memory circuit 1102 with the memory circuit 1004 in the same memory circuit 1100, the design of the memory circuit 1100 is more flexible than other methods with the same type of cells having the same type of characteristics, and the memory circuit 1100 is superior in performance to other methods. In some embodiments, by combining the memory circuit 1102 with the memory circuit 1004 in the same memory circuit 1100, the resistance and capacitance characteristics of the memory circuit 1100 are optimized compared to other methods with the same type of cells having the same type of characteristics, and result in better performance than other methods.

[0602] Other configurations of the memory circuit 1100 are also within the scope of the present disclosure.

[0603] Figure 12 is a schematic diagram of a memory circuit 1200 according to some embodiments.

[0604] The memory circuit 1200 is Figure 10 the memory circuit 1000 of Figure 11a variant of the memory circuit 1100, and thus similar detailed descriptions are omitted. Compared with Figure 10 the memory circuit 1000, Figure 12 the memory circuit 1200 further includes Figure 11 the memory circuit 1102, and thus similar detailed descriptions are omitted. Compared with Figure 11 the memory circuit 1100, Figure 12 the memory circuit 1200 further includes Figure 10 the memory circuit 1002, and thus similar detailed descriptions are omitted.

[0605] In some embodiments, the memory circuit 1200 is an integrated circuit chip.

[0606] The memory circuit 1200 includes the memory circuit 1002, the memory circuit 1004, and the memory circuit 1102.

[0607] The memory circuit 1200 is shown to include one memory circuit 1002, one memory circuit 1004, and one memory circuit 1102. In some embodiments, the memory circuit 1200 includes at least two or more memory circuits 1002. In some embodiments, the memory circuit 1200 includes at least two or more memory circuits 1004. In some embodiments, the memory circuit 1200 includes at least two or more memory circuits 1102. Other positions for at least one of the memory circuit 1002, the memory circuit 1004, and the memory circuit 1102 in the memory circuit 1200 are within the scope of the present disclosure.

[0608] In some embodiments, at least one of the heights H5a, H5b, and H5c is different from at least another of the heights H5a, H5b, and H5c. In some embodiments, at least one of the heights H5a, H5b, and H5c is the same as at least another of the heights H5a and H5b.

[0609] In some embodiments, at least one of the widths W5a, W5b, and W5c is different from at least another of the widths W5b, W5a, and W5c. In some embodiments, at least one of the widths W5a, W5b, and W5c is the same as at least another of the widths W5a, W5b, and W5c.

[0610] In some embodiments, at least one of the lengths L1a, L2a, and L3a is different from at least another of the lengths L1a, L2a, and L3. In some embodiments, at least one of the lengths L1a, L2a, and L3a is the same as at least another of the lengths L1a, L2a, and L3a.

[0611] In some embodiments, at least one of lengths L1b, L2b, and L3b is different from at least another of lengths L1b, L2b, and L3b. In some embodiments, at least one of lengths L1b, L2b, and L3b is the same as at least another of lengths L1b, L2b, and L3b.

[0612] Memory circuit 1200 realizes one or more advantages discussed herein.

[0613] Other configurations of memory circuit 1200 are also within the scope of the present disclosure.

[0614] Figure 13 is a schematic diagram of memory circuit 1300 according to some embodiments.

[0615] Memory circuit 1300 is Figure 11 a variant of memory circuit 1100 of Figure 11 so similar detailed descriptions are omitted. Compared with Figure 11 memory circuit 1102 of Figure 13 memory circuit 1302 of Figure 11 is replaced by Figure 13 memory circuit 1304 of

[0616] In some embodiments, memory circuit 1300 is an integrated circuit chip.

[0617] Memory circuit 1300 includes memory circuit 1302 and memory circuit 1304.

[0618] In some embodiments, memory circuit 1300 includes different types of memory circuits, so memory circuit 1300 is referred to as a "hybrid unit"

[0619] In some embodiments, memory circuit 1302 is Figure 7A memory circuit 700A of Figure 7A so similar detailed descriptions are omitted. In these embodiments, memory circuit 1302 is Figure 8 memory circuit 700A of Figure 2B including one or more replicas of memory circuit 800 of Figure 2B so similar detailed descriptions are omitted. In some embodiments, memory circuit 1302 is

[0620] In some embodiments, the memory circuit 1304 is Figure 7B the memory circuit 700B, and thus a similar detailed description is omitted. In these embodiments, the memory circuit 1304 includes Figure 9 one or more replicas of the memory circuit 900, and thus a similar detailed description is omitted. In some embodiments, the memory circuit 1304 is Figure 2B the memory circuit 200B, and thus a similar detailed description is omitted. In some embodiments, the memory circuit 1304 includes one or more regions similar to Figure 2B the memory circuit 200B of region 201b, and thus a similar detailed description is omitted.

[0621] The memory circuit 1300 is shown as including a memory circuit 1302 and a memory circuit 1304. In some embodiments, the memory circuit 1300 includes at least two or more memory circuits 1302. In some embodiments, the memory circuit 1300 includes at least two or more memory circuits 1304. Other positions for at least one of the memory circuit 1302 and the memory circuit 1304 in the memory circuit 1300 are within the scope of the present disclosure.

[0622] In some embodiments, the memory circuit 1302 is generated by a fourth storage compiler. In some embodiments, the memory circuit 1302 is generated by an SRAM storage compiler. Other types of storage compilers are also within the scope of the present disclosure.

[0623] In some embodiments, the memory circuit 1304 is generated by a fifth storage compiler. In some embodiments, the memory circuit 1304 is generated by an SRAM storage compiler. Other types of storage compilers are also within the scope of the present disclosure.

[0624] The memory circuit 1302 has a height H6a in the second direction Y. In some embodiments, the height H6a is equal to Figure 7A the height H3a of the memory circuit 700A.

[0625] The memory circuit 1302 has a width W6a in the first direction X. In some embodiments, the width W6a is equal to Figure 7A the width W3a of the memory circuit 700A.

[0626] The memory circuit 1304 has a height H6b in the second direction Y. In some embodiments, the height H6b is equal to Figure 7B the height H3b of the memory circuit 700B.

[0627] The memory circuit 1304 has a width W6b in the first direction X. In some embodiments, the width W6b is equal toFigure 7B the width W3b of the memory circuit 700B.

[0628] In some embodiments, the height H6a is different from the height H6b. In some embodiments, the height H6a is the same as the height H6b.

[0629] In some embodiments, the width W6a is different from the width W6b. In some embodiments, the width W6a is the same as the width W6b.

[0630] The memory circuit 1302 includes memory cells 1302a, memory cells 1302b, a bit line group BL4, an anti-phase line group BLB4, and a word line group WL4.

[0631] In some embodiments, the memory cells 1302a are at least one of the memory cells 701a, 701b, 701c, and 701d in one of columns 1 and 2, and the memory cells 1303b are at least one other in the other of columns 1 and 2. For ease of illustration, the memory circuit 1302 is shown as including 2 memory cells (memory cells 1302a and 1302b). However, other numbers of memory cells in the memory circuit 1302 are also within the scope of the present disclosure.

[0632] For ease of illustration, the memory circuit 1302 is shown as including 2 columns of memory cells and 2 rows of memory cells. However, other numbers of rows or columns of memory cells in the memory circuit 1302 are also within the scope of the present disclosure.

[0633] The memory circuit 1304 includes memory cells 1304a, memory cells 1304b, a bit line group BL5, an anti-phase line group BLB5, and a word line group WL5.

[0634] In some embodiments, the memory cells 1304a are at least one of the memory cells 721a, 721b, 721c, and 721d in one of columns 1 and 2, while the memory cells 1304b are at least one other of the memory cells 721a, 721b, 721c, and 721d in the other of columns 1 and 2. For ease of illustration, the memory circuit 1304 is shown as including 2 memory cells (memory cells 1304a and 1304b). However, other numbers of memory cells in the memory circuit 1304 are also within the scope of the present disclosure.

[0635] For ease of illustration, the memory circuit 1304 is shown as including 2 columns of memory cells and 2 rows of memory cells. However, other numbers of rows or columns of memory cells in the memory circuit 1304 are also within the scope of the present disclosure.

[0636] In some embodiments, Figure 13 and Figure 14One or more bit line groups BL4 or BL5 among them are similar to Figures 7A to 7B , Figure 8 and Figure 9 's bit line group BL, so similar detailed descriptions are omitted.

[0637] In some embodiments, Figure 13 and Figure 14 One or more anti-phase line groups BLB4 or BLB5 among them are similar to Figures 7A to 7B , Figure 8 and Figure 9 's anti-phase line group BLB, so similar detailed descriptions are omitted.

[0638] In some embodiments, Figure 13 and Figure 14 One or more word line groups WL4 or WL5 among them are similar to Figures 7A to 7B , Figure 8 and Figure 9 's word line group WL, so similar detailed descriptions are omitted.

[0639] The word line group WL4 has a length L4a in the second direction Y.

[0640] The bit line group BL4 and the anti-phase line group BLB4 have a length L4b in the first direction X.

[0641] In some embodiments, the length L4a of the word line group WL4 is greater than the length L4b of the bit line group BL4 and the length L4b of the anti-phase line group BLB4. In some embodiments, a memory circuit such as the memory circuit 1302 is referred to as a "high cell" (and also has a "high occupancy space") because the length L4a of the word line group WL4 is greater than the length L4b of the bit line group BL4 and the length L4b of the anti-phase line group BLB4. In some embodiments, since the length L4a of the word line group WL4 is greater than the length L4 of the bit line group BL4 and the length L4b of the anti-phase line group BLB4, the word line group WL4 is referred to as "long".

[0642] The word line group WL5 has a length L5a in the second direction Y.

[0643] The bit line group BL5 and the anti-phase line group BLB5 have a length L5b in the first direction X.

[0644] In some embodiments, the length L5a of the word line group WL5 is less than the length L5b of the bit line group BL5 and the length L5b of the anti-phase line group BLB5. In some embodiments, a memory circuit such as memory circuit 1304 is referred to as a "long cell" (and also has a "long footprint") because the length L5a of the word line WL5 is less than the length L5b of the bit line BL5 and the length L5b of the anti-phase line BLB5. In some embodiments, since the length L5a of the word line group WL5 is less than the length L5b of the bit line group BL5 and the length L5b of the anti-phase line group BLB5, the bit line group BL5 or the anti-phase line group BLB5 is referred to as "long".

[0645] In some embodiments, the length L4a of the word line group WL4 is greater than the length L5a of the word line group WL5.

[0646] In some embodiments, at least one of the length L4b of the bit line BL4 group and the length L4b of the anti-phase line BLB4 group is less than at least one of the length L5b of the bit line group BL5 and the length L5b of the anti-phase line BLB5 group.

[0647] In some embodiments, the memory circuit 1300 includes different memory circuits (e.g., memory circuit 1302 and memory circuit 1304) having different corresponding dimensions (e.g., tall cells and long cells) in the same direction, and thus the memory circuit 1300 is referred to as a "mixed cell arrangement". In some embodiments, the memory circuits (e.g., memory circuit 1302 and memory circuit 1304) having different corresponding dimensions in the same direction have different corresponding resistance and capacitance characteristics (e.g., as described in Table 1 above). In some embodiments, the different characteristics of the memory circuit 1300 include one or more of the resistance of the bit line or anti-phase line, the resistance of the word line, the capacitance of the bit line or anti-phase line, or the capacitance of the word line.

[0648] The memory circuit 1300 achieves one or more of the advantages discussed herein.

[0649] In some embodiments, the word line resistance (WL-R), word line capacitance (WL-C), bit line or anti-phase line resistance (BL-R), and bit line or anti-phase line capacitance (BL-C) of each of the memory circuit 1302 (e.g., labeled "2CPP") and the memory circuit 1304 (e.g., labeled "fake-4CPP") are as shown in Table 1 above. In some embodiments, Table 1 is also a table of different cells and parameters of the memory circuit 1302 (e.g., labeled "2CPP") and the memory circuit 1304 (e.g., labeled "fake-4CPP").

[0650] As shown in Table 1, the memory circuit 1302 has characteristics similar to those of the memory circuit 1102, and thus similar detailed descriptions are omitted.

[0651] As shown in Table 1, the memory circuit 1304 has characteristics similar to those of the memory circuit 1004, and thus similar detailed descriptions are omitted.

[0652] Other configurations of the memory circuit 1300 are also within the scope of the present disclosure.

[0653] Figure 14 is a schematic diagram of a memory circuit 1400 according to some embodiments.

[0654] The memory circuit 1400 is Figure 10 a variant of the memory circuit 1000, Figure 11 a variant of the memory circuit 1100, Figure 12 a variant of the memory circuit 1200, and Figure 13 a variant of the memory circuit 1300, and thus similar detailed descriptions are omitted. Compared with Figure 13 the memory circuit 1300, Figure 13 the memory circuit 1302 is Figure 14 replaced by the memory circuit 1402, Figure 13 and the memory circuit 1304 in Figure 14 is replaced by the memory circuit 1404 in, and thus similar detailed descriptions are omitted.

[0655] The memory circuit 1400 includes a memory circuit 1402 and a memory circuit 1404.

[0656] The memory circuit 1400 is shown as including one memory circuit 1402 and one memory circuit 1404. In some embodiments, the memory circuit 1400 includes at least two or more memory circuits 1402. In some embodiments, the memory circuit 1400 includes at least two or more memory circuits 1404. Other positions in the memory circuit 1400 for at least one of the memory circuit 1402 and the memory circuit 1404 are within the scope of the present disclosure.

[0657] In some embodiments, the memory circuit 1402 is Figure 10 one of the memory circuit 1002, Figure 11 the memory circuit 1102, and Figure 13 the memory circuit 1302, and the memory circuit 1404 is Figure 10 one of the memory circuit 1004 in Figure 13 and the memory circuit 1304 in, and thus similar detailed descriptions are omitted.

[0658] In some embodiments, at least one of the heights H5a, H5b, H5c, H6a, and H6b is different from at least another one of the heights H5a, H5b, H5c, H6a, and H6b. In some embodiments, at least one of the heights H5a, H5b, H5c, H6a, and H6b is the same as at least another one of the heights H5a, H5b, H5c, H6a, and H6b.

[0659] In some embodiments, at least one of the widths W5a, W5b, W5c, W6a, and W6b is different from at least another one of the widths W5a, W5b, W5c, W6a, and W6b. In some embodiments, at least one of the widths W5a, W5b, W5c, W6a, and W6b is the same as at least another one of the widths W5a, W5b, W5c, W6a, and W6b.

[0660] In some embodiments, at least one of the lengths L1a, L2a, L3a, L4a, and L5a is different from at least another one of the lengths L1a, L2a, L3a, L4a, and L5a. In some embodiments, at least one of the lengths L1a, L2a, L3a, L4a, and L5a is the same as at least another one of the lengths L1a, L2a, L3a, L4a, and L5a.

[0661] In some embodiments, at least one of the lengths L1b, L2b, L3b, L4b, and L5b is different from at least another one of the lengths L1b, L2b, L3b, L4b, and L5b. In some embodiments, at least one of the lengths L1b, L2b, L3b, L4b, and L5b is the same as at least another one of the lengths L1b, L2b, L3b, L4b, and L5b.

[0662] Memory circuit 1400 achieves one or more of the advantages discussed herein.

[0663] Other configurations of memory circuit 1400 are also within the scope of the present disclosure.

[0664] Figure 15 is a functional flowchart of a method 1500 for manufacturing an IC device according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1500 shown, and some other processes may be described only briefly herein. Figure 15 shown, and some other processes may be described only briefly herein.

[0665] In some embodiments, other orders of operations of methods 1500 to 1700 are within the scope of the present disclosure. Methods 1500 to 1700 include exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, replaced, reordered, and / or eliminated in accordance with the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of at least methods 1500, 1600, or 1700 are not performed.

[0666] In some embodiments, method 1500 is an embodiment of operation 1604 of method 1600. In some embodiments, methods 1500 to 1700 can be used to manufacture or fabricate at least memory circuits 100, 200A to 200B, 400A to 400C, 500A to 500B, 600, 700A to 700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or memory cells 300A to 300B.

[0667] In operation 1502 of method 1500, a first group of transistors in a first memory cell array is fabricated. In some embodiments, the first memory cell array of method 1500 includes at least one of memory cell arrays 1002, 1102, 1302, and 1402. In some embodiments, the first memory cell array has a first width in a first direction X and a first height in a second direction.

[0668] In some embodiments, the first width of method 1500 is at least one of widths W5a, W5c, and W6a. In some embodiments, the first height of method 1500 is at least one of heights H5a, H5c, and H6a.

[0669] In some embodiments, each memory cell in the first memory cell array includes a first group of transistors in a front side 490a of a substrate 490. In some embodiments, the first group of transistors of method 1500 includes transistors of at least one of memory cell arrays 1002, 1102, 1302, and 1402.

[0670] In some embodiments, the first group of transistors of method 1500 includes one or more transistors of at least one group of active regions 502, 602, 802, and 902.

[0671] In some embodiments, the first group of transistors includes a first number of transistors. In some embodiments, the first number of transistors of method 1500 is 6 or 8.

[0672] In operation 1504 of method 1500, a second set of transistors in a second memory cell array is fabricated. In some embodiments, the second memory cell array of method 1500 includes at least one of memory cell arrays 1004, 1304, and 1404. In some embodiments, the second memory cell array has a second width in a first direction X and a second height in a second direction.

[0673] In some embodiments, the second width of method 1500 is at least one of widths W5b and W6b. In some embodiments, the second height of method 1500 is at least one of heights H5b and H6b.

[0674] In some embodiments, each memory cell in the second memory cell array includes a second set of transistors in a front side 490a of a substrate 490. In some embodiments, the second set of transistors of method 1500 includes transistors of at least one of memory cell arrays 1002, 1102, 1302, and 1402.

[0675] In some embodiments, the second set of transistors of method 1500 includes one or more transistors of at least one set of active regions 502, 602, 802, and 902.

[0676] In some embodiments, the second set of transistors includes a second number of transistors. In some embodiments, the second number of transistors of method 1500 is 6 or 8.

[0677] In some embodiments, the second set of transistors includes a second number of transistors. In some embodiments, the second number of transistors of method 1500 is equal to the first number of transistors of method 1500. In some embodiments, the second number of transistors of method 1500 is different from the first number of transistors of method 1500.

[0678] In operation 1506 of method 1500, a third set of transistors in a third memory cell array is fabricated. In some embodiments, the third memory cell array of method 1500 includes at least one of memory cell arrays 1002, 1004, 1102, 1302, 1304, 1402, and 1404.

[0679] In some embodiments, the third memory cell array has a third width in a first direction X and a third height in a second direction.

[0680] In some embodiments, the third width of method 1500 is at least one of widths W5a, W5b, W5c, W6a, and W6b. In some embodiments, the third height of method 1500 is at least one of heights H5a, H5b, H5c, H6a, and H6b.

[0681] In some embodiments, at least one of the first width, the second width, and the third width is different from at least another of the first width, the second width, and the third width.

[0682] In some embodiments, at least one of the first width, the second width, or the third width is the same as at least another of the first width, the second width, and the third width.

[0683] In some embodiments, at least one of the first height, the second height, and the third height is different from at least another of the first height, the second height, and the third height.

[0684] In some embodiments, at least one of the first height, the second height, and the third height is the same as at least another of the first height, the second height, and the third height.

[0685] In some embodiments, each memory cell in the third memory cell array includes a third set of transistors in the front side 490a of the substrate 490. In some embodiments, the third set of transistors of method 1500 includes transistors of at least one of the memory cell arrays 1002, 1102, 1302, and 1402.

[0686] In some embodiments, the third set of transistors of method 1500 includes one or more transistors of at least one of the active regions 502, 602, 802, and 902.

[0687] In some embodiments, the third set of transistors includes a third number of transistors. In some embodiments, the third number of transistors of method 1500 is 6 or 8.

[0688] In some embodiments, the third number of transistors of method 1500 is equal to at least one of the first number of transistors of method 1500 and the second number of transistors of method 1500. In some embodiments, the third number of transistors of method 1500 is different from at least one of the first number of transistors of method 1500 and the number of transistors of method 1500.

[0689] In some embodiments, one or more of operations 1502, 1504, and 1506 are performed simultaneously. In some embodiments, one or more portions of operations 1502, 1504, and 1506 are performed simultaneously.

[0690] In some embodiments, at least one of operations 1502, 1504, and 1506 includes fabricating source and drain regions of the set of transistors in a first well. In some embodiments, the first well includes at least one of wells 501a, 501b, 501c, and 501d. In some embodiments, the first well includes a p-type dopant. In some embodiments, the p-dopant includes boron, aluminum, or other suitable p-type dopants. In some embodiments, the first well includes an epitaxial layer grown over the substrate. In some embodiments, the epitaxial layer is doped by adding dopants during an epitaxial process. In some embodiments, the epitaxial layer is doped by ion implantation after the epitaxial layer is formed. In some embodiments, the first well is formed by doping the substrate. In some embodiments, the doping is performed by ion implantation. In some embodiments, the dopant concentration of the first well ranges from 1x10 12 atoms / cm 3 to 1x10 14 atoms / cm 3 .

[0691] In some embodiments, the first well includes an n-type dopant. In some embodiments, the n-type dopant includes phosphorus, arsenic, or other suitable n-type dopants. In some embodiments, the range of the n-type dopant concentration is about 1x10 12 atoms / cm 3 to about 1x10 14 atoms / cm 3 .

[0692] In some embodiments, the formation of the source / drain component includes removing a portion of the substrate to form a groove at the edge of the spacer, and then performing a filling process by filling the groove in the substrate. In some embodiments, after removing the pad oxide layer or the sacrificial oxide layer, the groove is etched, for example, by wet etching or dry etching. In some embodiments, an etching process is performed to remove the top surface portion of the active region adjacent to the isolation region (such as the STI region). In some embodiments, the filling process is carried out by an epitaxial or epi process. In some embodiments, the groove is filled using a growth process that is carried out simultaneously with the etching process, wherein the growth rate of the growth process is greater than the etching rate of the etching process. In some embodiments, a combination of a growth process and an etching process is used to fill the groove. For example, a material layer is grown in the groove, and then an etching process is performed on the grown material to remove a portion of the material. Then a subsequent growth process is performed on the etched material until the material in the groove reaches the desired thickness. In some embodiments, the growth process continues until the top surface of the material is higher than the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first well is removed by an isotropic or anisotropic etching process. The etching process selectively etches the first well without etching the gate structure and any spacers. In some embodiments, a reactive ion etching (RIE), wet etching, or other suitable technique is used to perform the etching process. In some embodiments, a semiconductor material is deposited in the groove to form the source / drain component. In some embodiments, an epitaxial process is performed to deposit the semiconductor material in the groove. In some embodiments, the epitaxial process includes a selective epitaxial growth (SEG) process, a CVD process, molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epi process uses gaseous and / or liquid precursors that interact with the components of the substrate. In some embodiments, the source / drain component includes epitaxially grown silicon (epi-Si), silicon carbide, or silicon germanium. In some cases, the source / drain component of the IC device associated with the gate structure is either in-situ doped or undoped during the epitaxial process. When the source / drain component is undoped during the epitaxial process, in some cases, the source / drain component is doped during a subsequent process. The subsequent doping process is achieved by ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes, and / or combinations thereof. In some embodiments, after forming the source / drain component and / or after a subsequent doping process, the source / source component is further exposed to an annealing process.

[0693] In some embodiments, at least one of operations 1502, 1504, and 1506 further includes operation 1502a (not shown). In some embodiments, operation 1502a includes forming contacts for the first group of transistors, the second group of transistors, or the third group of transistors. In some embodiments, the contacts include at least one or more of contacts 506a, 506b, 506c, and 506d.

[0694] In some embodiments, at least one of operations 1502, 1504, and 1506 further includes forming a gate region for the first group of transistors, the second group of transistors, the third group of transistors, or the fourth group of transistors. In some embodiments, the gate regions of method 1500 include gate groups 504, 604, 804, or 904.

[0695] In some embodiments, the gate region is located between the drain region and the source region. In some embodiments, the gate region is located above the first well and the substrate. In some embodiments, fabricating the gate region of at least one of operations 1502, 1504, and 1506 includes performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, the deposition process includes chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other processes suitable for depositing one or more material layers. In some embodiments, fabricating the gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, fabricating the gate region includes forming a gate electrode or a dummy gate electrode. In some embodiments, fabricating the gate region includes depositing or growing at least one dielectric layer, such as a gate dielectric layer. In some embodiments, the gate region is formed using doped or undoped polycrystalline silicon (or polysilicon). In some embodiments, the gate region includes a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0696] In operation 1508 of method 1500, a first group of vias is formed on the front side 490a of substrate 490. In some embodiments, the first group of vias of method 1500 includes at least one or more portions of at least the via group 514. In some embodiments, the first group of vias includes at least one or more vias in the VD layer.

[0697] In some embodiments, operations 1508 and 1510 are performed in the same operation.

[0698] In some embodiments, the first group of vias is electrically connected to at least one of the first group of transistors and the second group of transistors.

[0699] In some embodiments, the first set of vias is electrically connected to at least one of the first set of transistors, the second set of transistors, and the third set of transistors.

[0700] In some embodiments, operation 1508 includes forming a first set of self-aligned contacts (SACs) in an insulating layer on the front side 490a of a substrate or a wafer.

[0701] In operation 1510 of method 1500, a second set of vias is formed on the front side 490a of substrate 490. In some embodiments, the second set of vias of method 1500 includes at least one or more portions of at least the via group 512. In some embodiments, the second set of vias includes at least one or more vias in the VG layer.

[0702] In some embodiments, the second set of vias is electrically connected to at least one of the first set of transistors and the second set of transistors.

[0703] In some embodiments, the second set of vias is electrically connected to at least one of the first set of transistors, the second set of transistors, and the third set of transistors.

[0704] In some embodiments, operation 1510 includes forming a second set of SACs in an insulating layer above the front side 490a of a substrate or a wafer.

[0705] In operation 1512 of method 1500, a first conductive material is deposited on a first metal layer on the front side 490a of the substrate, thereby forming a first set of conductors.

[0706] In some embodiments, the first set of conductors of method 1500 includes at least one conductor in conductor group 520.

[0707] In some embodiments, the first metal layer of method 1500 includes at least one conductor in the M0 layer. In some embodiments, the first metal layer of method 1500 includes at least one conductor in the M1 layer or the M2 layer.

[0708] In some embodiments, the first set of conductors overlaps with a first memory cell array and extends along a first direction X.

[0709] In some embodiments, the first set of conductors is electrically connected to the first set of transistors through the first set of vias or the second set of vias.

[0710] In some embodiments, the first set of conductors is electrically connected to the second set of transistors through the first set of vias or the second set of vias.

[0711] In some embodiments, the first set of conductors is electrically connected to the third set of transistors through the first set of vias or the second set of vias.

[0712] In operation 1514 of method 1500, a third set of vias is formed on the front side 490a of substrate 490. In some embodiments, the third set of vias of method 1500 includes at least one or more portions of at least via groups 402, 412, 422, 702, 722, or 522. In some embodiments, the third set of vias includes at least one or more vias in the V0 layer.

[0713] In some embodiments, the third set of vias is electrically connected to at least one of the first set of transistors, the second set of transistors, and the third set of transistors through at least the first set of conductors.

[0714] In some embodiments, operation 1514 includes forming a third set of SACs in an insulating layer above the front side 490a of the substrate or wafer.

[0715] In operation 1516 of method 1500, a second conductive material is deposited on the second layer of the front side 490a of the substrate, thereby forming at least one of the first set of word lines, the second set of word lines, the third set of word lines, or the second set of conductors.

[0716] In some embodiments, the first set of word lines of method 1500 includes at least one of the word line groups WL1, WL3, WL4, WL, WWL, and RWL.

[0717] In some embodiments, the second set of word lines of method 1500 includes at least one of the word line groups WL2, WL5, WL, WWL, and RWL.

[0718] In some embodiments, the third set of word lines of method 1500 includes at least one of the word line groups WL1, WL2, WL3, WL4, WL5, WL, WWL, and RWL.

[0719] In some embodiments, the second set of conductors of method 1500 includes conductor group 530.

[0720] In some embodiments, the second metal layer of method 1500 includes the M1 layer. In some embodiments, the second metal layer of method 1500 includes at least one of the M0 layer and the M2 layer.

[0721] In some embodiments, the first set of word lines is electrically connected to the first set of transistors through the second set of vias. In some embodiments, the first set of word lines overlaps with the first memory cell array and extends in the second direction Y.

[0722] In some embodiments, the second set of word lines is electrically connected to the second set of transistors through the second set of vias. In some embodiments, the second set of word lines overlaps with the second memory cell array and extends along the second direction Y.

[0723] In some embodiments, the third group of word lines is electrically connected to the third group of transistors through the second group of vias. In some embodiments, the third group of word lines overlaps with the third memory cell array and extends in the second direction Y.

[0724] In operation 1518 of method 1500, a fourth group of vias is formed on the front side 490a of substrate 490. In some embodiments, the fourth group of vias of method 1500 includes at least one or more portions of at least via groups 404, 414, 424, 704, or 724. In some embodiments, the fourth group of vias includes at least one or more vias in the V1 layer.

[0725] In some embodiments, the fourth group of vias is electrically connected to at least one of the first group of transistors, the second group of transistors, and the third group of transistors through at least the first group of conductors or the second group of conductors.

[0726] In some embodiments, operation 1518 includes forming a fourth group of SACs in an insulating layer on the front side 490a of the substrate or wafer.

[0727] In operation 1520 of method 1500, a third conductive material is deposited on the third metal layer on the front side 490a of the substrate, thereby forming at least one of the first group of bit lines, the second group of bit lines, and the third group of bit lines.

[0728] In some embodiments, the first group of bit lines of method 1500 includes at least one of bit line groups BL1, BLB1, BL3, BLB3, BL4, BLB4, BL, BLB, and RBL.

[0729] In some embodiments, the second group of bit lines of method 1500 includes at least one of bit line groups BL2, BLB2, BL5, BLB5, BL, BLB, and RBL.

[0730] In some embodiments, the third group of bit lines of method 1500 includes at least one of bit line groups BL1, BLB1, BL2, BLB2, BL3, BLB3, BL4, BLB4, BL5, BLB5, BL, BLB, and RBL.

[0731] In some embodiments, the third metal layer of method 1500 is different from the first metal layer and the second metal layer. In some embodiments, the third metal layer of method 1500 includes the M2 layer. In some embodiments, the third metal layer of method 1500 includes at least one of the M0 layer, the M1 layer, the M3 layer, and the M4 layer.

[0732] In some embodiments, the first group of bit lines is electrically connected to the first group of transistors through the first group of vias. In some embodiments, the first group of bit lines overlaps with the first memory cell array and extends along the first direction X.

[0733] In some embodiments, a second set of bit lines is electrically connected to a second set of transistors through a first set of vias. In some embodiments, the second set of bit lines overlaps with a second memory cell array and extends along a first direction X.

[0734] In some embodiments, a third set of bit lines is electrically connected to a third set of transistors through a first set of vias. In some embodiments, the third set of bit lines overlaps with a third memory cell array and extends along a first direction X.

[0735] In some embodiments, one or more of operations 1502, 1504, 1506, 1508, 1510, 1512, 1514, 1516, 1518, and 1520 of method 1500 include forming openings in an insulating layer (not shown) on a substrate using a combination of a lithography process and a material removal process. In some embodiments, the lithography process includes patterning a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the lithography process includes forming a hard mask, an anti-reflection structure, or another suitable lithography structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, an RIE process, laser drilling, or another suitable etching process. The openings are then filled with a conductive material, such as copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, the openings are filled using CVD, PVD, sputtering, ALD, or other suitable forming processes.

[0736] In some embodiments, at least one or more of the operations of method 1500 are performed by Figure 19 system 1900. In some embodiments, at least one manufacturing system, including system 1900, performs at least one method, such as method 1500 described above, in whole or in part. One or more of the operations of method 1500 are performed by IC foundry 1940 ( Figure 19 ) to manufacture IC device 1960. In some embodiments, one or more of the operations of method 1500 are performed by manufacturing tool 1952 to manufacture wafer 1942.

[0737] In some embodiments, the conductive material includes copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, the openings and trenches are filled using CVD, PVD, sputtering, ALD, or other suitable forming processes. In some embodiments, after depositing the conductive material in one or more of operations 1508, 1510, 1512, 1514, 1516, 1518, or 1520, the conductive material is planarized to provide a planar surface for subsequent steps.

[0738] In some embodiments, one or more of the operations of methods 1500, 1600, and 1700 are not performed.

[0739] One or more operations of methods 1600 to 1700 are performed by a processing device configured to execute instructions for manufacturing an integrated circuit, such as at least memory circuits 100, 200A to 200B, 400A to 400C, 500A to 500B, 600, 700A to 700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or memory cells 300A to 300B. In some embodiments, one or more operations of methods 1600 to 1700 are performed using the same processing device as that used in different one or more operations of methods 1600 to 1700. In some embodiments, one or more operations of methods 1600 to 1700 are performed using a processing device different from the processing device used for performing different one or more operations of methods 1600 to 1700. In some embodiments, other operation sequences of methods 1500, 1600, or 1700 are within the scope of the present disclosure. At least one of methods 1500, 1600, and 1700 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations in methods 1500, 1600, or 1700 may be appropriately added, replaced, reordered, and / or eliminated according to the spirit and scope of the disclosed embodiments.

[0740] Figure 16 is a flowchart of method 1600 for forming or manufacturing an integrated circuit according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1600 shown, and some other operations may only be briefly described herein. In some embodiments, method 1600 may be used to form an integrated circuit, such as at least memory circuits 100, 200A to 200B, 400A to 400C, 500A to 500B, 600, 700A to 700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or memory cells 300A to 300B. Figure 16 In operation 1602 of method 1600, a layout design of the integrated circuit is generated. Operation 1602 is performed by a processing device (e.g., processor 1802(

[0741] configured to execute instructions for generating the layout design). Figure 18)) Execution. In some embodiments, the layout design of method 1600 includes one or more layout patterns similar to one or more components of at least memory circuits 100, 200A - 200B, 400A - 400C, 500A - 500B, 600, 700A - 700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or memory cells 300A - 300B. In some embodiments, the layout design of the present disclosure employs the Graphic Database System (GDSII) file format. In some embodiments, operation 1602 corresponds to Figure 17 of method 1700.

[0742] In operation 1604 of method 1600, an integrated circuit is fabricated based on the layout design. In some embodiments, operation 1604 of method 1600 includes fabricating at least one mask based on the layout design and fabricating an integrated circuit based on the at least one mask. In some embodiments, operation 1604 corresponds to Figure 15 of method 1500.

[0743] Figure 17 is a flowchart of method 1700 for generating a layout design of an integrated circuit according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the Figure 17 method 1700 shown, and some other processes may only be briefly described herein. In some embodiments, method 1700 is an embodiment of operation 1602 of method 1600. In some embodiments, method 1700 can be used to generate one or more layout patterns similar to one or more components of at least memory circuits 100, 200A - 200B, 400A - 400C, 500A - 500B, 600, 700A - 700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or memory cells 300A - 300B.

[0744] In some embodiments, method 1700 can be used to generate one or more layout patterns having structural relationships including alignment, length, and width, as well as configurations and layers similar to at least integrated circuit memory circuits 100, 200A - 200B, 400A - 400C, 500A - 500B, 600, 700A - 700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or memory cells 300A - 300B. For the sake of brevity, Figure 17 similar detailed descriptions will not be described.

[0745] In operation 1702 of method 1700, a set of active region patterns is generated or placed on a layout design. In some embodiments, the set of active region patterns of method 1700 includes one or more regions similar to active region groups 502, 602, 802, or 902. In some embodiments, the set of active region patterns of method 1700 includes one or more patterns similar to elements in the OD layer.

[0746] In operation 1704 of method 1700, a set of gate patterns is generated or placed on a layout design. In some embodiments, the set of gate patterns of method 1700 includes one or more regions similar to gate groups 504, 604, 804, or 904. In some embodiments, the set of gate patterns of method 1700 includes at least a portion of one or more patterns of insulating pattern group 394. In some embodiments, the set of gate patterns of method 1700 includes one or more patterns similar to elements in the POLY layer.

[0747] In operation 1706 of method 1700, a set of contact patterns is generated or placed on a layout design. In some embodiments, the set of contact patterns of method 1700 includes one or more regions similar to contact pattern set 506. In some embodiments, the set of contact patterns of method 1700 includes one or more patterns similar to elements in the MD layer.

[0748] In operation 1708 of method 1700, a first set of via patterns is generated or placed on a layout design. In some embodiments, the first set of via patterns of method 1700 includes at least one or more via patterns similar to via groups 512 or 514. In some embodiments, the first set of via patterns of method 1700 includes one or more patterns or vias similar to elements in the VD layer or VG layer.

[0749] In operation 1710 of method 1700, a first set of conductive component patterns is generated or placed on a layout design. In some embodiments, the first set of conductive component patterns of method 1700 includes one or more regions similar to conductor group 520. In some embodiments, the first set of conductive component patterns of method 1700 includes one or more patterns similar to elements in the M0 layer.

[0750] In operation 1712 of method 1700, a second set of via patterns is generated or placed on a layout design. In some embodiments, the second set of via patterns of method 1700 includes at least one or more via patterns similar to via groups 402, 412, 422, 702, 722, or 522. In some embodiments, the second set of via patterns of method 1700 includes one or more patterns or vias similar to elements in the V0 layer.

[0751] In operation 1714 of method 1700, a first set of word line patterns is generated or placed on a layout design. In some embodiments, the first set of word line patterns of method 1700 includes one or more patterns similar to word line groups WL, WL1, WL2, WL3, WL4, WL5, WWL, and RWL. In some embodiments, the first set of word line patterns of method 1700 includes one or more patterns similar to elements in the POLY, M0 layer, M1 layer, or M2 layer. In some embodiments, operation 1714 further includes generating or placing a second set of conductive component patterns on the layout design. In some embodiments, the second set of conductive component patterns of method 1700 includes one or more regions similar to conductor group 530. In some embodiments, the second set of conductive component patterns of method 1700 includes one or more patterns similar to elements in the M1 layer.

[0752] In operation 1716 of method 1700, a third set of via patterns is generated or placed on the layout design. In some embodiments, the third set of via patterns of method 1700 includes at least one or more via patterns similar to via groups 404, 414, 424, 704, or 724. In some embodiments, the third set of via patterns of method 1700 includes one or more patterns or vias similar to elements in the V1 layer.

[0753] In operation 1718 of method 1700, a first set of bit line patterns or a first set of anti-phase line patterns is generated or placed on the layout design. In some embodiments, the first set of bit line patterns or the first set of anti-phase line patterns of method 1700 includes one or more patterns similar to bit line groups or anti-phase line groups BL, BLB, BL1, BLB1, BL2, BLB2, BL3, BLB3, BL4, BLB4, BL5, or BLB5. In some embodiments, the second set of word line patterns of method 1700 includes one or more patterns similar to elements in the M0 layer, M1 layer, or M2 layer.

[0754] In operation 1720 of method 1700, a second set of bit line patterns or a second set of anti-phase line patterns is generated or placed on the layout design. In some embodiments, the second set of bit line patterns or the second set of anti-phase line patterns of method 1700 includes one or more patterns similar to the read bit line group RBL. In some embodiments, the second set of bit line patterns of method 1700 includes one or more patterns similar to elements in the M0 layer, M1 layer, or M2 layer.

[0755] Figure 18 It is a schematic diagram of a system 1800 for designing an IC layout design and manufacturing an IC circuit according to some embodiments.

[0756] In some embodiments, system 1800 generates or places one or more IC layout designs described herein. System 1800 includes a hardware processor 1802 and a non-transitory computer-readable storage medium 1804 (e.g., memory 1804) that encodes computer program code 1806, i.e., a set of executable instructions 1806, for storing the computer program code. The computer-readable storage medium 1804 is configured to interface with a manufacturing machine for producing integrated circuits. The processor 1802 is electrically connected to the computer-readable storage medium 1804 via a bus 1808. The processor 1802 is also electrically coupled to an I / O interface 1810 via the bus 1808. A network interface 1812 is also electrically connected to the processor 1802 via the bus 1808. The network interface 1812 is connected to a network 1814 such that the processor 1802 and the computer-readable storage medium 1804 can be connected to external components via the network 1814. The processor 1802 is configured to execute the computer program code 1806 (also referred to as "instructions" or "non-transitory instructions") encoded in the computer-readable storage medium 1804 to enable the system 1800 to perform some or all of the operations described in methods 1600 to 1700.

[0757] In some embodiments, the processor 1802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0758] In some embodiments, the computer-readable storage medium 1804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1804 includes semiconductor or solid state memory, magnetic tape, removable computer disks, random access memory (RAM), read only memory (ROM), rigid disks, and / or optical disks. In some embodiments using optical disks, the computer-readable storage medium 1804 includes compact disk read only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0759] In some embodiments, the computer-readable storage medium 1804 stores computer program code 1806 that is configured to cause the system 1800 to execute methods 1600 to 1700. In some implementations, the computer-readable storage medium 1804 also stores information required to execute methods 1600 to 1700 and information generated during the execution of methods 1600 to 1700, such as layout design 1816, user interface 1818, and manufacturing unit 1820, and / or a set of executable instructions for operating methods 1600 to 1700. In some embodiments, the layout design 1816 includes one or more layout patterns similar to one or more components of at least memory circuits 100, 200A to 200B, 400A to 400C, 500A to 500B, 600, 700A to 700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or storage units 300A to 300B.

[0760] In some embodiments, the computer-readable storage medium 1804 stores instructions (e.g., computer program code 1806) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 1806) enable the processor 1802 to generate manufacturing instructions readable by the manufacturing machine to effectively implement methods 1600 to 1700 in a manufacturing process.

[0761] The system 1800 includes an I / O interface 1810. The I / O interface 1810 is connected to an external circuit. In some embodiments, the I / O interface 1810 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for passing information and commands to the processor 1802.

[0762] The system 1800 also includes a network interface 1812 connected to the processor 1802. The network interface 1812 allows the system 1800 to communicate with a network 1814 to which one or more other computer systems are connected. The network interface 1812 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-2094. In some embodiments, methods 1600 to 1700 are implemented in two or more systems 1800, and information such as layout design and user interface is exchanged between different systems 1800 via the network 1814.

[0763] System 1800 is configured to receive information related to a layout design via I / O interface 1810 or network interface 1812. This information is transmitted via bus 1808 to processor 1802 to determine a layout design for generating at least memory circuits 100, 200A to 200B, 400A to 400C, 500A to 500B, 600, 700A to 700B, 800, 900, 1000, 1100, 1200, 1300, or 1400 or memory cells 300A to 300B. The layout design is then stored as layout design 1816 in computer-readable storage medium 1804. System 1800 is configured to receive information related to a user interface via I / O interface 1810 or network interface 1812. This information is stored as user interface 1818 in computer-readable storage medium 1804. System 1800 is configured to receive information related to manufacturing unit 1820 via I / O interface 1810 or network interface 1812. This information is stored as manufacturing unit 1820 in computer-readable storage medium 1804. In some embodiments, manufacturing unit 1820 includes manufacturing information used by system 1800. In some embodiments, manufacturing unit 1820 corresponds to Figure 19 mask manufacturing 1934.

[0764] In some embodiments, methods 1600 to 1700 are implemented as stand-alone software applications executed by a processor. In some embodiments, methods 1600 to 1700 are implemented as software applications that are part of an additional software application. In some embodiments, methods 1600 to 1700 are implemented as plug-ins of a software application. In some embodiments, methods 1600 to 1700 are implemented as software applications that are part of an EDA tool. In some embodiments, methods 1600 to 1700 are implemented as software applications used by an EDA tool. In some embodiments, an EDA tool is used to generate a layout of an integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer-readable medium. In some embodiments, a tool such as obtained from CADENCE DESIGN SYSTEMS, INC. or another suitable layout generation tool is used to generate the layout. In some embodiments, the layout is generated based on a netlist, which is created based on a schematic design. In some embodiments, methods 1600 to 1700 are implemented by a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs generated by system 1800. In some embodiments, system 1800 is a manufacturing device configured to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs of the present disclosure. In some embodiments, Figure 18System 1800 generates an integrated circuit layout design that is smaller than other methods. In some embodiments, Figure 18 System 1800 generates a layout design of an integrated circuit structure that occupies less area and provides better routing resources compared to other methods.

[0765] Figure 19 is a block diagram of an integrated circuit (IC) manufacturing system 1900 and its associated IC manufacturing process according to at least one embodiment of the present disclosure. In some embodiments, based on a layout diagram, at least one component in (a) one or more semiconductor masks or (B) semiconductor integrated circuit layers is manufactured using manufacturing system 1900.

[0766] In Figure 19 , the IC manufacturing system 1900 (hereinafter referred to as "system 1900") includes entities such as a design company 1920, a mask company 1930, and an IC manufacturer / fabricator ("foundry") 1940 that interact in the design, development, and manufacturing cycle and / or services related to manufacturing an IC device 1960. The entities in system 1900 are connected by a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, one or more of the design house 1920, the mask house 1930, and the IC foundry 1940 are owned by a single larger company. In some embodiments, one or more of the design house 1920, the mask house 1930, and the IC foundry 1940 coexist in a common facility and use common resources.

[0767] A design company (or design team) 1920 generates an IC design layout 1922. The IC design layout 1922 includes various geometric patterns designed for the IC device 1960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers of various components that make up the IC device 1960 to be manufactured. The layers combine to form various IC components. For example, a part of the IC design layout 1922 includes various IC components such as active regions, gate electrodes, source electrodes, and drain electrodes, metal wires or vias for interlayer interconnection, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design company 1920 implements appropriate design procedures to form the IC design layout 1922. The design process includes one or more of logic design, physical design, or placement and routing. The IC design layout 1922 is presented in one or more data files having geometric pattern information. For example, the IC design layout 1922 can be represented in the GDSII file format or the DFII file format.

[0768] The mask room 1930 includes data preparation 1932 and mask manufacturing 1934. The mask room 1930 uses the IC design layout 1922 to fabricate one or more masks 1945 for use in fabricating the various layers of the IC device 1960 according to the IC design layout 922. The mask room 1930 performs mask data preparation 1932, in which the IC design layout 1922 is converted into a representative data file (RDF). The mask data preparation 1932 provides the RDF for the mask manufacturing 1934. The mask manufacturing in 1934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1945 or a semiconductor wafer 1942 (also referred to as "wafer 1942"). The IC design layout 1922 is manipulated by the mask data preparation 1932 (also referred to as "data preparation 1932") to conform to the specific characteristics of the mask writer and / or the requirements of the IC foundry 1940. In Figure 19 FIG., the mask data preparation 1932 and the mask manufacturing 1934 are shown as separate elements. In some embodiments, the mask data preparation 1932 and the mask manufacturing 1934 may be collectively referred to as mask data preparation.

[0769] In some embodiments, the mask data preparation 1932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. The OPC adjusts the IC design layout 1922. In some embodiments, the mask data preparation 1932 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0770] In some embodiments, the mask data preparation 1932 includes a mask rule checker (MRC), which uses a set of mask creation rules to check the OPC-processed IC design layout. The set of mask generation rules contains certain geometric and / or connectivity limitations to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for limitations during mask manufacturing 1934, which may undo some of the modifications performed by the OPC to meet the mask creation rules.

[0771] In some embodiments, mask data preparation 1932 includes lithography process check (LPC), which simulates the processes to be implemented by an IC foundry 1940 to fabricate an IC device 1960. LPC simulates the processes based on the IC design layout 1922 to create a simulated fabricated device, such as the IC device 1960. The process parameters in the LPC simulation can include parameters related to various processes of the IC manufacturing cycle, parameters related to the tools used for manufacturing the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc. or a combination thereof. In some embodiments, after LPC creates the simulated fabricated device, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further optimize the IC design layout 1922.

[0772] It should be understood that the above description of mask data preparation 1932 has been simplified for clarity. In some embodiments, data preparation 1932 includes additional components, such as logical operations (LOP) that modify the IC design layout according to manufacturing rules. Additionally, the processes applied to the IC design layout 1922 during data preparation 1932 can be executed in various different orders.

[0773] After mask data preparation 1932 and during mask manufacturing 1934, a mask 1945 or a set of masks 1945 is manufactured based on the modified IC design layout 1922. In some embodiments, mask manufacturing 1934 includes performing one or more lithographic exposures based on the IC design layout 1922. In some embodiments, based on the modified IC design layout 1922, a pattern is formed on the mask (photomask or reticle) 1945 using an electron beam (e-beam) or a mechanism of multiple electron beams. The mask 1945 can be formed using various techniques. In some embodiments, the mask 1945 is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, for exposing an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary version of the mask 1945 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1945 is formed using phase-shift techniques. In the phase-shift mask (PSM) version of the mask 1945, various components in the pattern formed on the mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask manufacturing 1934 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in the semiconductor wafer, and / or in other suitable processes.

[0774] The IC foundry 1940 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, the IC foundry 1940 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for the interconnect and packaging of the IC products, and a third manufacturing facility can provide other services for the foundry entity.

[0775] The IC foundry 1940 includes wafer manufacturing tools 1952 (hereinafter referred to as "manufacturing tools 1952"), which are configured to perform various manufacturing operations on the semiconductor wafer 1942 to manufacture the IC device 1960 according to a mask (e.g., mask 1945). In various embodiments, the manufacturing tools 1952 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing devices capable of performing one or more suitable manufacturing processes described herein.

[0776] IC foundry 1940 uses mask 1945 fabricated by mask shop 1930 to fabricate IC device 1960. Thus, IC foundry 1940 uses IC design layout 1922 at least indirectly to fabricate IC device 1960. In some embodiments, semiconductor wafer 1942 is fabricated by IC foundry 1940 using mask 1945 to form IC device 1960. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1922. Semiconductor wafer 1942 includes a silicon substrate or other suitable substrate with material layers formed thereon. Semiconductor wafer 1942 also includes one or more of various doped regions, dielectric components, multi-level interconnections, etc. (formed in subsequent fabrication steps).

[0777] System 1900 is shown as having design house 1920, mask shop 1930, or IC factory 1940 as separate components or entities. However, it should be understood that one or more of design house 1920, mask shop 1930, or IC fabrication plant 1940 are part of the same component or entity.

[0778] One aspect of this specification relates to an integrated circuit chip. In some embodiments, the integrated circuit chip includes a first memory cell array having a first width in a first direction and a second height in a second direction different from the first direction. In some embodiments, the integrated circuit chip further includes a second memory cell array having a second width in the first direction and a first height in the second direction. In some embodiments, the integrated circuit chip further includes a first set of bit lines extending in the first direction, connected to the first memory cell array, overlapping the first memory cell array, and located on at least a first metal layer on the front side of the substrate. In some embodiments, the integrated circuit chip further includes a second set of bit lines extending in the first direction, connected to the second memory cell array, overlapping the second memory cell array, and located on at least the first metal layer. In certain embodiments, at least the first width is different from the second width, or the first height is different from the second height.

[0779] In some embodiments, the integrated circuit chip further includes: a first set of word lines extending in the second direction, connected to the first memory cell array, overlapping the first memory cell array, and located on a second metal layer different from the first metal layer; and a second set of word lines extending in the second direction, connected to the second memory cell array, overlapping the second memory cell array, and located on the second metal layer.

[0780] In some embodiments, the first group of bit lines has a first length in the first direction; the first group of word lines has a second length in the second direction; the second group of bit lines has a third length in the first direction; and the second group of word lines has a fourth length in the second direction.

[0781] In some embodiments, at least one of the following is satisfied: the first length is less than the second length, and the third length is greater than the fourth length.

[0782] In some embodiments, at least one of the following is satisfied: the first length is less than the third length, and the second length is greater than the fourth length.

[0783] In some embodiments, the second memory cell array includes a first group of memory cell rows extending in the first direction and a first group of memory cell columns extending in the second direction; and the second group of word lines includes: a first word line of the second group of word lines overlaps with each memory cell in the first column of the first group of memory cell columns; and a second word line in the second group of word lines overlaps with each memory cell in the first column of the first group of memory cell columns, the second word line being adjacent to the first word line; and the first word line and the second word line are electrically connected to the staggered memory cells in the first column of the first group of memory cell columns.

[0784] In some embodiments, the first memory cell array includes a second group of memory cell rows extending in the first direction and a second group of memory cell columns extending in the second direction; and each word line of the first group of word lines overlaps and is electrically connected to each memory cell in the corresponding column of the second group of memory cell columns.

[0785] In some embodiments, each memory cell in the first memory cell array is a six-transistor (6T) memory cell; and each memory cell in the second memory cell array is a six-transistor memory cell.

[0786] In some embodiments, each memory cell in the first memory cell array is a six-transistor (6T) memory cell; and each memory cell in the second memory cell array is an eight-transistor (8T) memory cell.

[0787] In some embodiments, the second group of bit lines is shared by adjacent memory cell rows in the second memory cell array.

[0788] In some embodiments, the first memory cell array includes a first number of memory cells, and the second memory cell array includes the first number of memory cells.

[0789] Another aspect of this specification relates to an integrated circuit chip. In some embodiments, the integrated circuit chip includes a first memory cell array having a first width in a first direction and a first height in a second direction different from the first direction, and each memory cell in the first memory cell array includes a first number of transistors. In some embodiments, the integrated circuit chip further includes a second memory cell array having a second width in the first direction and a first height in the second direction, and each memory cell in the second memory cell array includes a second number of transistors greater than the first number of transistors. In some embodiments, the integrated circuit chip further includes a first set of word lines extending in the second direction, connected to the first memory cell array, overlapping the first memory cell array, and located on at least a first metal layer above the front side of the substrate. In some embodiments, the integrated circuit chip further includes a second set of word lines extending in the second direction, connected to the second memory cell array, overlapping the second memory cell array, and located on at least the first metal layer. In certain embodiments, at least the first width is different from the second width, or the first height is different from the second height.

[0790] In some embodiments, the integrated circuit chip further includes: a first set of bit lines extending in the first direction, connected to the first memory cell array, overlapping the first memory cell array, and located on a second metal layer different from the first metal layer; a second set of bit lines extending in the first direction, connected to the second memory cell array, overlapping the second memory cell array, and located on the second metal layer; and a third set of bit lines extending in the first direction, connected to the second memory cell array, overlapping the second memory cell array, located on the second metal layer, and separated from the second set of bit lines in the second direction.

[0791] In some embodiments, the first number of transistors is six, and each memory cell in the first memory cell array is a six-transistor (6T) memory cell; and the second number of transistors is eight, and each memory cell in the second memory cell array is an eight-transistor (8T) memory cell.

[0792] In some embodiments, the second memory cell array includes a first set of memory cell rows extending in the first direction and a first set of memory cell columns extending in the second direction; and the second set of word lines includes: a first read word line overlapping each memory cell in the first column of the first set of memory cell columns; and a second read word line overlapping each memory cell in the first column of the first set of memory cell columns, and the second read word line is adjacent to the first read word line; and the first read word line and the second read word line are electrically connected to the staggered memory cells in the first column of the first set of memory cell columns.

[0793] In some embodiments, the first memory cell array includes a second set of memory cell rows extending in the first direction and a second set of memory cell columns extending in the second direction; and the first set of word lines includes: a third word line, overlapping and electrically connected to each memory cell in the first column of the first set of memory cell columns; and a fourth word line, overlapping and electrically connected to each memory cell in the second column of the first set of memory cell columns, the fourth word line being adjacent to the third word line, and the second column in the first set of memory cell columns being adjacent to the first column in the first set of memory cell columns.

[0794] In some embodiments, the second memory cell array includes: a first memory cell located in at least the first row of the second memory cell array; a second memory cell located in the second row of the second memory cell array, the second row being adjacent to the first row; a third memory cell located in the third row of the second memory cell array, the third row being adjacent to the second row; and a fourth memory cell located in at least the fourth row of the second memory cell array, the fourth row being adjacent to the third row, wherein the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell are located in the first column of the second memory cell array.

[0795] In some embodiments, the first memory cell includes: a first portion in the first row of the second memory cell array and a second portion in the second row of the second memory cell array; and the fourth memory cell includes: a first portion in the fourth row of the second memory cell array and a second portion in the third row of the second memory cell array.

[0796] In some embodiments, the third set of bit lines includes: a first read bit line extending in the first direction, electrically connected to the second memory cell and the second portion of the first memory cell, and overlapping with the second memory cell and the second portion of the first memory cell; and a second read bit line extending in the first direction, electrically connected to the third memory cell and the second portion of the fourth memory cell, and overlapping with the third memory cell and the second portion of the fourth memory cell.

[0797] Another aspect of this specification relates to a method of manufacturing an integrated circuit chip. In some embodiments, the method includes fabricating a first set of memory cells in a first memory cell array. In some embodiments, the first memory cell array has a first width in a first direction and a second height in a second direction different from the first direction. Each memory cell in the first memory cell array includes a first set of transistors on a front side of a substrate, and the first set of transistors includes a first number of transistors. In some embodiments, the method further includes fabricating a second set of memory cells in a second memory cell array. In some embodiments, the second memory cell array has a second width in the first direction and a first height in the second direction. Each memory cell in the second memory cell array includes a second set of transistors on the front side of the substrate, and the second set of transistors includes a second number of transistors. In some embodiments, the method further includes fabricating a first set of vias on the front side of the substrate. In some embodiments, the first set of vias is electrically connected to at least the first set of transistors or the second set of transistors. In some embodiments, the method further includes fabricating a second set of vias on the front side of the substrate. In some embodiments, the second set of vias is electrically connected to at least the first set of transistors or the second set of transistors. In some embodiments, the method further includes depositing a first conductive material on a first metal layer on the front side of the substrate to form a first set of word lines and a second set of word lines. In some embodiments, the first set of word lines is electrically connected to the first set of transistors through the second set of vias, overlaps with the first memory cell array, and extends in the second direction. In some embodiments, the second set of word lines is electrically connected to the second set of transistors through the second set of vias, overlaps with the second memory cell array, and extends in the second direction. In some embodiments, the method further includes depositing a second conductive material on a second metal layer on the front side of the substrate to form a first set of bit lines and a second set of bit lines. In some embodiments, the first set of bit lines is electrically connected to the first set of transistors through the first set of vias, overlaps with the first memory cell array, and extends in the first direction. In some embodiments, the second set of bit lines is electrically connected to the second set of transistors through the first set of vias, overlaps with the second memory cell array, and extends in the first direction. In some embodiments, the second metal layer is different from the first metal layer. In certain embodiments, at least the first width is different from the second width, or the first height is different from the second height.

[0798] The foregoing outlines the features of several embodiments such that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit chip, comprising: A first memory cell array having a first width in a first direction and a second height in a second direction different from the first direction; A second memory cell array having a second width in the first direction and a second height in the second direction; A first group of bit lines extending along the first direction, connected to the first memory cell array, overlapping the first memory cell array, and located on a first metal layer that is above the front side of the substrate; And A second group of bit lines extending along the first direction, connected to the second memory cell array, overlapping the second memory cell array, and located on the first metal layer, Wherein at least the first width is different from the second width, or the first height is different from the second height.

2. The integrated circuit chip according to claim 1, further comprising: A first group of word lines extending along the second direction, connected to the first memory cell array, overlapping the first memory cell array, and located on a second metal layer different from the first metal layer; And A second group of word lines extending along the second direction, connected to the second memory cell array, overlapping the second memory cell array, and located on the second metal layer.

3. The integrated circuit chip according to claim 2, wherein The first group of bit lines has a first length in the first direction; The first group of word lines has a second length in the second direction; The second group of bit lines has a third length in the first direction; and The second group of word lines has a fourth length in the second direction.

4. The integrated circuit chip according to claim 3, wherein At least one of the following is satisfied: The first length is less than the second length, and The third length is greater than the fourth length.

5. The integrated circuit chip according to claim 3, wherein, At least one of the following is satisfied: The first length is less than the third length, and The second length is greater than the fourth length.

6. The integrated circuit chip according to claim 2, wherein The second memory cell array includes a first group of memory cell rows extending along the first direction and a first group of memory cell columns extending along the second direction; And The second group of word lines includes: A first word line of the second group of word lines overlaps each memory cell in the first column of the first group of memory cell columns; and A second word line in the second group of word lines overlaps each memory cell in the first column of the first group of memory cell columns, and the second word line is adjacent to the first word line; and The first word line and the second word line are electrically connected to the staggered memory cells in the first column of the first group of memory cell columns.

7. An integrated circuit chip, comprising: A first memory cell array having a first width in a first direction and a first height in a second direction different from the first direction, and each memory cell in the first memory cell array includes a first number of transistors; A second memory cell array having a second width in the first direction and a second height in the second direction, each memory cell in the second memory cell array including a second number of transistors greater than the first number of transistors; A first set of word lines extending in the second direction, connected to and overlapping the first memory cell array and located on a first metal layer above the front side of the substrate; And A second set of word lines extending in the second direction, connected to and overlapping the second memory cell array and located on the first metal layer, wherein at least the first width is different from the second width or the first height is different from the second height.

8. The integrated circuit chip according to claim 7, further comprising: A first set of bit lines extending in the first direction, connected to and overlapping the first memory cell array and located on a second metal layer different from the first metal layer; A second set of bit lines extending in the first direction, connected to and overlapping the second memory cell array and located on the second metal layer; And A third set of bit lines extending in the first direction, connected to and overlapping the second memory cell array, located on the second metal layer, and separated from the second set of bit lines in the second direction.

9. The integrated circuit chip according to claim 7, wherein the first number of transistors is six and each memory cell in the first memory cell array is a six-transistor (6T) memory cell; and the second number of transistors is eight and each memory cell in the second memory cell array is an eight-transistor (8T) memory cell.

10. A method of manufacturing an integrated circuit chip, the method comprising: Manufacturing a first set of memory cells in a first memory cell array having a first width in a first direction and a second height in a second direction different from the first direction, each memory cell in the first memory cell array including a first set of transistors on the front side of the substrate, wherein the first set of transistors includes a first number of transistors; Manufacturing a second set of memory cells in a second memory cell array having a second width in the first direction and a second height in the second direction, each memory cell in the second memory cell array including a second set of transistors on the front side of the substrate, the second set of transistors including a second number of transistors; Manufacturing a first set of vias (VD) and a second set of vias (VG) on the front side of the substrate, the first set of vias and the second set of vias being electrically connected to at least the first set of transistors or the second set of transistors; Deposit a first conductive material on a first metal layer (M1) on the front side of the substrate, thereby forming a first set of word lines and a second set of word lines, where the first set of word lines is electrically connected to the first set of transistors through the second set of vias and overlaps with the first memory cell array, and extends in the second direction, and the second set of word lines is electrically connected to the second set of transistors through the second set of vias and overlaps with the second memory cell array, and extends in the second direction; Fabricate a third set of vias (V1) on the front side of the substrate, where the third set of vias is electrically connected to at least the first set of transistors or the second set of transistors; and Deposit a second conductive material on a second metal layer (M2) on the front side of the substrate, thereby forming a first set of bit lines and a second set of bit lines, where the first set of bit lines is electrically connected to the first set of transistors through the first set of vias and the third set of vias and overlaps with the first memory cell array, and extends in the first direction, and the second set of bit lines is electrically connected to the second set of transistors through the first set of vias and the third set of vias and overlaps with the second memory cell array, and extends in the first direction, and the first metal layer is different from the second metal layer, where at least the first width is different from the second width, or the first height is different from the second height.

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