A clock duty cycle adjustment method and system

Abstract

The present invention relates to a clock duty cycle adjustment method and system in the field of clock adjustment technology, comprising the following steps: configuring the values ​​of a first current source, a first capacitor, a second current source and a second capacitor based on a target clock duty cycle; performing two-phase non-overlapping processing on an original input clock signal to obtain a first phase clock signal and a second phase clock signal, and simultaneously performing inversion processing on the original input clock signal to obtain an inverted input clock signal; causing the first current source to charge the first capacitor and the second current source to charge the second capacitor; obtaining a first voltage and a second voltage, and performing stability detection based on the first voltage and the second voltage; directly outputting the original input clock signal if a stable state is reached; and performing channel impedance adjustment according to the detection result until a stable state is reached, thereby solving the problems of low flexibility and low application scenario compatibility of existing fixed clock duty cycle settings.

Description

Technical Field

[0001] The present invention relates to the technical field of clock adjustment, and in particular to a clock duty cycle adjustment method and system. Background Art

[0002] With the continuous development of communication technology, the system's clock requirements are becoming increasingly higher. Existing technologies usually precisely adjust the clock duty cycle to a fixed value. However, in certain device applications, an excessively high clock duty cycle will affect the system's power consumption. For example, in the dynamic comparator of an analog-to-digital converter (ADC), when the comparator compares during the high-level period, two currents are generated: dynamic current and static current. Since the dynamic current drops to 0 after the comparison action is completed, the dynamic current is not affected by the duty cycle. However, the static current will continue throughout the entire high-level period of the clock. The larger the clock duty cycle and the longer the high-level time, the longer the static current lasts, and the corresponding power consumption of the analog-to-digital converter is also greater.

[0003] On the other hand, in some application scenarios, a clock duty cycle that is too low may not be able to meet timing constraints or compensate for signal path asymmetry. For example, in a digital-to-time converter (DTC), when dynamically delaying the input clock, the falling edge of the clock is typically used to sample the time delay control word to ensure sufficient time to complete switch control within the time-to-digital converter. However, when the clock duty cycle is too low, as the input clock frequency increases, the time interval between the falling edge of the clock and the rising edge of the subsequent clock is insufficient, resulting in the time-to-digital converter being unable to complete the sampling of the time delay control word.

[0004] Therefore, the existing fixed clock duty cycle setting has low flexibility, cannot achieve flexible allocation of multiple application scenarios, and cannot meet the clock duty cycle requirements in different application scenarios. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the present invention provides a clock duty cycle adjustment method and system, which solves the problems of low flexibility in setting the existing fixed clock duty cycle and low compatibility in application scenarios.

[0006] In order to solve the above technical problems, the present invention is solved by the following technical solutions:

[0007] A clock duty cycle adjustment method comprises the following steps:

[0008] configuring values ​​of a first current source, a first capacitor, a second current source, and a second capacitor in a duty cycle-to-voltage conversion circuit based on a target clock duty cycle so that the duty cycle-to-voltage conversion circuit is in a stable state after receiving a clock signal having the target clock duty cycle;

[0009] Performing two-phase non-overlapping processing on the original input clock signal to obtain a first phase clock signal and a second phase clock signal, and simultaneously performing inversion processing on the original input clock signal to obtain an inverted input clock signal;

[0010] Based on the first phase clock signal, the second phase clock signal, the reverse input clock signal, and the original input clock signal, the first current source charges the first capacitor, the second current source charges the second capacitor, and the first capacitor and the second capacitor are charged alternately;

[0011] Obtaining a first voltage each time the first capacitor is charged and a second voltage each time the second capacitor is charged, and performing stability detection on the first voltage and second voltage obtained each time;

[0012] If the detection result of the stability detection is that a stable state has been reached, the original input clock signal is directly output; if the detection result is that a stable state has not been reached, a primary voltage control signal is generated according to the detection result, and the channel impedance of the original input clock signal is adjusted based on the primary voltage control signal until the detection result reaches a stable state.

[0013] Optionally, the first current source charges the first capacitor, comprising the following steps:

[0014] When the first phase clock signal is at a low level, the second phase clock signal is at a high level, and the inverted input clock signal is at a high level, the first current source charges the first capacitor.

[0015] Optionally, the second current source charges the second capacitor, comprising the following steps:

[0016] When the first phase clock signal is at a low level, the second phase clock signal is at a high level, and the inverted input clock signal is at a low level, the second current charges the second capacitor.

[0017] Optionally, performing stability detection on the first voltage and the second voltage obtained each time includes the following steps:

[0018] amplifying the difference between the first voltage and the second voltage obtained each time to obtain an amplified voltage, and storing all the amplified voltages;

[0019] Comparing all the stored amplified voltages with a reference voltage, and generating an identification signal regarding a magnitude relationship between the first voltage and the second voltage after the comparison;

[0020] It is determined whether the high level average value and the low level average value of the identification signal are equal. If not, the detection result of the stability detection is that the stable state has not been reached; if so, the detection result of the stability detection is that the stable state has been reached.

[0021] Optionally, if the detection result indicates that the stable state has not been reached, generating a primary voltage control signal according to the detection result, and performing channel impedance adjustment on the original input clock signal based on the primary voltage control signal, including the following steps:

[0022] filtering the identification signal to generate a primary voltage control signal, and when the high level average value of the identification signal is greater than the low level average value, adjusting the channel impedance according to the primary voltage control signal so as to increase the falling edge slope and decrease the rising edge slope of the original input clock signal;

[0023] When the high level average value of the identification signal is less than the low level average value, the channel impedance is adjusted according to the primary voltage control signal to reduce the falling edge slope and increase the rising edge slope of the original input clock signal.

[0024] Optionally, performing channel impedance adjustment on the original input clock signal based on the primary voltage control signal until the detection result reaches a stable state includes the following steps:

[0025] Obtaining an input clock adjustment signal obtained after channel impedance adjustment, performing two-phase non-overlapping processing on the input clock adjustment signal to obtain a first-phase clock adjustment signal and a second-phase clock adjustment signal, and simultaneously performing inversion processing on the input clock adjustment signal to obtain an inverted input clock adjustment signal;

[0026] Based on the first phase clock adjustment signal, the second phase clock adjustment signal, the reverse input clock adjustment signal, and the input clock adjustment signal, the first current source charges the first capacitor, the second current source charges the second capacitor, and the first capacitor and the second capacitor are charged alternately;

[0027] Obtaining a first voltage each time the first capacitor is charged and a second voltage each time the second capacitor is charged, and re-performing a stability test on the first voltage and the second voltage obtained each time;

[0028] If the result of the re-test of the stability test is that a stable state has been reached, the input clock adjustment signal is directly output; if the test result is that a stable state has not been reached, a secondary voltage control signal is generated according to the test result, and the channel impedance of the input clock adjustment signal is adjusted based on the secondary voltage control signal until the test result reaches a stable state.

[0029] Optionally, after the cross-charging of the first capacitor and the second capacitor is completed, the method further includes the following steps:

[0030] Reset the first capacitor and the second capacitor.

[0031] Optionally, resetting the first capacitor and the second capacitor includes the following steps:

[0032] When the first phase clock signal is at a high level and the second phase clock signal is at a low level, the first capacitor and the second capacitor enter a discharge process, and when the first capacitor and the second capacitor complete the discharge, the reset is completed.

[0033] Optionally, a configuration formula for configuring the values ​​of the first current source, the first capacitor, the second current source, and the second capacitor in the duty cycle-to-voltage conversion circuit based on the target clock duty cycle is as follows:

[0034] , where D represents the target clock duty cycle, CH represents the capacitance value of the second capacitor, IL represents the current value of the first current source, CL represents the capacitance value of the first capacitor, and IH represents the current value of the second current source.

[0035] A clock duty cycle adjustment system, the clock duty cycle adjustment system is used to perform the clock duty cycle adjustment method as described in any one of the above, including a clock buffer circuit, a clock generation circuit, a duty cycle-voltage conversion circuit, a comparison circuit and a filter circuit;

[0036] The clock generating circuit is used to perform two-phase non-overlapping processing on the original input clock signal to obtain a first phase clock signal and a second phase clock signal, and at the same time perform inversion processing on the original input clock signal to obtain an inverted input clock signal;

[0037] The duty cycle-to-voltage conversion circuit is configured to cause the first current source to charge the first capacitor to obtain a first voltage, and the second current source to charge the second capacitor to obtain a second voltage, based on the first phase clock signal, the second phase clock signal, the reverse input clock signal, and the original input clock signal, wherein the first capacitor and the second capacitor are charged alternately;

[0038] The comparison circuit is configured to obtain a first voltage each time the first capacitor is charged and a second voltage each time the second capacitor is charged, and perform stability detection on the first voltage and the second voltage obtained each time;

[0039] The filtering circuit is used to filter the identification signal;

[0040] The clock buffer circuit is used to directly output the original input clock signal when the detection result of the stability detection is that a stable state has been reached; when the detection result is that a stable state has not been reached, generate a primary voltage control signal according to the detection result, and adjust the channel impedance of the original input clock signal based on the primary voltage control signal until the detection result reaches a stable state.

[0041] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0042] By configuring the values ​​of the first current source, the first capacitor, the second current source, and the second capacitor in the duty cycle-voltage conversion circuit, the duty cycle-voltage conversion circuit is in a stable state after inputting a clock signal with a target clock duty cycle, which serves as the basis for adjusting the clock duty cycle. At the same time, the configuration of the adjustment scheme is simple. It only needs to adjust the values ​​of the first current source, the first capacitor, the second current source, and the second capacitor to achieve arbitrary clock duty cycle adjustment, allowing users to flexibly change the clock duty cycle according to the requirements of different application scenarios, preventing the use of a unified clock duty cycle in different application scenarios, resulting in increased power consumption due to a high clock duty cycle, or failure to meet timing constraints or compensate for signal path asymmetry due to a low clock duty cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 This is a flow chart of a clock duty cycle adjustment method proposed in the first embodiment;

[0045] Figure 2 This is a circuit diagram for implementing the clock duty cycle adjustment method proposed in the first and second embodiments;

[0046] Figure 3 This is a circuit diagram of the clock buffer circuit proposed in the second embodiment;

[0047] Figure 4 This is a circuit diagram of the clock generation circuit proposed in the second embodiment;

[0048] Figure 5 This is a circuit diagram of the duty cycle-voltage conversion circuit proposed in the second embodiment;

[0049] Figure 6 This is a circuit diagram of the comparison circuit proposed in the second embodiment;

[0050] Figure 7 This is a circuit diagram of the low-pass filter circuit proposed in the second embodiment. DETAILED DESCRIPTION

[0051] The present invention will be further described in detail below with reference to the examples. The following examples are intended to explain the present invention but the present invention is not limited to the following examples.

[0052] Example 1

[0053] like Figure 1 As shown, a clock duty cycle adjustment method includes the following steps: Step 1, configuring the values ​​of a first current source, a first capacitor, a second current source, and a second capacitor in a duty cycle-to-voltage conversion circuit based on a target clock duty cycle, so that the duty cycle-to-voltage conversion circuit is in a stable state after inputting a clock signal with the target clock duty cycle;

[0054] like Figure 2 As shown, before modulating the clock duty cycle, a duty cycle-voltage conversion circuit is first configured. In the duty cycle-voltage conversion circuit, the values ​​of the first current source IL, the first capacitor CL, the second current source IH, and the second capacitor CH are set, and the first capacitor CL and the second capacitor CH are charged alternately. When the clock signal is input, the ratio of the charging time of the first current source IL for the first capacitor CL to the charging time of the second current source IH for the second capacitor CH is equal to the high and low level duration in the clock signal, thereby realizing modulation of the clock duty cycle.

[0055] Specifically, in order to achieve that the charging time of the first capacitor CL and the second capacitor CH is equal to the high and low level duration in the clock signal, it is necessary to satisfy the first voltage VL when the first capacitor CL is charged and the second voltage VH when the second capacitor CH is charged in the duty cycle-voltage conversion circuit that is equal, that is: VH=VL. According to the duty cycle-voltage conversion circuit, ; , therefore, it can be concluded that , and due to the clock duty cycle , where T is the entire clock cycle; TH is the charging time of the second capacitor, corresponding to the time when the input clock is high; TL is the charging time of the first capacitor, corresponding to the time when the input clock is low; therefore, Substituting into the calculation formula of clock duty cycle D, we can get .

[0056] Therefore, when the clock duty cycle of the clock signal needs to be modulated, the values ​​of the first current source, first capacitor, second current source and second capacitor in the duty cycle-voltage conversion circuit need to be configured based on the target clock duty cycle D.

[0057] After the configuration is completed, since the clock duty cycle of the input original clock signal cannot be confirmed to be the clock duty cycle required by this system, the clock duty cycle needs to be verified. First, execute step 2, perform two-phase non-overlapping processing on the original input clock signal to obtain the first phase clock signal and the second phase clock signal, and at the same time invert the original input clock signal to obtain the inverted input clock signal.

[0058] Specifically, the original input clock signal is processed in three directions. The first direction is to divide the original input clock signal into two phases through a divider, and then perform two-phase non-overlapping processing through a two-phase non-overlapping clock circuit, thereby obtaining a high-level, non-overlapping, and opposite-phase first-phase clock signal CLKIN2_N and a second-phase clock signal CLKIN2_P; the second processing direction is to reversely process the original input clock signal through an inverter, thereby obtaining an inverted input clock signal CK_L with an opposite phase to the original input clock signal; the last processing direction is to retain the original input clock signal and mark the signal as CK_H.

[0059] Finally, based on the obtained first-phase clock signal CLKIN2_N, the second-phase clock signal CLKIN2_P, the reverse input clock signal CK_L, and the retained original input clock signal CK_H, a charging trigger basis is provided for controlling the charging of the first capacitor and the second capacitor in the duty cycle-to-voltage conversion circuit, that is, step 3, based on the first-phase clock signal, the second-phase clock signal, the reverse input clock signal, and the original input clock signal, the first current source charges the first capacitor, and the second current source charges the second capacitor, and the first capacitor and the second capacitor are charged alternately.

[0060] The first current source charges the first capacitor, including the following steps: when the first phase clock signal CLKIN2_N is at a low level, the second phase clock signal CLKIN2_P is at a high level, and the inverting input clock signal CK_L is at a high level, the first current IL source charges the first capacitor CL; the second current source charges the second capacitor, including the following steps: when the first phase clock signal CLKIN2_N is at a low level, the second phase clock signal CLKIN2_P is at a high level, and the inverting input clock signal CK_L is at a low level, the second current IH charges the second capacitor CH.

[0061] Thus, the alternating charging of the first capacitor and the second capacitor is triggered according to the high and low levels of the first phase clock signal, the second phase clock signal, the reverse input clock signal and the original input clock signal.

[0062] Then, step 4 is performed, obtaining the first voltage VL each time the first capacitor is charged and the second voltage VH each time the second capacitor is charged, and performing a stability test on the first voltage VL and the second voltage VH obtained each time. Specifically, performing the stability test on the first voltage VL and the second voltage VH obtained each time includes the following steps: amplifying the difference between the first voltage and the second voltage obtained each time to obtain an amplified voltage, and storing all the amplified voltages; comparing all the stored amplified voltages with a reference voltage, and generating an identification signal regarding the magnitude relationship between the first voltage and the second voltage after the comparison; determining whether the high level average value and the low level average value of the identification signal are equal; if not, the detection result of the stability test is that the stable state has not been reached; if so, the detection result of the stability test is that the stable state has been reached;

[0063] More specifically, after the first capacitor CL is completely charged, the first voltage VL of the first capacitor CL is obtained when it is charged. After the second capacitor CH is completely charged, the second voltage VH of the second capacitor CH is obtained when it is charged. The first voltage VL is then input into the negative electrode of the operational amplifier, and the second voltage VH is input into the positive electrode of the operational amplifier, thereby outputting the amplified voltage EAO, and the amplified voltage EAO is stored in the holding capacitor C_HOLD.

[0064] It should be noted that since the clock signal alternates between high and low levels, the first voltage VL and the second voltage VH will be generated multiple times, and multiple amplified voltages will be generated through the operational amplifier and stored in the holding capacitor C_HOLD. The amplified voltages generated multiple times will be compared with the reference voltage in turn. Finally, all comparison results generate an identification signal, where the amplified voltage EAO = (second voltage VH - first voltage VL) * operational amplifier gain.

[0065] When the first phase clock signal is high and the second phase clock signal is low, the amplified voltage EAO stored in the holding capacitor C_HOLD is used as the positive input of the comparator and compared with the reference voltage VREF at the negative input of the comparator. If the second voltage VH is greater than the first voltage VL, it indicates that the clock duty cycle is too large. At this time, the output of the operational amplifier is high, and the holding capacitor C_HOLD connected to the positive electrode of the comparator maintains a high level. The high level is greater than the reference voltage VREF, and the identification signal CMPO output by the comparator is high, and the system has not reached a stable state. If the second voltage VH is less than the first voltage VL, it indicates that the clock duty cycle is too small. At this time, the output of the operational amplifier is low, and the holding capacitor C_HOLD connected to the positive electrode of the comparator maintains a low level. The low level is less than the reference voltage VREF, and the identification signal CMPO output by the comparator is low, and the system has not reached a stable state. If the second voltage VH is equal to the first voltage VL, it indicates that the clock duty cycle has reached the duty cycle that needs to be modulated. No channel impedance adjustment is required, and the original input clock signal can be directly output as CLKOUT.

[0066] On the other hand, when the first phase clock signal is at a high level and the second phase clock signal is at a low level, the first capacitor and the second capacitor enter a discharge process, that is, the first capacitor and the second capacitor are reset, and when the first capacitor and the second capacitor are completely discharged, the reset is completed, so that the next stability test is not affected by the previous test results.

[0067] Furthermore, when the detection result of the stability detection does not reach a stable state, it is necessary to generate a primary voltage control signal according to the detection result, and adjust the channel impedance of the original input clock signal based on the primary voltage control signal until the detection result reaches a stable state.

[0068] Specifically, the identification signal is filtered to generate a primary voltage control signal VC. When the high level average value of the identification signal CMPO is greater than the low level average value, the channel impedance is adjusted according to the primary voltage control signal VC to increase the falling edge slope and decrease the rising edge slope of the original input clock signal; when the high level average value of the identification signal CMPO is less than the low level average value, the channel impedance is adjusted according to the primary voltage control signal VC to decrease the falling edge slope and increase the rising edge slope of the original input clock signal.

[0069] This embodiment utilizes PMOS and NMOS devices to adjust channel impedance. The pull-up channel impedance of the PMOS device and the pull-down channel impedance of the NMOS device are controlled by a primary voltage control signal VC, thereby adjusting the clock edge slope of the original input clock signal. When the primary voltage control signal VC increases (i.e., the high level average value of the marker signal CMPO is greater than the low level average value), the corresponding pull-up channel impedance of the PMOS device increases, while the pull-down channel impedance of the NMOS device decreases. Consequently, the rising edge of the original input clock signal slows down, the falling edge steepens, and the clock duty cycle decreases. Conversely, when the primary voltage control signal VC decreases (i.e., the high level average value of the marker signal CMPO is less than the low level average value), the corresponding pull-up channel impedance of the PMOS device decreases, while the pull-down channel impedance of the NMOS device increases. Consequently, the rising edge of the original input clock signal steepens, the falling edge slows down, and the clock duty cycle increases.

[0070] After the channel impedance adjustment is completed, in order to ensure that the clock signal reaches the final target clock duty cycle, the input clock adjustment signal after the channel impedance adjustment needs to be tested for stability again until the test result reaches a stable state.

[0071] Specifically, the method includes the following steps: obtaining an input clock adjustment signal obtained after channel impedance adjustment, performing two-phase non-overlapping processing on the input clock adjustment signal to obtain a first phase clock adjustment signal and a second phase clock adjustment signal, and simultaneously performing inversion processing on the input clock adjustment signal to obtain an inverted input clock adjustment signal; based on the first phase clock adjustment signal, the second phase clock adjustment signal, the reverse input clock adjustment signal and the input clock adjustment signal, causing the first current source to charge the first capacitor and the second current source to charge the second capacitor, and the first capacitor and the second capacitor are charged alternately; obtaining a first voltage each time the first capacitor is charged and a second voltage each time the second capacitor is charged, and re-performing stability detection on the first voltage and the second voltage obtained each time; if the detection result of the re-performed stability detection is that a stable state is reached, directly outputting the input clock adjustment signal; if the detection result is that a stable state is not reached, generating a secondary voltage control signal according to the detection result, and performing channel impedance adjustment on the input clock adjustment signal based on the secondary voltage control signal until the detection result reaches a stable state.

[0072] The processing method of the input clock adjustment signal CLK is the same as that of the original input clock signal. First, the clock adjustment signal is processed in three directions. The first direction is to divide the input clock adjustment signal CLK by two using a divider, and then perform two-phase non-overlapping processing through a two-phase non-overlapping clock circuit, thereby obtaining a high-level, non-overlapping, and opposite-phase first-phase clock adjustment signal CLKIN2_N' and a second-phase clock adjustment signal CLKIN2_P'; the second processing direction is to reverse the input clock adjustment signal CLK through an inverter, thereby obtaining an inverted input clock adjustment signal CK_L with an opposite phase to the input clock adjustment signal CLK; the last processing direction is to retain the input clock adjustment signal CLK and mark this signal as CK_H.

[0073] Then, based on the obtained first-phase clock adjustment signal CLKIN2_N', the second-phase clock adjustment signal CLKIN2_P', the inverted input clock adjustment signal CK_L, and the retained input clock adjustment signal CK_H, a charging trigger basis is provided for controlling the charging of the first capacitor and the second capacitor in the duty cycle-to-voltage conversion circuit, so that the first current source charges the first capacitor and the second current source charges the second capacitor, and the first capacitor and the second capacitor are charged alternately.

[0074] The first current source charges the first capacitor, including the following steps: when the first-phase clock adjustment signal CLKIN2_N' is at a low level, the second-phase clock adjustment signal CLKIN2_P' is at a high level, and the inverted input clock adjustment signal CK_L is at a high level, the first current IL source charges the first capacitor CL; the second current source charges the second capacitor, including the following steps: when the first-phase clock adjustment signal CLKIN2_N' is at a low level, the second-phase clock adjustment signal CLKIN2_P' is at a high level, and the inverted input clock adjustment signal CK_L is at a low level, the second current IH charges the second capacitor CH.

[0075] It should be noted that, since the first capacitor and the second capacitor have been discharged and reset before being charged, when the first capacitor and the second capacitor are charged, the charging time of the two can accurately reflect the duration of the high and low levels respectively, that is, can accurately correspond to the duty cycle of the clock signal.

[0076] Thus, the alternating charging of the first capacitor and the second capacitor is triggered according to the high and low levels of the first phase clock adjustment signal, the second phase clock adjustment signal, the reverse input clock adjustment signal and the input clock adjustment signal.

[0077] Next, the difference between the first voltage and the second voltage obtained each time is amplified to obtain an amplified voltage, and all the amplified voltages are stored; all the stored amplified voltages are compared with the reference voltage, and after comparison, an identification signal about the relationship between the first voltage and the second voltage is generated; it is determined whether the high level average value and the low level average value of the identification signal are equal. If not, the detection result of the stability detection is that the stable state has not been reached; if so, the detection result of the stability detection is that the stable state has been reached.

[0078] More specifically, after the first capacitor CL is completely charged, the first voltage VL of the first capacitor CL is obtained when it is charged. After the second capacitor CH is completely charged, the second voltage VH of the second capacitor CH is obtained when it is charged. The first voltage VL is then input into the negative electrode of the operational amplifier, and the second voltage VH is input into the positive electrode of the operational amplifier, thereby outputting the amplified voltage EAO, and the amplified voltage EAO is stored in the holding capacitor C_HOLD.

[0079] When the first-phase clock adjustment signal is high and the second-phase clock adjustment signal is low, the amplified voltage EAO stored in the holding capacitor C_HOLD serves as the positive input of the comparator and is compared with the reference voltage VREF at the negative input of the comparator. If the second voltage VH is greater than the first voltage VL, it indicates that the clock duty cycle is too large. At this time, the operational amplifier outputs a high level, and the holding capacitor C_HOLD connected to the positive electrode of the comparator maintains a high level. This high level is greater than the reference voltage VREF, and the comparator outputs an identification signal CMPO at a high level, and the system has not reached a stable state. If the second voltage VH is less than the first voltage VL, it indicates that the clock duty cycle is too small. At this time, the operational amplifier outputs a low level, and the holding capacitor C_HOLD connected to the positive electrode of the comparator maintains a low level. This low level is less than the reference voltage VREF, and the comparator outputs an identification signal CMPO at a low level, and the system has not reached a stable state. If the second voltage VH is equal to the first voltage VL, it indicates that the clock duty cycle has reached the required modulation duty cycle, and no channel impedance adjustment is required. The original input clock signal can be directly output as CLKOUT.

[0080] On the other hand, when the first phase clock adjustment signal is at a high level and the second phase clock adjustment signal is at a low level, the first capacitor and the second capacitor enter a discharge process, that is, the first capacitor and the second capacitor are reset, and when the first capacitor and the second capacitor are completely discharged, the reset is completed, so that the next stability test is not affected by the previous test results.

[0081] Furthermore, when the detection result of the stability detection does not reach a stable state, a secondary voltage control signal needs to be generated according to the detection result, and the channel impedance of the original input clock signal needs to be adjusted based on the secondary voltage control signal until the detection result reaches a stable state.

[0082] Specifically, the identification signal is filtered to generate a secondary voltage control signal VC. When the high level average value of the identification signal CMPO is greater than the low level average value, the channel impedance is adjusted according to the secondary voltage control signal VC to increase the falling edge slope of the input clock adjustment signal and decrease the rising edge slope; when the high level average value of the identification signal CMPO is less than the low level average value, the channel impedance is adjusted according to the secondary voltage control signal VC to decrease the falling edge slope of the input clock adjustment signal and increase the rising edge slope.

[0083] This embodiment utilizes PMOS and NMOS devices to adjust channel impedance. The pull-up channel impedance of the PMOS device and the pull-down channel impedance of the NMOS device are controlled by a secondary voltage control signal VC, thereby adjusting the clock edge slope of the input clock adjustment signal. When the secondary voltage control signal VC increases (i.e., the high level average value of the marker signal CMPO is greater than the low level average value), the corresponding pull-up channel impedance of the PMOS device increases, while the pull-down channel impedance of the NMOS device decreases. Consequently, the rising edge of the input clock adjustment signal slows down, the falling edge steepens, and the clock duty cycle decreases. Conversely, when the secondary voltage control signal VC decreases (i.e., the high level average value of the marker signal CMPO is less than the low level average value), the corresponding pull-up channel impedance of the PMOS device decreases, while the pull-down channel impedance of the NMOS device increases. Consequently, the rising edge of the input clock adjustment signal steepens, the falling edge slows down, and the clock duty cycle increases.

[0084] After the channel impedance adjustment is completed, in order to ensure that the clock signal reaches the final target clock duty cycle, the input clock adjustment signal after the channel impedance adjustment is completed needs to be tested for stability again. If the stable state is not reached, the voltage control signal is repeatedly generated to adjust the channel impedance until the test result reaches a stable state.

[0085] The present invention configures the values ​​of the first current source, the first capacitor, the second current source and the second capacitor in the duty cycle-voltage conversion circuit so that the duty cycle-voltage conversion circuit is in a stable state after inputting a clock signal with a target clock duty cycle, which serves as the basis for adjusting the clock duty cycle. At the same time, the configuration of the adjustment scheme is simple. It only needs to adjust the values ​​of the first current source, the first capacitor, the second current source and the second capacitor to achieve arbitrary clock duty cycle adjustment, so that users can flexibly change the clock duty cycle according to the requirements of different application scenarios, and prevent the use of a unified clock duty cycle in different application scenarios, resulting in increased power consumption due to a high clock duty cycle, or the inability to meet timing constraints or compensate for signal path asymmetry due to a low clock duty cycle.

[0086] On the other hand, the present invention provides a control basis for alternately charging the first capacitor and the second capacitor by performing two-phase non-overlapping and inverting processing on the original input clock signal, maps the charging time of the first capacitor and the second capacitor to the high and low level duration of the original input clock signal, and verifies whether the clock duty cycle accurately reaches the target value based on stability detection. When the detection result does not reach a stable state, it is adjusted by channel impedance adjustment to achieve precise modulation of the clock duty cycle.

[0087] Example 2

[0088] like Figure 2 As shown, a clock duty cycle adjustment system includes a clock buffer circuit, a clock generation circuit, a duty cycle-voltage conversion circuit, a comparison circuit and a filter circuit; the output end of the clock generation circuit is connected to the input end of the duty cycle-voltage conversion circuit, the output end of the duty cycle-voltage conversion circuit is connected to the input end of the comparison circuit, the input end of the comparison circuit is also connected to the output end of the clock generation circuit, the input end of the filter circuit is respectively connected to the output end of the clock generator and the output end of the comparison circuit, the output end of the filter circuit is connected to the input end of the clock buffer circuit, and the output end of the clock buffer circuit is connected to the input end of the clock generation circuit.

[0089] Among them, Figure 3 As shown, the clock buffer circuit includes multiple PMOS devices and multiple NMOS devices connected in series, and the multiple PMOS devices connected in series are connected to the multiple NMOS devices connected in series. The input end of the clock buffer circuit inputs the original clock signal CLKIN and the voltage control signal VC.

[0090] The main function of the clock buffer circuit is to receive the input clock and adjust the output clock edge slope by controlling the pull-up channel impedance of the PMOS device and the pull-down channel impedance of the NMOS device through the voltage control signal VC. When the voltage control signal VC increases, the corresponding pull-up channel impedance of the PMOS device becomes larger and the pull-down channel impedance of the NMOS device becomes smaller. Therefore, the rising edge of the output clock becomes slower, the falling edge becomes steeper, and the duty cycle decreases; conversely, when the voltage control signal VC decreases, the corresponding pull-up channel impedance of the PMOS device becomes smaller and the pull-down channel impedance of the NMOS device becomes larger. Therefore, the rising edge of the output clock becomes steeper, the falling edge becomes slower, and the duty cycle increases.

[0091] like Figure 4As shown, the clock generation circuit includes a divider, a two-phase non-overlapping clock generation circuit, an inverter, and logic 1 and logic 2. The input end of the divider receives the signal CLK, the output end of the divider is connected to the output end of the two-phase non-overlapping clock generation circuit, and the output end of the two-phase non-overlapping clock generation circuit outputs signals CLKIN2_N and CLKIN2_P. The signal CLK is also input to the input end of the inverter. The output end of the inverter outputs the signal CK_L. The input end of the logic 1 receives the signal CLKIN2_P and the signal CK_L respectively and outputs the SL signal. The input end of the logic 2 receives the signal CLKIN2_P and the signal CLK (i.e., the signal CK_H) respectively and outputs the SH signal.

[0092] The main function of the clock generator is to generate non-overlapping clock signals to control the opening and closing of the subsequent switches. The principle is to use a divide-by-two circuit and a logic gate circuit for logical combination. The high-level time of SL and SH corresponds to the low-level time and high-level time of their input clocks. The divide-by-two circuit divides the input clock into two. The high-level period after division is used to convert the input clock duty cycle into voltage. During the low-level period, the comparison signal is filtered and fed back to the clock buffer, and the CL and CH capacitors are reset at the same time.

[0093] like Figure 5 As shown, the duty cycle-voltage conversion circuit includes a first current source IL, a second current source IH, a first switch S1, a second switch S2, a fourth switch S4, a fifth switch S5, a first capacitor CL and a second capacitor CH. Its main function is to convert the clock duty cycle information into a voltage signal. The principle is to control the constant current source through SL and SH to charge the capacitor, and finally generate a voltage signal on the capacitor.

[0094] The process of converting clock duty cycle information into a voltage signal is as follows:

[0095] When CLKIN2_P is high and CLKIN2_N is low: first, AND logic 1 and AND logic 2 transmit CK_L and CK_H to SL and SH normally. At the same time, the reset circuit controlled by CLKIN2_N disconnects the upper plate of the capacitor from the ground (that is, the fourth switch S4 and the fifth switch S5 are disconnected). Then, when CK_L is high, SL becomes high. At this time, the first switch S1 controlled by SL is closed, and the first current source IL charges the first capacitor CL with a constant current. If the high level duration of SL is TL, the first voltage VL at the node is equal to IL×TL÷CL. Similarly, when CK_H is high, SH becomes high. At this time, the second switch controlled by SH is closed, and the second current source IH charges the second capacitor CH with a constant current. If the high level duration of SH is TH, the second voltage VH at the node is equal to IH×TH÷CH.

[0096] When CLKIN2_P is low and CLKIN2_N is high: First, AND logic 1 and AND logic 2 output low levels. SL and SH are not controlled by CK_L and CK_H and remain low. The corresponding first switch S1 and second switch S2 remain open. Second, the reset circuit is turned on (i.e., the fourth switch S4 and the fifth switch S5 are closed). The first capacitor CL and the second capacitor CH discharge to ground through the reset switch (the fourth switch S4 and the fifth switch S5). After discharge, the voltage on the capacitor VH = VL = 0.

[0097] like Figure 6 As shown, the comparison circuit includes an operational amplifier, a holding capacitor, and a comparator. The positive terminal of the operational amplifier is input with the second voltage VH and the first voltage VL. The output of the operational amplifier is connected to a third switch S3, and the on-off of the third switch is controlled by the signal CLKIN2_P. The other end of the third switch is connected to the holding capacitor and the positive input terminal of the comparator. The negative input terminal of the comparator is input with the reference voltage VREF. The output terminal of the comparator outputs the identification signal CMPO.

[0098] The main function of the comparison circuit is to compare the size of VH and VL. The comparison result is the relationship between the actual duty cycle and the ideal duty cycle. When the output is high, it means that the duty cycle is larger than the expected value, otherwise the actual duty cycle is smaller than the expected duty cycle. Its principle is to amplify the difference between VH and VL through the operational amplifier, compare the amplified EAO with the reference voltage (VREF) input of the comparator, and generate an identification signal of the size relationship between VH and VL.

[0099] like Figure 7 As shown, the main function of the low-pass filter circuit is to filter the square wave signal output by the comparator and output a DC voltage signal. The low-pass filter circuit includes a sixth switch S6 and a low-pass filter. The on-off of the sixth switch S6 is controlled by the signal CLKIN2_N. When the sixth switch S6 is turned on, the input end of the low-pass filter receives the identification signal CMPO, and the output end of the low-pass filter outputs the voltage control signal VC.

[0100] Furthermore, the operating principles of the duty cycle-voltage conversion circuit, the comparison circuit, and the low-pass filter circuit are as follows:

[0101] When the CLKIN2_P clock is at a high level, the control signal SL of the first switch S1 is consistent with CK_L, the control signal SH of the second switch S2 is consistent with CK_H, the third switch S3 is turned on, and the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all in the off state. At this time, the system is in the sampling stage, and the duty cycle information of the clock output by the clock buffer circuit is sampled and processed through the duty cycle-voltage converter and the comparison circuit.

[0102] When the CLKIN2_N clock is at a high level, the first switch S1, the second switch S2, and the third switch S3 are all disconnected, and the fourth switch S4, the fifth switch S5, and the sixth switch S6 are turned on. At this time, the system is in the feedback stage. The pull-up impedance and the pull-down impedance of the clock buffer are controlled by the low-pass filter output voltage control signal VC to adjust the clock edge slope and ultimately adjust the output clock duty cycle.

[0103] The specific process is as follows:

[0104] First, when CLKIN2_P is high and CLKIN2_N is low:

[0105] If CLK is high, CK_H is high, SH is high, the second switch S2 is turned on, and the second current source IH charges the second capacitor CH. If the duration of SH high level is TH, then ;

[0106] If CLK is low, CK_L is high, SL is high, the first switch S1 is turned on, and the first current source IL charges the first capacitor CL. If the duration of SL high level is TL, then ;

[0107] If the second voltage VH is greater than the first voltage VL, it means that the duty cycle is too large. At this time, the operational amplifier output voltage EAO is at a high level. The holding capacitor C_HOLD connected to the positive terminal of the comparator maintains a high level. The high level is greater than the VREF voltage, and the comparator output CMPO is at a high level.

[0108] If the first voltage VL is greater than the second voltage VH, it means that the duty cycle is too small. At this time, the operational amplifier output voltage EAO is low, and the holding capacitor C_HOLD connected to the positive terminal of the comparator maintains a low level. The high level is less than the VREF voltage, and the comparator output CMPO is low.

[0109] Second, when CLKIN2_P is low and CLKIN2_N is high:

[0110] If the comparator output CMPO is high, the low-pass filter output voltage increases, that is, the VC voltage increases, the pull-down impedance of the clock buffer circuit decreases, and the pull-up impedance increases. At this time, the falling edge slope increases, the rising edge slope decreases, and the duty cycle decreases;

[0111] If the comparator output CMPO is low, the low-pass filter output voltage decreases, that is, the VC voltage decreases, the pull-down impedance of the clock buffer circuit increases, and the pull-up impedance decreases. At this time, the falling edge slope decreases, the rising edge slope increases, and the duty cycle increases;

[0112] When the system is stable, VH and VL are equal, and the average level of the comparator output CMPO is the average of its output high level and low level.

[0113] Finally, since the clock duty cycle adjustment system of this embodiment is used to execute the clock duty cycle adjustment method as shown in the first embodiment, the clock generation circuit is used to perform two-phase non-overlapping processing on the original input clock signal to obtain a first-phase clock signal and a second-phase clock signal, and at the same time invert the original input clock signal to obtain an inverted input clock signal; the duty cycle-to-voltage conversion circuit is used to cause the first current source to charge the first capacitor to obtain a first voltage, and the second current source to charge the second capacitor to obtain a second voltage based on the first-phase clock signal, the second-phase clock signal, the inverted input clock signal, and the original input clock signal. The first capacitor and the second capacitor are charged alternately; a comparison circuit is used to obtain a first voltage each time the first capacitor is charged and a second voltage each time the second capacitor is charged, and to perform stability detection on the first voltage and the second voltage obtained each time; a filtering circuit is used to filter the identification signal; a clock buffer circuit is used to directly output the original input clock signal when the detection result of the stability detection is that a stable state has been reached; when the detection result is that a stable state has not been reached, a primary voltage control signal is generated according to the detection result, and the channel impedance of the original input clock signal is adjusted based on the primary voltage control signal until the detection result reaches a stable state.

[0114] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form or substance. It should be pointed out that ordinary technicians in this technical field can make several improvements and supplements without departing from the method of the present invention. These improvements and supplements should also be regarded as the scope of protection of the present invention. Any equivalent changes, modifications and evolutions made by technicians familiar with this profession without departing from the spirit and scope of the present invention by using the technical content disclosed above are all equivalent embodiments of the present invention; at the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A clock duty cycle adjustment method, characterized in that: The following steps are involved: configuring values ​​of a first current source, a first capacitor, a second current source, and a second capacitor in a duty cycle-to-voltage conversion circuit based on a target clock duty cycle so that the duty cycle-to-voltage conversion circuit is in a stable state after receiving a clock signal having the target clock duty cycle; Performing two-phase non-overlapping processing on the original input clock signal to obtain a first phase clock signal and a second phase clock signal, and simultaneously performing inversion processing on the original input clock signal to obtain an inverted input clock signal; Based on the first phase clock signal, the second phase clock signal, the reverse input clock signal, and the original input clock signal, the first current source charges the first capacitor, the second current source charges the second capacitor, and the first capacitor and the second capacitor are charged alternately; Obtaining a first voltage each time the first capacitor is charged and a second voltage each time the second capacitor is charged, and performing stability detection on the first voltage and second voltage obtained each time; If the detection result of the stability detection is that a stable state has been reached, the original input clock signal is directly output; if the detection result is that a stable state has not been reached, a primary voltage control signal is generated according to the detection result, and the channel impedance of the original input clock signal is adjusted based on the primary voltage control signal until the detection result reaches a stable state; amplifying the difference between the first voltage and the second voltage obtained each time to obtain an amplified voltage, and storing all the amplified voltages; comparing all the stored amplified voltages with a reference voltage, and generating an identification signal regarding the magnitude relationship between the first voltage and the second voltage after the comparison; determining whether a high level average value and a low level average value of the identification signal are equal; if not, determining that a stability detection result is that a stable state has not been reached; if so, determining that a stable state has been reached; Among them, if the detection result is that the stable state has not been reached, a primary voltage control signal is generated according to the detection result, and the channel impedance of the original input clock signal is adjusted based on the primary voltage control signal, including the following steps: filtering the identification signal to generate a primary voltage control signal, when the high level average value of the identification signal is greater than the low level average value, adjusting the channel impedance according to the primary voltage control signal so that the falling edge slope of the original input clock signal increases and the rising edge slope decreases; when the high level average value of the identification signal is less than the low level average value, adjusting the channel impedance according to the primary voltage control signal so that the falling edge slope of the original input clock signal decreases and the rising edge slope increases.

2. The clock duty cycle adjustment method according to claim 1, wherein: The first current source charges the first capacitor, comprising the following steps: When the first phase clock signal is at a low level, the second phase clock signal is at a high level, and the inverted input clock signal is at a high level, the first current source charges the first capacitor.

3. The clock duty cycle adjustment method according to claim 1, wherein: The second current source charges the second capacitor, comprising the following steps: When the first phase clock signal is at a low level, the second phase clock signal is at a high level, and the inverted input clock signal is at a low level, the second current charges the second capacitor.

4. The clock duty cycle adjustment method according to claim 1, wherein: The channel impedance of the original input clock signal is adjusted based on the primary voltage control signal until the detection result reaches a stable state, comprising the following steps: Obtaining an input clock adjustment signal obtained after channel impedance adjustment, performing two-phase non-overlapping processing on the input clock adjustment signal to obtain a first-phase clock adjustment signal and a second-phase clock adjustment signal, and simultaneously performing inversion processing on the input clock adjustment signal to obtain an inverted input clock adjustment signal; Based on the first phase clock adjustment signal, the second phase clock adjustment signal, the reverse input clock adjustment signal, and the input clock adjustment signal, the first current source charges the first capacitor, the second current source charges the second capacitor, and the first capacitor and the second capacitor are charged alternately; Obtaining a first voltage each time the first capacitor is charged and a second voltage each time the second capacitor is charged, and re-performing a stability test on the first voltage and the second voltage obtained each time; If the result of the re-test of the stability test is that a stable state has been reached, the input clock adjustment signal is directly output; if the test result is that a stable state has not been reached, a secondary voltage control signal is generated according to the test result, and the channel impedance of the input clock adjustment signal is adjusted based on the secondary voltage control signal until the test result reaches a stable state.

5. The clock duty cycle adjustment method according to claim 1, wherein: After each cross-charging of the first capacitor and the second capacitor is completed, the method further includes the following steps: Reset the first capacitor and the second capacitor.

6. The clock duty cycle adjustment method according to claim 5, wherein: Resetting the first capacitor and the second capacitor includes the following steps: When the first phase clock signal is at a high level and the second phase clock signal is at a low level, the first capacitor and the second capacitor enter a discharge process, and when the first capacitor and the second capacitor complete the discharge, the reset is completed.

7. The clock duty cycle adjustment method according to claim 1, wherein: The configuration formula for configuring the values ​​of the first current source, the first capacitor, the second current source, and the second capacitor in the duty cycle-to-voltage conversion circuit based on the target clock duty cycle is as follows: , where D represents the target clock duty cycle, CH represents the capacitance value of the second capacitor, IL represents the current value of the first current source, CL represents the capacitance value of the first capacitor, and IH represents the current value of the second current source.

8. A clock duty cycle adjustment system, characterized in that: The clock duty cycle adjustment system is used to perform the clock duty cycle adjustment method according to any one of claims 1 to 7, comprising a clock buffer circuit, a clock generation circuit, a duty cycle-voltage conversion circuit, a comparison circuit, and a filter circuit; The clock generating circuit is used to perform two-phase non-overlapping processing on the original input clock signal to obtain a first phase clock signal and a second phase clock signal, and at the same time perform inversion processing on the original input clock signal to obtain an inverted input clock signal; The duty cycle-to-voltage conversion circuit is configured to cause the first current source to charge the first capacitor to obtain a first voltage, and the second current source to charge the second capacitor to obtain a second voltage, based on the first phase clock signal, the second phase clock signal, the reverse input clock signal, and the original input clock signal, wherein the first capacitor and the second capacitor are charged alternately; The comparison circuit is configured to obtain a first voltage each time the first capacitor is charged and a second voltage each time the second capacitor is charged, and perform stability detection on the first voltage and the second voltage obtained each time; The filtering circuit is used to filter the identification signal; The clock buffer circuit is used to directly output the original input clock signal when the detection result of the stability detection is that a stable state has been reached; when the detection result is that a stable state has not been reached, generate a primary voltage control signal according to the detection result, and adjust the channel impedance of the original input clock signal based on the primary voltage control signal until the detection result reaches a stable state.

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