Signal acquisition circuit and electronic equipment

Abstract

The invention discloses a signal acquisition circuit and electronic equipment, and the signal acquisition circuit comprises an acquisition interface which is used for electrically connecting a sensor and a signal processing circuit, so as to receive a signal collected and output by the sensor; the differential mode interference protection circuit is electrically connected with the acquisition interface and the signal processing circuit and is used for filtering differential mode interference signals in signals output by the acquisition interface; the common-mode interference protection circuit is electrically connected with the acquisition interface and the signal processing circuit and is used for filtering common-mode interference signals in signals output by the acquisition interface; and the signal processing circuit processes the signal after filtering the differential mode interference signal and the common mode interference signal. According to the embodiment of the invention, the interference protection level can be effectively improved, and the influence on devices in the signal processing device is avoided.

Description

Technical Field

[0001] This application relates to the technical field of signal acquisition and processing, and particularly to a signal acquisition circuit and an electronic device. Background Art

[0002] Signal acquisition is an important link for determining the working state of electronic devices such as switches and servers and adjusting the working state of electronic devices. It is necessary to strictly limit signal acquisition to obtain accurate signals, and then accurately determine the working state of electronic devices or adjust the state of electronic devices.

[0003] During the signal acquisition process, some interference signals may enter the signal processing related devices, affecting the operation of the signal processing related devices, and even damaging the devices, resulting in the signal processing related devices being unable to normally acquire accurate signals. Summary of the Invention

[0004] The main purpose of the embodiments of this application is to provide a signal acquisition circuit and an electronic device. The embodiments of this application can effectively filter out interference signals and prevent them from affecting the devices.

[0005] In a first aspect, the embodiments of this application provide a signal acquisition circuit. The signal acquisition circuit includes: an acquisition interface, a differential mode interference protection circuit, a common mode interference protection circuit, and a signal processing circuit;

[0006] The acquisition interface is used to electrically connect a sensor and the signal processing circuit to receive the signal collected and output by the sensor;

[0007] The differential mode interference protection circuit is electrically connected to the acquisition interface and the signal processing circuit respectively, and is used to filter out the differential mode interference signals in the signal output by the acquisition interface;

[0008] The common mode interference protection circuit is electrically connected to the acquisition interface and the signal processing circuit respectively, and is used to filter out the common mode interference signals in the signal output by the acquisition interface; and

[0009] The signal processing circuit is used to process the signal after filtering out the differential mode interference signal and the common mode interference signal.

[0010] In the embodiments of this application, a differential mode interference protection circuit and a common mode interference protection circuit electrically connected to the acquisition interface are provided. The differential mode interference protection circuit is used to filter out the differential mode interference signals in the signal, and the common mode interference protection circuit is used to filter out the common mode interference signals in the signal output by the acquisition interface, so as to effectively filter out all the interference signals, avoid the interference signals existing in the acquisition interface from affecting the signal processing related devices, and improve the interference protection level.

[0011] In some implementations of the first aspect, the differential-mode interference protection circuit includes: a first clamping circuit;

[0012] The first connection end of the first clamping circuit is connected to the first output end of the acquisition interface, and the second connection end of the first clamping circuit is connected to the second output end of the acquisition interface and the signal processing circuit;

[0013] The first clamping circuit is used to perform voltage clamping when a first voltage between the first output end and the second output end of the acquisition interface is greater than a first preset voltage.

[0014] In the embodiments of the present application, through the setting of the first clamping circuit, the first voltage between the first output end and the second output end of the acquisition interface can be clamped within a set range. Without differential-mode interference, the signal between the first output end and the second output end of the acquisition interface is output to the signal processing circuit.

[0015] In some implementations of the first aspect, the first clamping circuit includes a first clamping diode; the input end of the first clamping diode is electrically connected to the first power supply and the first output end of the acquisition interface, and the output end of the first clamping diode is electrically connected to the second output end of the acquisition interface and the signal processing circuit.

[0016] In some implementations of the first aspect, the common-mode interference protection circuit includes: a second clamping circuit and a common-mode discharge circuit; the first connection end of the second clamping circuit is electrically connected to the first output end and the second output end of the acquisition interface, and the second connection end of the second clamping circuit is electrically connected to the third output end of the acquisition interface and the common-mode discharge circuit; the second clamping circuit is used to perform voltage clamping when a second voltage between the first output end and the third output end of the acquisition interface is greater than a second preset voltage and / or a third voltage between the second output end and the third output end of the acquisition interface is greater than a third preset voltage; the common-mode discharge circuit is used to discharge the clamped second voltage and / or the clamped third voltage.

[0017] Through the setting of the second clamping circuit and the common-mode discharge circuit, the second voltage between the first output end and the third output end of the acquisition interface can be clamped within a set range, and the third voltage between the second output end and the third output end of the acquisition interface can be clamped within a set range. Moreover, the excess voltage in the clamped second voltage and third voltage is discharged, so that without common-mode interference, the signals between the first output end and the third output end and between the second output end and the third output end of the acquisition interface can be output to the signal processing circuit.

[0018] In some implementations of the first aspect, the second clamping circuit includes: a second clamping diode and a third clamping diode;

[0019] The input end of the second clamping diode is electrically connected to the first output end of the acquisition interface, the input end of the third clamping diode is electrically connected to the second output end of the acquisition interface, and the output ends of the second clamping diode and the third clamping diode are both electrically connected to the third output end of the acquisition interface and the common-mode discharge circuit.

[0020] In some implementations of the first aspect, the signal acquisition circuit further includes: a first capacitor; a first end of the first capacitor is electrically connected to the second end of the acquisition interface, the common-mode interference protection circuit, and the signal processing circuit respectively, and a second end of the first capacitor is electrically connected to the third end of the acquisition interface, the common-mode interference protection circuit, and the signal processing circuit respectively.

[0021] In some implementations of the first aspect, the signal acquisition circuit further includes: a first capacitor; the first capacitor is disposed in parallel across the two ends of the third clamping diode.

[0022] In the embodiment of the present application, by providing the first capacitor, it is possible to effectively avoid the voltage value applied across the third clamping diode D3 being too high instantaneously, thereby avoiding affecting the third clamping diode D3.

[0023] In some implementations of the first aspect, the common-mode discharge circuit includes: a gas discharge tube; a first end of the gas discharge tube is electrically connected to the second connection end of the second clamping circuit, and a second end of the gas discharge tube is electrically connected to the protective ground terminal.

[0024] In some implementations of the first aspect, the common-mode discharge circuit includes: a second capacitor; a first end of the second capacitor is electrically connected to the second connection end of the second clamping circuit, and a second end of the second capacitor is electrically connected to the protective ground terminal.

[0025] In the embodiment of the present application, the second clamping diode is used to clamp the second voltage between the first output end and the third output end of the acquisition interface, and the gas discharge tube and the second capacitor are used to discharge the clamped second voltage. Also, the third clamping diode is used to clamp the third voltage between the second output end and the third output end of the acquisition interface, and the second capacitor and the gas discharge tube are used to discharge the clamped third voltage, so as to prevent the common-mode interference signal transmitted by the acquisition interface from being transmitted to the signal processing circuit and affecting the working state of the signal processing circuit.

[0026] In some implementations of the first aspect, the signal processing circuit includes: a voltage follower circuit and a processing chip; the voltage follower circuit is electrically connected to the second output end of the acquisition interface, the differential-mode interference protection circuit, the common-mode interference protection circuit, and the processing chip respectively; the voltage follower circuit is used to perform voltage following on the signal.

[0027] In certain implementations of the first aspect, the voltage follower circuit includes: a first resistor, a second resistor, a third resistor, a third capacitor, and an inverting follower;

[0028] The first end of the first resistor is electrically connected to the first end of the second resistor and the output end of the acquisition interface, the second end of the first resistor is electrically connected to the non-inverting input end of the inverting follower, and the second end of the second resistor is grounded;

[0029] The inverting input end of the inverting follower is electrically connected to the output end of the inverting follower, the first end of the third resistor, and the first end of the third capacitor respectively;

[0030] The second end of the third resistor is electrically connected to the processing chip, and the second end of the third capacitor is grounded.

[0031] In the embodiments of the present application, the voltage follower circuit can perform voltage following on the signal according to the transmission timing set by the processing chip, so as to accurately transmit the signal to the processing chip; the processing chip can analyze the received signal to obtain the required data information.

[0032] In certain implementations of the first aspect, a power supply circuit and an anti-backflow circuit; the power supply circuit is electrically connected to the processing chip and the voltage follower circuit through the anti-backflow circuit; the power supply circuit is used to provide a power supply voltage for the processing chip through the anti-backflow circuit.

[0033] In the embodiments of the present application, the power supply circuit can generate the power supply voltage required by the processing chip, and then output the power supply voltage to the power supply terminal of the processing chip through the anti-backflow circuit to supply power to the processing chip.

[0034] In certain implementations of the first aspect, the power supply circuit includes: a voltage conversion circuit;

[0035] The voltage conversion circuit is electrically connected to the processing chip and the voltage follower circuit through the anti-backflow circuit; the voltage conversion circuit is also electrically connected to a second power supply;

[0036] The voltage conversion circuit is used to convert the power supply voltage output by the second power supply into the power supply voltage required by the processing chip.

[0037] In the power supply circuit of the embodiments of the present application, a voltage conversion circuit is provided, and the voltage conversion circuit can convert the power supply voltage output by the second power supply into the power supply voltage used by the processing chip, avoiding the mismatch between the power supply voltage output by the second power supply and the power supply voltage required by the processing chip.

[0038] In certain implementations of the first aspect, the power supply circuit further includes: a filtering circuit;

[0039] The filtering circuit is electrically connected to the voltage conversion circuit and the second power supply; the filtering circuit is used to filter the power supply voltage output by the second power supply.

[0040] A filter circuit is also provided in the power supply circuit of the embodiment of the present application. Through this filter circuit, interference signals in the second power supply can be filtered out to avoid interference in the power supply voltage.

[0041] In some implementation manners of the first aspect, the filter circuit includes: a fourth capacitor and a fifth capacitor;

[0042] The first end of the fourth capacitor is electrically connected to the positive output end of the second power supply and the input end of the voltage conversion circuit respectively, and the second end of the fourth capacitor is electrically connected to the protective grounding end;

[0043] The first end of the fifth capacitor is electrically connected to the negative output end of the second power supply, and the second end of the fifth capacitor is electrically connected to the protective grounding end.

[0044] In some implementation manners of the first aspect, the anti-backflow circuit includes a first diode and a second diode;

[0045] The cathode of the first diode is electrically connected to the output end of the power supply circuit, the anode of the first diode is electrically connected to the cathode of the second diode and the processing chip, and the cathode of the second diode is electrically connected to the negative output end of the second power supply.

[0046] In a second aspect, an embodiment of the present application provides an electronic device, which includes a sensor and a signal acquisition circuit;

[0047] The signal acquisition circuit is electrically connected to the acquisition interface of the sensor and the acquisition circuit.

[0048] The technical effects obtained in the above second aspect are similar to those obtained by the corresponding technical means in the above first aspect, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is the first structural schematic diagram of the first embodiment of the signal acquisition circuit in the present application;

[0050] Figure 2 It is the structural schematic diagram of the second embodiment of the signal acquisition circuit in the present application;

[0051] Figure 3 It is the circuit schematic diagram of the differential-mode interference protection circuit of the signal acquisition circuit in the present application;

[0052] Figure 4 It is the structural schematic diagram of the third embodiment of the signal acquisition circuit in the present application;

[0053] Figure 5 It is the circuit schematic diagram of the common-mode interference protection circuit of the signal acquisition circuit in the present application;

[0054] Figure 6It is the first structural schematic diagram of the fourth embodiment of the signal acquisition circuit in this application;

[0055] Figure 7 It is the circuit schematic diagram of the voltage follower circuit of the signal acquisition circuit in this application;

[0056] Figure 8 It is the second structural schematic diagram of the fourth embodiment of the signal acquisition circuit in this application;

[0057] Figure 9 It is the third structural schematic diagram of the fourth embodiment of the signal acquisition circuit in this application;

[0058] Figure 10 It is the fourth structural schematic diagram of the fourth embodiment of the signal acquisition circuit in this application;

[0059] Figure 11 It is the circuit schematic diagram of the signal acquisition circuit in this application.

[0060] Explanation of reference numerals:

[0061] 10, acquisition interface; 20, differential-mode interference protection circuit; 201, first clamping circuit; 30, common-mode interference protection circuit; 301, second clamping circuit; 302, common-mode discharge circuit; 40, signal processing circuit; 401, voltage follower circuit; 402, processing chip; 50, power supply circuit; 501, voltage conversion circuit; 502, filtering circuit; 60, anti-backflow circuit;

[0062] VCC1, first power supply; VCC2, second power supply; D1, first clamping diode; D2, second clamping diode; D3, third clamping diode; D4, first diode; D5, second diode; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; R1, first resistor; R2, second resistor; R3, third resistor; A, reverse follower; PE, protection ground terminal; AGND, analog ground terminal; DGND, digital ground terminal. Detailed implementation manners

[0063] For the convenience of clearly describing the technical solutions of the embodiments of this application, in the embodiments of this application, terms such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first chip and the second chip are only used to distinguish different chips, and their sequence is not limited. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and terms such as "first" and "second" do not necessarily limit being different.

[0064] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0065] In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b, or c can represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, c can be single or multiple.

[0066] The embodiments of the present application provide an electronic device, which includes a sensor and a signal acquisition circuit; the signal acquisition circuit is connected to the sensor. The sensor establishes a connection with the signal acquisition circuit through an acquisition interface. Among them, the signal acquisition circuit is a circuit for acquiring information such as temperature and humidity in the environment where the electronic device is located. The signal acquisition circuit can include a sensor or can be connected to a sensor.

[0067] Specifically, an electronic device is usually in a non-stop working state. In the case of long-term operation, it is necessary to detect the state of the electronic device to understand the current working environment of the electronic device and then adjust the working state of the electronic device. For example, when the electronic device is a server, the signal acquisition circuit can determine the current working state of the server through the acquired signals. Then, when there is a difference between the current working state and the standard working state of the server, the working state of the server can be adjusted through a controller to prevent the server from running in a non-standard working state for a long time. Among them, the controller for adjusting the server state can be one of the devices such as the Central Processing Unit (CPU), Field Programmable Gate Array (FPGA), Digital Signal Process (DSP), and Baseboard Management Controller (BMC) inside the server. The signal acquisition circuit can output the signal after filtering out interference to the controller. When receiving the signal, the controller can compare the specific value of the signal with the specific value in the normal operation state of the server, and then determine the current working state of the server and further determine whether it is necessary to adjust the server.

[0068] Of course, the processing chip in the signal acquisition circuit and the controller in the server can be the same device, which can simultaneously have the signal processing function and the working state control function of the server. Of course, the electronic device in this application is not limited to the above-mentioned server, and can also be devices such as switches. For the interference protection in the signal acquisition of other devices, reference can be made to the description of the server part.

[0069] It should be understood that during the signal acquisition process, some interference signals may enter the signal processing device, such as Electrical Fast Transient (EFT), Electro-Static discharge (ESD), surge interference, and conducted interference, etc. When this part of the interference enters the signal processing device, it will affect the working state of the signal processing device, such as burning out some devices, and some devices being unable to communicate normally, etc. During the test process, there is electrostatic interference of standard IEC61000-4-2, or transient pulse interference of IEC61000-4-4, or surge interference of IEC61000-4-5, and effective protection needs to be provided for the interference of this part of the standard. And in actual use, when any of the above interferences exists, in order to avoid the device from malfunctioning, interference protection also needs to be applied. Among them, the signal processing device can be devices such as FPGA and DSP equipped with a processing chip and peripheral circuits.

[0070] The first embodiment of the signal acquisition circuit proposed in the embodiments of the present application is shown in Figure 1 , Figure 1 which is the first structural schematic diagram of the first embodiment of the signal acquisition circuit of the present application.

[0071] In the first embodiment, the signal acquisition circuit includes: a collection interface 10, a differential-mode interference protection circuit 20, a common-mode interference protection circuit 30, and a signal processing circuit 40;

[0072] The collection interface 10 is used to electrically connect the sensor and the signal processing circuit 40 to receive the signal collected and output by the sensor;

[0073] The differential-mode interference protection circuit 20 is electrically connected to the collection interface 10 and the signal processing circuit 40 respectively, and is used to filter out the differential-mode interference signals in the signal output by the collection interface 10;

[0074] The common-mode interference protection circuit 30 is electrically connected to the collection interface 10 and the signal processing circuit 40 respectively, and is used to filter out the common-mode interference signals in the signal output by the collection interface 10; and

[0075] The signal processing circuit 40 is used to process the signal after filtering out the differential-mode interference signal and the common-mode interference signal.

[0076] It should be noted that the acquisition interface 10 is an interface for establishing a connection with a sensor. When the acquisition interface 10 is electrically connected to the sensor, it can receive the signals collected and output by the sensor. In addition, the acquisition interface 10 may also receive interference signals that affect other devices in the signal sampling circuit. The interference signals are manifested as common-mode interference signals and differential-mode interference signals on the transmission path of the acquisition interface 10. The sensor connected to the acquisition interface 10 can collect signals in the working state, working environment, etc. of the electronic device. For example, when it is necessary to collect temperature signals, the sensor connected to the acquisition interface 10 is a temperature sensor, and the temperature sensor can collect the temperature signal of the current location of the electronic device. By collecting the temperature signals in the environment, it can be determined whether it is necessary to adjust the working state of the electronic device; for another example, when it is necessary to collect humidity signals, the sensor connected to the acquisition interface 10 is a humidity sensor.

[0077] It can be understood that when interference such as electrostatic interference, transient pulse interference, and surge interference occurs, it is manifested in the form of differential-mode interference signals or common-mode interference signals on the transmission path. The interference protection circuit is a circuit for filtering interference signals to protect the signal processing circuit, and specifically may include a differential-mode interference protection circuit 20 and a common-mode interference protection circuit 30. The differential-mode interference protection circuit 20 is a circuit for filtering the differential-mode interference signals in the signals output by the acquisition interface 10. The differential-mode interference protection circuit 20 can filter the differential-mode interference signals in the signals output by the acquisition interface 10, thereby preventing the differential-mode interference signals belonging to the interference signals from entering the signal processing circuit 40. Similarly, the common-mode interference protection circuit 30 is a circuit for filtering the common-mode interference signals in the signals output by the acquisition interface 10, thereby preventing the common-mode interference signals belonging to the interference signals from entering the signal processing circuit 40. During the filtering process of the interference signals, the interference signals can be determined through the parameter differences between the interference signals and the signals. For example, if the interference signal is an electrostatic signal, the peak value of the electrostatic signal in a short period of time is significantly greater than the amplitude of the signal, and the amplitude of the signal is relatively stable. In the case of determining the signal with a larger peak value, the signal with the larger peak value can be filtered.

[0078] Among them, the signal processing circuit 40 is a circuit for processing the signals after filtering the differential-mode interference signals and the common-mode interference signals. Usually, the signals input by the sensor are voltage signals or current signals, and the signal processing circuit 40 can determine the information actually collected by the sensor according to the voltage signal or current signal. For example, when a temperature sensor inputs a voltage signal reflecting temperature changes, the signal processing circuit 40 can analyze the temperature information collected by the temperature sensor according to the specific waveform of the voltage signal.

[0079] In a specific implementation, the acquisition interface 10 can receive the signals input by the sensors connected thereto. During the signal transmission process, the differential-mode interference protection circuit 20 connected to the acquisition interface 10 can filter out the differential-mode interference signals in the signals output by the acquisition interface 10, and the common-mode interference protection circuit 30 connected to the differential-mode interference protection circuit 20 can filter out the common-mode interference signals in the signals. At this time, there are no differential-mode interference signals and common-mode interference signals in the signals output by the acquisition interface 10, and the signal processing circuit 40 can directly process the signals after filtering out the differential-mode interference signals and common-mode interference signals. The signal processing circuit 40 can determine the working state of the electronic device through the signal processing process. For example, when the acquired signal is a temperature signal, the temperature information of the electronic device in the environment can be determined by analyzing and processing the temperature signal, and then it can be determined whether it is necessary to adjust the working state of the electronic device.

[0080] Among them, the signal can reflect the environmental state where the electronic device is currently located. This signal is related to the sensors actually connected to the signal acquisition circuit. For example, the acquired information can be temperature information, humidity information, voltage information, current information, etc.

[0081] In the first embodiment, since the transmission paths of the differential-mode signal and the common-mode signal are different, the differential-mode interference signal will be transmitted through the differential-mode path between the first output terminal and the second output terminal of the acquisition interface 10, and the common-mode interference signal will be transmitted through the first output terminal and the third output terminal of the acquisition interface 10 and between the second output terminal and the third output terminal. A differential-mode interference protection circuit and a common-mode interference protection circuit are electrically connected to the acquisition interface. By using the differential-mode interference protection circuit to filter out the differential-mode interference signals in the signals and using the common-mode interference protection circuit to filter out the common-mode interference signals in the signals output by the acquisition interface, all the interference signals can be effectively filtered out, avoiding the interference signals existing in the acquisition interface from affecting the signal processing related devices and improving the interference protection level.

[0082] Based on the first embodiment of the signal acquisition circuit of the present application, a second embodiment of the signal acquisition circuit of the present application is proposed. Refer to Figure 2 , Figure 2 which is the structural schematic diagram of the second embodiment of the signal acquisition circuit in the present application.

[0083] In the second embodiment of the signal acquisition circuit of the present application, the same or similar content as that in the above first embodiment can be referred to the above introduction and will not be repeated hereinafter.

[0084] On this basis, in the embodiment of the present application, the differential-mode interference protection circuit 20 includes: a first clamping circuit 201;

[0085] The first connection terminal of the first clamping circuit 201 is electrically connected to the first output terminal of the acquisition interface 10, and the second connection terminal of the first clamping circuit 201 is electrically connected to the second output terminal of the acquisition interface 10 and the signal processing circuit 40.

[0086] It should be understood that there are many ways to filter interference signals. In the embodiments of the present application, the differential-mode interference signals in the transmission path can be filtered by means of voltage clamping.

[0087] It should be noted that the clamping circuit is a circuit used to clamp the voltage between the devices or wires connected to both ends of the clamping circuit. By means of clamping, the voltage between the devices or wires connected to both ends of the clamping circuit can be maintained below a certain voltage value, avoiding too high a voltage value between the devices or wires connected to both ends of the clamping circuit. The specific voltage value that the clamping circuit needs to clamp is related to the signal processing circuit 40 that receives the signal at the rear end.

[0088] Among them, the first clamping circuit 201 is used to clamp the signal voltage between the first output terminal and the second output terminal of the acquisition interface 10, avoiding too high a voltage value input from between the first output terminal and the second output terminal of the acquisition interface 10 to the signal processing circuit 40.

[0089] In a specific implementation, the first clamping circuit 201 can perform voltage clamping when the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 is greater than the first preset voltage. For example, when the first voltage output through the first output terminal and the second output terminal of the acquisition interface 10 is 10V, and the voltage that needs to be output from between the first output terminal and the second output terminal of the acquisition interface 10 to the signal processing circuit 40 is 3V, that is, the devices in the signal processing circuit 40 can withstand a maximum voltage of 3V; at this time, the first clamping circuit 201 can clamp the voltage value of the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 at 3V, so as to ensure that the voltage value input from between the first output terminal and the second output terminal of the acquisition interface 10 to the signal processing circuit 40 is maintained at 3V.

[0090] Among them, the first preset voltage is a voltage preset to determine whether there is a differential-mode interference signal between the first output terminal and the second output terminal of the acquisition interface 10. When the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 is greater than the first preset voltage, it indicates that there is a differential-mode interference signal between the first output terminal and the second output terminal of the acquisition interface 10; when the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 is not greater than the first preset voltage, it indicates that there is no differential-mode interference signal between the first output terminal and the second output terminal of the acquisition interface 10. The specific voltage value of the first preset voltage can be determined according to the voltage value of the signal, and a voltage value within a certain range greater than the signal voltage value can be selected; for example, if the voltage value of the signal is 3V, the first preset voltage can be set to 4V.

[0091] In the second embodiment, by setting the first clamping circuit 201, the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 can be clamped within a set range, and the signal between the first output terminal and the second output terminal of the acquisition interface 10 can be output to the signal processing circuit 40 while ensuring no differential-mode interference.

[0092] Refer to Figure 3 , in the second embodiment, the first clamping circuit 201 includes: a first clamping diode D1;

[0093] The input end of the first clamping diode D1 is connected to the first power supply (Volt Current Condenser1, VCC1) and the first output terminal of the acquisition interface 10, and the output end of the first clamping diode D1 is connected to the second output terminal of the acquisition interface 10 and the signal processing circuit 40.

[0094] It should be understood that the first clamping diode D1 can clamp the voltage between the devices or wires connected to both sides of the input end and the output end of the first clamping diode D1. The specific clamping voltage of the first clamping diode D1 is related to the first voltage that needs to be input to the signal processing circuit 40 between the first output terminal and the second output terminal of the acquisition interface 10. The first clamping diode D1 can be selected according to the voltage value that needs to be input to the signal processing circuit 40. The first power supply VCC1 can be a 15V power supply, and the first power supply VCC1 can form a high voltage at the first connection end of the first clamping diode D1. The first connection end of the first clamping diode D1 can be the input end, and the second connection end can be the output end.

[0095] In Figure 3In [the circuit], the first clamping circuit 201 includes a first clamping diode D1; in a specific implementation process, the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 can be clamped by the first clamping diode D1, so as to effectively avoid the differential-mode interference signal output between the first output terminal and the second output terminal of the acquisition interface 10 and input into the signal processing circuit 40.

[0096] Based on the first embodiment or the second embodiment of the signal acquisition circuit of the present application, a third embodiment of the signal acquisition circuit of the present application is proposed. Refer to Figure 4 , Figure 4 which is a schematic structural diagram of the third embodiment of the signal acquisition circuit in the present application.

[0097] In the third embodiment of the signal acquisition circuit of the present application, the content that is the same as or similar to the above first embodiment or second embodiment can be referred to the above introduction and will not be elaborated hereinafter.

[0098] On this basis, in the third embodiment, the common-mode interference protection circuit 30 includes: a second clamping circuit 301 and a common-mode discharge circuit 302;

[0099] The first connection end of the second clamping circuit 301 is electrically connected to the first output terminal and the second output terminal of the acquisition interface 10, and the second connection end of the second clamping circuit 301 is electrically connected to the third output terminal of the acquisition interface 10 and the common-mode discharge circuit 302.

[0100] In the third embodiment, the common-mode interference signal in the transmission path is also filtered by means of voltage clamping and discharge. The second clamping circuit 301 is used to clamp the signal voltage between the first output terminal and the third output terminal of the acquisition interface 10, and to clamp the signal voltage between the second output terminal and the third output terminal of the acquisition interface 10; to prevent the voltage value input from the first output terminal to the third output terminal or the second output terminal to the third output terminal of the acquisition interface 10 into the signal processing circuit 40 from being too high. The common-mode discharge circuit 302 is a circuit used to discharge the clamped voltage between the first output terminal and the third output terminal of the acquisition interface 10 and between the second output terminal and the third output terminal of the acquisition interface 10.

[0101] In a specific implementation, the second clamping circuit 301 can perform voltage clamping when the second voltage between the first output terminal and the third output terminal of the acquisition interface 10 is greater than a second preset voltage; the common-mode discharge circuit 302 can discharge the clamped second voltage; and the second clamping circuit 301 can perform voltage clamping when the third voltage between the second output terminal and the third output terminal of the acquisition interface 10 is greater than a third preset voltage; the common-mode discharge circuit 302 can also discharge the clamped third voltage.

[0102] Among them, the second preset voltage is a voltage preset for determining whether there is a common-mode interference signal between the first output terminal and the third output terminal of the acquisition interface 10. When the second voltage between the first output terminal and the third output terminal of the acquisition interface 10 is greater than the second preset voltage, it indicates that there is a common-mode interference signal between the first output terminal and the third output terminal of the acquisition interface 10; when the second voltage between the first output terminal and the third output terminal of the acquisition interface 10 is not greater than the second preset voltage, it indicates that there is no common-mode interference signal between the first output terminal and the third output terminal of the acquisition interface 10. Similarly, the third preset voltage is a voltage preset for determining whether there is a common-mode interference signal between the second output terminal and the third output terminal of the acquisition interface 10. When the third voltage between the second output terminal and the third output terminal of the acquisition interface 10 is greater than the third preset voltage, it indicates that there is a common-mode interference signal between the second output terminal and the third output terminal of the acquisition interface 10; when the third voltage between the second output terminal and the third output terminal of the acquisition interface 10 is not greater than the third preset voltage, it indicates that there is no common-mode interference signal between the second output terminal and the third output terminal of the acquisition interface 10. The specific voltage values of the second preset voltage and the third preset voltage can also be determined according to the voltage value of the signal, and a voltage value within a certain range greater than the signal voltage value can be selected.

[0103] It should be emphasized that when one of the second voltage between the first output terminal and the third output terminal of the acquisition interface 10 and the third voltage between the second output terminal and the third output terminal is greater than the corresponding preset voltage, the second clamping circuit 301 can directly clamp the second voltage or the third voltage with a common-mode interference signal, and the common-mode discharge circuit 302 can discharge the redundant voltage and the common-mode interference signal in the second voltage or the third voltage.

[0104] In the third embodiment, through the setting of the second clamping circuit 301 and the common-mode discharge circuit 302, the second voltage between the first output terminal and the third output terminal of the acquisition interface 10 can be clamped within a set range, and the third voltage between the second output terminal and the third output terminal of the acquisition interface 10 can be clamped within a set range, and the redundant voltage in the clamped second voltage and third voltage can be discharged, so that the signals between the first output terminal and the third output terminal and between the second output terminal and the third output terminal of the acquisition interface 10 can be output to the signal processing circuit 40 while ensuring no common-mode interference.

[0105] Refer to Figure 5 In the third embodiment, the second clamping circuit 301 includes: a second clamping diode D2 and a third clamping diode D3;

[0106] The input end of the second clamping diode D2 is connected to the first output end of the acquisition interface 10, and the input end of the third clamping diode D3 is connected to the second output end of the acquisition interface 10. The output ends of the second clamping diode D2 and the third clamping diode D3 are both connected to the third output end of the acquisition interface 10 and the common-mode discharge circuit 302.

[0107] It should be noted that the second clamping diode D2 can clamp the voltage between the devices or wires connected to both sides of the input end and the output end of the second clamping diode D2. The specific clamping voltage of the second clamping diode D2 is related to the second voltage that needs to be input to the signal processing circuit 40 between the first output end and the third output end of the acquisition interface 10. The third clamping diode D3 can clamp the voltage between the devices or wires connected to both sides of the input end and the output end of the third clamping diode D3. The specific clamping voltage of the third clamping diode D3 is related to the third voltage that needs to be input to the signal processing circuit 40 between the second output end and the third output end of the acquisition interface 10.

[0108] In addition, the second clamping diode D2 can be selected according to the voltage value that needs to be input to the signal processing circuit 40 between the first output end and the third output end of the acquisition interface 10; similarly, the third clamping diode D3 can be selected according to the voltage value that needs to be input to the signal processing circuit 40 between the second output end and the third output end of the acquisition interface 10. The first connection end of the second clamping diode D2 and the third clamping diode D3 can be the input end, and the second connection end can be the output end.

[0109] Furthermore, in the third embodiment, the signal acquisition circuit further includes: a first capacitor C1; the first end of the first capacitor C1 is electrically connected to the second end of the acquisition interface 10, the common-mode interference protection circuit 30, and the signal processing circuit 40 respectively, and the second end of the first capacitor C1 is electrically connected to the third end of the acquisition interface 10, the common-mode interference protection circuit 30, and the signal processing circuit 40 respectively.

[0110] It can be understood that during the process of the common-mode interference protection circuit 30 clamping the voltage between the second output end and the third output end of the acquisition interface 10 and the voltage between the first output end and the second output end, there may be a situation where the interference signal is too high or there may be an instantaneous current spike in the case of an interference signal, resulting in an excessively high instantaneous voltage input to the devices in the common-mode interference protection circuit 30, affecting the operation of these devices. The devices in the common-mode interference protection circuit 30 that may be affected are the devices that control the input voltage, such as clamping diodes.

[0111] In the third embodiment, a first capacitor C1 is further provided. The first capacitor C1 is connected between the input end and the output end of the common-mode interference protection circuit 30, and can control the voltage input to the common-mode interference protection circuit 30 to rise slowly, avoiding affecting the components in the common-mode interference protection circuit 30.

[0112] In some examples, the first capacitor C1 is disposed in parallel across both ends of the third clamping diode D3.

[0113] It can be understood that during the process of clamping the voltage between the second output end and the third output end of the acquisition interface 10 by the third clamping diode D3, there may be a situation where the interference signal is too high or there is an instantaneous current spike in the presence of an interference signal, resulting in too high an instantaneous voltage input to the third clamping diode D3, which affects the operation of the third clamping diode D3.

[0114] In the third embodiment, through the setting of the first capacitor C1, the capacitance of the first capacitor C1 enables the voltage value across the third clamping diode D3 to rise slowly until it reaches the clamping voltage corresponding to the third clamping diode D3. Therefore, even in the presence of a large voltage impact, the voltage value across the third clamping diode D3 can be controlled to rise slowly to reach the clamping voltage corresponding to the third clamping diode D3, thereby effectively avoiding too high a voltage value instantaneously applied across the third clamping diode D3 and affecting the third clamping diode D3.

[0115] In the third embodiment, the common-mode discharge circuit 302 includes: a gas discharge tube (GDT);

[0116] The first end of the gas discharge tube GDT is connected to the second connection end of the second clamping circuit 301, and the second end of the gas discharge tube GDT is connected to the protective ground terminal PE.

[0117] It should be understood that the gas discharge tube GDT is a discharge gap sealed in a ceramic cavity, and the cavity is filled with an inert gas to stabilize the discharge voltage of the discharge tube. In the presence of a large voltage impact, the current flowing through the gas discharge tube GDT is large, and the over-high voltage can instantaneously turn on the gas discharge tube GDT, thereby providing a low-impedance discharge path. The gas discharge tube GDT can be used to discharge the common-mode interference signals between the second output end and the third output end of the acquisition interface 10 and the common-mode interference signals between the first output end and the second output end.

[0118] The common-mode discharge circuit includes: a second capacitor C2; the first end of the second capacitor C2 is connected to the second connection end of the second clamping circuit 301, and the second end of the second capacitor C2 is connected to the protective ground terminal PE.

[0119] It can be understood that the second capacitor C2 is a low-impedance capacitor with respect to the common-mode interference signal. The common-mode interference signal between the first output terminal and the third output terminal of the acquisition interface 10 can be transmitted through the second capacitor C2, and then the common-mode interference signal is discharged. Of course, the common-mode interference signal between the second output terminal and the third output terminal of the acquisition interface 10 can also be transmitted through the second capacitor C2, and then the common-mode interference signal is discharged.

[0120] Considering that both the second capacitor C2 and the gas discharge tube GDT can discharge the power supply interference signal, therefore, in the embodiment of the present application, a second capacitor C2 or a gas discharge tube GDT can be provided between the second end of the second clamping circuit 301 and the protective grounding end; of course, a second capacitor C2 and a gas discharge tube GDT can also be provided between the second end of the second clamping circuit 301 and the protective grounding end at the same time, where the second capacitor C2 and the gas discharge tube GDT are connected in parallel.

[0121] In addition, the gas discharge tube GDT can be electrically connected to the second connection end of the second clamping diode D2 in the second clamping circuit 301, and the second capacitor C2 is connected to the second connection end of the third clamping diode D3 in the second clamping circuit 301; of course, the gas discharge tube GDT can be electrically connected to the second connection end of the third clamping diode D3 in the second clamping circuit 301, and the second capacitor C2 is connected to the second connection end of the second clamping diode D2 in the second clamping circuit 301; or the gas discharge tube GDT and the second capacitor C2 can also be electrically connected to the second connection end of the second clamping diode D2 and the second connection end of the third clamping diode D3.

[0122] In the third embodiment, when the second clamping diode D2 and the third clamping diode D3 are selected in the second clamping circuit 301, other devices can also be selected in the common-mode discharge circuit 302 to discharge the clamped second voltage and third voltage; similarly, when the second capacitor C2 and the gas discharge tube GDT are selected in the common-mode discharge circuit 302, other devices can also be selected in the second clamping circuit 301 to clamp the second voltage and third voltage transmitted by the acquisition interface 10, which is not specifically limited here.

[0123] In addition, when the third embodiment refers to the second embodiment, the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 can be clamped by the first clamping diode D1, thereby effectively avoiding the differential mode interference signal output from the first output terminal and the second output terminal of the acquisition interface 10 to the signal processing circuit 40; at the same time, the second clamping diode D2 can be used to clamp the second voltage between the first output terminal and the third output terminal of the acquisition interface 10, and the gas discharge tube GDT and the second capacitor C2 can be used to discharge the clamped second voltage, and the third clamping diode D3 can be used to clamp the third voltage between the second output terminal and the third output terminal of the acquisition interface 10, and the second capacitor C2 and the gas discharge tube GDT can be used to discharge the clamped third voltage, so as to avoid any interference signal of the differential mode interference signal and the common mode interference signal transmitted by the acquisition interface 10 from being transmitted to the signal processing circuit 40, thereby affecting the working state of the signal processing circuit 40.

[0124] Based on any one of the first to third embodiments of the signal acquisition circuit of the present application, a fourth embodiment of the signal acquisition circuit of the present application is proposed. Figure 6 , Figure 6 This is a first structural schematic diagram of the fourth embodiment of the signal acquisition circuit in this application.

[0125] In the fourth embodiment of the signal acquisition circuit of the present application, the same or similar contents as those in the first to third embodiments mentioned above can be referred to the above introduction and will not be described in detail later.

[0126] In the embodiment of the present application, the signal processing circuit 40 includes: a voltage follower circuit 401 and a processing chip 402;

[0127] The voltage follower circuit 401 is electrically connected to the acquisition interface 10 and the processing chip 402 respectively.

[0128] It should be understood that during the signal transmission process, there may be timing requirements for signal transmission. For example, when the transmission timing is set, the transmission timing of the signal is different from the set transmission timing, which may cause the processing chip 402 to be unable to identify the currently received signal as a signal, or the received signal has a partial waveform missing. The voltage follower circuit 401 is a circuit for adjusting the transmission timing of the signal. The following timing of the voltage follower circuit 401 is related to the specific setting timing of the processing chip 402.

[0129] It should be noted that the processing chip 402 is a chip used to parse signals to obtain acquisition information. The processing chip 402 can be set according to the information to be collected specifically. For example, when temperature signals need to be collected, since the signals output by the temperature sensor are analog signal waveforms, the processing chip 402 can be a digital signal processing (DSP) chip with analog-to-digital conversion settings at this time.

[0130] In a specific implementation, the voltage follower circuit 401 can perform voltage following on the signal according to the transmission timing set by the processing chip 402 to accurately transmit the signal to the processing chip 402; the processing chip 402 can analyze the received signal to obtain the data information to be acquired.

[0131] In the scenario where the electronic device is a server, considering that controllers such as BMC, CPU, FPGA, or DSP are usually set in the server, and this controller is mainly used to control the working state of the server. In the embodiments of the present application, the controller set in the server can also be used to replace the processing chip 402 to implement signal parsing and processing; of course, this controller can also implement other control functions inside the server, such as adjusting the operating parameters of the server. In addition, when the controller in the server does not have signal processing functions, a processing chip 402 can also be set separately, electrically connected to the controller in the server, and then the processed signal is transmitted to the controller through signal transmission, and then the working state of the server is adjusted.

[0132] Refer to Figure 7 , in the fourth embodiment, the voltage follower circuit 401 includes: a first resistor R1, a second resistor R2, a third resistor R3, a third capacitor C3, and an inverting follower A;

[0133] The first end of the first resistor R1 is electrically connected to the first end of the second resistor R2 and the output end of the acquisition interface 10, and the second end of the first resistor R1 is electrically connected to the non-inverting input terminal of the inverting follower A, and the second end of the second resistor R2 is grounded to GND;

[0134] The inverting input terminal of the inverting follower A is respectively electrically connected to the output terminal of the inverting follower A, the first end of the third resistor R3, and the first end of the third capacitor C3;

[0135] The second end of the third resistor R3 is electrically connected to the processing chip 402, and the second end of the third capacitor C3 is grounded to GND.

[0136] It should be noted that the first resistor R1 and the second resistor R2 are voltage-dividing resistors, which are used to adjust the voltage value input to the positive input terminal of the voltage follower A. The third resistor R3 is a voltage-dividing resistor, and the third capacitor C3 is a voltage-stabilizing capacitor. The voltage follower A is used to follow the input signal, thereby adjusting the timing of the signal.

[0137] In a specific implementation, the acquisition interface 10 can divide the signal through the first resistor R1 and the second resistor R2 and then output it to the positive input terminal of the voltage follower A. Then, the timing is adjusted inside the voltage follower A, and the signal after timing following is output at the output terminal of the voltage follower A, and the signal is input to the processing chip through the third capacitor C3 and the third resistor R3.

[0138] Refer to Figure 8 , Figure 8 which is the second structural schematic diagram of the fourth embodiment of the signal acquisition circuit in this application.

[0139] In the fourth embodiment, the signal acquisition circuit further includes: a power supply circuit 50 and an anti-backflow circuit 60;

[0140] The power supply circuit 50 is electrically connected to the processing chip 402 and the voltage follower circuit 401 through the anti-backflow circuit 60.

[0141] It should be understood that the processing chip 402 needs to be woken up by the supply voltage before it can work properly. When the processing chip 402 is in the wake-up state, it can receive signals and parse the signals.

[0142] It should be noted that the power supply circuit 50 is a power supply circuit for outputting the supply voltage to the processing chip 402 so that the control chip 402 can work properly. When the power supply circuit 50 is connected to the voltage follower circuit 401, it is possible that the supply voltage output by the power supply circuit 50 directly reversely inputs to the output terminal of the voltage follower circuit 401, thereby causing the sampling signal output by the voltage follower circuit 401 to not be able to be normally output to the processing chip 402. In the fourth embodiment, an anti-backflow circuit 60 is also provided. The anti-backflow circuit 60 is a circuit for preventing the supply voltage output by the power supply circuit 50 from flowing back to the voltage follower circuit 401 when the power supply circuit 50 is connected to the voltage follower circuit 401, so that the supply voltage can be prevented from flowing back to the voltage follower circuit 401.

[0143] In a specific implementation, the power supply circuit 50 can generate the supply voltage required by the processing chip 402, and then output the supply voltage to the power supply terminal of the processing chip 402 through the anti-backflow circuit 60 to supply power to the processing chip 402.

[0144] Refer to Figure 9 , Figure 9This is the third structural schematic diagram of the fourth embodiment of the signal acquisition circuit in this application. The power supply circuit includes: a voltage conversion circuit 501;

[0145] The voltage conversion circuit 501 is connected to the processing chip 402 and the voltage follower circuit 401 through an anti-backflow circuit 60; the voltage conversion circuit 501 is also connected to a second power supply (Volt Current Condenser2, VCC2).

[0146] It should be understood that the second power supply VCC2 can be a power supply that outputs a DC voltage, and the power supply voltage output by the second power supply VCC2 may not match the power supply voltage required by the processing chip 402. Generally, the power supply voltage output by the power supply does not change with the voltage required by the load. For example, fixed power supply voltages such as 12V and 5V. In order to avoid the power supply voltage output by the second power supply VCC2 not matching the power supply voltage required by the processing chip 402, a voltage conversion circuit 501 is provided in the power supply circuit 50. The voltage conversion circuit 501 can convert the power supply voltage output by the second power supply VCC2 into the power supply voltage used by the processing chip 402. For example, when the power supply voltage output by the second power supply VCC2 is 5V and the power supply voltage required by the processing chip 402 is 3.3V, at this time, the voltage conversion circuit 501 can convert the 5V voltage into 3.3V voltage, and then supply power to the processing chip 402.

[0147] It should be noted that the voltage conversion circuit 501 can be a transformer and related peripheral structures, or a Buck-Boost circuit, and no specific limitation is made here.

[0148] In a specific implementation, when the voltage conversion circuit 501 receives the power supply voltage output by the second power supply VCC2, it can convert the power supply voltage into the power supply voltage required by the processing chip 402 according to the power supply voltage required by the processing chip 402, and then supply power to the processing chip 402 through the anti-backflow circuit 60.

[0149] In addition, referring to Figure 10 , in the fourth embodiment, the power supply circuit 50 further includes: a filtering circuit 502;

[0150] The filtering circuit 502 is connected to the voltage conversion circuit 501 and the second power supply VCC2.

[0151] It should be noted that when the second power supply VCC2 outputs a power supply voltage, there may be interference signals affecting the voltage value of the power supply voltage. For example, there is electronic noise resulting in an unstable voltage value of the power supply voltage, which in turn causes an abnormality in the power supply voltage input to the processing chip 402, affecting the working state of the processing chip 402.

[0152] In the fourth embodiment, in order to avoid interference in the power supply voltage, a filter circuit 502 is further provided in the power supply circuit 50. The interference signals in the second power supply VCC2 can be filtered out through the filter circuit 502. The filter circuit 502 can be composed of a high-frequency filter or components with filtering functions, etc.

[0153] In a specific implementation, the filter circuit 502 can filter the power supply voltage output by the second power supply to obtain a stable power supply voltage, and then output the stable power supply voltage to the voltage conversion circuit 501. After being converted into a power supply voltage by the voltage conversion circuit 501, it supplies power to the processing chip 402.

[0154] Refer to Figure 11 , in the fourth embodiment, the filter circuit 502 includes: a fourth capacitor C4 and a fifth capacitor C5;

[0155] The first end of the fourth capacitor C4 is respectively connected to the positive output end of the second power supply VCC2 and the input end of the voltage conversion circuit 501, and the second end of the fourth capacitor C4 is connected to the protective grounding end PE;

[0156] The first end of the fifth capacitor C5 is connected to the negative output end of the second power supply VCC2, and the second end of the fifth capacitor C5 is connected to the protective grounding end PE.

[0157] It should be understood that the second power supply VCC2 is a DC power supply with a stable output voltage value. Usually, noise and interference signals are high-frequency signals. By setting capacitors, the high-frequency interference signals in the power supply voltage output by the second power supply VCC2 can be filtered out.

[0158] Therefore, in the fourth embodiment, by setting two capacitors, the fourth capacitor C4 and the fifth capacitor C5 respectively filter the voltage values output from the positive output end and the negative output end of the second power supply VCC2, and the high-frequency interference signals in the power supply voltage output by the second power supply VCC2 can be effectively filtered out, thereby avoiding the interference signals in the power supply voltage from affecting the working state of the processing chip 402.

[0159] In addition, refer to Figure 11 , in the fourth embodiment, the anti-backflow circuit 60 includes a first diode D4 and a second diode D5;

[0160] The cathode of the first diode D4 is connected to the output end of the power supply circuit 50, the anode of the first diode D4 is connected to the cathode of the second diode D5 and the processing chip 402, and the cathode of the second diode D5 is connected to the negative output end of the second power supply VCC2.

[0161] It should be understood that a diode has the characteristic of unidirectional conduction, and by using this diode, the current flow direction in the branch where the diode is located can be effectively controlled. In the fourth embodiment, two diodes can be set. One can prevent the power supply voltage output from the positive output terminal of the second power supply VCC2 from flowing back to the voltage follower circuit 401, and the other can prevent the signal output by the voltage follower circuit 401 from flowing back to the negative input terminal of the second power supply VCC2.

[0162] In a specific implementation, the first diode D4 can avoid the power supply voltage from being input to the voltage follower circuit 401 during the output process of the power supply voltage; the second diode D5 can avoid the signal output by the voltage follower circuit 401 from flowing back to the negative input terminal of the second power supply VCC2, thereby ensuring that there is no abnormality caused by voltage backflow between the voltage follower circuit 401 and the second power supply VCC2.

[0163] In addition, referring to Figure 11 , in Figure 11 , when the acquisition interface 10 transmits a common-mode interference signal, since the analog ground terminal AGND and the digital ground terminal DGND are directly connected, there are two discharge paths for the common-mode interference signal at this time: one is discharged through the second clamping diode D2, the third clamping diode D3, the gas discharge tube GDT, and the second capacitor C2; the other is discharged through the voltage follower circuit 401, the voltage conversion circuit 501, and the filtering circuit 502, that is, discharged through the analog ground terminal AGND, the digital ground terminal DGND, and the filtering circuit 502. Since the first discharge path and the second discharge path are arranged in parallel, when some common-mode interference signals are discharged through the second discharge path, they may be input to the processing chip 402, affecting the working state of the processing chip 402. During the operation of the signal sampling circuit, when there is electrostatic discharge, some static electricity may be input to the processing chip 402 through the voltage follower circuit 401, or input to the processing chip 402 through the analog ground terminal AGND and the digital ground terminal DGND.

[0164] Further, in this embodiment, by reducing the impedance in the first discharge path or increasing the impedance in the second discharge path, most of the common-mode interference signals are discharged through the first discharge path, and a very small part of the common-mode interference signals will not affect the working state of the processing chip 402. Reducing the impedance in the first discharge path can be achieved by optimizing the layout and wiring to shorten the distance between the common-mode discharge circuit 302 in the first discharge path and the protective ground terminal PE and increasing the diameter of the connection line between the common-mode discharge circuit 302 and the protective ground terminal PE; increasing the impedance in the second discharge path can be achieved by connecting an additional resistor in series, adjusting the resistance values of the first resistor R1 or the third resistor R3, and adjusting the capacitance values of the fourth capacitor C4 and the fifth capacitor C5. For example, the resistance value of the first resistor R1 can be adjusted from 10 ohm to 4.7 kohm, which can effectively increase the impedance in the second discharge path. By reducing the impedance in the first discharge path or increasing the impedance in the second discharge path, the settings of the fifth capacitor C5 and the fourth capacitor C4 can be retained, which can not only avoid the influence of interference signals on the working state of the processing chip 402, but also ensure the stability of the power supply voltage input to the processing chip 402.

[0165] Further, when the power supply voltage output by the second power supply VCC2 is stable, the fourth capacitor C4 and the fifth capacitor C5 can be removed to block the second discharge path and prevent the common-mode interference signals from entering the processing chip 402 and affecting the operation of the processing chip 402.

[0166] In Figure 11 this, the power supply voltage output by the second power supply VCC2 can be filtered by the fourth capacitor C4 and the fifth capacitor C5 and then input to the voltage conversion circuit 501. The voltage conversion circuit 501 can convert the power supply voltage into the power supply voltage required by the processing chip 402 and then supply power to the processing chip 402. When the processing chip 402 receives the normal power supply voltage and works, the sensor can collect the information to be collected and output a signal to the acquisition interface 10. The acquisition interface 10 can transmit the signal through the transmission path between the voltage follower circuit 401. After filtering the differential-mode interference signals in the transmission path by the first clamping diode D1 and the first capacitor C1 and filtering the common-mode interference signals in the transmission path by the second clamping diode D2, the third clamping diode D3, the gas discharge tube GDT, and the second capacitor C2, the signal in the transmission path is input to the positive input terminal of the inverting follower A after being divided by the first resistor R1 and the second resistor R2. After being output by the inverting follower A, it is transmitted to the processing chip 402 through the third capacitor C3 and the third resistor R3, and the processing chip 402 can analyze the corresponding acquisition information according to the signal.

[0167] In addition, it should be emphasized that there may be no interference signals in the signals output by the acquisition interface 10, that is, there are no differential-mode interference signals and common-mode interference signals. At this time, the signals output by the acquisition interface 10 are also free of interference and will not affect the working state of the signal processing circuit 40. The differential-mode interference protection circuit 20 and the common-mode interference protection circuit 30 do not need to filter out the interference signals and can directly output the signals to the signal processing circuit 40. Of course, in the case where there is one of the differential-mode interference signal and the common-mode interference signal, the corresponding differential-mode interference protection circuit 20 or common-mode interference protection circuit 30 needs to filter out the existing differential-mode interference signal or common-mode interference signal. For example, when there is a differential-mode interference signal in the signal, in the Figure 10 structure, when the acquisition interface 10 outputs a signal, the differential-mode interference protection circuit 20 can filter out the differential-mode interference signal in the signal, and the common-mode interference protection circuit 30 does not need to filter out the non-existent common-mode interference signal. The differential-mode interference protection circuit 20 and the common-mode interference protection circuit 30 can directly output the signal after filtering out the differential-mode interference signal to the signal processing circuit 40. Of course, when there is a common-mode interference signal in the signal, when the acquisition interface 10 outputs a signal, the common-mode interference protection circuit 30 can filter out the common-mode interference signal, and the differential-mode interference protection circuit 20 does not need to filter out the non-existent differential-mode interference signal. The differential-mode interference protection circuit 20 and the common-mode interference protection circuit 30 can directly output the signal after filtering out the common-mode interference signal to the signal processing circuit 40. That is, when there is one interference signal in the differential-mode interference signal or the common-mode interference signal, the differential-mode interference signal or the common-mode interference signal in the signal can be filtered out.

[0168] The above specific implementation manners further elaborate on the purpose, technical solution, and beneficial effects of the present application. It should be understood that the above is only the specific implementation manner of the present application and is not used to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solution of the present application should be included in the protection scope of the present application.

Claims

1. A signal acquisition circuit, characterized in that, The signal acquisition circuit includes an acquisition interface, a differential-mode interference protection circuit, a common-mode interference protection circuit, and a signal processing circuit; The acquisition interface is used for electrically connecting a sensor and the signal processing circuit to receive the signal collected and output by the sensor; The differential-mode interference protection circuit is respectively electrically connected to the acquisition interface and the signal processing circuit, and is used for filtering the differential-mode interference signal in the signal output by the acquisition interface; The common-mode interference protection circuit is respectively electrically connected to the acquisition interface and the signal processing circuit, and is used for filtering the common-mode interference signal in the signal output by the acquisition interface; And The signal processing circuit is used for processing the signal after filtering the differential-mode interference signal and the common-mode interference signal.

2. The signal acquisition circuit according to claim 1, wherein The differential-mode interference protection circuit includes: a first clamping circuit; The first connection end of the first clamping circuit is electrically connected to the first output end of the acquisition interface, and the second connection end of the first clamping circuit is electrically connected to the second output end of the acquisition interface and the signal processing circuit; The first clamping circuit is used for voltage clamping when the first voltage between the first output end and the second output end of the acquisition interface is greater than a first preset voltage.

3. The signal acquisition circuit according to claim 2, wherein The first clamping circuit includes: a first clamping diode; The input end of the first clamping diode is electrically connected to a first power supply and the first output end of the acquisition interface, and the output end of the first clamping diode is electrically connected to the second output end of the acquisition interface and the signal processing circuit.

4. The signal acquisition circuit according to claim 1, wherein The common-mode interference protection circuit includes: a second clamping circuit and a common-mode discharge circuit; The first connection end of the second clamping circuit is electrically connected to the first output end and the second output end of the acquisition interface, and the second connection end of the second clamping circuit is electrically connected to the third output end of the acquisition interface and the common-mode discharge circuit; The second clamping circuit is used for voltage clamping when the second voltage between the first output end and the third output end of the acquisition interface is greater than a second preset voltage and / or the third voltage between the second output end and the third output end of the acquisition interface is greater than a third preset voltage; The common-mode discharge circuit is used for discharging the clamped second voltage and / or the clamped third voltage.

5. The signal acquisition circuit according to claim 4, wherein The second clamping circuit includes: a second clamping diode and a third clamping diode; The input end of the second clamping diode is electrically connected to the first output end of the acquisition interface, the input end of the third clamping diode is electrically connected to the second output end of the acquisition interface, and the output ends of the second clamping diode and the third clamping diode are both electrically connected to the third output end of the acquisition interface and the common-mode discharge circuit.

6. The signal acquisition circuit according to claim 1, characterized in that The signal acquisition circuit further includes: a first capacitor; The first end of the first capacitor is respectively electrically connected to the second end of the acquisition interface, the common-mode interference protection circuit, and the signal processing circuit, and the second end of the first capacitor is respectively electrically connected to the third end of the acquisition interface, the common-mode interference protection circuit, and the signal processing circuit.

7. The signal acquisition circuit according to claim 4, wherein The common-mode discharge circuit includes: a gas discharge tube; The first end of the gas discharge tube is electrically connected to the second connection end of the second clamping circuit, and the second end of the gas discharge tube is electrically connected to the protective ground end; and / or, The common-mode discharge circuit includes: a second capacitor; The first end of the second capacitor is electrically connected to the second connection end of the second clamping circuit, and the second end of the second capacitor is electrically connected to the protective ground end.

8. The signal acquisition circuit according to any one of claims 1 to 7, characterized in that The signal processing circuit includes: a voltage follower circuit and a processing chip; The voltage follower circuit is electrically connected to the second output end of the acquisition interface, the differential-mode interference protection circuit, the common-mode interference protection circuit, and the processing chip respectively; The voltage follower circuit is configured to perform voltage following on the signal.

9. The signal acquisition circuit according to claim 8, wherein The signal acquisition circuit further includes: a power supply circuit and an anti-backflow circuit; The power supply circuit is electrically connected to the processing chip and the voltage follower circuit through the anti-backflow circuit; The power supply circuit is configured to provide a power supply voltage for the processing chip through the anti-backflow circuit.

10. An electronic device, characterized in that, The electronic device includes a sensor and the signal acquisition circuit according to any one of claims 1 to 9; The sensor is electrically connected to the acquisition interface of the acquisition circuit.

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