Low-delay SerDes communication system and method based on phase adjustment mechanism

Abstract

The invention relates to a low-delay SerDes communication system and method based on a phase adjustment mechanism. The system comprises a phase adjustment module connected between a PMA receiving end and a descrambling module, wherein the phase adjustment module comprises a feature code matching unit, a data phase adjustment unit, a clock phase adjustment unit and a state control unit which are in communication connection; the data phase adjusting unit is used for sending a data phase adjusting request when the feature code is not successfully matched, adjusting the data phase of the parallel data stream output by the PMA receiving end, and enabling the edge of the parallel data to be aligned with the edge of the transmitted data packet, and the clock phase adjusting unit is used for sending a clock phase adjusting request when the feature code is not successfully matched, and enabling the edge of the parallel data stream to be aligned with the edge of the transmitted data packet. And adjusting the clock phase of the parallel clock output by the PMA receiving end to enable the sending clock of the PCS receiving end to be in a safe sampling window. Compared with the prior art, the method has the advantages that the SerDes transmission delay is further reduced, so that the high-speed transmission of the low-delay serial data stream is realized, and the like.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to a low-latency SerDes communication system and method based on a phase adjustment mechanism. Background Art

[0002] Technologies such as 5G, big data, and artificial intelligence rely on communication devices to perform high-speed transmission of massive amounts of data. Moreover, with the continuous enrichment of applications and the continuous growth of data volume, higher requirements for data transmission rates will continue to be put forward. In this regard, the Chiplet technology is an effective solution. It allows chip designers to decompose functional units into smaller independent chips and build more complex systems by integrating them. High-speed data transmission needs to be achieved between Chiplets, which has high requirements in terms of latency, anti-interference ability, and driving ability. The SerDes technology improves the transmission rate by serializing data transmission while minimizing the complexity of circuit wiring. For Chiplet applications, the key advantage of the SerDes technology is that it can quickly transmit data between chips while controlling the timing and delay during the transmission process. However, this method introduces new challenges. In particular, the data transmission between chips is sensitive to transmission delay, which has a great impact on the overall working efficiency of the chip. How to transmit high-speed data with low latency has become a key issue.

[0003] SerDes is short for serializer / deserializer, which mainly consists of a PMA (Physical Medium Attachment) sublayer and a PCS (Physical Coding) sublayer, and includes independent transmit channels and receive channels. The transmit channel mainly performs encoding and parallel-to-serial conversion operations on the parallel data input by the upper-layer protocol chip, so that the generated serial stream has the characteristic of DC balance, and finally outputs it in the form of a low-voltage differential signal. The receive channel converts the received differential serial signal into a parallel signal, and returns it to the host computer in the form of a parallel signal after operations such as byte boundary alignment and descrambling. The SerDes interface converts low-speed parallel signals into high-speed serial signals for transmission. The transmission medium is only two differential signal lines, which can effectively reduce the wiring difficulty, the crosstalk impact between signal lines, and the cost. At the same time, it uses the clock data recovery technology to generate a precise clock signal from the clock information contained in the serial received data to sample the received data, improving the data stability. Since SerDes uses low-voltage differential signals for transmission, the data has strong anti-interference ability and can support a large data transmission rate and a long transmission distance.

[0004] In the prior art, for multi-channel SerDes transmission, an asynchronous FIFO is usually utilized in the receiving path of the PCS to solve the problems of cross-clock domain handover and skew between channels. For example, Chinese Patent CN116318412A discloses a SerDes high-speed communication system based on a domestic FPGA. The system includes a differential serial data interface, a differential clock interface, and an FPGA logic design module, a transmitting module, a receiving module, and a clock management module implemented by the FPGA. The differential serial data interface is a fiber optic interface based on SerDes. The clock management module is responsible for generating the clock signals required by each module and managing the phase relationship between these clocks. Both the transmitting module and the receiving module are composed of a PCS layer and a PMA layer. In the transmitting module, the TX PCS layer includes: an encoding module (TX Gearbox Block), a phase compensation FIFO, and a transmitting end polarity control module (TX Polarity). The phase compensation FIFO is used for rate and phase matching between the parallel clock domains of the TX PMA and the transmitting TX PCS.

[0005] However, this method of using an asynchronous FIFO for phase compensation will introduce several clock cycle delays to the SerDes transmission. Therefore, how to further reduce the SerDes transmission delay to achieve high-speed transmission of a low-delay serial data stream remains a problem to be solved in this field. Summary of the Invention

[0006] The purpose of the present invention is to overcome the above-mentioned defects existing in the prior art and provide a low-delay SerDes communication system and method based on a phase adjustment mechanism. Aiming at the existing cross-clock domain mechanism and channel skew elimination mechanism implemented by using an asynchronous FIFO, the system and method proposed by the present invention replace the role of the asynchronous FIFO through the phase adjustment mechanism, thereby reducing the existing SerDes transmission delay and achieving low-delay serial data stream transmission.

[0007] The purpose of the present invention can be achieved through the following technical solutions:

[0008] According to a first aspect of the present invention, a low-latency SerDes communication system based on a phase adjustment mechanism is provided. The system includes a PMA layer and a PCS layer that are communicatively connected. The PMA layer includes a PMA transmitter and a PMA receiver. The PCS layer includes a PCS transmitter, a PCS receiver, and a general module. The PCS transmitter includes a scrambling module, and the scrambling module is connected between the general module and the PMA transmitter. The PCS receiver includes a phase adjustment module and a descrambling module. The phase adjustment module is connected between the PMA receiver and the descrambling module, and the descrambling module is connected between the phase adjustment module and the general module. The general module is configured to allocate signal data from an upper computer to the PCS transmitter according to a pre-acquired link auto-negotiation result. The scrambling module is configured to perform scrambling processing on the signal data in the PCS transmitter. The PMA transmitter is configured to receive the scrambled signal data and output a serial data stream. The PMA receiver is configured to receive the serial data stream transmitted by a channel, restore the serial data stream to a parallel data stream, and generate a corresponding parallel clock. The phase adjustment module is configured to adjust the data phase and the clock phase of the PMA receiver in the PCS receiver.

[0009] As a preferred technical solution, the phase adjustment module includes a signature matching unit, a data phase adjustment unit, a clock phase adjustment unit, and a state control unit that are communicatively connected. The signature matching unit is configured to determine whether the received parallel data stream and the parallel clock match a preset signature. The data phase adjustment unit is configured to send a data phase adjustment request when the signature is not successfully matched. The data phase adjustment request is used to adjust the data phase of the parallel data stream output by the PMA receiver so that the edges of the parallel data are aligned with the edges of the transmitted data packet. The clock phase adjustment unit is configured to send a clock phase adjustment request when the signature is not successfully matched. The clock phase adjustment request is used to adjust the clock phase of the parallel clock output by the PMA receiver so that the transmission clock of the PCS receiver is within a safe sampling window. The state control unit is configured to control the phase adjustment module to jump between multiple working states and the signature matching unit, the data phase adjustment unit, and the clock phase adjustment unit to operate in corresponding working states.

[0010] As a preferred technical solution, the specific operation process of the signature matching unit includes: determining the data phase of the signature, and determining whether the received parallel data stream and the parallel clock meet the format of a 1-tap signature and a multi-tap PRBS data.

[0011] As a preferred technical solution, the specific operation process of the data phase adjustment unit includes: obtaining the current data phase position; if the current data phase position is within the first preset data interval, sending a data phase forward request; if the current data phase position is within the second preset data interval, sending a data phase backward request; wherein, the first preset data interval is before the second preset data interval.

[0012] As a preferred technical solution, the specific operation process of the clock phase adjustment unit includes: scanning all clock phases with a preset step size; obtaining the signature codes at each clock phase and determining whether they are correct; when the signature codes are correct, marking them as safe sampling phases, and further determining the optimal clock phase position that satisfies the safe sampling window and has the lowest delay, where the optimal clock phase position is the position within the safe sampling window and at a preset number of clock phases away from the window edge.

[0013] As a preferred technical solution, the working states include a power-on initialization state, a first data phase adjustment state, a second data phase adjustment state, a data phase verification state, a clock domain switching state, a clock phase adjustment state, a clock phase verification state, and a phase adjustment end state; when the state control unit receives an enable signal, the phase adjustment module jumps sequentially from the power-on initialization state to the phase adjustment end state; when the phase adjustment enable is turned off, the phase adjustment module jumps from any current working state to the power-on initialization state.

[0014] As a preferred technical solution, the specific operation processes of the first data phase adjustment state, the second data phase adjustment state, the clock domain switching state, and the clock phase adjustment state include: when in the first data phase adjustment state, controlling the signature code matching unit to perform a primary signature code matching on the received data, obtaining the data phase of the signature code and then jumping to the second data phase adjustment state; when in the second data phase adjustment state, controlling the signature code matching unit to perform a secondary signature code matching on the received data, and when the matching is not successful, controlling the data phase adjustment unit to send a data phase adjustment request, thereby adjusting the data phase output by the PMA receiver until the matching is successful and then jumping to the data phase verification state; when in the clock domain switching state, switching the working clock domain from the parallel clock of the PMA receiver to the transmission clock of the PCS receiver, and after the switching, jumping to the clock phase adjustment state; when in the clock phase adjustment state, controlling the signature code matching unit to perform a signature code matching on the received data, and when the matching is not successful, controlling the clock phase adjustment unit to send a clock phase adjustment request, thereby adjusting the clock phase output by the PMA receiver until the matching is successful and then jumping to the data clock phase verification state.

[0015] As a preferred technical solution, the process of obtaining the link auto-negotiation result specifically includes: In the first stage, all channels are marked as active states, and a preset test sequence TS1 is sent in all channels. After the first preset time, at the receiving end of each channel, it is detected whether the number of received test sequences TS1 meets the first preset threshold. If so, the corresponding channel is marked as a live state; In the second stage, a preset test sequence TS2 is sent on the channels marked as live states. After the second preset time, if there is any channel where the number of received test sequences TS2 meets the second preset threshold, the channels with bidirectional normal communication are selected as the actually used channels; In the third stage, the state machines at both ends of the link are synchronized, and the IDLE sequence is continuously sent, and the channel locking state is continuously detected. After the third preset time, the link is locked and the connection is completed.

[0016] According to the second aspect of the present invention, a low-latency SerDes communication method based on a phase adjustment mechanism is provided. The method is implemented based on the above system and includes the following steps: A signal sending step, where the PCS sending end receives signal data from the upper computer and performs scrambling processing, and the PMA sending end receives the scrambled signal data and outputs a serial data stream; A signal receiving and adjusting step, where the PMA receiving end receives the serial data stream transmitted by the channel, restores the serial data stream to a parallel data stream and generates a corresponding parallel clock, and the PCS receiving end adjusts the data phase and clock phase of the PMA receiving end.

[0017] As a preferred technical solution, the process of the PCS receiving end adjusting the data phase and clock phase of the PMA receiving end specifically includes: A data phase adjustment step, where the received parallel data stream is matched with a preset signature code. When the signature code is not successfully matched, a data phase adjustment request is sent to adjust the data phase of the parallel data stream output by the PMA receiving end to align the edges of the parallel data with the edges of the transmitted data packet; A clock phase adjustment step, where the received parallel clock is matched with a preset signature code. When the signature code is not successfully matched, a clock phase adjustment request is sent to adjust the clock phase of the parallel clock output by the PMA receiving end to make the sending clock of the PCS receiving end in the safe sampling window.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. The present invention adds a phase adjustment module in a SerDes communication system. This module can adjust the data phase and clock phase of the PMA receiver at the PCS receiver end. By adjusting the data phase, the data on multiple paths sent by the PMA is located in the same beat. By adjusting the clock phase, the clock phase of the PCS received clock is located in the safe sampling window overlapped by each link, enabling the PCS received clock to safely sample correct data, and the data on each path is data in the same beat. Thus, the channel skew cancellation mechanism is eliminated and the delay caused by the asynchronous FIFO is eliminated, reducing the delay of the PCS receiving path and realizing low-delay serial data stream transmission.

[0020] 2. In the present invention, in the second data phase adjustment state of the phase adjustment module, the data phase adjustment unit sends a data phase adjustment request and sends corresponding data phase forward or backward requests according to different positions of the data phase, thereby adjusting the data phase of the parallel data at the PMA receiver end, making the edges of the parallel data sent by the PMA receiver end align with the edges of the transmitted data packet, so as to realize that the data transmitted in each beat is a complete data packet, and thus realizing low-delay serial data stream transmission on the premise of eliminating the channel skew cancellation mechanism.

[0021] 3. In the present invention, in the clock domain switching state, after the working clock domain of the phase adjustment module is switched from the parallel clock of the PMA receiver end to the transmission clock of the PCS receiver end, it jumps to the clock phase adjustment state. In this state, the clock phase adjustment unit sends a clock phase adjustment request, obtains the safe sampling phase according to the result of whether the clock phase corresponding signature code is correct, obtains the safe sampling window, and determines the optimal clock phase position based on the safe sampling window, thereby adjusting the clock phase of the parallel clock at the PMA receiver end to meet the requirement of the PCS received clock to safely sample parallel data, thus avoiding the occurrence of metastability and reducing the overall delay of the SerDes communication transmission on the premise of eliminating the asynchronous FIFO cross-clock mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic structural diagram of a low-delay SerDes communication system based on a phase adjustment mechanism in an embodiment of the present invention;

[0023] Figure 2 It is a schematic diagram of the link auto-negotiation process in an embodiment of the present invention;

[0024] Figure 3 It is a schematic structural diagram of the phase adjustment module in an embodiment of the present invention;

[0025] Figure 4 It is a schematic diagram of the processing flow of the phase adjustment module in an embodiment of the present invention.

[0026] Figure 5Schematic diagram of multi-channel data flow of the SerDes communication system with low-latency transmission characteristics in the embodiments of the present invention. Detailed implementation manners

[0027] In the context of the present invention, the cross-clock mechanism means that since the transmission clock of the PMA and the reception clock of the PCS are asynchronous clocks, the prior art needs to use an asynchronous FIFO to buffer data to ensure that the PCS receives the correct data stream. The channel skew cancellation mechanism means that since the transmission delays of each channel are different, resulting in the data arriving in a sequential order, the prior art needs to cache and reorganize the data of all paths in a general module. The purpose of the present invention is to provide a low-latency SerDes communication system and method based on a phase adjustment mechanism, which eliminates the cross-clock mechanism of the asynchronous FIFO and the channel skew cancellation mechanism in the PCS reception path through the phase adjustment mechanism, reduces the delay of the PCS reception path, and realizes low-latency serial data stream transmission.

[0028] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are implemented on the premise of the technical solution of the present invention, and detailed implementation manners and specific operation processes are given, but the protection scope of the present invention is not limited to the following embodiments.

[0029] Embodiment

[0030] As Figure 1 shown, the low-latency SerDes communication system provided in this embodiment includes a PMA layer and a PCS layer connected by communication. The PMA layer includes a PMA transmitter and a PMA receiver. The PCS layer includes a PCS transmitter, a PCS receiver, and a general module. The general module is communicatively connected to an external host computer. The PMA transmitter and the PCS transmitter form a transmission path, and the PMA receiver and the PCS receiver form a reception path. Among them, the PCS transmitter includes a scrambling module, which is connected between the general module and the PMA transmitter. The PCS receiver includes a phase adjustment module and a descrambling module. The phase adjustment module is connected between the PMA receiver and the descrambling module, and the descrambling module is connected between the phase adjustment module and the general module. The PMA transmitter and the PMA receiver perform serial data stream transmission through a channel.

[0031] The functions of each module in the foregoing system are as follows: The general module is used to allocate the signal data from the host computer to the PCS transmitter according to the pre-acquired link auto-negotiation result; the scrambling module is used to scramble the signal data in the PCS transmitter; the PMA transmitter is used to receive the scrambled signal data and output a serial data stream; the PMA receiver is used to receive the serial data stream transmitted by the channel, restore the serial data stream to a parallel data stream and generate a corresponding parallel clock; the phase adjustment module is used to adjust the data phase and clock phase of the PMA receiver in the PCS receiver.

[0032] The phase adjustment module is constructed based on a phase adjustment mechanism, and the phase adjustment mechanism includes data phase adjustment and clock phase adjustment. Among them, data phase adjustment means that the PCS receiver judges according to whether the received parallel data matches the signature. When the two do not match, it means that the edge of the received parallel data is not aligned with the edge of the transmitted data packet. Therefore, the PCS needs to send a data phase adjustment request to make the PMA receiver shift left or right each time (for example, 1-bit data phase) until the parallel data received by the PCS receiver matches the signature; clock phase adjustment means that when sampling the parallel data in the PMA parallel clock domain using the transmission clock of the PCS receiver, the PCS receiver may be in a metastable state, that is, the received parallel data does not match the signature. At this time, the PCS needs to send a clock phase adjustment request to make the clock phase of the PMA receiver's parallel clock shift left or right each time (for example, 1 / 32 clock cycle phase) until the transmission clock of the PCS receiver is within the safe sampling window, so that the parallel data transmitted by the PMA receiver can be directly and safely sampled. At this time, the received parallel data matches the signature.

[0033] In this embodiment, the system first needs to complete the link auto-negotiation process to achieve reliable transmission between links. As Figure 2 shown, the link auto-negotiation process can be divided into three stages:

[0034] In the first stage, mark all channels as active states, start sending the test sequence TS1 in all channels, and after the first preset time, detect whether the number of received test sequences TS1 in the receiving end of each channel meets the first preset threshold. If so, that is, if it can be successfully detected, mark the channel as a live state; in the second stage, send the test sequence TS2 on the channels marked as live states. After the second preset time, if there is any channel that can receive the number of test sequences TS2 meeting the second preset threshold, it indicates that the number of channels has been negotiated, and select the channels with normal two-way communication as the actual used channels; in the third stage, the state machines at both ends of the link are synchronized, continue to send the IDLE sequence, continuously detect the channel locking state, and after the third preset time, the link is locked and the connection is completed.

[0035] Optionally, link auto-negotiation supports auto-negotiation after reset or manual re-negotiation, and the auto-negotiation function can also be disabled.

[0036] Exemplarily, Figure 3 This is the structure of the phase adjustment module provided in this embodiment. The phase adjustment module is used to adjust the clock phase and data phase of the PMA receiving path in the PCS receiving end, which can eliminate the asynchronous FIFO cross-clock mechanism and channel skew cancellation mechanism of the PCS receiving path, replacing the role of the asynchronous FIFO. In this way, the latency cost brought by the asynchronous FIFO in the PCS receiving path can be reduced, and low-latency serial data transmission can be achieved. As Figure 3 shown, the phase adjustment module includes a signature matching unit, a data phase adjustment unit, a clock phase adjustment unit, and a state control unit that are communicatively connected. Among them:

[0037] The signature matching unit is used to determine whether the received parallel data stream and parallel clock match a preset signature. Specifically, it determines the data phase of the signature, and determines whether the received data satisfies the 1-beat signature and the multi-beat PRBS data format. Optionally, the signature is a custom 32-bit special codeword with a value of "0x4C70F03F". This codeword ensures DC balance and also takes into account as many spectrum types as possible. Optionally, several beats of 32-bit PRBS (pseudo-random binary sequence) need to be sent after sending the signature. Since the PRBS is not only DC balanced but also closer to white noise in terms of spectral characteristics, a special training sequence can be formed by combining the signature and the PRBS. By continuously sending this training sequence, the data phase and clock phase of the PMA at the receiving end can be calibrated.

[0038] The data phase adjustment unit is used to adjust the data phase of the parallel data at the PMA receiving end. Specifically, when the signature is not successfully matched, a data phase adjustment request is sent, and the PMA receiving end responds to this data phase adjustment request. Thus, the data phase adjustment unit can control the PMA receiving end to adjust the data phase of the output parallel data stream, so that the parallel data is the edge of the packet transmitted with edge alignment, so as to make each beat of data a complete data packet. Taking the transmission of 32-bit parallel data as an example, first, the data of two beats will be stored, that is, 64 bits. The 32-bit signature is found in the 64-bit data to determine the current data phase. When the current data phase position is 0, no adjustment is required; when the current data phase position is between 1 and 31 (i.e., the first preset data interval in this embodiment), a data phase advance request needs to be sent; when the current data phase position is between 32 and 63 (i.e., the second preset data interval in this embodiment), a data phase retreat request needs to be sent, so that each beat of data received is a complete signature or PRBS data, so as to make the data output per beat a complete data packet.

[0039] The clock phase adjustment unit is used to adjust the clock phase of the parallel clock at the PMA receiving end, find the safe sampling window, and reduce the sampling delay of the PMA parallel data. Specifically, when the signature is not successfully matched, a clock phase adjustment request is sent, and the PMA receiving end responds to this clock phase adjustment request. Thus, the clock phase adjustment unit can control the PMA receiving end to adjust the clock phase of the output parallel clock, so that the transmission clock of the PCS receiving end is within the safe sampling window, and further, the asynchronous FIFO cross-clock mechanism and the channel skew cancellation mechanism can be eliminated, thereby reducing the overall delay of the SerDes circuit. Exemplarily, the clock phase adjustment unit scans all clock phases in 1 / 32 steps (i.e., the preset step in this embodiment), records the signatures at 32 clock phases and determines whether they are correct. If the signature is correct, it is recorded as the safe sampling phase, and the best clock phase position that meets the safe sampling window and has the lowest delay is found. The best clock phase position is defined as the position that is within the safe sampling window and 3 (i.e., the preset number in this embodiment) clock phases away from the window edge. This clock phase adjustment unit can adjust the clock phase of the parallel clock at the PMA receiving end so that the receiving clock of the PCS is within the safe sampling window, thereby avoiding metastability and replacing the function of the asynchronous FIFO cross-clock mechanism, thus reducing the overall delay of the SerDes communication system.

[0040] The state control unit is used to control the working process of the phase adjustment module, specifically including controlling the phase adjustment module to jump between multiple working states and the aforementioned signature matching unit, data phase adjustment unit, and clock phase adjustment unit to operate in the corresponding working states, so as to finally find the best data phase and clock phase and achieve low-delay transmission.

[0041] Exemplarily, Figure 4 This is a schematic diagram of the state control unit controlling the working process of the phase adjustment module in this embodiment. Based on the state control unit, the phase adjustment processing flow of this embodiment can be divided into eight states: power-on initialization state (state one), first data phase adjustment state (state two), second data phase adjustment state (state three), data phase verification state (state four), clock domain switching state (state five), clock phase adjustment state (state six), clock phase verification state (state seven), and phase adjustment end state (state eight). The specific process is as follows:

[0042] 1) Power-on initialization state: In the power-on initialization state, all registers are in the reset state. When an enable signal is received, it jumps to state two.

[0043] 2) First data phase adjustment state: Controls the signature matching unit to perform an initial signature match on the received data. The initial signature match is to detect the position of the signature in the total data volume (i.e., the data phase). When the signature is successfully matched and the position is determined, the relevant data phase is recorded and the process jumps to state three. Exemplarily, the total data volume is 64 bits. If the length of the signature is 32 bits, the position where the signature appears may be in [10:41] or may also appear in [20:51]. In other words, the 32-bit signature will definitely appear in the 64 bits. This state is to find the position of the signature in the 64 bits, that is, the data phase, record it, and then jump to the next state.

[0044] 3) Second data phase adjustment state: Controls the signature matching unit to perform a secondary signature match on the received data. The secondary signature match is to detect whether the received data is in the format of a periodic 1-beat signature and several beats of PRBS data. If so, the match is successful; otherwise, the match is unsuccessful. When the match is unsuccessful, controls the data phase adjustment unit to send a data phase adjustment request, thereby adjusting the data phase output by the PMA receiver until the match is successful and then jumps to the data phase verification state. Exemplarily, by sending a data phase advance or retreat request, the PMA receiver adjusts the data phase to the edge position, that is, a complete signature can be obtained in one beat. After the adjustment is completed, it jumps to state four.

[0045] 4) Data phase verification state: Uses the signature matching unit to verify again whether the signature obtained in one beat is complete. This state is to prevent errors in data phase adjustment. After the verification is completed, it jumps to state five.

[0046] 5) Clock domain switching state: In this state, the phase adjustment module issues a clock switching request to switch the PCS operating clock domain from the parallel clock of the PMA receiver to the transmission clock of the PCS side. After the switching is completed, it jumps to state six.

[0047] 6) Clock phase adjustment state: Controls the signature matching unit to perform a signature match on the received data. When the match is unsuccessful, controls the clock phase adjustment unit to send a clock phase adjustment request, thereby adjusting the clock phase output by the PMA receiver until the match is successful and then jumps to the data clock phase verification state. Exemplarily, the parallel data clock phase of the PMA receiver is scanned by adjusting the clock phase advance request, and the signature match results at 32 clock phases are recorded. After the phase scan is completed, the optimal clock phase is determined. The optimal clock phase is the safe sampling window that satisfies the transmission clock of the PCS receiving path and is the overlapping safe sampling window for each link. By adjusting the clock phase retreat request, the clock phase of the PMA output data is adjusted to the optimal position, and then it jumps to state seven.

[0048] 7) Clock phase verification status: Verify whether the received data meets the format of a one-beat signature and several beats of PRBS data. Specifically, use the signature matching unit again to verify whether the signature obtained in one beat is complete. This state is to prevent errors in clock phase adjustment. After the verification is completed, jump to state eight.

[0049] 8) Phase adjustment end status: This is the normal working state after the adjustment is completed.

[0050] In any state, when the phase adjustment enable is turned off, the state will jump to state one.

[0051] During the training phase, the signature matching unit detects whether it periodically receives the format of a one-beat signature and several beats of PRBS data. When the matching is unsuccessful, it will notify the data phase adjustment unit and the clock phase adjustment unit to send corresponding adjustment requests; when the matching is successful and the quantity exceeds the set threshold, the signature matching unit will inform the state control unit that the next step can be taken. Specifically, the matching actions of the signature matching unit are performed in state three (the second data phase adjustment state), state four (data phase verification state), and state seven (clock phase verification state). When the matching determination is established, that is, when these states end, it will jump to the next state, which is to perform the next step.

[0052] Exemplarily, Figure 5 This is a schematic diagram of the data flow of the SerDes communication system with low-latency transmission characteristics in this embodiment. The data source of the PCS layer in this embodiment can be 128-bit data sent by the media access host computer. The specific data transfer process is as follows:

[0053] The general module of the PCS layer distributes 128-bit data to the successfully established PCS transmitter according to the link auto-negotiation result. Each PCS layer can send or receive 32-bit data, and each PCS layer corresponds to one channel. There are four channels in this embodiment;

[0054] The scrambling module performs scrambling processing on the transmitted data to disrupt long sequences of consecutive '0's and long sequences of consecutive '1's, which can ensure DC balance in channel transmission;

[0055] The PMA transmitter receives the data processed by the scrambling module and outputs multiple parallel data bits one by one through a high-speed clock, thereby forming a serial data stream. The serial data stream is conditioned by a forward feedback equalizer and then sent to the channel by the driver;

[0056] The PMA receiver receives the serial data stream transmitted by the channel. The serial data stream is first conditioned by a linear equalizer to compensate for signal loss during channel transmission. The phase-locked loop then recovers the sampling clock from the serial data stream, restores the serial data stream to a parallel data stream through the sampling clock, and generates a corresponding parallel clock.

[0057] In the PCS receiver, the phase adjustment module adjusts the data phase and clock phase of the PMA receiver to find the optimal data phase and clock phase. At this time, the PCS receiver can directly receive the parallel data sent by the PMA without any delay.

[0058] The descrambling module performs descrambling processing on the received parallel data to obtain the 32-bit original data sent by the host computer. The general module integrates the 32-bit data from each receiving path, restores the original 128-bit data, and sends it to the subsequent processing module.

[0059] The prior art needs to add an asynchronous FIFO between the PMA receiver and the descrambling module to solve the cross-clock domain problem, and at least 6 beats of PCS receive clock delay are added in this process. However, the present invention solves the cross-clock problem by adding a phase adjustment mechanism without using an asynchronous FIFO, which can save at least 6 beats of delay.

[0060] For multi-channel transmission, due to the use of the asynchronous FIFO mechanism in the prior art, and the receive clocks of each PCS channel are asynchronous clocks, resulting in a sequential arrival of data, a data skew problem will be introduced between the channels. Therefore, an asynchronous FIFO needs to be used in the general module to cache the data of all paths, and the data is uniformly read out by the transmit clock in the general module and sent to the subsequent processing module. The introduced delay depends on the delay between the channels, but at least 6 beats of delay are required. However, the present invention avoids the transmission delay of each path through the phase adjustment mechanism, thereby saving at least 6 beats of delay.

[0061] Furthermore, this embodiment also provides a low-delay SerDes communication method based on the phase adjustment mechanism. This method is implemented based on the foregoing system and includes a signal transmission step and a signal reception and adjustment step. Among them, in the signal transmission step, the PCS transmitter receives the signal data from the host computer and performs scrambling processing, and the PMA transmitter receives the scrambled signal data and outputs a serial data stream; in the signal reception and adjustment step, the PMA receiver receives the serial data stream transmitted by the channel, restores the serial data stream to a parallel data stream and generates a corresponding parallel clock, and the PCS receiver adjusts the data phase and clock phase of the PMA receiver. The specific processes of the data phase adjustment step and the clock phase adjustment step are basically the same as the operation processes of the corresponding adjustment units in the foregoing system, and will not be elaborated here.

[0062] The preferred specific embodiments of the present invention have been described in detail above. It should be understood that those of ordinary skill in the art can make many modifications and variations based on the concept of the present invention without creative efforts. Therefore, all technical solutions that can be obtained by those skilled in the art in this technical field based on the concept of the present invention through logical analysis, reasoning, or limited experiments on the basis of the prior art shall fall within the protection scope determined by the claims.

Claims

1. A low-latency SerDes communication system based on a phase adjustment mechanism, the system comprising a PMA layer and a PCS layer connected for communication, the PMA layer including a PMA transmitter and a PMA receiver, characterized in that, The PCS layer includes a PCS transmitter, a PCS receiver, and a general module. The PCS transmitter includes a scrambling module, which is connected between the general module and the PMA transmitter. The PCS receiver includes a phase adjustment module and a descrambling module. The phase adjustment module is connected between the PMA receiver and the descrambling module, and the descrambling module is connected between the phase adjustment module and the general module; The general module is configured to allocate signal data from the host computer to the PCS transmitter according to the pre-obtained link auto-negotiation result; The scrambling module is configured to perform scrambling processing on the signal data in the PCS transmitter; The PMA transmitter is configured to receive the scrambled signal data and output a serial data stream; The PMA receiver is configured to receive the serial data stream transmitted by the channel, restore the serial data stream to a parallel data stream, and generate a corresponding parallel clock; The phase adjustment module is configured to adjust the data phase and clock phase of the PMA receiver in the PCS receiver; 2. The low-latency SerDes communication system based on a phase adjustment mechanism according to claim 1, wherein The phase adjustment module includes a signature matching unit, a data phase adjustment unit, a clock phase adjustment unit, and a state control unit that are communicatively connected; The signature matching unit is configured to determine whether the received parallel data stream and parallel clock match a preset signature; The data phase adjustment unit is configured to send a data phase adjustment request when the signature is not successfully matched. The data phase adjustment request is used to adjust the data phase of the parallel data stream output by the PMA receiver to align the edges of the parallel data with the edges of the transmitted data packet; The clock phase adjustment unit is configured to send a clock phase adjustment request when the signature is not successfully matched. The clock phase adjustment request is used to adjust the clock phase of the parallel clock output by the PMA receiver to make the transmit clock of the PCS receiver within the safe sampling window; The state control unit is configured to control the phase adjustment module to jump between multiple working states and the signature matching unit, the data phase adjustment unit, and the clock phase adjustment unit to operate in the corresponding working states.

3. The low-latency SerDes communication system based on a phase adjustment mechanism according to claim 2, wherein The specific operation process of the signature matching unit includes: determining the data phase of the signature, and determining whether the received parallel data stream and parallel clock meet the format of the 1-tap signature and the multi-tap PRBS data.

4. The low-latency SerDes communication system based on a phase adjustment mechanism according to claim 2, wherein The specific operation process of the data phase adjustment unit includes: Obtaining the current data phase position; If the current data phase position is within the first preset data interval, sending a data phase forward request; If the current data phase position is within the second preset data interval, sending a data phase backward request; Wherein, the first preset data interval is before the second preset data interval.

5. The low-latency SerDes communication system based on a phase adjustment mechanism according to claim 2, wherein The specific operation process of the clock phase adjustment unit includes: Scanning all clock phases with a preset step size; Obtaining the signature at each clock phase and determining whether it is correct; When the signature is correct, it is recorded as the safe sampling phase, and then the optimal clock phase position that satisfies the safe sampling window and has the lowest delay is determined. The optimal clock phase position is the position within the safe sampling window and at a preset number of clock phases away from the window edge.

6. The low-latency SerDes communication system based on a phase adjustment mechanism according to claim 2, wherein The working states include the power-on initialization state, the first data phase adjustment state, the second data phase adjustment state, the data phase verification state, the clock domain switching state, the clock phase adjustment state, the clock phase verification state, and the phase adjustment end state; When the state control unit receives an enable signal, the phase adjustment module jumps sequentially from the power-on initialization state to the phase adjustment end state; when the phase adjustment enable is turned off, the phase adjustment module jumps from any current working state to the power-on initialization state.

7. The low-latency SerDes communication system based on a phase adjustment mechanism according to claim 6, wherein The specific operation processes of the first data phase adjustment state, the second data phase adjustment state, the clock domain switching state, and the clock phase adjustment state include: When in the first data phase adjustment state, control the signature matching unit to perform an initial signature match on the received data. After obtaining the data phase of the signature, jump to the second data phase adjustment state; When in the second data phase adjustment state, control the signature matching unit to perform a secondary signature match on the received data. When the match is not successful, control the data phase adjustment unit to send a data phase adjustment request, and then adjust the data phase output by the PMA receiver until the match is successful and then jump to the data phase verification state; When in the clock domain switching state, switch the working clock domain from the parallel clock of the PMA receiver to the transmit clock of the PCS receiver. After the switch, jump to the clock phase adjustment state; When in the clock phase adjustment state, control the signature matching unit to perform a signature match on the received data. When the match is not successful, control the clock phase adjustment unit to send a clock phase adjustment request, and then adjust the clock phase output by the PMA receiver until the match is successful and then jump to the data clock phase verification state.

8. The low-latency SerDes communication system based on a phase adjustment mechanism according to claim 1, wherein The process of obtaining the link auto-negotiation result specifically includes: In the first stage, mark all channels as active states, and send a preset test sequence TS1 in all channels. After a first preset time, detect at the receiving end of each channel whether the number of received test sequences TS1 meets a first preset threshold. If so, mark the corresponding channel as a surviving state; In the second stage, send a preset test sequence TS2 on the channels marked as surviving states. After a second preset time, if there is any channel that receives the number of test sequences TS2 meeting a second preset threshold, select the channels with normal two-way communication as the actually used channels; In the third stage, synchronize the state machines at both ends of the link, continue to send IDLE sequences, continuously detect the channel locking state. After a third preset time, the link is locked and the connection is completed.

9. A low-latency SerDes communication method based on a phase adjustment mechanism, characterized in that, The method is implemented based on the system according to any one of claims 1-8, and includes the following steps: Signal transmission step: The PCS transmitter receives signal data from the host computer and performs scrambling processing, and the PMA transmitter receives the scrambled signal data and outputs a serial data stream. Signal reception and adjustment step: The PMA receiver receives the serial data stream transmitted by the channel, restores the serial data stream to a parallel data stream and generates a corresponding parallel clock, and the PCS receiver adjusts the data phase and clock phase of the PMA receiver.

10. The low-latency SerDes communication method based on a phase adjustment mechanism according to claim 9, wherein, The PCS receiver adjusts the data phase and clock phase of the PMA receiver. The specific process includes: Data phase adjustment step: Match the received parallel data stream with a preset signature. When the signature is not successfully matched, send a data phase adjustment request to adjust the data phase of the parallel data stream output by the PMA receiver so that the edges of the parallel data are aligned with the edges of the transmitted data packet. Clock phase adjustment step: Match the received parallel clock with a preset signature. When the signature is not successfully matched, send a clock phase adjustment request to adjust the clock phase of the parallel clock output by the PMA receiver so that the transmission clock of the PCS receiver is within the safe sampling window.

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